mirror of https://github.com/openXC7/prjxray.git
Merge pull request #857 from antmicro/fuzzer_007_ff_sr_to_q
Fixed fuzzer 007 to make it extract missing timings for FFs
This commit is contained in:
Karol Gugala
GitHub
commit
0f37f0c294
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@ -6,8 +6,16 @@ clean:
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build/bel_timings.txt:
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bash runme.sh
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build/bel_timings.json: build/bel_timings.txt
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python3 tim2json.py --timings=build/bel_timings.txt --json=build/bel_timings.json --properties=build/bel_properties.txt --propertiesmap=properties_map.json --belpins=build/bel_pins.txt --sitepins=build/tile_pins.txt --debug true
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build/fixup_timings: build/bel_timings.txt
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python3 fixup_timings_txt.py --txtin build/bel_timings.txt --txtout build/bel_timings.txt --site RAMBFIFO36E1 --slice BRAM_L --type timings
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python3 fixup_timings_txt.py --txtin build/bel_timings.txt --txtout build/bel_timings.txt --site RAMBFIFO36E1 --slice BRAM_R --type timings
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python3 fixup_timings_txt.py --txtin build/bel_pins.txt --txtout build/bel_pins.txt --site RAMBFIFO36E1 --slice BRAM_L --type pins
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python3 fixup_timings_txt.py --txtin build/bel_pins.txt --txtout build/bel_pins.txt --site RAMBFIFO36E1 --slice BRAM_R --type pins
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python3 fixup_timings_txt.py --txtin build/bel_properties.txt --txtout build/bel_properties.txt --site RAMBFIFO36E1 --slice BRAM_L --type properties
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python3 fixup_timings_txt.py --txtin build/bel_properties.txt --txtout build/bel_properties.txt --site RAMBFIFO36E1 --slice BRAM_R --type properties
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build/bel_timings.json: build/fixup_timings
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python3 tim2json.py --timings=build/bel_timings.txt --json=build/bel_timings.json --properties=build/bel_properties.txt --propertiesmap=properties_map.json --pinaliasmap=pin_alias_map.json --belpins=build/bel_pins.txt --sitepins=build/tile_pins.txt --debug true
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build/sdf: build/bel_timings.json
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python3 ${XRAY_UTILS_DIR}/makesdf.py --json=${PWD}/build/bel_timings.json --sdf=${PWD}/build
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@ -0,0 +1,45 @@
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# BEL timings fuzzer
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This fuzzer is suppose to extract all the BEL timings for Xilinx 7-series FPGAs.
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The extracted timings are saved as SDF files.
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Single SDF file is produced for every FPGA tile type.
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## Fuzzer flow
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Fuzzer flow is the following:
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Vivado/`runme.tcl` -> `fixup_timings_txt.py` -> `tim2json.py` -> `makesdf.py` -> `sdfmerge.py`
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The fuzzer uses Vivado tcl script to read all the FPGA timings data.
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This data is dumped to a text file.
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Beside timings data the tcl scipt dumps the following information:
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* Sites pins
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* BELs pins
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* BELs attributes
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The tcl script iterates over every BEL for all the sites in each tile type.
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The timings, pins and attributes are dumped in the same hierarchy.
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This hierarchy is used by the `tim2json` script to process the txt dump.
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Main task of the `tim2json` script is to figure out what the dumped timings mean and what paths do they describe.
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This is done by parsing the string timings, searching the BEL/Sites pins and BEL attributes.
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Since for some pins there was no naming convention, the names are provided directly via `pin_alias_map.json`.
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Some BELs (e.g. BRAMs) reports the timings with incorrect site name.
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To work around this issue the `fixup_timings_txt.py` script is used to flatten the timings dump file.
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As a result all the timings for a selected tile are squashed into one site.
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### Text files format
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The files dumped by the Vivado scrips have the following format:
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Each line starts with a tile name, proceeded by a number of sites in the tile.
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After the tiles count, each tile info is placed.
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The tile info starts with a tile name followed by number of BELs in the tile.
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The bels number is followed by BEL entries.
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Each BEL entry starts with BEL name followed by a number of entries.
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The entries differ between the file types:
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* timings file: each timing entry starts with entry name followed by 5 timings values
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* properties file: each properties entry starts with property name followed by a number of possible property values, followed by a list of the possible property values
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* pins file: each pin entry starts with pin name, followed by pin direction (IN/OUT), followed by 0 or 1 flag saying if the pin is a clock pin
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@ -0,0 +1,104 @@
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#!/usr/bin/env python3
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import argparse
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def fix_line(line, site, filetype):
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"""
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Squashes the entries for multiple sites into one.
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This is required when entries are defined for a different
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site than they are reported.
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Such situation happend e.g.
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for BRAM_[LR]. All the entries are defined for RAMBFIFO36E1,
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while they are reported for RAMB18E1 or FIFO18E1
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Parameters
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----------
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line: str
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raw dump file line
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site: str
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site to which all the entries will be squashed
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filetype: str
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entries type. One of [timings, pins, properties]
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Returns
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-------
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str
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line with squashed entries
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"""
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assert filetype in [
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"timings", "pins", "properties"
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], "Unsupported filetype"
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line = line.split()
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newline = list()
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sites_count = int(line[1])
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newline.append(line[0])
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# we'll emit only one site
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newline.append("1")
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newline.append(site)
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newline.append("1")
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newline.append(site)
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entries = list()
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all_entries = 0
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loc = 2
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for site in range(0, sites_count):
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bels_count = int(line[loc + 1])
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loc += 2
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for bel in range(0, bels_count):
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entries_count = int(line[loc + 1])
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loc += 2
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all_entries += entries_count
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for entry in range(0, entries_count):
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if filetype == 'timings':
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for delay_word in range(0, 6):
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entries.append(line[loc])
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loc += 1
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elif filetype == 'pins':
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for pin_word in range(0, 3):
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entries.append(line[loc])
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loc += 1
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elif filetype == 'properties':
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entries.append(line[loc])
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loc += 1
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values_count = int(line[loc])
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entries.append(line[loc])
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loc += 1
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for value in range(0, values_count):
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entries.append(line[loc])
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loc += 1
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newline.append(str(all_entries))
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newline.extend(entries)
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return " ".join(newline) + "\n"
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('--txtin', type=str, help='Input text file')
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parser.add_argument('--txtout', type=str, help='Output text file')
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parser.add_argument(
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'--site',
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type=str,
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help='Site to which the entries should be squashed')
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parser.add_argument(
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'--slice', type=str, help='Slice for which the entries shall be fixed')
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parser.add_argument(
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'--type', type=str, choices=['timings', 'pins', 'properties'])
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args = parser.parse_args()
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lines = list()
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with open(args.txtin, 'r') as fp:
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for line in fp:
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if line.startswith(args.slice):
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line = fix_line(line, args.site, args.type)
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lines.append(line)
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with open(args.txtout, 'w') as fp:
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for line in lines:
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fp.write(line)
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if __name__ == "__main__":
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main()
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@ -0,0 +1,60 @@
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{
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"ff_init": {
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"Q": {
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"names" : ["QL", "QH"],
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"is_property_related" : true
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}
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},
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"reg_init": {
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"Q": {
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"names" : ["QL", "QH"],
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"is_property_related" : true
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}
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},
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"rambfifo36e1" : {
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"RSTRAMARSTRAMLRST" : {
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"names" : ["rstramarstl"],
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"is_property_related" : false
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},
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"ADDRARDADDRU0" : {
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"names" : ["addrau"],
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"is_property_related" : false
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},
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"ADDRARDADDRL15" : {
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"names" : ["addra15l"],
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"is_property_related" : false
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},
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"RSTRAMARSTRAMU" : {
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"names" : ["rstramau"],
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"is_property_related" : false
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},
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"ADDRBWRADDRU0" : {
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"names" : ["addrbu"],
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"is_property_related" : false
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},
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"ADDRBWRADDRL15" : {
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"names" : ["addrb15l"],
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"is_property_related" : false
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},
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"WEBWEU0" : {
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"names" : ["webu"],
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"is_property_related" : false
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},
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"DOADO0" : {
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"names" : ["doadol", "doadou"],
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"is_property_related" : false
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},
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"DOBDO0" : {
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"names" : ["dobdol", "dobdou"],
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"is_property_related" : false
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},
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"DOPADOP0" : {
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"names" : ["dopadopl", "dopadopu"],
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"is_property_related" : false
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},
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"DOPBDOP0" : {
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"names" : ["dopbdopl", "dopbdopu"],
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"is_property_related" : false
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}
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}
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}
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@ -45,11 +45,120 @@ def clean_bname(bname):
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return bname
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def pin_in_model(pin, model, direction=None):
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def find_aliased_pin(pin, model, pin_aliases):
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"""
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Searches for aliased pins in the timing model.
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The check is done using data from pin_aliases dictionary.
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The dictionary has an entry for each aliased pin.
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Each entry has two fields:
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* names : a list of all the possible aliases
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* is_property_related: a flag saying if the alias is in fact
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pin name combined with BEL property (e.g. Q[LH] pins
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in FF - in this case the pin name is Q [original name],
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but is named Q[LH] in the timing model. The suffix
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determines polarity of the FF's set/reset input).
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If is_property_related is set the function returns the original
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pin name, aliased name is returned otherwise.
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Parameters
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----------
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pin: str
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Pin name to look for
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model: str
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Timing model
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pin_aliases: dict
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A dict of list of aliases for given bel/site
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Returns
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-------
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bool, str
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The first bool value is set to true if pin is found
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in the timing model, false otherwise.
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The second returned value is found pin name. If pin
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is not found None is returned
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>>> find_aliased_pin("a", "a_b_some_test_string", None)
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(False, None)
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>>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "is_property_related" : False}})
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(True, 'din')
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>>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "is_property_related" : True}})
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(True, 'd')
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>>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["notdin"], "is_property_related" : True}})
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(False, None)
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"""
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if (pin_aliases is not None) and (pin.upper() in pin_aliases):
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for alias in pin_aliases[pin.upper()]['names']:
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single_word_alias = (len(alias.split('_')) == 1)
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pin_alias = alias.lower()
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if single_word_alias:
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model_to_check = model.split('_')
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else:
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model_to_check = model
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if pin_alias in model_to_check:
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if pin_aliases[pin.upper()]['is_property_related']:
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return True, pin.lower()
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else:
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return True, pin_alias
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return False, None
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def pin_in_model(pin, pin_aliases, model, direction=None):
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"""
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Checks if a given pin belongs to the model.
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Parameters
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----------
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pin: str
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Pin name to look for
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pin_aliases: dict
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A dict of list of aliases for given bel/site
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model: str
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Timing model name
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direction: str
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Optional pin direction suffix [IN|OUT]
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Returns
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-------
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bool, str
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The first returned value is set to true if pin is found,
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false otherwise.
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The second returned value contains found pin name. If the
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pin is not found, None is returned.
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>>> pin_in_model("d", None, "ff_init_din_q", "in")
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(True, 'din')
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>>> pin_in_model("q", None, "ff_init_clk_q", None)
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(True, 'q')
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>>> pin_in_model("q", {"Q": {"names" : ["QL", "QH"], "is_property_related" : True}}, "ff_init_clk_ql", None)
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(True, 'q')
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>>> pin_in_model("logic_out", None, "my_cell_i_logic_out", None)
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(True, 'logic_out')
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>>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_logic_o", None)
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(True, 'logic_o')
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>>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_o", None)
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(True, 'o')
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"""
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# strip site location
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model = model.split(':')[0]
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extended_pin_name = pin
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aliased_pin, aliased_pin_name = find_aliased_pin(
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pin.upper(), model, pin_aliases)
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# some timings reports pins with their directions
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# this happens for e.g. CLB reg_init D pin, which
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@ -63,26 +172,62 @@ def pin_in_model(pin, model, direction=None):
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return True, pin
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elif extended_pin_name in model.split('_'):
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return True, extended_pin_name
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elif aliased_pin:
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return True, aliased_pin_name
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else:
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return False, None
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else:
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# pin name is multi word, search for a string
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return (pin in model), pin
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if pin in model:
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return True, pin
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elif aliased_pin:
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return True, aliased_pin_name
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else:
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return False, None
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def remove_pin_from_model(pin, model):
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"""
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Removes the pin from model name if present.
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Arguments
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---------
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|
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pin: str
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Pin name
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mode: str
|
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Timing model name
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Returns
|
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-------
|
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str
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Updated timing model name
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>>> remove_pin_from_model("q", "ff_init_d_q")
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'ff_init_d'
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>>> remove_pin_from_model("q", "ff_init_d_ql")
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'ff_init_d_ql'
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>>> remove_pin_from_model("logic_out", "ff_init_d_logic_out")
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'ff_init_d'
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>>> remove_pin_from_model("logic_out", "ff_init_d_second_out")
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'ff_init_d_second_out'
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"""
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|
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if len(pin.split('_')) == 1:
|
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# pin name is one word, search it in the model
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tmp = model.split('_')
|
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tmp.remove(pin)
|
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return "_".join(tmp)
|
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if pin in tmp:
|
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tmp.remove(pin)
|
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return "_".join(tmp)
|
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else:
|
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return model
|
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else:
|
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# pin name is multi word, search for a string
|
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return "_".join(list(filter(None, model.replace(pin, '').split('_'))))
|
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|
||||
|
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def read_raw_timings(fin, properties, pins, site_pins):
|
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def read_raw_timings(fin, properties, pins, site_pins, pin_alias_map):
|
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|
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timings = dict()
|
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with open(fin, "r") as f:
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|
|
@ -150,15 +295,21 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
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if speed_model.startswith(delay_btype):
|
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speed_model_clean = speed_model[len(delay_btype):]
|
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|
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# Get pin alias map
|
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pin_aliases = pin_alias_map.get(delay_btype, None)
|
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|
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# locate pins
|
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for pin in pins[slice][site_name][delay_btype_orig]:
|
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orig_pin = pin
|
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pim, pin = pin_in_model(
|
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pin.lower(), speed_model_clean, 'in')
|
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pin.lower(), pin_aliases, speed_model_clean,
|
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'in')
|
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|
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if pim:
|
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if pins[slice][site_name][delay_btype_orig][
|
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orig_pin]['is_clock']:
|
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bel_clock = pin
|
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bel_clock_orig_pin = orig_pin
|
||||
elif pins[slice][site_name][delay_btype_orig][
|
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orig_pin]['direction'] == 'IN':
|
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bel_input = pin
|
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|
|
@ -168,11 +319,13 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
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speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
# Some speed models describe delays from/to site pins instead of BEL pins
|
||||
if bel_clock is None:
|
||||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
pin.lower(), pin_aliases,
|
||||
speed_model_clean)
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['is_clock']:
|
||||
|
|
@ -181,13 +334,13 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
|||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
# Some speed models describe delays from/to site pins instead of BEL pins
|
||||
if bel_input is None:
|
||||
# search site inputs
|
||||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(
|
||||
pin.lower(), speed_model_clean, 'in')
|
||||
pin.lower(), pin_aliases,
|
||||
speed_model_clean, 'in')
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['direction'] == 'IN':
|
||||
|
|
@ -199,7 +352,8 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
|||
for pin in site_pins[slice][site_name.lower()]:
|
||||
orig_pin = pin
|
||||
pim, pin = pin_in_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
pin.lower(), pin_aliases,
|
||||
speed_model_clean)
|
||||
if pim:
|
||||
if site_pins[slice][site_name.lower(
|
||||
)][orig_pin]['direction'] == 'OUT':
|
||||
|
|
@ -207,6 +361,15 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
|||
speed_model_clean = remove_pin_from_model(
|
||||
pin.lower(), speed_model_clean)
|
||||
|
||||
# if we couldn't find input, check if the clock is the
|
||||
# only input. This applies only to combinational paths
|
||||
if (sequential is None) and (bel_input is None) and (
|
||||
bel_clock is not None):
|
||||
if bel_clock_orig_pin in site_pins[slice][site_name.lower()] and \
|
||||
site_pins[slice][site_name.lower(
|
||||
)][bel_clock_orig_pin]['direction'] == 'IN':
|
||||
bel_input = bel_clock
|
||||
|
||||
# check if the input is not a BEL property
|
||||
if bel_input is None:
|
||||
# if there is anything not yet decoded
|
||||
|
|
@ -218,38 +381,38 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
|||
speed_model_clean = remove_pin_from_model(
|
||||
prop.lower(), speed_model_clean)
|
||||
break
|
||||
# if we couldn't find input, check if the clock is the
|
||||
# only input
|
||||
if bel_input is None and (bel_clock is not None):
|
||||
if bel_clock_orig_pin in site_pins[slice][site_name.lower()] and \
|
||||
site_pins[slice][site_name.lower(
|
||||
)][bel_clock_orig_pin]['direction'] == 'IN':
|
||||
bel_input = bel_clock
|
||||
|
||||
# if we still don't have the input check if the input
|
||||
# is wider than 1 bit and timing defined for the whole
|
||||
# port
|
||||
import re
|
||||
if bel_input is None:
|
||||
if (bel_input is None) or (bel_output is None):
|
||||
for pin in pins[slice][site_name][
|
||||
delay_btype_orig]:
|
||||
number = re.search(r'\d+$', pin)
|
||||
if number is not None:
|
||||
orig_pin = pin[:-(
|
||||
len(str(number.group())))]
|
||||
orig_pin_full = pin
|
||||
pim, pin = pin_in_model(
|
||||
orig_pin.lower(), speed_model_clean)
|
||||
orig_pin.lower(), pin_aliases,
|
||||
speed_model_clean)
|
||||
if not pim:
|
||||
# some inputs pins are named with unsignificant zeros
|
||||
# remove ti and try again
|
||||
orig_pin = orig_pin + str(
|
||||
int(number.group()))
|
||||
pim, pin = pin_in_model(
|
||||
orig_pin.lower(),
|
||||
orig_pin.lower(), pin_aliases,
|
||||
speed_model_clean)
|
||||
|
||||
if pim:
|
||||
bel_input = pin
|
||||
if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'IN' \
|
||||
and bel_input is None:
|
||||
bel_input = pin
|
||||
if pins[slice][site_name][delay_btype_orig][orig_pin_full]['direction'] == 'OUT' \
|
||||
and bel_output is None:
|
||||
bel_output = pin
|
||||
speed_model_clean = remove_pin_from_model(
|
||||
orig_pin.lower(),
|
||||
speed_model_clean)
|
||||
|
|
@ -263,7 +426,8 @@ def read_raw_timings(fin, properties, pins, site_pins):
|
|||
speed_model = delay_btype + speed_model_clean
|
||||
|
||||
if sequential is not None:
|
||||
if bel_output is None and bel_clock is None:
|
||||
if bel_output is None and bel_clock is None or \
|
||||
bel_output is None and bel_clock == bel_input:
|
||||
delay_loc += 6
|
||||
continue
|
||||
else:
|
||||
|
|
@ -439,11 +603,16 @@ def main():
|
|||
'--debug', type=bool, default=False, help='Enable debug json dumps')
|
||||
parser.add_argument(
|
||||
'--propertiesmap', type=str, help='Properties names mappings')
|
||||
parser.add_argument(
|
||||
'--pinaliasmap', type=str, help='Pin name alias mappings')
|
||||
args = parser.parse_args()
|
||||
|
||||
with open(args.propertiesmap, 'r') as fp:
|
||||
properties_map = json.load(fp)
|
||||
|
||||
with open(args.pinaliasmap, 'r') as fp:
|
||||
pin_alias_map = json.load(fp)
|
||||
|
||||
properties = read_bel_properties(args.properties, properties_map)
|
||||
|
||||
if args.debug:
|
||||
|
|
@ -460,7 +629,8 @@ def main():
|
|||
with open('debug_site_pins.json', 'w') as fp:
|
||||
json.dump(site_pins, fp, indent=4, sort_keys=True)
|
||||
|
||||
timings = read_raw_timings(args.timings, properties, pins, site_pins)
|
||||
timings = read_raw_timings(
|
||||
args.timings, properties, pins, site_pins, pin_alias_map)
|
||||
with open(args.json, 'w') as fp:
|
||||
json.dump(timings, fp, indent=4, sort_keys=True)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue