Merge pull request #286 from mcmasterg/tcl_reformat

Tcl reformat

Makefile

@@ -19,6 +19,7 @@ format:
 	find . -name \*.cc -and -not -path './third_party/*' -and -not -path './.git/*' -exec $(CLANG_FORMAT) -style=file -i {} \;
 	find . -name \*.h -and -not -path './third_party/*' -and -not -path './.git/*' -exec $(CLANG_FORMAT) -style=file -i {} \;
 	find . -name \*.py -and -not -path './third_party/*' -and -not -path './.git/*' -exec yapf -p -i {} \;
+	find . -name \*.tcl -and -not -path './third_party/*' -and -not -path './.git/*' -exec ${XRAY_TCL_REFORMAT} {} \; 2>/dev/null
 
 clean:
 	$(MAKE) -C database clean

experiments/clbpips/generate.tcl

@@ -40,4 +40,3 @@ proc write_txtdata {filename} {
 
 write_bitstream -force design.bit
 write_txtdata design.txt
-

experiments/gndvcc/generate.tcl

@@ -84,4 +84,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

experiments/gndvcc/piplist.tcl

@@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
 
 print_tile_pips INT_L pips_int_l.txt
 print_tile_pips INT_R pips_int_r.txt
-

experiments/pipsroute/generate.tcl

@@ -80,4 +80,3 @@ for {set i 100} {$i < 200} {incr i} {
     write_bitstream -quiet -force design_$i.bit
     write_txtdata design_$i.txt
 }
-

experiments/pipsroute/piplist.tcl

@@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
 
 print_tile_pips INT_L pips_int_l.txt
 print_tile_pips INT_R pips_int_r.txt
-

fuzzers/005-tilegrid/generate_bram.tcl

@@ -53,4 +53,3 @@ proc run {} {
 }
 
 run
-

fuzzers/005-tilegrid/generate_clb.tcl

@@ -59,4 +59,3 @@ proc run {} {
 }
 
 run
-

fuzzers/005-tilegrid/generate_iob.tcl

@@ -40,4 +40,3 @@ proc run {} {
 }
 
 run
-

fuzzers/005-tilegrid/generate_tiles.tcl

@@ -38,4 +38,3 @@ proc run {} {
 }
 
 run
-

fuzzers/005-tilegrid/util.tcl

@@ -167,4 +167,3 @@ proc make_project_roi { roi_var } {
 
     set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 }
-

fuzzers/007-timing/minitest/test_cell_opins.tcl

@@ -27,4 +27,3 @@ set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
 puts "Took ms: $TIME_taken"
 puts "Result: $opins_zero / $nnets zero"
 puts "Result: $opins_multi / $nnets multi"
-

fuzzers/007-timing/minitest/test_unique/generate.tcl

@@ -93,4 +93,3 @@ proc wires_all {} {
 build_design
 pips_all
 wires_all
-

fuzzers/007-timing/projects/oneblinkw/generate.tcl

@@ -43,4 +43,3 @@ proc build_design {} {
 
 build_design
 write_info4
-

fuzzers/007-timing/projects/picorv32/generate.tcl

@@ -44,4 +44,3 @@ proc build_design {} {
 
 build_design
 write_info4
-

fuzzers/007-timing/projects/placelut/generate.tcl

@@ -43,4 +43,3 @@ proc build_design {} {
 
 build_design
 write_info4
-

fuzzers/007-timing/projects/placelut_fb/generate.tcl

@@ -43,4 +43,3 @@ proc build_design {} {
 
 build_design
 write_info4
-

fuzzers/007-timing/projects/placelut_ff_fb/generate.tcl

@@ -43,4 +43,3 @@ proc build_design {} {
 
 build_design
 write_info4
-

fuzzers/007-timing/projects/project.tcl

@@ -219,4 +219,3 @@ proc write_info4 {} {
 # for debugging
 # source ../project.tcl
 # write_info4
-

fuzzers/007-timing/speed/generate.tcl

@@ -170,4 +170,3 @@ proc nodes_unique_cc {} {
 build_design_full
 speed_models2
 nodes_unique_cc
-

fuzzers/007-timing/timgrid/generate.tcl

@@ -116,4 +116,3 @@ proc write_data {} {
 
 build_project
 write_data
-

fuzzers/010-lutinit/generate.tcl

@@ -87,4 +87,3 @@ foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
 
 write_bitstream -force design_2.bit
 write_txtdata design_2.txt
-

fuzzers/011-ffconfig/generate.tcl

@@ -62,4 +62,3 @@ foreach ff $ffs {
     puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
 }
 close $fp
-

fuzzers/012-clbn5ffmux/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/013-clbncy0/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/014-ffsrcemux/generate.tcl

@@ -56,4 +56,3 @@ foreach ff $ffs {
     puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
 }
 close $fp
-

fuzzers/015-clbnffmux/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/016-clbnoutmux/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/017-clbprecyinit/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/018-clbram/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/019-ndi1mux/generate.tcl

@@ -24,4 +24,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/025-bram-config/generate.tcl

@@ -23,4 +23,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/025-bram-config/minitest/runme.tcl

@@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
 # BRAM SDP WEA check, to make test slightly easier to write
 set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
 write_bitstream -force design.bit
-

fuzzers/026-bram-data/generate.tcl

@@ -22,4 +22,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/026-bram-data/minitest/runme.tcl

@@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
 # BRAM SDP WEA check, to make test slightly easier to write
 set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
 write_bitstream -force design.bit
-

fuzzers/050-intpips/generate.tcl

@@ -47,4 +47,3 @@ proc write_txtdata {filename} {
 
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/051-imuxlout/generate.tcl

@@ -88,4 +88,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/052-clkin/generate.tcl

@@ -84,4 +84,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/053-ctrlin/generate.tcl

@@ -84,4 +84,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/054-gfan/generate.tcl

@@ -94,4 +94,3 @@ proc run {} {
 }
 
 run
-

fuzzers/055-gnd/generate.tcl

@@ -85,4 +85,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/056-rempips/generate.tcl

@@ -84,4 +84,3 @@ route_design
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
 write_txtdata design.txt
-

fuzzers/057-bipips/bipiplist.tcl

@@ -37,4 +37,3 @@ proc print_tile_pips {tile_type filename} {
 
 print_tile_pips INT_L bipips_int_l.txt
 print_tile_pips INT_R bipips_int_r.txt
-

fuzzers/057-bipips/generate.tcl

@@ -76,4 +76,3 @@ close $fp
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

fuzzers/058-hclkpips/generate.tcl

@@ -40,4 +40,3 @@ for {set i 0} {$i < [llength $pips]} {incr i} {
     puts $fp "$tile $pip"
     close $fp
 }
-

fuzzers/071-ppips/generate.tcl

@@ -67,4 +67,3 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R INT_L INT_R} {
         write_clb_ppips_db "ppips_[string tolower $tile_type].txt" $tile
     }
 }
-

fuzzers/100-dsp-mskpat/generate.tcl

@@ -68,4 +68,3 @@ for {set i 10} {$i < 30} {incr i} {
     write_bitstream -force design_${i}.bit
     write_txtdata design_${i}.txt
 }
-

fuzzers/piplist.tcl

@@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
 
 print_tile_pips INT_L pips_int_l.txt
 print_tile_pips INT_R pips_int_r.txt
-

gridinfo/logicframes.tcl

@@ -14,4 +14,3 @@ foreach site $sites {
     set_property INIT 64'h8000000000000001 [get_cells lut]
     write_bitstream -force logicframes_${site}_1.bit
 }
-

gridinfo/tiledata.tcl

@@ -13,4 +13,3 @@ foreach site [get_sites] {
         puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]"
     }
 }
-

minitests/carry_cin_cyinit/runme.tcl

@@ -19,4 +19,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

minitests/clbconfigs/runme.tcl

@@ -23,4 +23,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

minitests/clkbuf/runme.tcl

@@ -50,4 +50,3 @@ foreach it {
     write_checkpoint -force design_$id.dcp
     write_bitstream -force design_$id.bit
 }
-

minitests/eccbits/runme.tcl

@@ -47,4 +47,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

minitests/fixedpnr/runme.tcl

@@ -43,4 +43,3 @@ foreach variant {fdse fdce fdce_inv fdpe ldce ldpe} {
 
     close_project
 }
-

minitests/iob/DRIVE.tcl

@@ -6,4 +6,3 @@ source "$::env(SRC_DIR)/template.tcl"
 set prop DRIVE
 set port [get_ports do]
 source "$::env(SRC_DIR)/sweep.tcl"
-

minitests/iob/IOSTANDARD.tcl

@@ -3,4 +3,3 @@ source "$::env(SRC_DIR)/template.tcl"
 set prop IOSTANDARD
 set port [get_ports do]
 source "$::env(SRC_DIR)/sweep.tcl"
-

minitests/iob/PULLTYPE.tcl

@@ -12,4 +12,3 @@ foreach {val} $vals {
     write_checkpoint -force design_$val.dcp
     write_bitstream -force design_$val.bit
 }
-

minitests/iob/SLEW.tcl

@@ -5,4 +5,3 @@ source "$::env(SRC_DIR)/template.tcl"
 set prop SLEW
 set port [get_ports do]
 source "$::env(SRC_DIR)/sweep.tcl"
-

minitests/iob/runme.tcl

@@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
 
 # set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
 write_bitstream -force design.bit
-

minitests/iob/sweep.tcl

@@ -19,4 +19,3 @@ foreach {val} $vals {
     # Only write checkpoints for acceptable bitstreams
     write_checkpoint -force design_$val.dcp
 }
-

minitests/iob/template.tcl

@@ -23,4 +23,3 @@ write_checkpoint -force design.dcp
 # set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
 # set_property PULLTYPE PULLUP $port
 # set_property PULLTYPE PULLDOWN $port
-

minitests/lvb_long_mux/runme.tcl

@@ -62,4 +62,3 @@ route_via o_OBUF {
 route_design
 write_checkpoint -force design_b.dcp
 write_bitstream -force design_b.bit
-

minitests/nodes_wires_list/runme.tcl

@@ -27,4 +27,3 @@ foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] {
     if {$wires != $node} {puts $fp $wires}
 }
 close $fp
-

minitests/partial_reconfig_flow/roi_synthesize.tcl

@@ -1,4 +1,3 @@
 read_verilog [lindex $argv 0]
 synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
 write_checkpoint -force [lindex $argv 1]
-

minitests/picorv32-v/runme.tcl

@@ -23,4 +23,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

minitests/picorv32-y/runme.tcl

@@ -29,4 +29,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

minitests/roi_harness/runme.tcl

@@ -482,4 +482,3 @@ if {$fixed_xdc eq ""} {
 write_checkpoint -force design.dcp
 #set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
 write_bitstream -force design.bit
-

minitests/switchboxes/pips.tcl

@@ -60,4 +60,3 @@ proc tile_pip_report {fd tile_name} {
 
 tile_pip_report [open "pips_clbll.txt" w] CLBLL_L_X12Y119
 tile_pip_report [open   "pips_int.txt" w]   INT_L_X12Y119
-

minitests/switchboxes/routes.tcl

@@ -10,4 +10,3 @@ route_design
 
 write_checkpoint -force routes.dcp
 write_bitstream -force routes.bit
-

minitests/switchboxes/runme.tcl

@@ -23,4 +23,3 @@ write_bitstream -force design.bit
 source ../../utils/utils.tcl
 source pips.tcl
 source routes.tcl
-

minitests/tiles_wires_pips/runme.tcl

@@ -38,4 +38,3 @@ proc print_tile_info {tile} {
 foreach tile [lsort [get_tiles]] {
     print_tile_info $tile
 }
-

minitests/util/runme.tcl

@@ -22,4 +22,3 @@ route_design
 
 write_checkpoint -force design.dcp
 write_bitstream -force design.bit
-

third_party/reformat.tcl

@@ -0,0 +1,108 @@
+#!/usr/bin/env tclsh
+# From: https://gist.github.com/yyamasak/af250f7ca74e18526734#file-reformat-tcl-L10
+# Which is based on https://wiki.tcl-lang.org/page/Reformatting+Tcl+code+indentation
+# See for licensing
+
+proc reformat {tclcode {pad 4}} {
+    set lines [split $tclcode \n]
+    set out ""
+    set continued no
+    set oddquotes 0
+    set line [lindex $lines 0]
+    set indent [expr {([string length $line]-[string length [string trimleft $line \ \t]])/$pad}]
+    set pad [string repeat " " $pad]
+
+    foreach orig $lines {
+        set newline [string trim $orig \ \t]
+        set line [string repeat $pad $indent]$newline
+        if {[string index $line end] eq "\\"} {
+            if {!$continued} {
+                incr indent 2
+                set continued yes
+            }
+        } elseif {$continued} {
+            incr indent -2
+            set continued no
+        }
+
+        if { ! [regexp {^[ \t]*\#} $line] } {
+
+            # oddquotes contains : 0 when quotes are balanced
+            # and 1 when they are not
+            set oddquotes [expr {([count $line \"] + $oddquotes) % 2}]
+            if {! $oddquotes} {
+                set  nbbraces  [count $line \{]
+                incr nbbraces -[count $line \}]
+                set brace   [string equal [string index $newline end] \{]
+                set unbrace [string equal [string index $newline 0] \}]
+                if {$nbbraces!=0 || $brace || $unbrace} {
+                    incr indent $nbbraces ;# [GWM] 010409 multiple close braces
+                    if {$indent<0} {
+                        error "unbalanced braces"
+                    }
+                    puts $unbrace
+                    puts $pad
+                    puts $nbbraces
+                    set np [expr {$unbrace? [string length $pad]:-$nbbraces*[string length $pad]}]
+                    set line [string range $line $np end]
+                }
+            } else {
+                # unbalanced quotes, preserve original indentation
+                set line $orig
+            }
+        }
+        append out $line\n
+    }
+    return $out
+}
+
+proc eol {} {
+    switch -- $::tcl_platform(platform) {
+        windows {return \r\n}
+        unix {return \n}
+        macintosh {return \r}
+        default {error "no such platform: $::tc_platform(platform)"}
+    }
+}
+
+proc count {string char} {
+    set count 0
+    while {[set idx [string first $char $string]]>=0} {
+        set backslashes 0
+        set nidx $idx
+        while {[string equal [string index $string [incr nidx -1]] \\]} {
+            incr backslashes
+        }
+        if {$backslashes % 2 == 0} {
+            incr count
+        }
+        set string [string range $string [incr idx] end]
+    }
+    return $count
+}
+
+set usage "reformat.tcl ?-indent number? filename"
+
+if {[llength $argv]!=0} {
+    if {[lindex $argv 0] eq "-indent"} {
+        set indent [lindex $argv 1]
+        set argv [lrange $argv 2 end]
+    } else  {
+        set indent 4
+    }
+    if {[llength $argv]>1} {
+        error $usage
+    }
+    set f [open $argv r]
+    set data [read $f]
+    close $f
+
+    set filename "$argv.tmp"
+    set f [open $filename  w]
+
+    puts -nonewline $f [reformat [string map [list [eol] \n] $data] $indent]
+    close $f
+    file copy -force $filename  $argv
+    file delete -force $filename
+
+}

utils/environment.sh

@@ -28,4 +28,6 @@ export XRAY_FASM2FRAMES="python3 ${XRAY_UTILS_DIR}/fasm2frames.py"
 export XRAY_BITTOOL="${XRAY_TOOLS_DIR}/bittool"
 export XRAY_BLOCKWIDTH="python3 ${XRAY_UTILS_DIR}/blockwidth.py"
 export XRAY_PARSEDB="python3 ${XRAY_UTILS_DIR}/parsedb.py"
+export XRAY_REFORMAT_TCL="${XRAY_DIR}/third_party/reformat.tcl"
+export XRAY_TCL_REFORMAT="${XRAY_UTILS_DIR}/tcl-reformat.sh"
 

utils/tcl-reformat.sh

@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+# Wrapper to clean up newlines
+# We could do this in tcl...but tcl
+
+fn=$1
+
+$XRAY_REFORMAT_TCL $fn >/dev/null
+# Always puts a newline at the end, even if there was one before
+# remove duplicates, but keep at least one
+printf "%s\n" "$(< $fn)" >$fn.tmp
+mv $fn.tmp $fn
+
+# Remove trailing spaces
+sed -i 's/[ \t]*$//' "$fn"
+

utils/utils.tcl

@@ -106,4 +106,3 @@ proc lintersect {lst1 lst2} {
 proc putl {lst} {
     foreach line $lst {puts $line}
 }
-