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FORMAT - Whitespace Fixes 

CI is failing due to this.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
This commit is contained in:
Jake Mercer 2019-11-02 11:45:43 +00:00
parent 6a3db24da1
commit 0a79eb6753
2 changed files with 8 additions and 8 deletions
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8
minitests/litex_litedram/src.vivado/verilog/VexRiscv.v
View File

@ -2523,7 +2523,7 @@ module VexRiscv (
end end
end end
InstructionCache IBusCachedPlugin_cache ( InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_221_), .io_flush(_zz_221_),
.io_cpu_prefetch_isValid(_zz_222_), .io_cpu_prefetch_isValid(_zz_222_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
@ -2569,9 +2569,9 @@ module VexRiscv (
.io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error), .io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk), .clk(clk),
.reset(reset) .reset(reset)
); );
DataCache dataCache_1_ ( DataCache dataCache_1_ (
.io_cpu_execute_isValid(_zz_230_), .io_cpu_execute_isValid(_zz_230_),
.io_cpu_execute_address(_zz_231_), .io_cpu_execute_address(_zz_231_),
.io_cpu_execute_args_wr(execute_MEMORY_WR), .io_cpu_execute_args_wr(execute_MEMORY_WR),
@ -2619,7 +2619,7 @@ module VexRiscv (
.io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_data(dBus_rsp_payload_data),
.io_mem_rsp_payload_error(dBus_rsp_payload_error), .io_mem_rsp_payload_error(dBus_rsp_payload_error),
.clk(clk), .clk(clk),
.reset(reset) .reset(reset)
); );
always @(*) begin always @(*) begin
case(_zz_371_) case(_zz_371_)

8
minitests/litex_litedram/src.yosys/verilog/VexRiscv.v
View File

@ -2523,7 +2523,7 @@ module VexRiscv (
end end
end end
InstructionCache IBusCachedPlugin_cache ( InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_221_), .io_flush(_zz_221_),
.io_cpu_prefetch_isValid(_zz_222_), .io_cpu_prefetch_isValid(_zz_222_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
@ -2569,9 +2569,9 @@ module VexRiscv (
.io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error), .io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk), .clk(clk),
.reset(reset) .reset(reset)
); );
DataCache dataCache_1_ ( DataCache dataCache_1_ (
.io_cpu_execute_isValid(_zz_230_), .io_cpu_execute_isValid(_zz_230_),
.io_cpu_execute_address(_zz_231_), .io_cpu_execute_address(_zz_231_),
.io_cpu_execute_args_wr(execute_MEMORY_WR), .io_cpu_execute_args_wr(execute_MEMORY_WR),
@ -2619,7 +2619,7 @@ module VexRiscv (
.io_mem_rsp_payload_data(dBus_rsp_payload_data), .io_mem_rsp_payload_data(dBus_rsp_payload_data),
.io_mem_rsp_payload_error(dBus_rsp_payload_error), .io_mem_rsp_payload_error(dBus_rsp_payload_error),
.clk(clk), .clk(clk),
.reset(reset) .reset(reset)
); );
always @(*) begin always @(*) begin
case(_zz_371_) case(_zz_371_)