Simplify BRAM data fuzzer and rename to match RAMB18E1 parameter names.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/025-bram-config/generate.py

@@ -65,7 +65,7 @@ def bus_tags(segmk, ps, site):
             # Magic bit positions from experimentation
             # we could just only solve when parity, but this check documents the fine points a bit better
             if hasparity or i not in (1, 9):
-                segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
+                segmk.add_site_tag(site, '%s[%u]' % (tagname, i), 1 ^ bitstr[i])
 
 
 def rw_width_tags(segmk, ps, site):

fuzzers/026-bram-data/generate.py

@@ -1,29 +1,49 @@
 #!/usr/bin/env python3
 
-import sys, re, os
+import json
-
 from prjxray.segmaker import Segmaker
 
-c2i = {'0': 0, '1': 1}
+BITS_PER_PARAM = 256
+NUM_INITP_PARAMS = 8
+NUM_INIT_PARAMS = 0x40
+BITS_PER_SITE = BITS_PER_PARAM * (NUM_INITP_PARAMS + NUM_INIT_PARAMS)
 
-segmk = Segmaker("design.bits")
-segmk.set_def_bt('BLOCK_RAM')
 
-print("Loading tags")
+def main():
-'''
+    segmk = Segmaker("design.bits")
-'''
+    segmk.set_def_bt('BLOCK_RAM')
-f = open('params.csv', 'r')
-f.readline()
-for l in f:
-    l = l.strip()
-    module, loc, pdata, data = l.split(',')
 
-    for i, d in enumerate(pdata):
+    print("Loading tags")
-        # Keep dec convention used on LUT?
+    '''
-        segmk.add_site_tag(loc, "INITP[%04d]" % i, c2i[d])
+    '''
-    for i, d in enumerate(data):
-        # Keep dec convention used on LUT?
-        segmk.add_site_tag(loc, "INIT[%04d]" % i, c2i[d])
 
-segmk.compile()
+    with open('params.json') as f:
-segmk.write()
+        params = json.load(f)
+
+    for param in params:
+        for initp in range(NUM_INITP_PARAMS):
+            p = 'INITP_{:02X}'.format(initp)
+            val = param[p]
+            for bit in range(BITS_PER_PARAM):
+                segmk.add_site_tag(
+                    param['site'], "{p}[{bit:03d}]".format(
+                        p=p,
+                        bit=bit,
+                    ), val & (1 << bit) != 0)
+
+        for init in range(NUM_INIT_PARAMS):
+            p = 'INIT_{:02X}'.format(init)
+            val = param[p]
+            for bit in range(BITS_PER_PARAM):
+                segmk.add_site_tag(
+                    param['site'], "{p}[{bit:03d}]".format(
+                        p=p,
+                        bit=bit,
+                    ), val & (1 << bit) != 0)
+
+    segmk.compile()
+    segmk.write()
+
+
+if __name__ == "__main__":
+    main()

fuzzers/026-bram-data/generate.tcl

@@ -2,21 +2,10 @@ create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
 
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
-
-create_pblock roi
-add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
-
 set_property CFGBVS VCCO [current_design]
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
-
 place_design
 route_design
 

fuzzers/026-bram-data/top.py

@@ -1,136 +1,69 @@
 #!/usr/bin/env python
 
 import os
+import json
 import random
 random.seed(int(os.getenv("SEED"), 16))
 from prjxray import util
-from prjxray import verilog
-import sys
 
 
-def gen_bram36():
+def gen_sites():
-    for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
+    for tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
-        ['RAMBFIFO36E1']):
+        ['RAMB18E1', 'FIFO18E1'])):
-        yield site_name
+        yield tile_name, site_name
 
 
-DUTN = len(list(gen_bram36()))
+BITS_PER_PARAM = 256
-DIN_N = DUTN * 8
+NUM_INITP_PARAMS = 8
-DOUT_N = DUTN * 8
+NUM_INIT_PARAMS = 0x40
-
+BITS_PER_SITE = BITS_PER_PARAM * (NUM_INITP_PARAMS + NUM_INIT_PARAMS)
-verilog.top_harness(DIN_N, DOUT_N)
-
-f = open('params.csv', 'w')
-f.write('module,loc,pdata,data\n')
-print(
-    'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
-    (DIN_N - 1, DOUT_N - 1))
 
 
-def randbits(n):
+def main():
-    return ''.join([random.choice(('0', '1')) for _x in range(n)])
+    print("module top();")
 
+    list_of_params = []
+    for tile_name, site in gen_sites():
+        params = {}
+        params['tile'] = tile_name
+        params['site'] = site
 
-def make(module, gen_locs, pdatan, datan):
+        p = []
-    loci = 0
+        for initp_idx in range(NUM_INITP_PARAMS):
+            param = 'INITP_{:02X}'.format(initp_idx)
+            params[param] = random.randint(0, 2**BITS_PER_PARAM - 1)
+            p.append(
+                ".{param}(256'h{val:x})".format(
+                    param=param, val=params[param]))
 
-    for loci, loc in enumerate(gen_locs()):
+        for init_idx in range(NUM_INIT_PARAMS):
-        if loci >= DUTN:
+            param = 'INIT_{:02X}'.format(init_idx)
-            break
+            params[param] = random.randint(0, 2**BITS_PER_PARAM - 1)
+            p.append(
+                ".{param}(256'h{val:x})".format(
+                    param=param, val=params[param]))
 
-        pdata = randbits(pdatan * 0x100)
+        params['params'] = ','.join(p)
-        data = randbits(datan * 0x100)
 
-        print('    %s #(' % module)
-        for i in range(pdatan):
-            print(
-                "        .INITP_%02X(256'b%s)," %
-                (i, pdata[i * 256:(i + 1) * 256]))
-        for i in range(datan):
-            print(
-                "        .INIT_%02X(256'b%s)," %
-                (i, data[i * 256:(i + 1) * 256]))
-        print('        .LOC("%s"))' % (loc, ))
         print(
-            '            inst_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));'
+            """
-            % (loci, 8 * loci, 8 * loci))
+    (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+    RAMB18E1 #(
+        .READ_WIDTH_A(1),
+        .READ_WIDTH_B(1),
+        .RAM_MODE("TDP"),
+        {params}
+        ) bram_{site} (
+        );
+        """.format(**params))
 
-        f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
+        list_of_params.append(params)
-        print('')
+
-        loci += 1
+    print("endmodule")
-    assert loci == DUTN
+
+    with open('params.json', 'w') as f:
+        json.dump(list_of_params, f, indent=2)
 
 
-make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
+if __name__ == "__main__":
-
+    main()
-f.close()
-print(
-    '''endmodule
-
-// ---------------------------------------------------------------------
-
-''')
-
-print(
-    '''
-module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
-    parameter LOC = "";
-    ''')
-for i in range(16):
-    print(
-        "    parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
-        % i)
-print('')
-for i in range(0x80):
-    print(
-        "    parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
-        % i)
-print('')
-print('''\
-    (* LOC=LOC *)
-    RAMB36E1 #(''')
-for i in range(16):
-    print('            .INITP_%02X(INITP_%02X),' % (i, i))
-print('')
-for i in range(0x80):
-    print('            .INIT_%02X(INIT_%02X),' % (i, i))
-print('')
-print(
-    '''
-            .IS_CLKARDCLK_INVERTED(1'b0),
-            .IS_CLKBWRCLK_INVERTED(1'b0),
-            .IS_ENARDEN_INVERTED(1'b0),
-            .IS_ENBWREN_INVERTED(1'b0),
-            .IS_RSTRAMARSTRAM_INVERTED(1'b0),
-            .IS_RSTRAMB_INVERTED(1'b0),
-            .IS_RSTREGARSTREG_INVERTED(1'b0),
-            .IS_RSTREGB_INVERTED(1'b0),
-            .RAM_MODE("TDP"),
-            .WRITE_MODE_A("WRITE_FIRST"),
-            .WRITE_MODE_B("WRITE_FIRST"),
-            .SIM_DEVICE("VIRTEX6")
-        ) ram (
-            .CLKARDCLK(din[0]),
-            .CLKBWRCLK(din[1]),
-            .ENARDEN(din[2]),
-            .ENBWREN(din[3]),
-            .REGCEAREGCE(din[4]),
-            .REGCEB(din[5]),
-            .RSTRAMARSTRAM(din[6]),
-            .RSTRAMB(din[7]),
-            .RSTREGARSTREG(din[0]),
-            .RSTREGB(din[1]),
-            .ADDRARDADDR(din[2]),
-            .ADDRBWRADDR(din[3]),
-            .DIADI(din[4]),
-            .DIBDI(din[5]),
-            .DIPADIP(din[6]),
-            .DIPBDIP(din[7]),
-            .WEA(din[0]),
-            .WEBWE(din[1]),
-            .DOADO(dout[0]),
-            .DOBDO(dout[1]),
-            .DOPADOP(dout[2]),
-            .DOPBDOP(dout[3]));
-endmodule
-''')