mirror of https://github.com/openXC7/prjxray.git
Simplify BRAM data fuzzer and rename to match RAMB18E1 parameter names.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
parent
9832078689
commit
0595663bb1
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@ -65,7 +65,7 @@ def bus_tags(segmk, ps, site):
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# Magic bit positions from experimentation
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# we could just only solve when parity, but this check documents the fine points a bit better
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if hasparity or i not in (1, 9):
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segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i])
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segmk.add_site_tag(site, '%s[%u]' % (tagname, i), 1 ^ bitstr[i])
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def rw_width_tags(segmk, ps, site):
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@ -1,29 +1,49 @@
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#!/usr/bin/env python3
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import sys, re, os
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import json
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from prjxray.segmaker import Segmaker
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c2i = {'0': 0, '1': 1}
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BITS_PER_PARAM = 256
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NUM_INITP_PARAMS = 8
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NUM_INIT_PARAMS = 0x40
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BITS_PER_SITE = BITS_PER_PARAM * (NUM_INITP_PARAMS + NUM_INIT_PARAMS)
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segmk = Segmaker("design.bits")
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segmk.set_def_bt('BLOCK_RAM')
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print("Loading tags")
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'''
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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l = l.strip()
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module, loc, pdata, data = l.split(',')
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def main():
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segmk = Segmaker("design.bits")
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segmk.set_def_bt('BLOCK_RAM')
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for i, d in enumerate(pdata):
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# Keep dec convention used on LUT?
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segmk.add_site_tag(loc, "INITP[%04d]" % i, c2i[d])
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for i, d in enumerate(data):
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# Keep dec convention used on LUT?
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segmk.add_site_tag(loc, "INIT[%04d]" % i, c2i[d])
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print("Loading tags")
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'''
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'''
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segmk.compile()
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segmk.write()
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with open('params.json') as f:
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params = json.load(f)
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for param in params:
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for initp in range(NUM_INITP_PARAMS):
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p = 'INITP_{:02X}'.format(initp)
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val = param[p]
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for bit in range(BITS_PER_PARAM):
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segmk.add_site_tag(
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param['site'], "{p}[{bit:03d}]".format(
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p=p,
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bit=bit,
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), val & (1 << bit) != 0)
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for init in range(NUM_INIT_PARAMS):
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p = 'INIT_{:02X}'.format(init)
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val = param[p]
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for bit in range(BITS_PER_PARAM):
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segmk.add_site_tag(
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param['site'], "{p}[{bit:03d}]".format(
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p=p,
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bit=bit,
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), val & (1 << bit) != 0)
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segmk.compile()
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segmk.write()
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if __name__ == "__main__":
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main()
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@ -2,21 +2,10 @@ create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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@ -1,136 +1,69 @@
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#!/usr/bin/env python
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import os
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import json
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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import sys
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def gen_bram36():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMBFIFO36E1']):
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yield site_name
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def gen_sites():
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for tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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['RAMB18E1', 'FIFO18E1'])):
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yield tile_name, site_name
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DUTN = len(list(gen_bram36()))
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.csv', 'w')
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f.write('module,loc,pdata,data\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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BITS_PER_PARAM = 256
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NUM_INITP_PARAMS = 8
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NUM_INIT_PARAMS = 0x40
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BITS_PER_SITE = BITS_PER_PARAM * (NUM_INITP_PARAMS + NUM_INIT_PARAMS)
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def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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def main():
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print("module top();")
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list_of_params = []
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for tile_name, site in gen_sites():
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params = {}
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params['tile'] = tile_name
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params['site'] = site
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def make(module, gen_locs, pdatan, datan):
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loci = 0
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p = []
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for initp_idx in range(NUM_INITP_PARAMS):
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param = 'INITP_{:02X}'.format(initp_idx)
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params[param] = random.randint(0, 2**BITS_PER_PARAM - 1)
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p.append(
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".{param}(256'h{val:x})".format(
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param=param, val=params[param]))
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for loci, loc in enumerate(gen_locs()):
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if loci >= DUTN:
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break
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for init_idx in range(NUM_INIT_PARAMS):
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param = 'INIT_{:02X}'.format(init_idx)
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params[param] = random.randint(0, 2**BITS_PER_PARAM - 1)
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p.append(
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".{param}(256'h{val:x})".format(
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param=param, val=params[param]))
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pdata = randbits(pdatan * 0x100)
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data = randbits(datan * 0x100)
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params['params'] = ','.join(p)
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print(' %s #(' % module)
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for i in range(pdatan):
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print(
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" .INITP_%02X(256'b%s)," %
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(i, pdata[i * 256:(i + 1) * 256]))
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for i in range(datan):
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print(
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" .INIT_%02X(256'b%s)," %
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(i, data[i * 256:(i + 1) * 256]))
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print(' .LOC("%s"))' % (loc, ))
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print(
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' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (loci, 8 * loci, 8 * loci))
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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RAMB18E1 #(
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.READ_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.RAM_MODE("TDP"),
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{params}
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) bram_{site} (
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);
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""".format(**params))
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f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
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print('')
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loci += 1
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assert loci == DUTN
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list_of_params.append(params)
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print("endmodule")
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with open('params.json', 'w') as f:
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json.dump(list_of_params, f, indent=2)
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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for i in range(16):
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print(
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" parameter INITP_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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for i in range(0x80):
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print(
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" parameter INIT_%02X = 256'h0000000000000000000000000000000000000000000000000000000000000000;"
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% i)
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print('')
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print('''\
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(* LOC=LOC *)
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RAMB36E1 #(''')
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for i in range(16):
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print(' .INITP_%02X(INITP_%02X),' % (i, i))
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print('')
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for i in range(0x80):
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print(' .INIT_%02X(INIT_%02X),' % (i, i))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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if __name__ == "__main__":
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main()
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