Merge pull request #184 from litghost/roi_metadata

Create design.json that describes roi harness boundry,

minitests/roi_harness/create_design_json.py

@@ -0,0 +1,33 @@
+import json
+import csv
+import argparse
+import sys
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description=
+        "Creates design.json from output of ROI generation tcl script.")
+    parser.add_argument('--design_txt', required=True)
+    parser.add_argument('--design_info_txt', required=True)
+
+    args = parser.parse_args()
+
+    j = {}
+    j['ports'] = []
+    j['info'] = {}
+    with open(args.design_txt) as f:
+        for d in csv.DictReader(f, delimiter=' '):
+            j['ports'].append(d)
+
+    with open(args.design_info_txt) as f:
+        for l in f:
+            name, value = l.strip().split(' = ')
+
+            j['info'][name] = int(value)
+
+    json.dump(j, sys.stdout, indent=2, sort_keys=True)
+
+
+if __name__ == '__main__':
+    main()

minitests/roi_harness/runme.sh

@@ -24,7 +24,7 @@ EOF
 stat ${XRAY_DIR}/database/artix7/${XRAY_PART}.yaml >/dev/null
 
 # 6x by 18y CLBs (108)
-if [ $SMALL = Y ] ; then
+if [ "$SMALL" = Y ] ; then
     echo "Design: small"
     export PITCH=1
     export DIN_N=8
@@ -37,6 +37,7 @@ else
     export DIN_N=8
     export DOUT_N=8
     export XRAY_ROI=SLICE_X12Y100:SLICE_X27Y149
+    #export XRAY_ROI=SLICE_X12Y100:SLICE_X5Y149
 fi
 
 mkdir -p $BUILD_DIR
@@ -59,6 +60,8 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
 ${XRAY_SEGPRINT} -zd design.bits >design.segp
 ${XRAY_DIR}/utils/bits2fasm.py --verbose design.bits > design.fasm
 ${XRAY_DIR}/utils/fasm2frames.py design.fasm design.frm
+python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt > design.json
+
 # Hack to get around weird clock error related to clk net not found
 # Remove following lines:
 #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]

minitests/roi_harness/runme.tcl

@@ -360,6 +360,17 @@ proc node2wire {node} {
     return $wire
 }
 
+proc write_grid_roi {fp} {
+    puts $fp "GRID_X_MIN = $::env(XRAY_ROI_GRID_X1)"
+    puts $fp "GRID_X_MAX = $::env(XRAY_ROI_GRID_X2)"
+    puts $fp "GRID_Y_MIN = $::env(XRAY_ROI_GRID_Y1)"
+    puts $fp "GRID_Y_MAX = $::env(XRAY_ROI_GRID_Y2)"
+}
+
+set fp [open "design_info.txt" w]
+write_grid_roi $fp
+close $fp
+
 # XXX: maybe add IOB?
 set fp [open "design.txt" w]
 puts $fp "name node pin wire"

prjxray/grid.py

@@ -12,7 +12,7 @@ class BlockType(enum.Enum):
 
 
 GridLoc = namedtuple('GridLoc', 'grid_x grid_y')
-GridInfo = namedtuple('GridInfo', 'segment bits sites tile_type in_roi')
+GridInfo = namedtuple('GridInfo', 'segment bits sites tile_type')
 Bits = namedtuple('Bits', 'base_address frames offset words')
 BitsInfo = namedtuple('BitsInfo', 'segment_type tile bits')
 
@@ -43,11 +43,6 @@ class Grid(object):
             assert grid_loc not in self.loc
             self.loc[grid_loc] = tile
 
-            if 'in_roi' in tileinfo:
-                in_roi = tileinfo['in_roi']
-            else:
-                in_roi = True
-
             bits = {}
 
             if 'segment' in tileinfo:
@@ -72,7 +67,6 @@ class Grid(object):
                 bits=bits,
                 sites=tileinfo['sites'],
                 tile_type=tileinfo['type'],
-                in_roi=in_roi,
             )
 
         x, y = zip(*self.loc.keys())