cells_data: add clock information on ports.json

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

docs/dev_database/common/cell_data.rst

@@ -65,7 +65,8 @@ Ports files
 
 This is a JSON file containing a dictionary of ports, each one with two attributes:
 
-    - Direction: Corresponds to the port directiona and can have the ``input`` or ``output`` values.
+    - Direction: Corresponds to the port directiona and can have the ``input``, ``output``, ``clock`` values.
+                 Note that the ``clock`` value is implicitly considered also as an ``input``.
     - Width: Indicates the width of the port bus.
 
 As an example of parameter please, refer to the following::

fuzzers/061-pcie-conf/generate_ports.tcl

@@ -6,28 +6,7 @@
 #
 # SPDX-License-Identifier: ISC
 
-proc dump_pins {file_name site_prefix} {
+source "$::env(XRAY_DIR)/utils/utils.tcl"
-    set fp [open $file_name w]
-
-    puts $fp "name,is_input,is_output"
-    set site [lindex [get_sites $site_prefix*] 0]
-
-    set pins [get_site_pins -of_objects $site]
-    foreach pin $pins {
-        set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
-
-        if { $connected_pip == "" } {
-            continue
-        }
-
-        set pin_name [lindex [split $pin "/"] 1]
-        set is_input [get_property IS_INPUT $pin]
-        set is_output [get_property IS_OUTPUT $pin]
-
-        puts $fp "$pin_name,$is_input,$is_output"
-    }
-    close $fp
-}
 
 create_project -force -name design -part $::env(XRAY_PART)
 set_property design_mode PinPlanning [current_fileset]

fuzzers/063-gtp-common-conf/generate_ports.tcl

@@ -6,28 +6,7 @@
 #
 # SPDX-License-Identifier: ISC
 
-proc dump_pins {file_name site_prefix} {
+source "$::env(XRAY_DIR)/utils/utils.tcl"
-    set fp [open $file_name w]
-
-    puts $fp "name,is_input,is_output"
-    set site [lindex [get_sites $site_prefix*] 0]
-
-    set pins [get_site_pins -of_objects $site]
-    foreach pin $pins {
-        set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
-
-        if { $connected_pip == "" } {
-            continue
-        }
-
-        set pin_name [lindex [split $pin "/"] 1]
-        set is_input [get_property IS_INPUT $pin]
-        set is_output [get_property IS_OUTPUT $pin]
-
-        puts $fp "$pin_name,$is_input,$is_output"
-    }
-    close $fp
-}
 
 create_project -force -name design -part $::env(XRAY_PART)
 set_property design_mode PinPlanning [current_fileset]

fuzzers/064-gtp-channel-conf/generate_ports.tcl

@@ -6,28 +6,7 @@
 #
 # SPDX-License-Identifier: ISC
 
-proc dump_pins {file_name site_prefix} {
+source "$::env(XRAY_DIR)/utils/utils.tcl"
-    set fp [open $file_name w]
-
-    puts $fp "name,is_input,is_output"
-    set site [lindex [get_sites $site_prefix*] 0]
-
-    set pins [get_site_pins -of_objects $site]
-    foreach pin $pins {
-        set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
-
-        if { $connected_pip == "" } {
-            continue
-        }
-
-        set pin_name [lindex [split $pin "/"] 1]
-        set is_input [get_property IS_INPUT $pin]
-        set is_output [get_property IS_OUTPUT $pin]
-
-        puts $fp "$pin_name,$is_input,$is_output"
-    }
-    close $fp
-}
 
 create_project -force -name design -part $::env(XRAY_PART)
 set_property design_mode PinPlanning [current_fileset]

utils/make_ports.py

@@ -81,9 +81,12 @@ def main():
         # Get direction
         is_input = int(pin["is_input"])
         is_output = int(pin["is_output"])
+        is_clock = int(pin["is_clock"])
 
         if is_input:
             direction = "input"
+            if is_clock:
+                direction = "clock"
         elif is_output:
             direction = "output"
         else:

utils/utils.tcl

@@ -168,3 +168,37 @@ proc generate_top {} {
     write_checkpoint -force design.dcp
     write_bitstream -force design.bit
 }
+
+# Dumps all pins of a site, with the direction info (clock, input, output)
+proc dump_pins {file_name site_prefix} {
+    set fp [open $file_name w]
+
+    puts $fp "name,is_input,is_output,is_clock"
+    set site [lindex [get_sites $site_prefix*] 0]
+    set bel [get_bels -of_objects $site]
+    set bel_pins [get_bel_pins -of_objects $bel]
+
+    set bel_pins_dict [dict create]
+    foreach pin $bel_pins {
+        set pin_name [lindex [split $pin "/"] 2]
+        set is_clock [get_property IS_CLOCK $pin]
+        dict set bel_pins_dict $pin_name $is_clock
+    }
+
+    set site_pins [get_site_pins -of_objects $site]
+    foreach pin $site_pins {
+        set connected_pip [get_pips -of_objects [get_nodes -of_objects $pin]]
+
+        if { $connected_pip == "" } {
+            continue
+        }
+
+        set pin_name [lindex [split $pin "/"] 1]
+        set is_input [get_property IS_INPUT $pin]
+        set is_output [get_property IS_OUTPUT $pin]
+        set is_clock [dict get $bel_pins_dict $pin_name]
+
+        puts $fp "$pin_name,$is_input,$is_output,$is_clock"
+    }
+    close $fp
+}