mirror of https://github.com/openXC7/prjxray.git
63 lines
2.0 KiB
ReStructuredText
63 lines
2.0 KiB
ReStructuredText
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===========
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ppips files
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===========
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The *ppips files* are generated for every FPGA :term:`tile <tile>` type.
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They store the information about the pseudo-PIPs, inside the tile.
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Programable Interconnect point (:term:`PIP <pip>`) is a connection inside the
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:term:`tile <tile>` that can be enabled or disabled. Pseudo PIPs appears as standard
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:term:`PIPs <pip>` in the Vivado tool, but they do not have actual configuration
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bit pattern (they are not configurable).
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Naming convention
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-----------------
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The naming scheme for the PPIPs files is the following::
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ppips_<tile>.db
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In example:
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- ``ppips_dsp_l.db``
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- ``ppips_clbll_l.db``
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- ``ppips_bram_int_interface_l.db``
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File format
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-----------
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The file contains one entry per pseudo-PIP, each with one of the following
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three tags: ``always``, ``default`` or ``hint``. The entries are of the form:::
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<ppip_location> <tag>
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The tag ``always`` is used for pseudo-PIPs that are actually always-on, i.e.,
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that are permanent connections between two wires.
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The tag ``default`` is used for pseudo-PIPs that represent the default behavior
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if no other driver has been configured for the destination net
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(all default pseudo-PIPs connect to the VCC_WIRE net).
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The tag ``hint`` is used for PIPs that are used by Vivado to tell the router
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that two logic slice outputs drive the same value, i.e., behave like they
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are connected as far as the routing process is concerned.
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Example
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-------
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Below there is a part of artix7 ``ppips_clbll_l.db`` file::
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<...>
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CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
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CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
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CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
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CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
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CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
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CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
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CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
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<...>
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The ``<ppip_location>`` name is arbitrary. However, we named them in the convention
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similar to the Vivado tool, which allows us to identify them quickly and provides
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suggestions about their role in the FPGA chip.
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