mirror of https://github.com/openXC7/prjxray.git
13 lines
172 B
Verilog
13 lines
172 B
Verilog
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module top(input clk, ce, sr, d, output q);
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(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
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FDPE ff (
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.C(clk),
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.CE(ce),
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.PRE(sr),
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.D(d),
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.Q(q)
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);
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endmodule
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