mirror of https://github.com/openXC7/prjxray.git
102 lines
2.0 KiB
ReStructuredText
102 lines
2.0 KiB
ReStructuredText
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Fuzzers
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=======
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Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
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This is how the contents of the database are generated.
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The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target.
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If you picked the IOB (no one is working on that yet), you'd write a design that is implemented in a specific IOB.
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Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin.
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A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually.
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By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design.
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Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
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Configurable Logic Blocks (CLB)
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-------------------------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*clb*
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Block RAM (BRAM)
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----------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*bram*
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Input / Output (IOB)
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--------------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*iob*
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Clocking (CMT, PLL, BUFG, etc)
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------------------------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*clk*
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*cmt*
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Programmable Interconnect Points (PIPs)
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---------------------------------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*int*
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*pip*
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Hard Block Fuzzers
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------------------
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.. toctree::
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:maxdepth: 1
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:glob:
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*xadc
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Grid and Wire
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-------------
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.. toctree::
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:maxdepth: 1
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:glob:
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tilegrid
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tileconn
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ordered_wires
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get_counts
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dump_all
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Timing
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------
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.. toctree::
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:maxdepth: 1
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:glob:
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timing
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All Fuzzers
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-----------
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.. toctree::
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:maxdepth: 1
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:glob:
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*
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