mirror of https://github.com/openXC7/prjxray.git
105 lines
2.5 KiB
Python
105 lines
2.5 KiB
Python
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.verilog import vrandbit, vrandbits
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import sys
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import json
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def gen_sites():
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for _tile_name, site_name, _site_type in sorted(util.get_roi().gen_sites(
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["PLLE2_ADV"])):
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yield site_name
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sites = list(gen_sites())
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DUTN = len(sites)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for loci, site in enumerate(sites):
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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"CLKOUT0_DIVIDE": random.randint(1, 128),
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}
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modname = "my_PLLE2_ADV"
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verilog.instance(modname, "inst_%u" % loci, ports, params=params)
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# LOC isn't support
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params["LOC"] = verilog.quote(site)
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module my_PLLE2_ADV (input clk, input [7:0] din, output [7:0] dout);
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parameter CLKOUT0_DIVIDE = 1;
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parameter CLKOUT1_DIVIDE = 1;
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parameter CLKOUT2_DIVIDE = 1;
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parameter CLKOUT3_DIVIDE = 1;
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parameter CLKOUT4_DIVIDE = 1;
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parameter CLKOUT5_DIVIDE = 1;
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parameter DIVCLK_DIVIDE = 1;
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parameter CLKFBOUT_MULT = 5;
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(* KEEP, DONT_TOUCH *)
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PLLE2_ADV #(
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.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
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.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
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.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
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.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
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.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
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.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
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.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
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.CLKFBOUT_MULT(CLKFBOUT_MULT)
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) dut(
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.CLKFBOUT(),
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.CLKOUT0(dout[0]),
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.CLKOUT1(),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.DRDY(),
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.LOCKED(),
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.DO(),
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.CLKFBIN(),
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.CLKIN1(),
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.CLKIN2(),
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.CLKINSEL(),
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.DCLK(),
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.DEN(),
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.DWE(),
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.PWRDWN(),
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.RST(din[0]),
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.DI(),
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.DADDR());
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endmodule
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''')
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