mirror of https://github.com/openXC7/prjxray.git
519 lines
17 KiB
Python
519 lines
17 KiB
Python
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import argparse
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import json
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from openpyxl import Workbook, utils
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from prjxray.tile import OutPinTiming, InPinTiming
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from prjxray.timing import Outpin, Inpin, Wire, Buffer, \
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PassTransistor, IntristicDelay, RcElement, PvtCorner
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from prjxray.math_models import ExcelMathModel
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from prjxray.db import Database
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FAST = PvtCorner.FAST
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SLOW = PvtCorner.SLOW
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class TimingLookup(object):
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def __init__(self, db, nodes):
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self.db = db
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self.grid = db.grid()
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self.nodes = nodes
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def try_find_site_pin(self, site_pin_node, node_idx):
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site_pin_wire = self.nodes[site_pin_node]['wires'][node_idx]['name']
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tile, wire_in_tile = site_pin_wire.split('/')
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gridinfo = self.grid.gridinfo_at_tilename(tile)
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tile_type = self.db.get_tile_type(gridinfo.tile_type)
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for site in tile_type.get_sites():
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for site_pin in site.site_pins:
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if site_pin.wire == wire_in_tile:
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return site_pin
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return None
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def find_site_pin(self, site_pin_node, node_idx):
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site_pin = self.try_find_site_pin(site_pin_node, node_idx)
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assert site_pin is not None, site_pin_node
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return site_pin
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def find_pip(self, pip_name):
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tile, pip = pip_name.split('/')
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gridinfo = self.grid.gridinfo_at_tilename(tile)
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tile_type = self.db.get_tile_type(gridinfo.tile_type)
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return tile_type.get_pip_by_name(pip)
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def find_wire(self, wire_name):
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tile, wire_in_tile = wire_name.split('/')
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gridinfo = self.grid.gridinfo_at_tilename(tile)
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tile_type = self.db.get_tile_type(gridinfo.tile_type)
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return tile_type.wires[wire_in_tile]
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def delays_to_cells(ws, row, delays, cells):
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cells['FAST_MAX'] = 'E{}'.format(row)
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cells['FAST_MIN'] = 'F{}'.format(row)
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cells['SLOW_MAX'] = 'G{}'.format(row)
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cells['SLOW_MIN'] = 'H{}'.format(row)
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if delays is not None:
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ws[cells['FAST_MAX']] = delays[FAST].max
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ws[cells['FAST_MIN']] = delays[FAST].min
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ws[cells['SLOW_MAX']] = delays[SLOW].max
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ws[cells['SLOW_MIN']] = delays[SLOW].min
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else:
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ws[cells['FAST_MAX']] = 0
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ws[cells['FAST_MIN']] = 0
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ws[cells['SLOW_MAX']] = 0
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ws[cells['SLOW_MIN']] = 0
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def cells_to_delays(cells):
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return {
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FAST: IntristicDelay(min=cells['FAST_MIN'], max=cells['FAST_MAX']),
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SLOW: IntristicDelay(min=cells['SLOW_MIN'], max=cells['SLOW_MAX']),
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}
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class Net(object):
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def __init__(self, net):
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self.net = net
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self.ipin_nodes = {}
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self.row = None
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self.math = ExcelMathModel()
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self.models = {}
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for ipin in net['ipins']:
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self.ipin_nodes[ipin['node']] = ipin
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# Map of wire name to parent node
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self.wire_to_node = {}
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# Map of node name to node
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self.node_name_to_node = {}
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for node in net['nodes']:
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self.node_name_to_node[node['name']] = node
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for wire in node['wires']:
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self.wire_to_node[wire['name']] = node
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# Map of (src node, dst wire).
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self.pips = {}
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for pip in net['pips']:
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src_node = self.wire_to_node[pip['src_wire']]['name']
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dst_wire = pip['dst_wire'].split('/')[1]
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self.pips[(src_node, dst_wire)] = pip
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if not pip['is_directional']:
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dst_node = self.wire_to_node[pip['dst_wire']]['name']
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src_wire = pip['src_wire'].split('/')[1]
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self.pips[(dst_node, src_wire)] = pip
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def extend_rc_tree(self, ws, current_rc_root, timing_lookup, node):
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rc_elements = []
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for wire in node['wires']:
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wire_timing = timing_lookup.find_wire(wire['name'])
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ws['A{}'.format(self.row)] = wire['name']
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ws['B{}'.format(self.row)] = 'Part of wire'
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if wire_timing is not None:
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cells = {}
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cells['R'] = 'C{}'.format(self.row)
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cells['C'] = 'D{}'.format(self.row)
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ws[cells['R']] = wire_timing.resistance
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ws[cells['C']] = wire_timing.capacitance
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rc_elements.append(
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RcElement(
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resistance=cells['R'],
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capacitance=cells['C'],
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))
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self.row += 1
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wire_rc_node = Wire(rc_elements=rc_elements, math=self.math)
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self.models[self.row - 1] = wire_rc_node
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current_rc_root.set_sink_wire(wire_rc_node)
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return wire_rc_node
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def descend_route(
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self,
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ws,
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timing_lookup,
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current_node,
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route,
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route_idx,
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current_rc_root,
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was_opin=False):
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""" Traverse the next pip, or recurse deeper. """
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# descend_route should've consumed this token
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assert route[route_idx] != '}'
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while route[route_idx] == '{':
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# Go deeper
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route_idx = self.descend_route(
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ws,
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timing_lookup,
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current_node,
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route,
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route_idx=route_idx + 1,
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current_rc_root=current_rc_root,
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was_opin=was_opin)
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next_edge = (current_node, route[route_idx])
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route_idx += 1
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assert next_edge in self.pips, (next_edge, self.pips.keys())
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pip = self.pips[next_edge]
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is_backward = self.wire_to_node[
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pip['dst_wire']]['name'] == current_node
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if not is_backward:
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assert self.wire_to_node[
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pip['src_wire']]['name'] == current_node, (current_node, pip)
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pip_info = timing_lookup.find_pip(pip['name'])
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if not is_backward:
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pip_timing = pip_info.timing
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current_node = self.wire_to_node[pip['dst_wire']]['name']
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else:
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pip_timing = pip_info.backward_timing
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current_node = self.wire_to_node[pip['src_wire']]['name']
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ws['A{}'.format(self.row)] = pip['name']
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cells = {}
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cells['R'] = 'C{}'.format(self.row)
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cells['C'] = 'D{}'.format(self.row)
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delays_to_cells(
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ws, row=self.row, delays=pip_timing.delays, cells=cells)
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delays = cells_to_delays(cells)
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if pip_info.is_pass_transistor:
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ws['B{}'.format(self.row)] = 'PassTransistor'
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ws[cells['R']] = pip_timing.drive_resistance
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pip_model = PassTransistor(
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drive_resistance=cells['R'],
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delays=delays,
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)
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else:
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ws['B{}'.format(self.row)] = 'Buffer'
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if pip_timing.drive_resistance is not None:
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ws[cells['R']] = pip_timing.drive_resistance
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if pip_timing.drive_resistance == 0 and was_opin:
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new_site_pin = timing_lookup.try_find_site_pin(
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current_node, node_idx=0)
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if new_site_pin is not None:
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ws[cells['R']] = new_site_pin.timing.drive_resistance
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else:
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ws[cells['R']] = 0
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if pip_timing.internal_capacitance is not None:
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ws[cells['C']] = pip_timing.internal_capacitance
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else:
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ws[cells['C']] = 0
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pip_model = Buffer(
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drive_resistance=cells['R'],
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internal_capacitance=cells['C'],
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delays=cells_to_delays(cells),
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)
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self.models[self.row] = pip_model
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current_rc_root.add_child(pip_model)
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self.row += 1
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if current_node in self.ipin_nodes:
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assert route[route_idx] == '}'
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route_idx += 1
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node = self.node_name_to_node[current_node]
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current_rc_root = self.extend_rc_tree(
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ws, pip_model, timing_lookup, node)
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if current_node in self.ipin_nodes:
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ipin = self.ipin_nodes[current_node]
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cells = {}
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name = '{} to {}'.format(self.net['opin']['name'], ipin['name'])
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ws['A{}'.format(self.row)] = ipin['name']
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ws['B{}'.format(self.row)] = 'Inpin'
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site_pin = timing_lookup.find_site_pin(ipin['node'], node_idx=-1)
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assert isinstance(site_pin.timing, InPinTiming)
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cells = {}
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cells['C'] = 'D{}'.format(self.row)
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delays_to_cells(
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ws, row=self.row, delays=site_pin.timing.delays, cells=cells)
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delays = cells_to_delays(cells)
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ws[cells['C']] = site_pin.timing.capacitance
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ipin_model = Inpin(
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capacitance=cells['C'], delays=delays, name=name)
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self.models[self.row] = ipin_model
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current_rc_root.add_child(ipin_model)
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self.row += 1
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#Sum delays only (sum*1000)
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#Sum delays + capacitive delay
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#
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#Total delay (from Vivado)
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ws['A{}'.format(self.row)] = '{}: {} sum delays'.format(
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self.net['net'], name)
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self.row += 1
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ws['A{}'.format(self.row)] = '{}: {}sum delays + cap delay'.format(
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self.net['net'], name)
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self.row += 2
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ws['A{}'.format(
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self.row)] = '{}: {}Total delay (from Vivado)'.format(
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self.net['net'], name)
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ws['E{}'.format(self.row)] = ipin['ic_delays']['FAST_MAX']
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ws['F{}'.format(self.row)] = ipin['ic_delays']['FAST_MIN']
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ws['G{}'.format(self.row)] = ipin['ic_delays']['SLOW_MAX']
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ws['H{}'.format(self.row)] = ipin['ic_delays']['SLOW_MIN']
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self.row += 2
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return route_idx
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else:
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return self.descend_route(
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ws,
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timing_lookup,
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current_node,
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route,
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route_idx=route_idx,
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current_rc_root=current_rc_root)
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def walk_route(self, ws, timing_lookup):
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""" Walk route, creating rows in table.
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First row will always be the OPIN, followed by the node/wire connected
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to the OPIN. After a node/wire is always 1 or more pips. After a pip
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is always a node/wire. A terminal node/wire will then reach an IPIN.
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"""
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self.row = 2
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ws['A{}'.format(self.row)] = self.net['opin']['wire']
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site_pin = timing_lookup.find_site_pin(
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self.net['opin']['node'], node_idx=0)
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assert isinstance(site_pin.timing, OutPinTiming)
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ws['B{}'.format(self.row)] = 'Outpin'
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ws['C{}'.format(self.row)] = site_pin.timing.drive_resistance
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cells = {}
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cells['R'] = 'C{}'.format(self.row)
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delays_to_cells(
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ws, row=self.row, delays=site_pin.timing.delays, cells=cells)
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model_root = Outpin(
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resistance=cells['R'], delays=cells_to_delays(cells))
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self.models[self.row] = model_root
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self.row += 1
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node = self.net['opin']['node']
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tile, first_wire = self.net['opin']['node'].split('/')
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route = [r for r in self.net['route'].strip().split(' ') if r != '']
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assert route[0] == '{'
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assert route[1] == first_wire
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node = self.node_name_to_node[node]
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current_rc_root = self.extend_rc_tree(
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ws, model_root, timing_lookup, node)
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self.descend_route(
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ws,
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timing_lookup,
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node['name'],
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route,
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route_idx=2,
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current_rc_root=current_rc_root,
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was_opin=True)
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model_root.propigate_delays(self.math)
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model_rows = {}
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for row, model in self.models.items():
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model_rows[id(model)] = row
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for row, model in self.models.items():
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rc_delay = model.get_rc_delay()
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if rc_delay is not None:
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ws['J{}'.format(row)] = self.math.eval(rc_delay)
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downstream_cap = model.get_downstream_cap()
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if downstream_cap is not None:
|
||
|
|
ws['I{}'.format(row)] = self.math.eval(downstream_cap)
|
||
|
|
|
||
|
|
if isinstance(model, Inpin):
|
||
|
|
ipin_results = {
|
||
|
|
'Name': model.name,
|
||
|
|
'truth': {},
|
||
|
|
'computed': {},
|
||
|
|
}
|
||
|
|
|
||
|
|
ipin_delays = {}
|
||
|
|
|
||
|
|
DELAY_COLS = (
|
||
|
|
('E', 'FAST_MAX'),
|
||
|
|
('F', 'FAST_MIN'),
|
||
|
|
('G', 'SLOW_MAX'),
|
||
|
|
('H', 'SLOW_MIN'),
|
||
|
|
)
|
||
|
|
|
||
|
|
for col, value in DELAY_COLS:
|
||
|
|
ipin_delays[value] = []
|
||
|
|
ipin_results['computed'][
|
||
|
|
value] = '{title}!{col}{row}'.format(
|
||
|
|
title=utils.quote_sheetname(ws.title),
|
||
|
|
col=col,
|
||
|
|
row=row + 2)
|
||
|
|
ipin_results['truth'][value] = '{title}!{col}{row}'.format(
|
||
|
|
title=utils.quote_sheetname(ws.title),
|
||
|
|
col=col,
|
||
|
|
row=row + 4)
|
||
|
|
|
||
|
|
rc_delays = []
|
||
|
|
|
||
|
|
for model in model.get_delays():
|
||
|
|
delays = model.get_intrinsic_delays()
|
||
|
|
if delays is not None:
|
||
|
|
ipin_delays['FAST_MAX'].append(delays[FAST].max)
|
||
|
|
ipin_delays['FAST_MIN'].append(delays[FAST].min)
|
||
|
|
ipin_delays['SLOW_MAX'].append(delays[SLOW].max)
|
||
|
|
ipin_delays['SLOW_MIN'].append(delays[SLOW].min)
|
||
|
|
|
||
|
|
if id(model) in model_rows:
|
||
|
|
rc_delays.append('J{}'.format(model_rows[id(model)]))
|
||
|
|
|
||
|
|
ws['J{}'.format(row + 1)] = self.math.eval(
|
||
|
|
self.math.sum(rc_delays))
|
||
|
|
|
||
|
|
for col, value in DELAY_COLS:
|
||
|
|
ws['{}{}'.format(col, row + 1)] = self.math.eval(
|
||
|
|
self.math.sum(ipin_delays[value]))
|
||
|
|
ws['{}{}'.format(
|
||
|
|
col, row + 2)] = '=1000*({col}{row} + J{row})'.format(
|
||
|
|
col=col, row=row + 1)
|
||
|
|
|
||
|
|
yield ipin_results
|
||
|
|
|
||
|
|
|
||
|
|
def add_net(wb, net, timing_lookup):
|
||
|
|
ws = wb.create_sheet(
|
||
|
|
title="Net {}".format(net['net'].replace('[', '_').replace(']', '_')))
|
||
|
|
|
||
|
|
# Header
|
||
|
|
ws['A1'] = 'Name'
|
||
|
|
ws['B1'] = 'Type'
|
||
|
|
ws['C1'] = 'RES'
|
||
|
|
ws['D1'] = 'CAP'
|
||
|
|
ws['E1'] = 'FAST_MAX'
|
||
|
|
ws['F1'] = 'FAST_MIN'
|
||
|
|
ws['G1'] = 'SLOW_MAX'
|
||
|
|
ws['H1'] = 'SLOW_MIN'
|
||
|
|
ws['I1'] = 'Downstream C'
|
||
|
|
ws['J1'] = 'Delay from cap'
|
||
|
|
|
||
|
|
net_obj = Net(net)
|
||
|
|
yield from net_obj.walk_route(ws, timing_lookup)
|
||
|
|
|
||
|
|
|
||
|
|
def main():
|
||
|
|
parser = argparse.ArgumentParser(
|
||
|
|
description="Create timing worksheet for 7-series timing analysis.")
|
||
|
|
|
||
|
|
parser.add_argument('--timing_json', required=True)
|
||
|
|
parser.add_argument('--db_root', required=True)
|
||
|
|
parser.add_argument('--output_xlsx', required=True)
|
||
|
|
|
||
|
|
args = parser.parse_args()
|
||
|
|
|
||
|
|
with open(args.timing_json) as f:
|
||
|
|
timing = json.load(f)
|
||
|
|
|
||
|
|
db = Database(args.db_root)
|
||
|
|
|
||
|
|
nodes = {}
|
||
|
|
for net in timing:
|
||
|
|
for node in net['nodes']:
|
||
|
|
nodes[node['name']] = node
|
||
|
|
|
||
|
|
timing_lookup = TimingLookup(db, nodes)
|
||
|
|
|
||
|
|
wb = Workbook()
|
||
|
|
summary_ws = wb.get_sheet_by_name(wb.sheetnames[0])
|
||
|
|
summary_ws.title = 'Summary'
|
||
|
|
|
||
|
|
summary_ws['A1'] = 'Name'
|
||
|
|
|
||
|
|
cols = ['FAST_MAX', 'FAST_MIN', 'SLOW_MAX', 'SLOW_MIN']
|
||
|
|
cur_col = 'B'
|
||
|
|
for col in cols:
|
||
|
|
summary_ws['{}1'.format(cur_col)] = col
|
||
|
|
cur_col = chr(ord(cur_col) + 1)
|
||
|
|
summary_ws['{}1'.format(cur_col)] = 'Computed ' + col
|
||
|
|
cur_col = chr(ord(cur_col) + 3)
|
||
|
|
|
||
|
|
summary_row = 2
|
||
|
|
for net in timing:
|
||
|
|
if '<' in net['route']:
|
||
|
|
print(
|
||
|
|
"WARNING: Skipping net {} because it has complicated route description."
|
||
|
|
.format(net['net']))
|
||
|
|
continue
|
||
|
|
|
||
|
|
for summary_cells in add_net(wb, net, timing_lookup):
|
||
|
|
summary_ws['A{}'.format(summary_row)] = summary_cells['Name']
|
||
|
|
|
||
|
|
cur_col = 'B'
|
||
|
|
for col in cols:
|
||
|
|
truth_col = chr(ord(cur_col) + 0)
|
||
|
|
computed_col = chr(ord(cur_col) + 1)
|
||
|
|
error_col = chr(ord(cur_col) + 2)
|
||
|
|
error_per_col = chr(ord(cur_col) + 3)
|
||
|
|
summary_ws['{}{}'.format(
|
||
|
|
truth_col,
|
||
|
|
summary_row)] = '=' + summary_cells['truth'][col]
|
||
|
|
summary_ws['{}{}'.format(
|
||
|
|
computed_col,
|
||
|
|
summary_row)] = '=' + summary_cells['computed'][col]
|
||
|
|
summary_ws['{}{}'.format(
|
||
|
|
error_col,
|
||
|
|
summary_row)] = '={truth}{row}-{comp}{row}'.format(
|
||
|
|
truth=truth_col, comp=computed_col, row=summary_row)
|
||
|
|
summary_ws['{}{}'.format(
|
||
|
|
error_per_col,
|
||
|
|
summary_row)] = '={error}{row}/{truth}{row}'.format(
|
||
|
|
error=error_col, truth=truth_col, row=summary_row)
|
||
|
|
|
||
|
|
cur_col = chr(ord(cur_col) + 4)
|
||
|
|
|
||
|
|
summary_row += 1
|
||
|
|
|
||
|
|
wb.save(filename=args.output_xlsx)
|
||
|
|
|
||
|
|
|
||
|
|
if __name__ == "__main__":
|
||
|
|
main()
|