2018-02-14 12:24:18 +01:00
|
|
|
# CLBRAM Fuzzer
|
2017-12-20 04:18:25 +01:00
|
|
|
|
2018-02-14 12:24:18 +01:00
|
|
|
## Purpose
|
|
|
|
|
Solves SLICEM specific bits:
|
2018-02-18 03:02:33 +01:00
|
|
|
- Shift register LUT (SRL)
|
|
|
|
|
- Memory size
|
|
|
|
|
- RAM vs LUT
|
|
|
|
|
- Related muxes
|
2018-02-14 12:24:18 +01:00
|
|
|
|
|
|
|
|
## Algorithm
|
|
|
|
|
|
|
|
|
|
## Outcome
|
|
|
|
|
```
|
2017-12-20 04:18:25 +01:00
|
|
|
CLB.SLICE_X0.ALUT.RAM 31_16
|
|
|
|
|
CLB.SLICE_X0.ALUT.SMALL 00_04
|
|
|
|
|
CLB.SLICE_X0.ALUT.SRL 30_16
|
|
|
|
|
CLB.SLICE_X0.BLUT.RAM 31_17
|
|
|
|
|
CLB.SLICE_X0.BLUT.SMALL 00_24
|
|
|
|
|
CLB.SLICE_X0.BLUT.SRL 30_17
|
|
|
|
|
CLB.SLICE_X0.CLUT.RAM 31_46
|
|
|
|
|
CLB.SLICE_X0.CLUT.SMALL 00_28
|
|
|
|
|
CLB.SLICE_X0.CLUT.SRL 30_46
|
|
|
|
|
CLB.SLICE_X0.DLUT.RAM 31_47
|
|
|
|
|
CLB.SLICE_X0.DLUT.SMALL 01_59
|
|
|
|
|
CLB.SLICE_X0.DLUT.SRL 30_47
|
|
|
|
|
CLB.SLICE_X0.WA7USED 00_40
|
|
|
|
|
CLB.SLICE_X0.WA8USED 01_27
|
|
|
|
|
CLB.SLICE_X0.WEMUX.CE 01_23
|
2018-02-14 12:24:18 +01:00
|
|
|
```
|
