mirror of https://github.com/openXC7/prjxray.git
11 lines
634 B
Markdown
11 lines
634 B
Markdown
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# LiteX Litex BaseSoC + LiteDRAM minitest
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This folder contains a minitest for the Litex memory controller (LiteDRAM).
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For checking the memory interface we leverage the fact that the BIOS firmware performs a memory test at startup.
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The SoC is a Basic LiteX SoC configuration for the Arty board with the VexRiscv core.
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## Synthesis+implementation
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There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run `make`.
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Once the bitstream is generated and loaded to the board, we should see the test result on the terminal connected to one of the serial ports.
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