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Updating info based on "Missing closing of if.". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2018-10-14 20:44:38 +00:00
parent fcb76b4ac9
commit fd147ad569
173 changed files with 1026233 additions and 31488 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

204
Info.md
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@ -37,27 +37,26 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Wed Jan 3 16:21:55 UTC 2018 (2018-01-03T16:21:55+00:00).
Last updated on Sun Oct 14 20:44:37 UTC 2018 (2018-10-14T20:44:37+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-391-g2500500](https://github.com/SymbiFlow/prjxray/commit/250050024f7878ed6697f79fad80b6e0e6e8f8c3).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-767-g0a9e24](https://github.com/SymbiFlow/prjxray/commit/0a9e24373eccb22dfe41073f8a3a0fa72627e5c0).
Latest commit was;
```
commit 250050024f7878ed6697f79fad80b6e0e6e8f8c3
Merge: 21fbacd 800f4b4
Author: Clifford Wolf <clifford@clifford.at>
Date: Mon Jan 1 19:50:25 2018 +0100
commit 0a9e24373eccb22dfe41073f8a3a0fa72627e5c0
Author: Tim 'mithro' Ansell <me@mith.ro>
Date: Fri Oct 12 13:45:42 2018 +0000
Merge pull request #26 from SymbiFlow/next-clifford
Replace 070-tileconn with a new (hopefully strictly better) implementation
Missing closing of if.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
```
## Database for [artix7](artix7/)
### Settings
Created using following [settings.sh (sha256: 994008cff37affae1b334cba5908a1b8fe51ec69c47c553943f3d246763fb300)](https://github.com/SymbiFlow/prjxray/blob/250050024f7878ed6697f79fad80b6e0e6e8f8c3/database/artix7/settings.sh)
Created using following [settings.sh (sha256: 994008cff37affae1b334cba5908a1b8fe51ec69c47c553943f3d246763fb300)](https://github.com/SymbiFlow/prjxray/blob/0a9e24373eccb22dfe41073f8a3a0fa72627e5c0/database/artix7/settings.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -82,11 +81,16 @@ source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
Results have checksums;
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
* [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
* [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
@ -95,26 +99,182 @@ Results have checksums;
* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`44a3df910f13680e4260f1c6826c41d1857e06e63d47c072f7a37c9a0cce0c08 ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`8ea1e0f36947b7eba067f15c73748ec7dfd018f1c6be516e35390af403ae4732 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`925dde8bf30f777ec348ddaede0080f31cb09fd93d61548850e57cd6416c2b25 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`6df1413549da3321bb95e42ea7ebad96d5db47d4357a2b18756d973549046849 ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`fe607671c984e2d3e55fcfdcfb57f78ec16a511daf65567e615dd789a9062774 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`8227de5bfcaf99d69bff616644670c07d59e9f624b93319fae54c4e4e3b25993 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`8aba20247656e287de5d0033bfaf31f2514cff0d041bd438719116673dc5e815 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`46c98e9e1d05d5d57055e67922560d85bb639981476ac8b69577cd00792878ff ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`33e7a95886148e7418eda981147c90b15ffc770414a00fb7eca543300bbf0d5a ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`4bd2d802fb5b62ebe2941d658edc466bab26b87c12d3c6fcbdcd614e51eb2e3f ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`20f7bf469951b04a56e5e140b6327470750b08960643353384b35baf85eb9117 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`d6ef0d4cc5a9afd7a493ffa6aeaf2f5a5e71f9afdf901852858ce9d06140e3dc ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`7ee1d2714dde4b1e6f1d8c89076f67e1575b9c65f078ade0fe07c0c6bf30cbd8 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`64e07cac8ac2dc7f2bfca584cda816a4b3e2feb629acb85bd8db843f7114563e ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`be5f0c64ee17ad010dfea5125200216b2c69a558477a80133d043ed466e565be ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`994008cff37affae1b334cba5908a1b8fe51ec69c47c553943f3d246763fb300 ./artix7/settings.sh`](./artix7/settings.sh)
* [`5a3b3d6a121e85235f1c8a306a4d35fccfa363088503649955b4b72fee33a173 ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`236dde5e55842e3944c6194b45adddbdc7b89043c64da2be3348a15c9d779443 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`86376865f572d83f9c7dc0fdf8caf1184da9fb924f859eecc3357f8b5205e3d6 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
* [`68d7c7a9a5c97fbca8e7867536b43ac030e955710daea776d3858632be03b289 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`48e835223effc9d381b53063018f109ca4f8f1d133770b369ee13627039018af ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
* [`44ba2a2267847c6b818d7c4d77582060acaabaadeed73251fe20b91fe994c1b6 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
* [`3c3defc9905964a71ea5479cb567e25ee9fe570f3265111cbbd4e8fd0e4a8523 ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json)
* [`8831721614d683525ca4731d7f8134a9b753a1c92fd6bdd7bcb7658eb943bfe4 ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json)
* [`de735a235f7a446de50a3be308d5cd81f7da0e1232b58aa053d4b782ac246ca0 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json)
* [`209848c604c17479294dc8ebed63f461aae730eaff0540d424d523ef587f759a ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json)
* [`987784fbf675e48be322751374983394cc9487133a6c94549a993fbc07e8a2d4 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json)
* [`62289a287b963c2b6b129fa8a5f31c49a500cfb8c3ab27f75ec57b9ffc552989 ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json)
* [`2d0af6b7ef658b20cbf8fe32b9d095f145b7c50449eb5f9d947f67d5927fe3a0 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json)
* [`64cf02d69a36a13742dabcdbb6e806574535f9d32f601a788dbeb31c9464f010 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json)
* [`cbe6698e675c86092cf45398e2a01c7d50c102408594040c5bc8c17e9cc18880 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json)
* [`2d5277673e613068f64113f124e27c3fb9c5ebd5e0aee8d18509ea6be0ddf102 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json)
* [`7fb7b4e064d7797b57dd52e5562d6610a60901d69373c6e6430e18ab5ee5b5a4 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json)
* [`75bb5f8208c20f3411d51b6db6ca2fc7269527e820f0c75147f06980d6e9870b ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json)
* [`802946f229a9cae335d14b7ec454a1b00c99ffa386a2757ff0e08cf173f4e586 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json)
* [`800265d879b19d71d149eca330d7af7782b20af5beedc7b56a9de7ab6a495484 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json)
* [`a2cb0e085e57ef5aae3fdf0ad581ccb1d70e637c7e6fd8eabaf6b8e7b8296fb5 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json)
* [`419dd4ac567c033750e5a3d1c719546b42a4aec43b7997ff754aa5d05a3f4957 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json)
* [`81374e99a343bd404d4398914f00c0ad70e4ce61260a0d4291acdff521a207ff ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json)
* [`d0234256fb9d69ef8772ac862cb31f62c528551c85b8b89dcd9419e7e6e97dbf ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json)
* [`e281b48b2ae05c81afd47274491bfb9dab16739b0410fc398901348feae0148f ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json)
* [`efb16e39739c19f68d5d93d05f3cb8ec02b1e21507d09248bde860e56fb88bc0 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json)
* [`4675291cdfdb138134a81bb417c6669678da41d7c0d414cd76bdc9b127376daa ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json)
* [`2b57b762c98a9d0dd4a0c9df64d3079c87d498affa8f44864e3865a56a9c4337 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json)
* [`c6f41a771b2c41cdf9d2c8f359b31c60a82ddc785cc37674dd3186b766f7e195 ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json)
* [`a9b9d3b45879b1ba94d1e23951829abed8a3a74045c426f9608a6cd710037159 ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json)
* [`52c3f259afb284b5fcd0b2f5c6cce1f10bbaba928c54314918deae733e1209c8 ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json)
* [`785e40e885e6e0e30ad7c8c5b1bae91b2a66ee198de467cbe311207a1883a763 ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json)
* [`bec68a01b085f668b3d670ba2eec33c6b013d91206074102dd0718a74f52a265 ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json)
* [`a86aae218a0de991c702bb18989965a01a449022411c9bcc446a77b999a29f4f ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json)
* [`1770469ab1f80899f97b2a73bcdab7dc1ac8264382fbb5a873a25c40f63f4025 ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json)
* [`fb9790f8d144f07032d58f0661b6c57d04d59d01fe9dbcdf04785075d95f9775 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json)
* [`a255ece7302b4b9084000b2e59673f6226f9a20b65cd79f16b855959b9a5ef9a ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json)
* [`0d6e8a27c97972610583753e8a55c30da363a077e66baab044102d9d68e4625c ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json)
* [`55c262e8e810f40dc2a48c1610105a6188e6497b0edcd6a85e1b3f9746efcb69 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json)
* [`4a52dd7412da5863de0c97f8c9c18cdf9f7c18964a52cf210eac3a633ab7b020 ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json)
* [`36d213c6a6b1834ad2069fce877c93f4de0be19a7d5d149881f92a5fe2d03660 ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json)
* [`ac08ae36561e4da581fdad9d5b368585edfffe9ee0ac0f637583a5bb2dbc1b31 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json)
* [`60e7076d85bae6e3b91c13aebc5c5cdb8bbb3085f1e659111a96b3ff6aa30c0c ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json)
* [`7b059e5a5f1ae6969e81e1467d65faae77094d08b37013fef3ee5f6eae138f4d ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json)
* [`b0d154bdf6f088bd1dec95b51b7f7e3d2214816d03dd8515491e1468d8da7d50 ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json)
* [`e8c9663846548b9d015c8bd9790ea2d546d1370a1be625d55cf67d2f2fdd85b0 ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json)
* [`bed5b08143b80a48843489c99f454a5520622f4d07cfcec844cf5ae5a4d3a02a ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json)
* [`05dc0f913271acdc3b847df1b865ca4eecb1aa4d62ed8c09a33c3fe4a94e5310 ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`cfcf625768dd4a389bc4f58144a96a5339836ee4d6c135f8d4b8a21e24cc8e1f ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`d9b746969fe43418700400f5eb28098ab1db1cd3c201646b4f98933e4ea4513c ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`1ace1125bc9f15f8d4c5b099c87c8879ebed5c782b019d3292ab309cf4c9f9f6 ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`fb0a193b9767c9aa6843b21642d7b22531ba99b1b20df73eb0e87d9d07323ff8 ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json)
* [`2a1c2972e742277d748c70d9fb10de1e4e8db4a8cff78a1426373eede785045b ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json)
* [`514495745877b0950efa5a6e85260e48311c7ec06639491b268596a1fcb1804e ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json)
* [`8270a7c38061544fd554489395b2fcf5ca1d5b2657e86909115513e5df4632c1 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json)
* [`161d83d9c4f465ada1f97de86f033cef0307a77033a9bcd84b6dc5db72c3ce5e ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json)
* [`e3495a6a48df14e4d2b46d37ba5b6d6e0b48e58f5079076c198cbf885e348687 ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json)
* [`03b08aeaed997c64ed4b5eaf67c4ed7d2664b912d8b9ee3525dbcc60372fd33a ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json)
* [`1d03a9c30038f68f985c3aa4c6b11eb67d351669a73741531843b67dfeb2d3bd ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json)
* [`273c69bd73e8da97c8c5f6e46239f5b42519559db2ba6526db0cc5eb997f2810 ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json)
* [`8728c790ff8a5b20b0b186128e7cac18a385416c3ce7e4fdfd016e63a9606e20 ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json)
* [`8c2539052f41244e1efedacec1bceac3127c537829005721afe2e0fb68bbd954 ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json)
* [`c53cb55ca3987567e1d92c8158921bf9040938d4fec0dcd46edd2fa66a8b0f96 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json)
* [`63e370ea04427f8f105645e6fb6ada35831db5c11d3193bebd8cf8a9b12466a9 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json)
* [`92dad8dfd99b93585fa663c9b8676a7396322efacf7eed4317ff17d34adc9e96 ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json)
* [`ac1bb0479076e19e72f26ff0d30574062fa9e3c0975ea27d49492fb76cd2ccda ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json)
* [`9017d2764450bd8abfb8130e8723a3c812d08594f33cfa30cd20cbbaa1d88ccc ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json)
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* [`33b79b15bec3527cbc3bb5befa16c56b3e9871107eb9a0c7d1ab47f8fb5e7fca ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json)
* [`6456207a5ded60d693c5a7fe2de6913dd857a0fea45dac839d5894c9eca07a3a ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json)
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* [`d2cc007c28f96e15a045cadae16e737c44d0cdb5b6feb6ac7a0e2d7d2a633113 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json)
* [`ca12c02dcb5161096b6615d740cda2286e203a8a6e58bac765553dba30fa03b5 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json)
* [`a4b3c90abc3b25401a35fc7311838c1256d2f7abf3434b8be4f077a9c211b5f5 ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json)
* [`78402da14a8d33516e657f5cd8bc03167ea130381bf9fd49e529bc07f7d21bd1 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json)
* [`d70153bcd8b20080449614a1c3af5d5610b038f3b047c773ba089233235be199 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json)
* [`d26c22cea469b765bf86cba805da21f439914984d78c00ecea4637cfb04e53b4 ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json)
* [`43731915b919e07a1e8cc06adcfbd20d04dcda35fedb1bd79ad9fc9d6babd35a ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json)
* [`3cd7b7f864d5f3b01a9dd81240a0768d3b5a23e9f42f47d55fd38ffd42391ac2 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json)
* [`15dcfb0e7681e036c9f983c08cdafce8aa5ca4d851b398fcc57796d50956cd6f ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json)
* [`13c071a98962402cfaf03ea8170a8bc95e777fa25e8907bcc9dd6e7392da620f ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json)
* [`4882141fe5d8c8d99a1f8e54111e45fa1f72da72afb82b9338dc1f8d5339c47c ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json)
* [`01831f7959fd450ebd4ff369effb58cd8dd6edb8c0a32910314e615bba7d0453 ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json)
* [`6e14d1df41c7babcabc2a70642c979c233d29964dee547f97d6e6611eb3cf0fa ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json)
* [`f11e6c8cb237981c22723594e11b91ba9a0520608c26b686984fa3a580006a53 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json)
* [`719e92c33454605348b48326a7216a05ed94972cbce07c009b9f91721354037d ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json)
* [`71b43263ec93d4fb4b2a1908a3797960fdb889a956aa4c4b0417662a3c6134c6 ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json)
* [`a43128995a064bdc7fb2912d85865045616e7566f17c04c7e0f2bfc069288021 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`3d3cc99ab7581f1c79346167a4a674db38badee88093088984285cf4486ffabc ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`2353553a03e3a9add958c19eefd91666e7f65bb700e45cf55a51feeb1f1538a1 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`546b36f818e4ce5bbbaeb004f0958bc71c196116df945a6a1cc15865b3ad36e0 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`dcff89d800085c5ba4815965d96ee6e51ba0e0c2da67c5ab109a14ac8221f149 ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json)
* [`df04301e96cb3a401a2410a59d5a8668b085eedc63136b2d83f13c1266ff0c7d ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`53aed496f57f63e85c4ca2e994efb90d5c411e1f7b2a2fdec7d591bbfd52911d ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`c5a8e11c13a7efff28f7ec890f79d5dbfa02879390b88ddf205ac0b80898219d ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`a27684136404d082ede94a76308e3e37ebc406014bab99be40f0db209582e778 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json)
* [`446e3735753ece77f4ff94587d02a71525bf1d800bdbdc9e5f8c6c7e2eb1ab7d ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json)
* [`89c0f5064866f01eb7573184af6ad5b7a7cec268371140eb6d9a44022941ad90 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json)
* [`20df90e6bd299275e2a770fab0aa75d86c1044b075fc458431da325ac37f721a ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json)
* [`9dba1b622368e6d7730e0cbb791821f059c7c5ae2836f745402be6a898e6be88 ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json)
* [`64236bca14a2f24e555677d87688affea8db7690c9019b71a23094f26180d7ce ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json)
* [`7b9e02947c682e6409bad34c945d54a457ac1e233f41801f58c3e1f8980408f8 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json)
* [`42c9dea1a7776d599a3427963e5018e257b780192f92021b304d843db8fdeaad ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json)
* [`9ef4d2dd47b07c41632e3871079a0da594cb9dc2870a0477d2736284b38275c7 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json)
* [`39079ee2dbd2b38eba97db6755e40baf476f5f69ad48e240133d9b39aa2cfd13 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json)
* [`cbf55319ba7ac9fb21f588cc419894842458580754c82058651de357c5a9818c ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json)
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* [`dfa72bfc5d8892ced732e5211c13febe1528448e170de2211ae820561f08abd4 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json)
* [`ad94ca9de878402479ae3b5c42aca142a765f25b5053d0a1875a6b22ff4760eb ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json)
* [`117742d824958474ae4c985f716aeb8f6d0255ebb4e93b4b22ec4cbebd73493f ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json)
* [`db44dcb5af12e6e66f2477f44ba121e0394b3808474d52e25bfb835d700b4fc4 ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json)
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* [`fc6af43c34178d5b5e080673a26baa7ed44484ef800d93fbeb8b6026a06f8859 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json)
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* [`07bf11c14b2b7f4987005095198fed32bb591c55509c03d2e63c61df6db07893 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json)
* [`05e1236960af05dfc5ebe18026e4c4011ecd04edfbbbcd284df2cf7b6875d0c7 ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json)
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* [`3321ac396d19e3c6ea5e483f2e03eff301ca62d0896cc1a0d6bc1e5be88501b3 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json)
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* [`b2e0fa4a38dc2955ec6781d3d4acd45344b27db6de2b50252e07b086fd34ac10 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json)
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* [`2c56c5f629504e4ebdeb2170e6f09313ad58130aa82c3d28dfba2f0135d23577 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json)
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* [`db40d427ccf1aff3cc792ac065afba46812d333698eabd46b0fe0d4dc1cb7e2a ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json)
* [`89f3d258950a4313b243eb78a11a68e0097c2dcbe6ea40fa3c1dcd87fbb0feab ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json)
* [`b44973d83b020d2da4ad0f968bc5365d596c1962f7cfd7365060776261b08fbd ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json)
* [`0b2928bf771913d137df312a58dd915192733d25e7ba020bcfa70f23f8704e5a ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json)
* [`5f641bc2117a4a45d6db58dff650df2c876f9f2ce6b60ca89a8813b2b32f627a ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
* [`301ae67062447199afc4626fffe2e935d96b58002b133c285ade08e179392642 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json)
* [`5e105635aa264b9a73d178102ee2950519964cbe6e3d18a48070edfbe5c26e98 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml)
## Database for [kintex7](kintex7/)
### Settings
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/250050024f7878ed6697f79fad80b6e0e6e8f8c3/database/kintex7/settings.sh)
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/0a9e24373eccb22dfe41073f8a3a0fa72627e5c0/database/kintex7/settings.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"

9
artix7/element_counts.csv Normal file
View File

@ -0,0 +1,9 @@
type,count
tiles,18055
sites,15509
site_pins,534165
site_pips,1189418
pips,22002368
package_pins,484
nodes,1953452
wires,6193757
1 type count
2 tiles 18055
3 sites 15509
4 site_pins 534165
5 site_pips 1189418
6 pips 22002368
7 package_pins 484
8 nodes 1953452
9 wires 6193757

8030
artix7/mask_bram_l.db Normal file
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File diff suppressed because it is too large Load Diff

8040
artix7/mask_bram_r.db Normal file
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File diff suppressed because it is too large Load Diff

8030
artix7/mask_dsp_l.db Normal file
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File diff suppressed because it is too large Load Diff

8040
artix7/mask_dsp_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

64
artix7/ppips_int_l.db
View File

@ -1,67 +1,3 @@
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always

64
artix7/ppips_int_r.db
View File

@ -1,67 +1,3 @@
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always

100
artix7/segbits_clbll_l.db
View File

@ -2,6 +2,8 @@ CLBLL_L.SLICEL_X0.A5FF.MUX.A 30_09
CLBLL_L.SLICEL_X0.A5FF.MUX.B 30_10
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.ADI1MUX.AI 00_00
CLBLL_L.SLICEL_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
@ -11,6 +13,12 @@ CLBLL_L.SLICEL_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -84,10 +92,17 @@ CLBLL_L.SLICEL_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.MUX.A 30_19
CLBLL_L.SLICEL_X0.B5FF.MUX.B 30_18
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BDI1MUX.BI 00_20
CLBLL_L.SLICEL_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
@ -97,6 +112,12 @@ CLBLL_L.SLICEL_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -170,10 +191,17 @@ CLBLL_L.SLICEL_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_L.SLICEL_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FF.MUX.A 31_45
CLBLL_L.SLICEL_X0.C5FF.MUX.B 30_39
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
@ -188,6 +216,12 @@ CLBLL_L.SLICEL_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -262,10 +296,17 @@ CLBLL_L.SLICEL_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.MUX.A 30_55
CLBLL_L.SLICEL_X0.D5FF.MUX.B 30_54
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
@ -273,6 +314,11 @@ CLBLL_L.SLICEL_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -345,6 +391,10 @@ CLBLL_L.SLICEL_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12
@ -358,6 +408,8 @@ CLBLL_L.SLICEL_X1.A5FF.MUX.A 31_08
CLBLL_L.SLICEL_X1.A5FF.MUX.B 31_11
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
@ -366,6 +418,12 @@ CLBLL_L.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -436,10 +494,17 @@ CLBLL_L.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_L.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FF.MUX.A 31_19
CLBLL_L.SLICEL_X1.B5FF.MUX.B 31_18
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
@ -448,6 +513,12 @@ CLBLL_L.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -518,10 +589,17 @@ CLBLL_L.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_L.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FF.MUX.A 31_44
CLBLL_L.SLICEL_X1.C5FF.MUX.B 31_39
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
@ -535,6 +613,12 @@ CLBLL_L.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -606,10 +690,17 @@ CLBLL_L.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.MUX.A 31_55
CLBLL_L.SLICEL_X1.D5FF.MUX.B 31_54
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
@ -617,6 +708,11 @@ CLBLL_L.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -686,6 +782,10 @@ CLBLL_L.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11

100
artix7/segbits_clbll_r.db
View File

@ -2,6 +2,8 @@ CLBLL_R.SLICEL_X0.A5FF.MUX.A 30_09
CLBLL_R.SLICEL_X0.A5FF.MUX.B 30_10
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.ADI1MUX.AI 00_00
CLBLL_R.SLICEL_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
@ -11,6 +13,12 @@ CLBLL_R.SLICEL_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
@ -84,10 +92,17 @@ CLBLL_R.SLICEL_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.MUX.A 30_19
CLBLL_R.SLICEL_X0.B5FF.MUX.B 30_18
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BDI1MUX.BI 00_20
CLBLL_R.SLICEL_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
@ -97,6 +112,12 @@ CLBLL_R.SLICEL_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
@ -170,10 +191,17 @@ CLBLL_R.SLICEL_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLL_R.SLICEL_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FF.MUX.A 31_45
CLBLL_R.SLICEL_X0.C5FF.MUX.B 30_39
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
@ -188,6 +216,12 @@ CLBLL_R.SLICEL_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CLKINV 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
@ -262,10 +296,17 @@ CLBLL_R.SLICEL_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.MUX.A 30_55
CLBLL_R.SLICEL_X0.D5FF.MUX.B 30_54
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
@ -273,6 +314,11 @@ CLBLL_R.SLICEL_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
@ -345,6 +391,10 @@ CLBLL_R.SLICEL_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12
@ -358,6 +408,8 @@ CLBLL_R.SLICEL_X1.A5FF.MUX.A 31_08
CLBLL_R.SLICEL_X1.A5FF.MUX.B 31_11
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
@ -366,6 +418,12 @@ CLBLL_R.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -436,10 +494,17 @@ CLBLL_R.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLL_R.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FF.MUX.A 31_19
CLBLL_R.SLICEL_X1.B5FF.MUX.B 31_18
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
@ -448,6 +513,12 @@ CLBLL_R.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -518,10 +589,17 @@ CLBLL_R.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLL_R.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FF.MUX.A 31_44
CLBLL_R.SLICEL_X1.C5FF.MUX.B 31_39
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
@ -535,6 +613,12 @@ CLBLL_R.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CLKINV 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -606,10 +690,17 @@ CLBLL_R.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.MUX.A 31_55
CLBLL_R.SLICEL_X1.D5FF.MUX.B 31_54
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
@ -617,6 +708,11 @@ CLBLL_R.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -686,6 +782,10 @@ CLBLL_R.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11

100
artix7/segbits_clblm_l.db
View File

@ -2,6 +2,8 @@ CLBLM_L.SLICEL_X1.A5FF.MUX.A 31_08
CLBLM_L.SLICEL_X1.A5FF.MUX.B 31_11
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
@ -10,6 +12,12 @@ CLBLM_L.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -80,10 +88,17 @@ CLBLM_L.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_L.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FF.MUX.A 31_19
CLBLM_L.SLICEL_X1.B5FF.MUX.B 31_18
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
@ -92,6 +107,12 @@ CLBLM_L.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -162,10 +183,17 @@ CLBLM_L.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_L.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FF.MUX.A 31_44
CLBLM_L.SLICEL_X1.C5FF.MUX.B 31_39
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
@ -179,6 +207,12 @@ CLBLM_L.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CLKINV 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -250,10 +284,17 @@ CLBLM_L.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.MUX.A 31_55
CLBLM_L.SLICEL_X1.D5FF.MUX.B 31_54
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
@ -261,6 +302,11 @@ CLBLM_L.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -330,6 +376,10 @@ CLBLM_L.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11
@ -340,6 +390,8 @@ CLBLM_L.SLICEM_X0.A5FF.MUX.A 30_09
CLBLM_L.SLICEM_X0.A5FF.MUX.B 30_10
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.ADI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
@ -349,6 +401,12 @@ CLBLM_L.SLICEM_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
@ -422,10 +480,17 @@ CLBLM_L.SLICEM_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.MUX.A 30_19
CLBLM_L.SLICEM_X0.B5FF.MUX.B 30_18
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
@ -435,6 +500,12 @@ CLBLM_L.SLICEM_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
@ -508,10 +579,17 @@ CLBLM_L.SLICEM_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_L.SLICEM_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FF.MUX.A 31_45
CLBLM_L.SLICEM_X0.C5FF.MUX.B 30_39
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
@ -526,6 +604,12 @@ CLBLM_L.SLICEM_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
@ -600,10 +684,17 @@ CLBLM_L.SLICEM_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.MUX.A 30_55
CLBLM_L.SLICEM_X0.D5FF.MUX.B 30_54
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
@ -611,6 +702,11 @@ CLBLM_L.SLICEM_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
@ -683,6 +779,10 @@ CLBLM_L.SLICEM_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12

100
artix7/segbits_clblm_r.db
View File

@ -2,6 +2,8 @@ CLBLM_R.SLICEL_X1.A5FF.MUX.A 31_08
CLBLM_R.SLICEL_X1.A5FF.MUX.B 31_11
CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.DMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFF.DMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFF.DMUX.F7 !30_04 !31_02 31_00 31_01
@ -10,6 +12,12 @@ CLBLM_R.SLICEL_X1.AFF.DMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFF.DMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -80,10 +88,17 @@ CLBLM_R.SLICEL_X1.AMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AMUX.O6 !30_05 !31_07 !31_10 31_09
CLBLM_R.SLICEL_X1.AMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FF.MUX.A 31_19
CLBLM_R.SLICEL_X1.B5FF.MUX.B 31_18
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.DMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFF.DMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFF.DMUX.F8 !31_24 !31_26 31_25 31_27
@ -92,6 +107,12 @@ CLBLM_R.SLICEL_X1.BFF.DMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFF.DMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -162,10 +183,17 @@ CLBLM_R.SLICEL_X1.BMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BMUX.O6 !30_28 !30_29 !31_21 31_20
CLBLM_R.SLICEL_X1.BMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FF.MUX.A 31_44
CLBLM_R.SLICEL_X1.C5FF.MUX.B 31_39
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
@ -179,6 +207,12 @@ CLBLM_R.SLICEL_X1.CFF.DMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFF.DMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CLKINV 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -250,10 +284,17 @@ CLBLM_R.SLICEL_X1.CMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.CMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.CMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.CMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.MUX.A 31_55
CLBLM_R.SLICEL_X1.D5FF.MUX.B 31_54
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.DMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFF.DMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFF.DMUX.O5 !31_61 !31_62 30_58 31_60
@ -261,6 +302,11 @@ CLBLM_R.SLICEL_X1.DFF.DMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFF.DMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -330,6 +376,10 @@ CLBLM_R.SLICEL_X1.DMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DMUX.O6 !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11
@ -340,6 +390,8 @@ CLBLM_R.SLICEM_X0.A5FF.MUX.A 30_09
CLBLM_R.SLICEM_X0.A5FF.MUX.B 30_10
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.ADI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.AFF.DMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFF.DMUX.CY !30_01 !30_03 30_00 30_02
@ -349,6 +401,12 @@ CLBLM_R.SLICEM_X0.AFF.DMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFF.DMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
@ -422,10 +480,17 @@ CLBLM_R.SLICEM_X0.AMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.MUX.A 30_19
CLBLM_R.SLICEM_X0.B5FF.MUX.B 30_18
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BFF.DMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFF.DMUX.CY !30_24 !30_26 30_25 30_27
@ -435,6 +500,12 @@ CLBLM_R.SLICEM_X0.BFF.DMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFF.DMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
@ -508,10 +579,17 @@ CLBLM_R.SLICEM_X0.BMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BMUX.O6 !30_21 !30_22 !30_23 30_20
CLBLM_R.SLICEM_X0.BMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FF.MUX.A 31_45
CLBLM_R.SLICEM_X0.C5FF.MUX.B 30_39
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
@ -526,6 +604,12 @@ CLBLM_R.SLICEM_X0.CFF.DMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFF.DMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
@ -600,10 +684,17 @@ CLBLM_R.SLICEM_X0.CMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.CMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.CMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.CMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.MUX.A 30_55
CLBLM_R.SLICEM_X0.D5FF.MUX.B 30_54
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFF.DMUX.O5 !30_60 !30_61 30_59 30_62
@ -611,6 +702,11 @@ CLBLM_R.SLICEM_X0.DFF.DMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFF.DMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
@ -683,6 +779,10 @@ CLBLM_R.SLICEM_X0.DMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DMUX.O6 !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12

2
artix7/segbits_int_l.db
View File

@ -19,6 +19,7 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -43,6 +44,7 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15

3
artix7/segbits_int_r.db
View File

@ -19,6 +19,7 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -43,6 +44,7 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -701,6 +703,7 @@ INT_R.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_R.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 00_20 01_43 21_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS10 !22_40 21_40 23_40 24_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS16 !22_40 !23_40 !25_40 21_40 24_40

39
artix7/site_type_BSCAN.json Normal file
View File

@ -0,0 +1,39 @@
{
"site_pins": {
"UPDATE": {
"direction": "OUT"
},
"RESET": {
"direction": "OUT"
},
"SEL": {
"direction": "OUT"
},
"SHIFT": {
"direction": "OUT"
},
"CAPTURE": {
"direction": "OUT"
},
"RUNTEST": {
"direction": "OUT"
},
"DRCK": {
"direction": "OUT"
},
"TDI": {
"direction": "OUT"
},
"TMS": {
"direction": "OUT"
},
"TCK": {
"direction": "OUT"
},
"TDO": {
"direction": "IN"
}
},
"site_pips": {},
"type": "BSCAN"
}

82
artix7/site_type_BUFGCTRL.json Normal file
View File

@ -0,0 +1,82 @@
{
"site_pins": {
"IGNORE1": {
"direction": "IN"
},
"IGNORE0": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"S1": {
"direction": "IN"
},
"CE0": {
"direction": "IN"
},
"I0": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"S0": {
"direction": "IN"
},
"I1": {
"direction": "IN"
}
},
"site_pips": {
"S0INV:S0_B": {
"from_pin": "S0_B",
"to_pin": "OUT"
},
"CE0INV:CE0_B": {
"from_pin": "CE0_B",
"to_pin": "OUT"
},
"S1INV:S1": {
"from_pin": "S1",
"to_pin": "OUT"
},
"S0INV:S0": {
"from_pin": "S0",
"to_pin": "OUT"
},
"S1INV:S1_B": {
"from_pin": "S1_B",
"to_pin": "OUT"
},
"CE0INV:CE0": {
"from_pin": "CE0",
"to_pin": "OUT"
},
"CE1INV:CE1_B": {
"from_pin": "CE1_B",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1": {
"from_pin": "IGNORE1",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1_B": {
"from_pin": "IGNORE1_B",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0": {
"from_pin": "IGNORE0",
"to_pin": "OUT"
},
"CE1INV:CE1": {
"from_pin": "CE1",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0_B": {
"from_pin": "IGNORE0_B",
"to_pin": "OUT"
}
},
"type": "BUFGCTRL"
}

24
artix7/site_type_BUFHCE.json Normal file
View File

@ -0,0 +1,24 @@
{
"site_pins": {
"O": {
"direction": "OUT"
},
"I": {
"direction": "IN"
},
"CE": {
"direction": "IN"
}
},
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"type": "BUFHCE"
}

12
artix7/site_type_BUFIO.json Normal file
View File

@ -0,0 +1,12 @@
{
"site_pins": {
"O": {
"direction": "OUT"
},
"I": {
"direction": "IN"
}
},
"site_pips": {},
"type": "BUFIO"
}

24
artix7/site_type_BUFMRCE.json Normal file
View File

@ -0,0 +1,24 @@
{
"site_pins": {
"O": {
"direction": "OUT"
},
"I": {
"direction": "IN"
},
"CE": {
"direction": "IN"
}
},
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"type": "BUFMRCE"
}

18
artix7/site_type_BUFR.json Normal file
View File

@ -0,0 +1,18 @@
{
"site_pins": {
"I": {
"direction": "IN"
},
"CLR": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "BUFR"
}

12
artix7/site_type_CAPTURE.json Normal file
View File

@ -0,0 +1,12 @@
{
"site_pins": {
"CLK": {
"direction": "IN"
},
"CAP": {
"direction": "IN"
}
},
"site_pips": {},
"type": "CAPTURE"
}

12
artix7/site_type_DCIRESET.json Normal file
View File

@ -0,0 +1,12 @@
{
"site_pins": {
"LOCKED": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
}
},
"site_pips": {},
"type": "DCIRESET"
}

21
artix7/site_type_DNA_PORT.json Normal file
View File

@ -0,0 +1,21 @@
{
"site_pins": {
"READ": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"DIN": {
"direction": "IN"
},
"SHIFT": {
"direction": "IN"
},
"DOUT": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "DNA_PORT"
}

1402
artix7/site_type_DSP48E1.json Normal file
View File

File diff suppressed because it is too large Load Diff

102
artix7/site_type_EFUSE_USR.json Normal file
View File

@ -0,0 +1,102 @@
{
"site_pins": {
"EFUSEUSR14": {
"direction": "OUT"
},
"EFUSEUSR17": {
"direction": "OUT"
},
"EFUSEUSR0": {
"direction": "OUT"
},
"EFUSEUSR3": {
"direction": "OUT"
},
"EFUSEUSR11": {
"direction": "OUT"
},
"EFUSEUSR1": {
"direction": "OUT"
},
"EFUSEUSR25": {
"direction": "OUT"
},
"EFUSEUSR2": {
"direction": "OUT"
},
"EFUSEUSR10": {
"direction": "OUT"
},
"EFUSEUSR23": {
"direction": "OUT"
},
"EFUSEUSR21": {
"direction": "OUT"
},
"EFUSEUSR26": {
"direction": "OUT"
},
"EFUSEUSR30": {
"direction": "OUT"
},
"EFUSEUSR22": {
"direction": "OUT"
},
"EFUSEUSR9": {
"direction": "OUT"
},
"EFUSEUSR18": {
"direction": "OUT"
},
"EFUSEUSR7": {
"direction": "OUT"
},
"EFUSEUSR8": {
"direction": "OUT"
},
"EFUSEUSR27": {
"direction": "OUT"
},
"EFUSEUSR28": {
"direction": "OUT"
},
"EFUSEUSR31": {
"direction": "OUT"
},
"EFUSEUSR5": {
"direction": "OUT"
},
"EFUSEUSR20": {
"direction": "OUT"
},
"EFUSEUSR15": {
"direction": "OUT"
},
"EFUSEUSR12": {
"direction": "OUT"
},
"EFUSEUSR4": {
"direction": "OUT"
},
"EFUSEUSR16": {
"direction": "OUT"
},
"EFUSEUSR29": {
"direction": "OUT"
},
"EFUSEUSR13": {
"direction": "OUT"
},
"EFUSEUSR24": {
"direction": "OUT"
},
"EFUSEUSR19": {
"direction": "OUT"
},
"EFUSEUSR6": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "EFUSE_USR"
}

537
artix7/site_type_FIFO18E1.json Normal file
View File

@ -0,0 +1,537 @@
{
"site_pins": {
"WRCOUNT10": {
"direction": "OUT"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"DO20": {
"direction": "OUT"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"DIADI11": {
"direction": "IN"
},
"DO29": {
"direction": "OUT"
},
"DO21": {
"direction": "OUT"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"DO22": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"WEBWE5": {
"direction": "IN"
},
"DIADI7": {
"direction": "IN"
},
"RDCOUNT3": {
"direction": "OUT"
},
"DO27": {
"direction": "OUT"
},
"DIADI3": {
"direction": "IN"
},
"DO14": {
"direction": "OUT"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"DO19": {
"direction": "OUT"
},
"DIBDI8": {
"direction": "IN"
},
"DO6": {
"direction": "OUT"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"DIBDI5": {
"direction": "IN"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"RDERR": {
"direction": "OUT"
},
"DO24": {
"direction": "OUT"
},
"DIBDI7": {
"direction": "IN"
},
"WRCOUNT7": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"DIBDI11": {
"direction": "IN"
},
"DO12": {
"direction": "OUT"
},
"DIADI0": {
"direction": "IN"
},
"DO2": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"DO23": {
"direction": "OUT"
},
"WRCOUNT3": {
"direction": "OUT"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DOP3": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"DIPBDIP1": {
"direction": "IN"
},
"RDCLK": {
"direction": "IN"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"DIADI5": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"DIBDI14": {
"direction": "IN"
},
"WEA3": {
"direction": "IN"
},
"DIADI14": {
"direction": "IN"
},
"WEA0": {
"direction": "IN"
},
"DIADI1": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"RDCOUNT11": {
"direction": "OUT"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"WRCOUNT4": {
"direction": "OUT"
},
"WRCOUNT0": {
"direction": "OUT"
},
"DIPBDIP0": {
"direction": "IN"
},
"DOP1": {
"direction": "OUT"
},
"DIADI8": {
"direction": "IN"
},
"DO30": {
"direction": "OUT"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"DO4": {
"direction": "OUT"
},
"RDCOUNT7": {
"direction": "OUT"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"RSTREGB": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"DIBDI4": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"RDCOUNT2": {
"direction": "OUT"
},
"WEBWE6": {
"direction": "IN"
},
"REGCE": {
"direction": "IN"
},
"REGCLKB": {
"direction": "IN"
},
"RDCOUNT5": {
"direction": "OUT"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"WRCOUNT1": {
"direction": "OUT"
},
"DIBDI6": {
"direction": "IN"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"RDCOUNT4": {
"direction": "OUT"
},
"WEBWE3": {
"direction": "IN"
},
"RDRCLK": {
"direction": "IN"
},
"DO7": {
"direction": "OUT"
},
"DO25": {
"direction": "OUT"
},
"RSTRAMB": {
"direction": "IN"
},
"DIADI15": {
"direction": "IN"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"DIADI6": {
"direction": "IN"
},
"RDCOUNT0": {
"direction": "OUT"
},
"DO18": {
"direction": "OUT"
},
"RSTREG": {
"direction": "IN"
},
"RDCOUNT8": {
"direction": "OUT"
},
"WRCOUNT11": {
"direction": "OUT"
},
"WRCOUNT6": {
"direction": "OUT"
},
"REGCEB": {
"direction": "IN"
},
"DO8": {
"direction": "OUT"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"WRERR": {
"direction": "OUT"
},
"WEBWE0": {
"direction": "IN"
},
"DO13": {
"direction": "OUT"
},
"DIBDI2": {
"direction": "IN"
},
"DIBDI13": {
"direction": "IN"
},
"WRCOUNT5": {
"direction": "OUT"
},
"WRCOUNT9": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"DO17": {
"direction": "OUT"
},
"ADDRARDADDR0": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"DIBDI15": {
"direction": "IN"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"DO16": {
"direction": "OUT"
},
"DIBDI3": {
"direction": "IN"
},
"DO28": {
"direction": "OUT"
},
"DIBDI9": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"DO5": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"DOP0": {
"direction": "OUT"
},
"WEA2": {
"direction": "IN"
},
"DO31": {
"direction": "OUT"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"WEBWE7": {
"direction": "IN"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"WEBWE1": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DIADI2": {
"direction": "IN"
},
"DIPADIP1": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"DIADI13": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"WRCLK": {
"direction": "IN"
},
"WRCOUNT8": {
"direction": "OUT"
},
"DIADI4": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"RDCOUNT9": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DOP2": {
"direction": "OUT"
},
"DIPADIP0": {
"direction": "IN"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"WEBWE4": {
"direction": "IN"
},
"WREN": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"DIADI12": {
"direction": "IN"
},
"DO26": {
"direction": "OUT"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"DIADI9": {
"direction": "IN"
},
"DIBDI12": {
"direction": "IN"
}
},
"site_pips": {
"RDRCLKINV:RDRCLK": {
"from_pin": "RDRCLK",
"to_pin": "OUT"
},
"RDENINV:RDEN_B": {
"from_pin": "RDEN_B",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"RDCLKINV:RDCLK": {
"from_pin": "RDCLK",
"to_pin": "OUT"
},
"WRENINV:WREN_B": {
"from_pin": "WREN_B",
"to_pin": "OUT"
},
"RDRCLKINV:RDRCLK_B": {
"from_pin": "RDRCLK_B",
"to_pin": "OUT"
},
"RDENINV:RDEN": {
"from_pin": "RDEN",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK": {
"from_pin": "WRCLK",
"to_pin": "OUT"
},
"RSTREGINV:RSTREG": {
"from_pin": "RSTREG",
"to_pin": "OUT"
},
"RDCLKINV:RDCLK_B": {
"from_pin": "RDCLK_B",
"to_pin": "OUT"
},
"WRENINV:WREN": {
"from_pin": "WREN",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK_B": {
"from_pin": "WRCLK_B",
"to_pin": "OUT"
},
"RSTREGINV:RSTREG_B": {
"from_pin": "RSTREG_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "FIFO18E1"
}

171
artix7/site_type_FRAME_ECC.json Normal file
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@ -0,0 +1,171 @@
{
"site_pins": {
"FAR24": {
"direction": "OUT"
},
"SYNWORD5": {
"direction": "OUT"
},
"FAR5": {
"direction": "OUT"
},
"SYNWORD3": {
"direction": "OUT"
},
"FAR8": {
"direction": "OUT"
},
"SYNDROME12": {
"direction": "OUT"
},
"SYNWORD6": {
"direction": "OUT"
},
"FAR0": {
"direction": "OUT"
},
"CRCERROR": {
"direction": "OUT"
},
"FAR1": {
"direction": "OUT"
},
"FAR7": {
"direction": "OUT"
},
"FAR20": {
"direction": "OUT"
},
"FAR12": {
"direction": "OUT"
},
"SYNDROME7": {
"direction": "OUT"
},
"FAR13": {
"direction": "OUT"
},
"FAR22": {
"direction": "OUT"
},
"SYNDROMEVALID": {
"direction": "OUT"
},
"FAR19": {
"direction": "OUT"
},
"FAR6": {
"direction": "OUT"
},
"SYNDROME3": {
"direction": "OUT"
},
"SYNDROME0": {
"direction": "OUT"
},
"SYNDROME2": {
"direction": "OUT"
},
"FAR16": {
"direction": "OUT"
},
"SYNBIT1": {
"direction": "OUT"
},
"FAR2": {
"direction": "OUT"
},
"SYNDROME8": {
"direction": "OUT"
},
"SYNBIT4": {
"direction": "OUT"
},
"SYNBIT2": {
"direction": "OUT"
},
"SYNDROME6": {
"direction": "OUT"
},
"FAR9": {
"direction": "OUT"
},
"FAR23": {
"direction": "OUT"
},
"ECCERROR": {
"direction": "OUT"
},
"SYNWORD2": {
"direction": "OUT"
},
"FAR15": {
"direction": "OUT"
},
"FAR25": {
"direction": "OUT"
},
"FAR14": {
"direction": "OUT"
},
"SYNDROME1": {
"direction": "OUT"
},
"FAR21": {
"direction": "OUT"
},
"SYNDROME5": {
"direction": "OUT"
},
"FAR10": {
"direction": "OUT"
},
"SYNDROME4": {
"direction": "OUT"
},
"SYNDROME10": {
"direction": "OUT"
},
"SYNBIT0": {
"direction": "OUT"
},
"ECCERRORSINGLE": {
"direction": "OUT"
},
"FAR3": {
"direction": "OUT"
},
"SYNBIT3": {
"direction": "OUT"
},
"SYNDROME11": {
"direction": "OUT"
},
"SYNWORD4": {
"direction": "OUT"
},
"SYNWORD0": {
"direction": "OUT"
},
"SYNDROME9": {
"direction": "OUT"
},
"SYNWORD1": {
"direction": "OUT"
},
"FAR18": {
"direction": "OUT"
},
"FAR11": {
"direction": "OUT"
},
"FAR4": {
"direction": "OUT"
},
"FAR17": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "FRAME_ECC"
}

1874
artix7/site_type_GTPE2_CHANNEL.json Normal file
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542
artix7/site_type_GTPE2_COMMON.json Normal file
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@ -0,0 +1,542 @@
{
"site_pins": {
"PLL1REFCLKLOST": {
"direction": "OUT"
},
"BGRCALOVRD0": {
"direction": "IN"
},
"DRPDI4": {
"direction": "IN"
},
"DRPDO9": {
"direction": "OUT"
},
"DRPDO7": {
"direction": "OUT"
},
"PMASCANOUT4": {
"direction": "OUT"
},
"PMASCANCLK1": {
"direction": "IN"
},
"PMARSVDOUT4": {
"direction": "OUT"
},
"PLL0REFCLKSEL1": {
"direction": "IN"
},
"PLL0OUTCLK": {
"direction": "OUT"
},
"DRPDI11": {
"direction": "IN"
},
"PMARSVDOUT2": {
"direction": "OUT"
},
"PLL0LOCKDETCLK": {
"direction": "IN"
},
"PMARSVDOUT3": {
"direction": "OUT"
},
"DRPDI14": {
"direction": "IN"
},
"PMARSVDOUT11": {
"direction": "OUT"
},
"DMONITOROUT6": {
"direction": "OUT"
},
"PLLRSVD24": {
"direction": "IN"
},
"DRPDI1": {
"direction": "IN"
},
"BGRCALOVRD2": {
"direction": "IN"
},
"DRPDO1": {
"direction": "OUT"
},
"DMONITOROUT1": {
"direction": "OUT"
},
"PMASCANIN4": {
"direction": "IN"
},
"BGRCALOVRDENB": {
"direction": "IN"
},
"DRPADDR5": {
"direction": "IN"
},
"DRPDO3": {
"direction": "OUT"
},
"QDPMASCANMODEB": {
"direction": "IN"
},
"PMARSVDOUT0": {
"direction": "OUT"
},
"PMARSVDOUT1": {
"direction": "OUT"
},
"PLLRSVD114": {
"direction": "IN"
},
"REFCLKOUTMONITOR0": {
"direction": "OUT"
},
"DRPDO5": {
"direction": "OUT"
},
"PMARSVD6": {
"direction": "IN"
},
"DRPDO10": {
"direction": "OUT"
},
"PLL1REFCLKSEL2": {
"direction": "IN"
},
"DRPDO12": {
"direction": "OUT"
},
"PMASCANOUT0": {
"direction": "OUT"
},
"DRPDI12": {
"direction": "IN"
},
"PLL0LOCK": {
"direction": "OUT"
},
"PLL0PD": {
"direction": "IN"
},
"PLL0REFCLKSEL2": {
"direction": "IN"
},
"GTWESTREFCLK1": {
"direction": "IN"
},
"RCALENB": {
"direction": "IN"
},
"PMARSVD0": {
"direction": "IN"
},
"PLL1PD": {
"direction": "IN"
},
"PLL1OUTCLK": {
"direction": "OUT"
},
"DRPEN": {
"direction": "IN"
},
"DMONITOROUT3": {
"direction": "OUT"
},
"PMASCANIN1": {
"direction": "IN"
},
"PLL1RESET": {
"direction": "IN"
},
"BGBYPASSB": {
"direction": "IN"
},
"DRPWE": {
"direction": "IN"
},
"DRPDO6": {
"direction": "OUT"
},
"PLLRSVD22": {
"direction": "IN"
},
"DRPDI15": {
"direction": "IN"
},
"PMARSVDOUT15": {
"direction": "OUT"
},
"PLLRSVD14": {
"direction": "IN"
},
"PMASCANOUT1": {
"direction": "OUT"
},
"PMARSVDOUT9": {
"direction": "OUT"
},
"PMARSVDOUT14": {
"direction": "OUT"
},
"DRPDI8": {
"direction": "IN"
},
"PLLRSVD115": {
"direction": "IN"
},
"PLLRSVD10": {
"direction": "IN"
},
"DRPDI3": {
"direction": "IN"
},
"PLL0LOCKEN": {
"direction": "IN"
},
"DRPRDY": {
"direction": "OUT"
},
"BGPDB": {
"direction": "IN"
},
"DRPCLK": {
"direction": "IN"
},
"PMARSVD4": {
"direction": "IN"
},
"PMASCANOUT2": {
"direction": "OUT"
},
"DRPADDR4": {
"direction": "IN"
},
"PMARSVDOUT8": {
"direction": "OUT"
},
"DRPDO14": {
"direction": "OUT"
},
"PLLRSVD13": {
"direction": "IN"
},
"PLLRSVD12": {
"direction": "IN"
},
"DRPADDR2": {
"direction": "IN"
},
"PLLRSVD17": {
"direction": "IN"
},
"PLLRSVD23": {
"direction": "IN"
},
"PLLRSVD20": {
"direction": "IN"
},
"PMARSVD1": {
"direction": "IN"
},
"PMARSVD7": {
"direction": "IN"
},
"PLL1LOCKDETCLK": {
"direction": "IN"
},
"PLLRSVD112": {
"direction": "IN"
},
"PLLRSVD111": {
"direction": "IN"
},
"PLL1OUTREFCLK": {
"direction": "OUT"
},
"DRPADDR6": {
"direction": "IN"
},
"PMARSVD2": {
"direction": "IN"
},
"PLLRSVD21": {
"direction": "IN"
},
"PLL1LOCKEN": {
"direction": "IN"
},
"BGRCALOVRD1": {
"direction": "IN"
},
"DRPDI0": {
"direction": "IN"
},
"PMASCANIN0": {
"direction": "IN"
},
"PLLRSVD16": {
"direction": "IN"
},
"PLL1REFCLKSEL1": {
"direction": "IN"
},
"PMASCANIN2": {
"direction": "IN"
},
"DRPDI13": {
"direction": "IN"
},
"PMARSVD5": {
"direction": "IN"
},
"DRPDI9": {
"direction": "IN"
},
"DRPDO15": {
"direction": "OUT"
},
"PLL0REFCLKSEL0": {
"direction": "IN"
},
"PMARSVDOUT6": {
"direction": "OUT"
},
"DRPADDR3": {
"direction": "IN"
},
"DRPDO8": {
"direction": "OUT"
},
"PLLCLKSPARE": {
"direction": "IN"
},
"DRPDO11": {
"direction": "OUT"
},
"DMONITOROUT4": {
"direction": "OUT"
},
"GTEASTREFCLK1": {
"direction": "IN"
},
"GTEASTREFCLK0": {
"direction": "IN"
},
"PMARSVDOUT7": {
"direction": "OUT"
},
"DRPDI5": {
"direction": "IN"
},
"DMONITOROUT2": {
"direction": "OUT"
},
"DMONITOROUT7": {
"direction": "OUT"
},
"PMARSVD3": {
"direction": "IN"
},
"PMARSVDOUT10": {
"direction": "OUT"
},
"DRPDI6": {
"direction": "IN"
},
"GTGREFCLK0": {
"direction": "IN"
},
"PLLRSVD110": {
"direction": "IN"
},
"PLL1FBCLKLOST": {
"direction": "OUT"
},
"PLL0OUTREFCLK": {
"direction": "OUT"
},
"DRPDI10": {
"direction": "IN"
},
"PLL0FBCLKLOST": {
"direction": "OUT"
},
"DRPDI7": {
"direction": "IN"
},
"DRPDO2": {
"direction": "OUT"
},
"DRPADDR7": {
"direction": "IN"
},
"REFCLKOUTMONITOR1": {
"direction": "OUT"
},
"PLL0REFCLKLOST": {
"direction": "OUT"
},
"DRPDO13": {
"direction": "OUT"
},
"DMONITOROUT0": {
"direction": "OUT"
},
"PMASCANCLK0": {
"direction": "IN"
},
"QDPMASCANRSTEN": {
"direction": "IN"
},
"BGRCALOVRD3": {
"direction": "IN"
},
"DRPADDR1": {
"direction": "IN"
},
"PMASCANENB": {
"direction": "IN"
},
"GTGREFCLK1": {
"direction": "IN"
},
"GTWESTREFCLK0": {
"direction": "IN"
},
"DMONITOROUT5": {
"direction": "OUT"
},
"DRPDO0": {
"direction": "OUT"
},
"BGRCALOVRD4": {
"direction": "IN"
},
"PLL0RESET": {
"direction": "IN"
},
"PLLRSVD113": {
"direction": "IN"
},
"PMASCANIN3": {
"direction": "IN"
},
"DRPDI2": {
"direction": "IN"
},
"PMASCANOUT3": {
"direction": "OUT"
},
"BGMONITORENB": {
"direction": "IN"
},
"DRPDO4": {
"direction": "OUT"
},
"GTREFCLK1": {
"direction": "IN"
},
"PLL1REFCLKSEL0": {
"direction": "IN"
},
"PMARSVDOUT13": {
"direction": "OUT"
},
"DRPADDR0": {
"direction": "IN"
},
"PLL1LOCK": {
"direction": "OUT"
},
"PLLRSVD15": {
"direction": "IN"
},
"GTREFCLK0": {
"direction": "IN"
},
"PMARSVDOUT12": {
"direction": "OUT"
},
"PLLRSVD19": {
"direction": "IN"
},
"PLLRSVD11": {
"direction": "IN"
},
"PLLRSVD18": {
"direction": "IN"
},
"PMARSVDOUT5": {
"direction": "OUT"
}
},
"site_pips": {
"PLLCLKSPAREINV:PLLCLKSPARE_B": {
"from_pin": "PLLCLKSPARE_B",
"to_pin": "OUT"
},
"PMASCANCLK1INV:PMASCANCLK1": {
"from_pin": "PMASCANCLK1",
"to_pin": "OUT"
},
"DRPCLKINV:DRPCLK": {
"from_pin": "DRPCLK",
"to_pin": "OUT"
},
"DRPCLKINV:DRPCLK_B": {
"from_pin": "DRPCLK_B",
"to_pin": "OUT"
},
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK_B": {
"from_pin": "PLL1LOCKDETCLK_B",
"to_pin": "OUT"
},
"PMASCANCLK1INV:PMASCANCLK1_B": {
"from_pin": "PMASCANCLK1_B",
"to_pin": "OUT"
},
"GTGREFCLK0INV:GTGREFCLK0_B": {
"from_pin": "GTGREFCLK0_B",
"to_pin": "OUT"
},
"PMASCANCLK0INV:PMASCANCLK0_B": {
"from_pin": "PMASCANCLK0_B",
"to_pin": "OUT"
},
"GTGREFCLK0INV:GTGREFCLK0": {
"from_pin": "GTGREFCLK0",
"to_pin": "OUT"
},
"GTGREFCLK1INV:GTGREFCLK1_B": {
"from_pin": "GTGREFCLK1_B",
"to_pin": "OUT"
},
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK_B": {
"from_pin": "PLL0LOCKDETCLK_B",
"to_pin": "OUT"
},
"PLL0LOCKDETCLKINV:PLL0LOCKDETCLK": {
"from_pin": "PLL0LOCKDETCLK",
"to_pin": "OUT"
},
"PLLCLKSPAREINV:PLLCLKSPARE": {
"from_pin": "PLLCLKSPARE",
"to_pin": "OUT"
},
"PMASCANCLK0INV:PMASCANCLK0": {
"from_pin": "PMASCANCLK0",
"to_pin": "OUT"
},
"GTGREFCLK1INV:GTGREFCLK1": {
"from_pin": "GTGREFCLK1",
"to_pin": "OUT"
},
"PLL1LOCKDETCLKINV:PLL1LOCKDETCLK": {
"from_pin": "PLL1LOCKDETCLK",
"to_pin": "OUT"
}
},
"type": "GTPE2_COMMON"
}

33
artix7/site_type_IBUFDS_GTE2.json Normal file
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{
"site_pins": {
"O": {
"direction": "OUT"
},
"CLKTESTSIG": {
"direction": "IN"
},
"IB": {
"direction": "IN"
},
"CEB": {
"direction": "IN"
},
"ODIV2": {
"direction": "OUT"
},
"I": {
"direction": "IN"
}
},
"site_pips": {
"CLKTESTSIGINV:CLKTESTSIG": {
"from_pin": "CLKTESTSIG",
"to_pin": "OUT"
},
"CLKTESTSIGINV:CLKTESTSIG_B": {
"from_pin": "CLKTESTSIG_B",
"to_pin": "OUT"
}
},
"type": "IBUFDS_GTE2"
}

207
artix7/site_type_ICAP.json Normal file
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{
"site_pins": {
"O8": {
"direction": "OUT"
},
"O2": {
"direction": "OUT"
},
"O24": {
"direction": "OUT"
},
"I22": {
"direction": "IN"
},
"O16": {
"direction": "OUT"
},
"I20": {
"direction": "IN"
},
"O25": {
"direction": "OUT"
},
"O26": {
"direction": "OUT"
},
"O5": {
"direction": "OUT"
},
"O3": {
"direction": "OUT"
},
"I15": {
"direction": "IN"
},
"I17": {
"direction": "IN"
},
"O31": {
"direction": "OUT"
},
"I10": {
"direction": "IN"
},
"O18": {
"direction": "OUT"
},
"O12": {
"direction": "OUT"
},
"I19": {
"direction": "IN"
},
"I12": {
"direction": "IN"
},
"I28": {
"direction": "IN"
},
"I14": {
"direction": "IN"
},
"O30": {
"direction": "OUT"
},
"RDWRB": {
"direction": "IN"
},
"I29": {
"direction": "IN"
},
"I0": {
"direction": "IN"
},
"O0": {
"direction": "OUT"
},
"I18": {
"direction": "IN"
},
"I21": {
"direction": "IN"
},
"O14": {
"direction": "OUT"
},
"O11": {
"direction": "OUT"
},
"O17": {
"direction": "OUT"
},
"I8": {
"direction": "IN"
},
"I31": {
"direction": "IN"
},
"I1": {
"direction": "IN"
},
"I11": {
"direction": "IN"
},
"I3": {
"direction": "IN"
},
"O23": {
"direction": "OUT"
},
"O27": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"I30": {
"direction": "IN"
},
"I26": {
"direction": "IN"
},
"CSIB": {
"direction": "IN"
},
"I23": {
"direction": "IN"
},
"O9": {
"direction": "OUT"
},
"O13": {
"direction": "OUT"
},
"I5": {
"direction": "IN"
},
"O6": {
"direction": "OUT"
},
"O28": {
"direction": "OUT"
},
"O22": {
"direction": "OUT"
},
"O10": {
"direction": "OUT"
},
"O21": {
"direction": "OUT"
},
"O20": {
"direction": "OUT"
},
"I24": {
"direction": "IN"
},
"O7": {
"direction": "OUT"
},
"I9": {
"direction": "IN"
},
"I13": {
"direction": "IN"
},
"I7": {
"direction": "IN"
},
"I27": {
"direction": "IN"
},
"I25": {
"direction": "IN"
},
"O29": {
"direction": "OUT"
},
"O4": {
"direction": "OUT"
},
"I2": {
"direction": "IN"
},
"O1": {
"direction": "OUT"
},
"I16": {
"direction": "IN"
},
"I4": {
"direction": "IN"
},
"O15": {
"direction": "OUT"
},
"I6": {
"direction": "IN"
},
"O19": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "ICAP"
}

27
artix7/site_type_IDELAYCTRL.json Normal file
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{
"site_pins": {
"OUTN65": {
"direction": "OUT"
},
"OUTN1": {
"direction": "OUT"
},
"DNPULSEOUT": {
"direction": "OUT"
},
"UPPULSEOUT": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"REFCLK": {
"direction": "IN"
},
"RDY": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "IDELAYCTRL"
}

100
artix7/site_type_IDELAYE2.json Normal file
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@ -0,0 +1,100 @@
{
"site_pins": {
"CNTVALUEOUT4": {
"direction": "OUT"
},
"INC": {
"direction": "IN"
},
"REGRST": {
"direction": "IN"
},
"CNTVALUEIN3": {
"direction": "IN"
},
"IDATAIN": {
"direction": "IN"
},
"CNTVALUEIN0": {
"direction": "IN"
},
"CNTVALUEOUT1": {
"direction": "OUT"
},
"IFDLY1": {
"direction": "IN"
},
"IFDLY2": {
"direction": "IN"
},
"LD": {
"direction": "IN"
},
"DATAOUT": {
"direction": "OUT"
},
"CNTVALUEIN2": {
"direction": "IN"
},
"C": {
"direction": "IN"
},
"CNTVALUEOUT3": {
"direction": "OUT"
},
"CNTVALUEOUT2": {
"direction": "OUT"
},
"IFDLY0": {
"direction": "IN"
},
"CNTVALUEIN1": {
"direction": "IN"
},
"LDPIPEEN": {
"direction": "IN"
},
"CNTVALUEOUT0": {
"direction": "OUT"
},
"DATAIN": {
"direction": "IN"
},
"CINVCTRL": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"CNTVALUEIN4": {
"direction": "IN"
}
},
"site_pips": {
"CINV:C_B": {
"from_pin": "C_B",
"to_pin": "OUT"
},
"DATAININV:DATAIN": {
"from_pin": "DATAIN",
"to_pin": "OUT"
},
"CINV:C": {
"from_pin": "C",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN_B": {
"from_pin": "IDATAIN_B",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN": {
"from_pin": "IDATAIN",
"to_pin": "OUT"
},
"DATAININV:DATAIN_B": {
"from_pin": "DATAIN_B",
"to_pin": "OUT"
}
},
"type": "IDELAYE2"
}

208
artix7/site_type_ILOGICE3.json Normal file
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{
"site_pins": {
"SHIFTOUT2": {
"direction": "OUT"
},
"Q4": {
"direction": "OUT"
},
"SHIFTIN1": {
"direction": "IN"
},
"Q6": {
"direction": "OUT"
},
"Q7": {
"direction": "OUT"
},
"OCLKB": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"DDLY": {
"direction": "IN"
},
"CE2": {
"direction": "IN"
},
"OFB": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"BITSLIP": {
"direction": "IN"
},
"Q8": {
"direction": "OUT"
},
"OCLK": {
"direction": "IN"
},
"D": {
"direction": "IN"
},
"TFB": {
"direction": "IN"
},
"DYNCLKDIVPSEL": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"DYNCLKDIVSEL": {
"direction": "IN"
},
"CLKDIV": {
"direction": "IN"
},
"REV": {
"direction": "IN"
},
"Q1": {
"direction": "OUT"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"CLKDIVP": {
"direction": "IN"
},
"DYNCLKSEL": {
"direction": "IN"
},
"Q5": {
"direction": "OUT"
},
"SHIFTIN2": {
"direction": "IN"
},
"Q2": {
"direction": "OUT"
},
"Q3": {
"direction": "OUT"
}
},
"site_pips": {
"IFFDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
},
"IDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"CLKBINV:CLKB": {
"from_pin": "CLKB",
"to_pin": "OUT"
},
"IMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"REVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2OBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IFFMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"IDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"SRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DINV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"IFFMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKBINV:CLKB_B": {
"from_pin": "CLKB_B",
"to_pin": "OUT"
},
"IMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CE1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"DINV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"D2OBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
}
},
"type": "ILOGICE3"
}

453
artix7/site_type_IN_FIFO.json Normal file
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@ -0,0 +1,453 @@
{
"site_pins": {
"TESTMODEB": {
"direction": "IN"
},
"Q71": {
"direction": "OUT"
},
"Q46": {
"direction": "OUT"
},
"Q93": {
"direction": "OUT"
},
"Q97": {
"direction": "OUT"
},
"D52": {
"direction": "IN"
},
"D51": {
"direction": "IN"
},
"D57": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"Q15": {
"direction": "OUT"
},
"D43": {
"direction": "IN"
},
"Q56": {
"direction": "OUT"
},
"D32": {
"direction": "IN"
},
"Q87": {
"direction": "OUT"
},
"Q73": {
"direction": "OUT"
},
"Q23": {
"direction": "OUT"
},
"Q30": {
"direction": "OUT"
},
"D53": {
"direction": "IN"
},
"Q51": {
"direction": "OUT"
},
"Q57": {
"direction": "OUT"
},
"Q01": {
"direction": "OUT"
},
"Q77": {
"direction": "OUT"
},
"D30": {
"direction": "IN"
},
"Q35": {
"direction": "OUT"
},
"Q82": {
"direction": "OUT"
},
"Q26": {
"direction": "OUT"
},
"Q75": {
"direction": "OUT"
},
"Q24": {
"direction": "OUT"
},
"Q04": {
"direction": "OUT"
},
"Q40": {
"direction": "OUT"
},
"D65": {
"direction": "IN"
},
"Q43": {
"direction": "OUT"
},
"Q14": {
"direction": "OUT"
},
"Q96": {
"direction": "OUT"
},
"D10": {
"direction": "IN"
},
"Q81": {
"direction": "OUT"
},
"TESTREADDISB": {
"direction": "IN"
},
"Q06": {
"direction": "OUT"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"RDCLK": {
"direction": "IN"
},
"Q63": {
"direction": "OUT"
},
"Q60": {
"direction": "OUT"
},
"D42": {
"direction": "IN"
},
"Q64": {
"direction": "OUT"
},
"Q07": {
"direction": "OUT"
},
"D56": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"Q47": {
"direction": "OUT"
},
"Q91": {
"direction": "OUT"
},
"Q55": {
"direction": "OUT"
},
"SCANIN2": {
"direction": "IN"
},
"Q17": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
},
"Q61": {
"direction": "OUT"
},
"D64": {
"direction": "IN"
},
"Q33": {
"direction": "OUT"
},
"D91": {
"direction": "IN"
},
"Q92": {
"direction": "OUT"
},
"D66": {
"direction": "IN"
},
"Q21": {
"direction": "OUT"
},
"D11": {
"direction": "IN"
},
"Q74": {
"direction": "OUT"
},
"Q83": {
"direction": "OUT"
},
"Q95": {
"direction": "OUT"
},
"D54": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"SCANOUT2": {
"direction": "OUT"
},
"Q67": {
"direction": "OUT"
},
"Q90": {
"direction": "OUT"
},
"Q62": {
"direction": "OUT"
},
"D60": {
"direction": "IN"
},
"D93": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"Q45": {
"direction": "OUT"
},
"Q12": {
"direction": "OUT"
},
"D03": {
"direction": "IN"
},
"Q36": {
"direction": "OUT"
},
"Q27": {
"direction": "OUT"
},
"Q41": {
"direction": "OUT"
},
"D23": {
"direction": "IN"
},
"Q34": {
"direction": "OUT"
},
"Q13": {
"direction": "OUT"
},
"Q54": {
"direction": "OUT"
},
"SCANENB": {
"direction": "IN"
},
"Q52": {
"direction": "OUT"
},
"Q32": {
"direction": "OUT"
},
"SCANIN0": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"D72": {
"direction": "IN"
},
"D20": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D82": {
"direction": "IN"
},
"D21": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"Q31": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"D01": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"D92": {
"direction": "IN"
},
"D61": {
"direction": "IN"
},
"Q84": {
"direction": "OUT"
},
"Q05": {
"direction": "OUT"
},
"SCANOUT3": {
"direction": "OUT"
},
"D40": {
"direction": "IN"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"Q85": {
"direction": "OUT"
},
"D80": {
"direction": "IN"
},
"Q42": {
"direction": "OUT"
},
"D41": {
"direction": "IN"
},
"D00": {
"direction": "IN"
},
"Q53": {
"direction": "OUT"
},
"Q50": {
"direction": "OUT"
},
"Q94": {
"direction": "OUT"
},
"D02": {
"direction": "IN"
},
"Q37": {
"direction": "OUT"
},
"SCANIN1": {
"direction": "IN"
},
"Q25": {
"direction": "OUT"
},
"D67": {
"direction": "IN"
},
"D33": {
"direction": "IN"
},
"Q66": {
"direction": "OUT"
},
"D70": {
"direction": "IN"
},
"D55": {
"direction": "IN"
},
"D12": {
"direction": "IN"
},
"Q80": {
"direction": "OUT"
},
"Q20": {
"direction": "OUT"
},
"SCANOUT1": {
"direction": "OUT"
},
"WREN": {
"direction": "IN"
},
"Q03": {
"direction": "OUT"
},
"Q16": {
"direction": "OUT"
},
"D83": {
"direction": "IN"
},
"Q86": {
"direction": "OUT"
},
"WRCLK": {
"direction": "IN"
},
"D22": {
"direction": "IN"
},
"Q10": {
"direction": "OUT"
},
"D50": {
"direction": "IN"
},
"D71": {
"direction": "IN"
},
"Q02": {
"direction": "OUT"
},
"Q70": {
"direction": "OUT"
},
"D63": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"Q44": {
"direction": "OUT"
},
"Q76": {
"direction": "OUT"
},
"D31": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"Q00": {
"direction": "OUT"
},
"D62": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"Q72": {
"direction": "OUT"
},
"Q65": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "IN_FIFO"
}

94
artix7/site_type_IOB33.json Normal file
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@ -0,0 +1,94 @@
{
"site_pins": {
"PADOUT": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"I": {
"direction": "OUT"
},
"T_IN": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFFI_IN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
}
},
"site_pips": {
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
}
},
"type": "IOB33"
}

106
artix7/site_type_IOB33M.json Normal file
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@ -0,0 +1,106 @@
{
"site_pins": {
"PADOUT": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"I": {
"direction": "OUT"
},
"T_IN": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFFI_IN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
}
},
"site_pips": {
"DIFFO_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"O_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "IOB33M"
}

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{
"site_pins": {
"PADOUT": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"I": {
"direction": "OUT"
},
"T_IN": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFFI_IN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
}
},
"site_pips": {
"OUTMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"TINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"OUTMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFO_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "IOB33S"
}

9
artix7/site_type_IPAD.json Normal file
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{
"site_pins": {
"O": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "IPAD"
}

545
artix7/site_type_MMCME2_ADV.json Normal file
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@ -0,0 +1,545 @@
{
"site_pins": {
"TESTIN4": {
"direction": "IN"
},
"TESTIN23": {
"direction": "IN"
},
"DO6": {
"direction": "OUT"
},
"TESTIN14": {
"direction": "IN"
},
"TESTOUT38": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"DO3": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"DI15": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"TESTOUT55": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"TESTIN28": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"TESTOUT12": {
"direction": "OUT"
},
"CLKFBOUTB": {
"direction": "OUT"
},
"DADDR4": {
"direction": "IN"
},
"TESTOUT37": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"DADDR2": {
"direction": "IN"
},
"TESTOUT54": {
"direction": "OUT"
},
"DCLK": {
"direction": "IN"
},
"CLKOUT3": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"TESTOUT62": {
"direction": "OUT"
},
"TESTOUT28": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"CLKFBOUT": {
"direction": "OUT"
},
"TESTIN27": {
"direction": "IN"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTOUT14": {
"direction": "OUT"
},
"DI9": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"TESTOUT57": {
"direction": "OUT"
},
"DI13": {
"direction": "IN"
},
"TESTIN29": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"DO15": {
"direction": "OUT"
},
"DI4": {
"direction": "IN"
},
"TESTOUT48": {
"direction": "OUT"
},
"DI1": {
"direction": "IN"
},
"TESTOUT4": {
"direction": "OUT"
},
"DADDR6": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"TESTOUT22": {
"direction": "OUT"
},
"TESTIN22": {
"direction": "IN"
},
"CLKINSTOPPED": {
"direction": "OUT"
},
"TESTOUT21": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"DO1": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTIN26": {
"direction": "IN"
},
"TESTIN20": {
"direction": "IN"
},
"TESTOUT32": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"TESTIN17": {
"direction": "IN"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT13": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"CLKOUT3B": {
"direction": "OUT"
},
"TESTOUT15": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"DO4": {
"direction": "OUT"
},
"DADDR3": {
"direction": "IN"
},
"PSEN": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"TESTIN12": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"TESTIN16": {
"direction": "IN"
},
"DEN": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"DO14": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"TESTOUT19": {
"direction": "OUT"
},
"TESTOUT60": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"CLKOUT0": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"PSDONE": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DI2": {
"direction": "IN"
},
"DO7": {
"direction": "OUT"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN30": {
"direction": "IN"
},
"TESTIN31": {
"direction": "IN"
},
"TESTOUT46": {
"direction": "OUT"
},
"CLKOUT2B": {
"direction": "OUT"
},
"TESTIN19": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTOUT16": {
"direction": "OUT"
},
"TESTOUT45": {
"direction": "OUT"
},
"CLKOUT1B": {
"direction": "OUT"
},
"CLKOUT4": {
"direction": "OUT"
},
"CLKOUT6": {
"direction": "OUT"
},
"TESTIN11": {
"direction": "IN"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTOUT36": {
"direction": "OUT"
},
"TESTIN21": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"DO8": {
"direction": "OUT"
},
"CLKINSEL": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"PSINCDEC": {
"direction": "IN"
},
"CLKIN1": {
"direction": "IN"
},
"DO13": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"TESTOUT34": {
"direction": "OUT"
},
"TESTOUT50": {
"direction": "OUT"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTIN10": {
"direction": "IN"
},
"CLKOUT0B": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTOUT9": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT63": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"DI5": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTOUT31": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"CLKIN2": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTIN18": {
"direction": "IN"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT29": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"DO0": {
"direction": "OUT"
},
"TESTOUT30": {
"direction": "OUT"
},
"DI3": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"CLKFBSTOPPED": {
"direction": "OUT"
},
"TESTOUT8": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"DI8": {
"direction": "IN"
},
"TESTOUT53": {
"direction": "OUT"
},
"DADDR1": {
"direction": "IN"
},
"CLKOUT2": {
"direction": "OUT"
},
"CLKFBIN": {
"direction": "IN"
},
"TESTOUT26": {
"direction": "OUT"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT42": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTIN25": {
"direction": "IN"
},
"TESTOUT41": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
},
"PSCLK": {
"direction": "IN"
}
},
"site_pips": {
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC_B": {
"from_pin": "PSINCDEC_B",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"PSENINV:PSEN_B": {
"from_pin": "PSEN_B",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PSENINV:PSEN": {
"from_pin": "PSEN",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC": {
"from_pin": "PSINCDEC",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "MMCME2_ADV"
}

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artix7/site_type_OLOGICE3.json Normal file
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{
"site_pins": {
"OCE": {
"direction": "IN"
},
"CLKDIVF": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"TQ": {
"direction": "OUT"
},
"SHIFTIN1": {
"direction": "IN"
},
"T2": {
"direction": "IN"
},
"TBYTEOUT": {
"direction": "OUT"
},
"CLKDIV": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"OFB": {
"direction": "OUT"
},
"CLKDIVFB": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"T4": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"TFB": {
"direction": "OUT"
},
"D4": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"T1": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"OQ": {
"direction": "OUT"
},
"CLKDIVB": {
"direction": "IN"
},
"REV": {
"direction": "IN"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"TBYTEIN": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"IOCLKGLITCH": {
"direction": "OUT"
},
"D8": {
"direction": "IN"
},
"T3": {
"direction": "IN"
},
"TCE": {
"direction": "IN"
},
"SHIFTIN2": {
"direction": "IN"
},
"D7": {
"direction": "IN"
}
},
"site_pips": {
"T2INV:T2_B": {
"from_pin": "T2_B",
"to_pin": "OUT"
},
"T1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2INV:D2": {
"from_pin": "D2",
"to_pin": "OUT"
},
"T1INV:T1_B": {
"from_pin": "T1_B",
"to_pin": "OUT"
},
"OMUX:OUTFF": {
"from_pin": "OUTFF",
"to_pin": "OUT"
},
"OMUX:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"D1INV:D1_B": {
"from_pin": "D1_B",
"to_pin": "OUT"
},
"OCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T2INV:T2": {
"from_pin": "T2",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"OREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TMUX:TFF": {
"from_pin": "TFF",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"D2INV:D2_B": {
"from_pin": "D2_B",
"to_pin": "OUT"
},
"TSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"O1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"D1INV:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"TMUX:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"OSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "OLOGICE3"
}

9
artix7/site_type_OPAD.json Normal file
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{
"site_pins": {
"I": {
"direction": "IN"
}
},
"site_pips": {},
"type": "OPAD"
}

453
artix7/site_type_OUT_FIFO.json Normal file
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@ -0,0 +1,453 @@
{
"site_pins": {
"D47": {
"direction": "IN"
},
"D24": {
"direction": "IN"
},
"D15": {
"direction": "IN"
},
"D97": {
"direction": "IN"
},
"D35": {
"direction": "IN"
},
"D51": {
"direction": "IN"
},
"D96": {
"direction": "IN"
},
"Q93": {
"direction": "OUT"
},
"D17": {
"direction": "IN"
},
"Q56": {
"direction": "OUT"
},
"D86": {
"direction": "IN"
},
"D05": {
"direction": "IN"
},
"D32": {
"direction": "IN"
},
"Q73": {
"direction": "OUT"
},
"Q23": {
"direction": "OUT"
},
"Q30": {
"direction": "OUT"
},
"D07": {
"direction": "IN"
},
"D53": {
"direction": "IN"
},
"D37": {
"direction": "IN"
},
"D83": {
"direction": "IN"
},
"Q01": {
"direction": "OUT"
},
"TESTMODEB": {
"direction": "IN"
},
"D30": {
"direction": "IN"
},
"D52": {
"direction": "IN"
},
"Q82": {
"direction": "OUT"
},
"D25": {
"direction": "IN"
},
"Q33": {
"direction": "OUT"
},
"D65": {
"direction": "IN"
},
"Q43": {
"direction": "OUT"
},
"D46": {
"direction": "IN"
},
"D66": {
"direction": "IN"
},
"D54": {
"direction": "IN"
},
"D10": {
"direction": "IN"
},
"Q81": {
"direction": "OUT"
},
"D36": {
"direction": "IN"
},
"Q65": {
"direction": "OUT"
},
"SCANOUT1": {
"direction": "OUT"
},
"D06": {
"direction": "IN"
},
"RDCLK": {
"direction": "IN"
},
"Q63": {
"direction": "OUT"
},
"Q60": {
"direction": "OUT"
},
"Q80": {
"direction": "OUT"
},
"D42": {
"direction": "IN"
},
"Q64": {
"direction": "OUT"
},
"SCANOUT3": {
"direction": "OUT"
},
"D56": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"Q91": {
"direction": "OUT"
},
"Q55": {
"direction": "OUT"
},
"SCANIN2": {
"direction": "IN"
},
"Q02": {
"direction": "OUT"
},
"D74": {
"direction": "IN"
},
"Q61": {
"direction": "OUT"
},
"D64": {
"direction": "IN"
},
"D43": {
"direction": "IN"
},
"D91": {
"direction": "IN"
},
"Q92": {
"direction": "OUT"
},
"D45": {
"direction": "IN"
},
"Q21": {
"direction": "OUT"
},
"D11": {
"direction": "IN"
},
"D84": {
"direction": "IN"
},
"Q83": {
"direction": "OUT"
},
"Q72": {
"direction": "OUT"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"Q70": {
"direction": "OUT"
},
"SCANOUT2": {
"direction": "OUT"
},
"D87": {
"direction": "IN"
},
"Q67": {
"direction": "OUT"
},
"Q90": {
"direction": "OUT"
},
"Q62": {
"direction": "OUT"
},
"D60": {
"direction": "IN"
},
"D93": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"Q12": {
"direction": "OUT"
},
"D03": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"D34": {
"direction": "IN"
},
"Q41": {
"direction": "OUT"
},
"D23": {
"direction": "IN"
},
"Q13": {
"direction": "OUT"
},
"Q54": {
"direction": "OUT"
},
"D44": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"Q52": {
"direction": "OUT"
},
"Q40": {
"direction": "OUT"
},
"D27": {
"direction": "IN"
},
"SCANIN0": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"D72": {
"direction": "IN"
},
"D20": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D82": {
"direction": "IN"
},
"D21": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"Q31": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"D01": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"D14": {
"direction": "IN"
},
"D61": {
"direction": "IN"
},
"D04": {
"direction": "IN"
},
"D16": {
"direction": "IN"
},
"D40": {
"direction": "IN"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"D85": {
"direction": "IN"
},
"D77": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"D80": {
"direction": "IN"
},
"D94": {
"direction": "IN"
},
"Q42": {
"direction": "OUT"
},
"D41": {
"direction": "IN"
},
"D76": {
"direction": "IN"
},
"D00": {
"direction": "IN"
},
"Q53": {
"direction": "OUT"
},
"Q50": {
"direction": "OUT"
},
"SCANIN1": {
"direction": "IN"
},
"D63": {
"direction": "IN"
},
"D02": {
"direction": "IN"
},
"D92": {
"direction": "IN"
},
"D67": {
"direction": "IN"
},
"D33": {
"direction": "IN"
},
"Q66": {
"direction": "OUT"
},
"D70": {
"direction": "IN"
},
"D55": {
"direction": "IN"
},
"D12": {
"direction": "IN"
},
"Q51": {
"direction": "OUT"
},
"Q20": {
"direction": "OUT"
},
"WREN": {
"direction": "IN"
},
"Q03": {
"direction": "OUT"
},
"Q71": {
"direction": "OUT"
},
"D57": {
"direction": "IN"
},
"Q57": {
"direction": "OUT"
},
"D22": {
"direction": "IN"
},
"Q32": {
"direction": "OUT"
},
"D50": {
"direction": "IN"
},
"D71": {
"direction": "IN"
},
"TESTREADDISB": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"D31": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"Q00": {
"direction": "OUT"
},
"D62": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"D95": {
"direction": "IN"
},
"D75": {
"direction": "IN"
},
"D26": {
"direction": "IN"
},
"Q10": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "OUT_FIFO"
}

6753
artix7/site_type_PCIE_2_1.json Normal file
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291
artix7/site_type_PHASER_IN_PHY.json Normal file
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{
"site_pins": {
"TESTIN4": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"EDGEADV": {
"direction": "IN"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"FINEENABLE": {
"direction": "IN"
},
"DQSFOUND": {
"direction": "OUT"
},
"STG1REGL1": {
"direction": "IN"
},
"STG1REGL8": {
"direction": "IN"
},
"TESTOUT2": {
"direction": "OUT"
},
"STG1INCDEC": {
"direction": "IN"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"STG1REGL5": {
"direction": "IN"
},
"ENSTG1ADJUSTB": {
"direction": "IN"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"ICLK": {
"direction": "OUT"
},
"STG1REGL6": {
"direction": "IN"
},
"PHASEREFCLK": {
"direction": "IN"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"DQSOUTOFRANGE": {
"direction": "OUT"
},
"STG1REGL2": {
"direction": "IN"
},
"MEMREFCLK": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"PHASELOCKED": {
"direction": "OUT"
},
"STG1REGR3": {
"direction": "OUT"
},
"DIVIDERST": {
"direction": "IN"
},
"TESTOUT1": {
"direction": "OUT"
},
"ENSTG1": {
"direction": "IN"
},
"STG1REGL4": {
"direction": "IN"
},
"STG1REGR6": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"RANKSEL1": {
"direction": "IN"
},
"STG1REGR0": {
"direction": "OUT"
},
"STG1REGR2": {
"direction": "OUT"
},
"STG1REGR8": {
"direction": "OUT"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"COUNTERREADEN": {
"direction": "IN"
},
"SCANCLK": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"STG1OVERFLOW": {
"direction": "OUT"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"TESTIN0": {
"direction": "IN"
},
"STG1REGR1": {
"direction": "OUT"
},
"RSTDQSFIND": {
"direction": "IN"
},
"RANKSELPHY1": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"ICLKDIV": {
"direction": "OUT"
},
"BURSTPENDING": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"SYSCLK": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"ENCALIB1": {
"direction": "IN"
},
"STG1REGR7": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"STG1REGL0": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"RANKSEL0": {
"direction": "IN"
},
"STG1REGL7": {
"direction": "IN"
},
"RCLK": {
"direction": "OUT"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"STG1LOAD": {
"direction": "IN"
},
"FINEINC": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"STG1REGL3": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"STG1READ": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"SELCALORSTG1": {
"direction": "IN"
},
"STG1REGR5": {
"direction": "OUT"
},
"WRENABLE": {
"direction": "OUT"
},
"ISERDESRST": {
"direction": "OUT"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"FREQREFCLK": {
"direction": "IN"
},
"RANKSELPHY0": {
"direction": "IN"
},
"STG1REGR4": {
"direction": "OUT"
}
},
"site_pips": {
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "PHASER_IN_PHY"
}

246
artix7/site_type_PHASER_OUT_PHY.json Normal file
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@ -0,0 +1,246 @@
{
"site_pins": {
"TESTIN4": {
"direction": "IN"
},
"OCLKDIV": {
"direction": "OUT"
},
"ENCALIB1": {
"direction": "IN"
},
"SELFINEOCLKDELAY": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"DTSBUS0": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"FINEENABLE": {
"direction": "IN"
},
"COARSEOVERFLOW": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"OCLK": {
"direction": "OUT"
},
"BURSTPENDING": {
"direction": "IN"
},
"TESTOUT2": {
"direction": "OUT"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"SYSCLK": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"OCLKDELAYED": {
"direction": "OUT"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"TESTOUT0": {
"direction": "OUT"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"COARSEENABLE": {
"direction": "IN"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"COUNTERLOADVAL6": {
"direction": "IN"
},
"RDENABLE": {
"direction": "OUT"
},
"COUNTERLOADVAL8": {
"direction": "IN"
},
"PHASEREFCLK": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"COUNTERREADVAL6": {
"direction": "OUT"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"OSERDESRST": {
"direction": "OUT"
},
"CTSBUS1": {
"direction": "OUT"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"MEMREFCLK": {
"direction": "IN"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"COUNTERREADVAL7": {
"direction": "OUT"
},
"FINEINC": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"EDGEADV": {
"direction": "IN"
},
"CTSBUS0": {
"direction": "OUT"
},
"TESTIN7": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"DIVIDERST": {
"direction": "IN"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTIN10": {
"direction": "IN"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"DQSBUS0": {
"direction": "OUT"
},
"DTSBUS1": {
"direction": "OUT"
},
"COARSEINC": {
"direction": "IN"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"COUNTERLOADVAL7": {
"direction": "IN"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"DQSBUS1": {
"direction": "OUT"
},
"TESTIN12": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"FREQREFCLK": {
"direction": "IN"
},
"COUNTERREADVAL8": {
"direction": "OUT"
},
"COUNTERREADEN": {
"direction": "IN"
},
"SCANCLK": {
"direction": "IN"
}
},
"site_pips": {
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "PHASER_OUT_PHY"
}

89
artix7/site_type_PHASER_REF.json Normal file
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{
"site_pins": {
"TESTIN4": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"CLKOUT": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TMUXOUT": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"LOCKED": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"CLKIN": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
}
},
"site_pips": {
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "PHASER_REF"
}

318
artix7/site_type_PHY_CONTROL.json Normal file
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@ -0,0 +1,318 @@
{
"site_pins": {
"INRANKA0": {
"direction": "OUT"
},
"TESTOUTPUT4": {
"direction": "OUT"
},
"INRANKD0": {
"direction": "OUT"
},
"TESTOUTPUT15": {
"direction": "OUT"
},
"PHYCTLWD20": {
"direction": "IN"
},
"PHYCTLWD8": {
"direction": "IN"
},
"TESTOUTPUT10": {
"direction": "OUT"
},
"TESTOUTPUT9": {
"direction": "OUT"
},
"PHYCTLWD9": {
"direction": "IN"
},
"PHYCTLWD6": {
"direction": "IN"
},
"TESTINPUT14": {
"direction": "IN"
},
"OUTBURSTPENDING2": {
"direction": "OUT"
},
"INBURSTPENDING2": {
"direction": "OUT"
},
"TESTINPUT1": {
"direction": "IN"
},
"TESTINPUT5": {
"direction": "IN"
},
"INBURSTPENDING1": {
"direction": "OUT"
},
"TESTOUTPUT13": {
"direction": "OUT"
},
"INRANKB1": {
"direction": "OUT"
},
"AUXOUTPUT2": {
"direction": "OUT"
},
"PHYCTLWD27": {
"direction": "IN"
},
"PHYCTLWD23": {
"direction": "IN"
},
"PHYCTLWD17": {
"direction": "IN"
},
"PHYCTLWD22": {
"direction": "IN"
},
"PHYCTLWD15": {
"direction": "IN"
},
"TESTINPUT3": {
"direction": "IN"
},
"TESTOUTPUT11": {
"direction": "OUT"
},
"PHYCTLWD18": {
"direction": "IN"
},
"PHYCTLWD30": {
"direction": "IN"
},
"TESTINPUT15": {
"direction": "IN"
},
"MEMREFCLK": {
"direction": "IN"
},
"PHYCTLWD4": {
"direction": "IN"
},
"REFDLLLOCK": {
"direction": "IN"
},
"PHYCTLWD12": {
"direction": "IN"
},
"PLLLOCK": {
"direction": "IN"
},
"PHYCTLWRENABLE": {
"direction": "IN"
},
"TESTINPUT7": {
"direction": "IN"
},
"PHYCTLWD0": {
"direction": "IN"
},
"OUTBURSTPENDING0": {
"direction": "OUT"
},
"INRANKB0": {
"direction": "OUT"
},
"TESTOUTPUT14": {
"direction": "OUT"
},
"TESTOUTPUT7": {
"direction": "OUT"
},
"PHYCTLWD1": {
"direction": "IN"
},
"TESTINPUT0": {
"direction": "IN"
},
"PHYCTLWD14": {
"direction": "IN"
},
"OUTBURSTPENDING1": {
"direction": "OUT"
},
"TESTINPUT12": {
"direction": "IN"
},
"AUXOUTPUT1": {
"direction": "OUT"
},
"PHYCTLWD25": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"TESTSELECT0": {
"direction": "IN"
},
"PHYCTLALMOSTFULL": {
"direction": "OUT"
},
"PHYCTLWD3": {
"direction": "IN"
},
"PHYCLK": {
"direction": "IN"
},
"PCENABLECALIB0": {
"direction": "OUT"
},
"PHYCTLWD11": {
"direction": "IN"
},
"TESTINPUT10": {
"direction": "IN"
},
"PHYCTLREADY": {
"direction": "OUT"
},
"INRANKD1": {
"direction": "OUT"
},
"TESTOUTPUT6": {
"direction": "OUT"
},
"PHYCTLWD2": {
"direction": "IN"
},
"PCENABLECALIB1": {
"direction": "OUT"
},
"TESTOUTPUT2": {
"direction": "OUT"
},
"READCALIBENABLE": {
"direction": "IN"
},
"PHYCTLWD10": {
"direction": "IN"
},
"PHYCTLWD7": {
"direction": "IN"
},
"INRANKC0": {
"direction": "OUT"
},
"AUXOUTPUT0": {
"direction": "OUT"
},
"TESTOUTPUT8": {
"direction": "OUT"
},
"TESTSELECT1": {
"direction": "IN"
},
"PHYCTLWD13": {
"direction": "IN"
},
"PHYCTLWD29": {
"direction": "IN"
},
"TESTINPUT9": {
"direction": "IN"
},
"TESTINPUT6": {
"direction": "IN"
},
"WRITECALIBENABLE": {
"direction": "IN"
},
"TESTOUTPUT0": {
"direction": "OUT"
},
"INRANKA1": {
"direction": "OUT"
},
"TESTOUTPUT1": {
"direction": "OUT"
},
"INBURSTPENDING0": {
"direction": "OUT"
},
"TESTINPUT13": {
"direction": "IN"
},
"TESTINPUT2": {
"direction": "IN"
},
"OUTBURSTPENDING3": {
"direction": "OUT"
},
"PHYCTLWD26": {
"direction": "IN"
},
"PHYCTLMSTREMPTY": {
"direction": "IN"
},
"TESTINPUT8": {
"direction": "IN"
},
"PHYCTLWD28": {
"direction": "IN"
},
"TESTSELECT2": {
"direction": "IN"
},
"SCANENABLEN": {
"direction": "IN"
},
"PHYCTLWD5": {
"direction": "IN"
},
"TESTOUTPUT5": {
"direction": "OUT"
},
"PHYCTLFULL": {
"direction": "OUT"
},
"AUXOUTPUT3": {
"direction": "OUT"
},
"PHYCTLWD24": {
"direction": "IN"
},
"INBURSTPENDING3": {
"direction": "OUT"
},
"TESTINPUT4": {
"direction": "IN"
},
"PHYCTLWD16": {
"direction": "IN"
},
"PHYCTLWD31": {
"direction": "IN"
},
"TESTINPUT11": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"INRANKC1": {
"direction": "OUT"
},
"PHYCTLWD19": {
"direction": "IN"
},
"TESTOUTPUT3": {
"direction": "OUT"
},
"PHYCTLWD21": {
"direction": "IN"
},
"PHYCTLEMPTY": {
"direction": "OUT"
},
"TESTOUTPUT12": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "PHY_CONTROL"
}

493
artix7/site_type_PLLE2_ADV.json Normal file
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@ -0,0 +1,493 @@
{
"site_pins": {
"TESTIN4": {
"direction": "IN"
},
"CLKFBOUT": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"TESTOUT48": {
"direction": "OUT"
},
"TESTIN23": {
"direction": "IN"
},
"TESTOUT38": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"TESTOUT55": {
"direction": "OUT"
},
"TESTIN28": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"TESTOUT12": {
"direction": "OUT"
},
"DADDR4": {
"direction": "IN"
},
"TESTOUT37": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTOUT54": {
"direction": "OUT"
},
"DCLK": {
"direction": "IN"
},
"CLKOUT3": {
"direction": "OUT"
},
"TESTOUT62": {
"direction": "OUT"
},
"TESTIN14": {
"direction": "IN"
},
"TESTOUT28": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTIN21": {
"direction": "IN"
},
"DI9": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"TESTIN27": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"TESTIN29": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"DO15": {
"direction": "OUT"
},
"DI4": {
"direction": "IN"
},
"TESTOUT63": {
"direction": "OUT"
},
"DI1": {
"direction": "IN"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"TESTOUT22": {
"direction": "OUT"
},
"TESTIN22": {
"direction": "IN"
},
"TESTOUT21": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTIN26": {
"direction": "IN"
},
"TESTIN20": {
"direction": "IN"
},
"TESTOUT32": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"TESTIN17": {
"direction": "IN"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT13": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"TESTOUT15": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"DO4": {
"direction": "OUT"
},
"DADDR3": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"TESTIN12": {
"direction": "IN"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTIN16": {
"direction": "IN"
},
"DEN": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"DO14": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"CLKOUT0": {
"direction": "OUT"
},
"TESTOUT19": {
"direction": "OUT"
},
"TESTOUT30": {
"direction": "OUT"
},
"CLKOUT2": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"TESTOUT45": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DI2": {
"direction": "IN"
},
"DO7": {
"direction": "OUT"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN30": {
"direction": "IN"
},
"TESTOUT46": {
"direction": "OUT"
},
"TESTIN19": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTOUT16": {
"direction": "OUT"
},
"TESTIN31": {
"direction": "IN"
},
"CLKOUT4": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTIN11": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"TESTOUT36": {
"direction": "OUT"
},
"DI5": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"CLKINSEL": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"CLKIN1": {
"direction": "IN"
},
"DO13": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"TESTOUT14": {
"direction": "OUT"
},
"TESTOUT34": {
"direction": "OUT"
},
"TESTOUT50": {
"direction": "OUT"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTIN10": {
"direction": "IN"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTOUT9": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"TESTOUT31": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"CLKIN2": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTIN18": {
"direction": "IN"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT29": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"DO0": {
"direction": "OUT"
},
"TESTOUT60": {
"direction": "OUT"
},
"DI3": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"TESTOUT8": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"DI8": {
"direction": "IN"
},
"TESTOUT53": {
"direction": "OUT"
},
"DADDR1": {
"direction": "IN"
},
"CLKFBIN": {
"direction": "IN"
},
"TESTOUT57": {
"direction": "OUT"
},
"TESTOUT26": {
"direction": "OUT"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT42": {
"direction": "OUT"
},
"TESTIN25": {
"direction": "IN"
},
"TESTOUT41": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
}
},
"site_pips": {
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
}
},
"type": "PLLE2_ADV"
}

27
artix7/site_type_PMV2.json Normal file
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@ -0,0 +1,27 @@
{
"site_pins": {
"O": {
"direction": "OUT"
},
"A2": {
"direction": "IN"
},
"ODIV4": {
"direction": "OUT"
},
"EN": {
"direction": "IN"
},
"ODIV2": {
"direction": "OUT"
},
"A0": {
"direction": "IN"
},
"A1": {
"direction": "IN"
}
},
"site_pips": {},
"type": "PMV2"
}

561
artix7/site_type_RAMB18E1.json Normal file
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@ -0,0 +1,561 @@
{
"site_pins": {
"WRCOUNT10": {
"direction": "OUT"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"DIADI11": {
"direction": "IN"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"WRCOUNT9": {
"direction": "OUT"
},
"DIADI5": {
"direction": "IN"
},
"WEBWE5": {
"direction": "IN"
},
"DIADI7": {
"direction": "IN"
},
"WEBWE0": {
"direction": "IN"
},
"DIADI3": {
"direction": "IN"
},
"WEBWE3": {
"direction": "IN"
},
"DOBDO7": {
"direction": "OUT"
},
"WEBWE7": {
"direction": "IN"
},
"DOADO12": {
"direction": "OUT"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"DOBDO13": {
"direction": "OUT"
},
"DOPBDOP0": {
"direction": "OUT"
},
"RDERR": {
"direction": "OUT"
},
"DOADO5": {
"direction": "OUT"
},
"DIBDI7": {
"direction": "IN"
},
"WRCOUNT7": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"DIBDI11": {
"direction": "IN"
},
"DOADO7": {
"direction": "OUT"
},
"DIADI0": {
"direction": "IN"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"RSTRAMB": {
"direction": "IN"
},
"DOADO8": {
"direction": "OUT"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"DOBDO14": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"REGCLKB": {
"direction": "IN"
},
"DOBDO10": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"DOBDO2": {
"direction": "OUT"
},
"DOBDO11": {
"direction": "OUT"
},
"DOPBDOP1": {
"direction": "OUT"
},
"RSTREGARSTREG": {
"direction": "IN"
},
"DOADO1": {
"direction": "OUT"
},
"WEA0": {
"direction": "IN"
},
"DIBDI14": {
"direction": "IN"
},
"DOADO0": {
"direction": "OUT"
},
"WEA3": {
"direction": "IN"
},
"DIADI14": {
"direction": "IN"
},
"DOBDO9": {
"direction": "OUT"
},
"DIADI1": {
"direction": "IN"
},
"CLKARDCLK": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"RDCOUNT11": {
"direction": "OUT"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"WRCOUNT4": {
"direction": "OUT"
},
"DIBDI8": {
"direction": "IN"
},
"DIPBDIP0": {
"direction": "IN"
},
"DIADI8": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"RDCOUNT5": {
"direction": "OUT"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"DOADO2": {
"direction": "OUT"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"RDCOUNT7": {
"direction": "OUT"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"DIBDI4": {
"direction": "IN"
},
"DIBDI2": {
"direction": "IN"
},
"DOADO6": {
"direction": "OUT"
},
"DOADO11": {
"direction": "OUT"
},
"RDCOUNT2": {
"direction": "OUT"
},
"WEBWE6": {
"direction": "IN"
},
"WEBWE1": {
"direction": "IN"
},
"DOADO13": {
"direction": "OUT"
},
"DIBDI3": {
"direction": "IN"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"WRCOUNT1": {
"direction": "OUT"
},
"DIBDI6": {
"direction": "IN"
},
"DOBDO8": {
"direction": "OUT"
},
"RDCOUNT4": {
"direction": "OUT"
},
"DOBDO1": {
"direction": "OUT"
},
"DOPADOP0": {
"direction": "OUT"
},
"RSTRAMARSTRAM": {
"direction": "IN"
},
"DOBDO5": {
"direction": "OUT"
},
"DIADI15": {
"direction": "IN"
},
"DOADO10": {
"direction": "OUT"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"DIADI6": {
"direction": "IN"
},
"RDCOUNT0": {
"direction": "OUT"
},
"REGCLKARDRCLK": {
"direction": "IN"
},
"DIPBDIP1": {
"direction": "IN"
},
"DOADO9": {
"direction": "OUT"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"WRCOUNT6": {
"direction": "OUT"
},
"REGCEB": {
"direction": "IN"
},
"DOBDO15": {
"direction": "OUT"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"DOBDO0": {
"direction": "OUT"
},
"DIBDI5": {
"direction": "IN"
},
"WRERR": {
"direction": "OUT"
},
"RDCOUNT3": {
"direction": "OUT"
},
"DIBDI12": {
"direction": "IN"
},
"WRCOUNT5": {
"direction": "OUT"
},
"DIBDI13": {
"direction": "IN"
},
"ENARDEN": {
"direction": "IN"
},
"RDCOUNT8": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"ADDRARDADDR0": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"DIBDI15": {
"direction": "IN"
},
"DOBDO4": {
"direction": "OUT"
},
"DOBDO3": {
"direction": "OUT"
},
"ENBWREN": {
"direction": "IN"
},
"DOADO4": {
"direction": "OUT"
},
"RSTREGB": {
"direction": "IN"
},
"DIBDI9": {
"direction": "IN"
},
"DIADI12": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"WEA2": {
"direction": "IN"
},
"DOBDO6": {
"direction": "OUT"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"DIPADIP0": {
"direction": "IN"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DOADO14": {
"direction": "OUT"
},
"WRCOUNT3": {
"direction": "OUT"
},
"DIPADIP1": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"DIADI13": {
"direction": "IN"
},
"DOADO15": {
"direction": "OUT"
},
"DIADI4": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"REGCEAREGCE": {
"direction": "IN"
},
"WRCOUNT8": {
"direction": "OUT"
},
"RDCOUNT9": {
"direction": "OUT"
},
"CLKBWRCLK": {
"direction": "IN"
},
"WRCOUNT0": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"WEBWE4": {
"direction": "IN"
},
"DOBDO12": {
"direction": "OUT"
},
"EMPTY": {
"direction": "OUT"
},
"DIADI9": {
"direction": "IN"
},
"DOADO3": {
"direction": "OUT"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"DOPADOP1": {
"direction": "OUT"
},
"DIADI2": {
"direction": "IN"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"WRCOUNT11": {
"direction": "OUT"
}
},
"site_pips": {
"ENARDENINV:ENARDEN": {
"from_pin": "ENARDEN",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB": {
"from_pin": "RSTREGB",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN": {
"from_pin": "ENBWREN",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK": {
"from_pin": "CLKBWRCLK",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK": {
"from_pin": "REGCLKARDRCLK",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK_B": {
"from_pin": "REGCLKARDRCLK_B",
"to_pin": "OUT"
},
"CLKARDCLKINV:CLKARDCLK": {
"from_pin": "CLKARDCLK",
"to_pin": "OUT"
},
"CLKARDCLKINV:CLKARDCLK_B": {
"from_pin": "CLKARDCLK_B",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG": {
"from_pin": "RSTREGARSTREG",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB_B": {
"from_pin": "REGCLKB_B",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG_B": {
"from_pin": "RSTREGARSTREG_B",
"to_pin": "OUT"
},
"RSTRAMBINV:RSTRAMB": {
"from_pin": "RSTRAMB",
"to_pin": "OUT"
},
"ENARDENINV:ENARDEN_B": {
"from_pin": "ENARDEN_B",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": {
"from_pin": "RSTRAMARSTRAM_B",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM": {
"from_pin": "RSTRAMARSTRAM",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK_B": {
"from_pin": "CLKBWRCLK_B",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN_B": {
"from_pin": "ENBWREN_B",
"to_pin": "OUT"
},
"RSTRAMBINV:RSTRAMB_B": {
"from_pin": "RSTRAMB_B",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB": {
"from_pin": "REGCLKB",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB_B": {
"from_pin": "RSTREGB_B",
"to_pin": "OUT"
}
},
"type": "RAMB18E1"
}

1235
artix7/site_type_RAMBFIFO36E1.json Normal file
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694
artix7/site_type_SLICEL.json Normal file
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@ -0,0 +1,694 @@
{
"site_pins": {
"CMUX": {
"direction": "OUT"
},
"C2": {
"direction": "IN"
},
"AQ": {
"direction": "OUT"
},
"A6": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"DQ": {
"direction": "OUT"
},
"A5": {
"direction": "IN"
},
"B1": {
"direction": "IN"
},
"C5": {
"direction": "IN"
},
"COUT": {
"direction": "OUT"
},
"B5": {
"direction": "IN"
},
"B2": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"CIN": {
"direction": "IN"
},
"C1": {
"direction": "IN"
},
"B4": {
"direction": "IN"
},
"BMUX": {
"direction": "OUT"
},
"BX": {
"direction": "IN"
},
"CQ": {
"direction": "OUT"
},
"C4": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"CE": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"BQ": {
"direction": "OUT"
},
"D": {
"direction": "OUT"
},
"A3": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"DX": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"A": {
"direction": "OUT"
},
"D3": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"CX": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"AX": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"C6": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"B6": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"A1": {
"direction": "IN"
}
},
"site_pips": {
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
}
},
"type": "SLICEL"
}

769
artix7/site_type_SLICEM.json Normal file
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@ -0,0 +1,769 @@
{
"site_pins": {
"CI": {
"direction": "IN"
},
"CMUX": {
"direction": "OUT"
},
"C2": {
"direction": "IN"
},
"AQ": {
"direction": "OUT"
},
"A6": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"DQ": {
"direction": "OUT"
},
"WE": {
"direction": "IN"
},
"B1": {
"direction": "IN"
},
"C5": {
"direction": "IN"
},
"COUT": {
"direction": "OUT"
},
"B5": {
"direction": "IN"
},
"DI": {
"direction": "IN"
},
"B2": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"CIN": {
"direction": "IN"
},
"C1": {
"direction": "IN"
},
"A": {
"direction": "OUT"
},
"BMUX": {
"direction": "OUT"
},
"BX": {
"direction": "IN"
},
"CQ": {
"direction": "OUT"
},
"C4": {
"direction": "IN"
},
"A5": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"B4": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"BI": {
"direction": "IN"
},
"BQ": {
"direction": "OUT"
},
"D": {
"direction": "OUT"
},
"A3": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"DX": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"D3": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"CX": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"AX": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"C6": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"AI": {
"direction": "IN"
},
"B6": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"A1": {
"direction": "IN"
}
},
"site_pips": {
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"WA8USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"WEMUX:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"WEMUX:WE": {
"from_pin": "WE",
"to_pin": "OUT"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DOUTMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"ADI1MUX:AI": {
"from_pin": "AI",
"to_pin": "OUT"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BDI1MUX:CMC31": {
"from_pin": "CMC31",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"CDI1MUX:CI": {
"from_pin": "CI",
"to_pin": "OUT"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"ADI1MUX:BDI1": {
"from_pin": "BDI1",
"to_pin": "OUT"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"BDI1MUX:BI": {
"from_pin": "BI",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"WA7USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"CDI1MUX:DMC31": {
"from_pin": "DMC31",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"ADI1MUX:BMC31": {
"from_pin": "BMC31",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"DFFMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
}
},
"type": "SLICEM"
}

45
artix7/site_type_STARTUP.json Normal file
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@ -0,0 +1,45 @@
{
"site_pins": {
"GSR": {
"direction": "IN"
},
"CFGCLK": {
"direction": "OUT"
},
"PACK": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"USRCCLKTS": {
"direction": "IN"
},
"USRCCLKO": {
"direction": "IN"
},
"USRDONEO": {
"direction": "IN"
},
"CFGMCLK": {
"direction": "OUT"
},
"USRDONETS": {
"direction": "IN"
},
"KEYCLEARB": {
"direction": "IN"
},
"EOS": {
"direction": "OUT"
},
"PREQ": {
"direction": "OUT"
},
"GTS": {
"direction": "IN"
}
},
"site_pips": {},
"type": "STARTUP"
}

12
artix7/site_type_TIEOFF.json Normal file
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@ -0,0 +1,12 @@
{
"site_pins": {
"HARD1": {
"direction": "OUT"
},
"HARD0": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "TIEOFF"
}

108
artix7/site_type_USR_ACCESS.json Normal file
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@ -0,0 +1,108 @@
{
"site_pins": {
"DATA14": {
"direction": "OUT"
},
"DATA26": {
"direction": "OUT"
},
"DATA17": {
"direction": "OUT"
},
"DATA3": {
"direction": "OUT"
},
"CFGCLK": {
"direction": "OUT"
},
"DATA9": {
"direction": "OUT"
},
"DATA29": {
"direction": "OUT"
},
"DATA27": {
"direction": "OUT"
},
"DATA19": {
"direction": "OUT"
},
"DATA25": {
"direction": "OUT"
},
"DATA8": {
"direction": "OUT"
},
"DATA1": {
"direction": "OUT"
},
"DATA7": {
"direction": "OUT"
},
"DATAVALID": {
"direction": "OUT"
},
"DATA24": {
"direction": "OUT"
},
"DATA30": {
"direction": "OUT"
},
"DATA22": {
"direction": "OUT"
},
"DATA23": {
"direction": "OUT"
},
"DATA13": {
"direction": "OUT"
},
"DATA16": {
"direction": "OUT"
},
"DATA15": {
"direction": "OUT"
},
"DATA4": {
"direction": "OUT"
},
"DATA28": {
"direction": "OUT"
},
"DATA2": {
"direction": "OUT"
},
"DATA10": {
"direction": "OUT"
},
"DATA6": {
"direction": "OUT"
},
"DATA0": {
"direction": "OUT"
},
"DATA11": {
"direction": "OUT"
},
"DATA18": {
"direction": "OUT"
},
"DATA12": {
"direction": "OUT"
},
"DATA5": {
"direction": "OUT"
},
"DATA20": {
"direction": "OUT"
},
"DATA21": {
"direction": "OUT"
},
"DATA31": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "USR_ACCESS"
}

683
artix7/site_type_XADC.json Normal file
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@ -0,0 +1,683 @@
{
"site_pins": {
"DO6": {
"direction": "OUT"
},
"ALM2": {
"direction": "OUT"
},
"TESTADCIN212": {
"direction": "IN"
},
"TESTADCIN15": {
"direction": "IN"
},
"DO1": {
"direction": "OUT"
},
"VAUXP2": {
"direction": "IN"
},
"TESTSCANCLK2": {
"direction": "IN"
},
"TESTSCANMODE4": {
"direction": "IN"
},
"TESTSE1": {
"direction": "IN"
},
"BUSY": {
"direction": "OUT"
},
"TESTUPDATE": {
"direction": "IN"
},
"TESTADCIN211": {
"direction": "IN"
},
"EOS": {
"direction": "OUT"
},
"TESTSCANRESET": {
"direction": "IN"
},
"TESTADCIN13": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"CHANNEL1": {
"direction": "OUT"
},
"DCLK": {
"direction": "IN"
},
"TESTADCIN3": {
"direction": "IN"
},
"TESTDB2": {
"direction": "OUT"
},
"ALM7": {
"direction": "OUT"
},
"TESTTDI": {
"direction": "IN"
},
"TESTADCIN218": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"TESTSO3": {
"direction": "OUT"
},
"DI14": {
"direction": "IN"
},
"VAUXP6": {
"direction": "IN"
},
"TESTADCIN21": {
"direction": "IN"
},
"DI1": {
"direction": "IN"
},
"TESTADCOUT10": {
"direction": "OUT"
},
"ALM3": {
"direction": "OUT"
},
"CONVSTCLK": {
"direction": "IN"
},
"MUXADDR2": {
"direction": "OUT"
},
"TESTADCOUT7": {
"direction": "OUT"
},
"TESTDB4": {
"direction": "OUT"
},
"TESTSO1": {
"direction": "OUT"
},
"CHANNEL0": {
"direction": "OUT"
},
"TESTSCANCLK4": {
"direction": "IN"
},
"VAUXN0": {
"direction": "IN"
},
"TESTADCIN7": {
"direction": "IN"
},
"TESTSHIFT": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"DEN": {
"direction": "IN"
},
"TESTADCOUT19": {
"direction": "OUT"
},
"DI6": {
"direction": "IN"
},
"TESTSE0": {
"direction": "IN"
},
"VAUXP1": {
"direction": "IN"
},
"TESTSI2": {
"direction": "IN"
},
"TESTSCANMODE1": {
"direction": "IN"
},
"TESTADCOUT16": {
"direction": "OUT"
},
"VAUXN3": {
"direction": "IN"
},
"TESTADCOUT2": {
"direction": "OUT"
},
"VAUXN7": {
"direction": "IN"
},
"VAUXN9": {
"direction": "IN"
},
"VAUXN4": {
"direction": "IN"
},
"TESTADCIN29": {
"direction": "IN"
},
"TESTADCOUT9": {
"direction": "OUT"
},
"TESTDB12": {
"direction": "OUT"
},
"TESTSE4": {
"direction": "IN"
},
"TESTSE3": {
"direction": "IN"
},
"TESTADCIN14": {
"direction": "IN"
},
"TESTADCOUT8": {
"direction": "OUT"
},
"TESTADCIN16": {
"direction": "IN"
},
"TESTADCOUT12": {
"direction": "OUT"
},
"TESTDB15": {
"direction": "OUT"
},
"TESTADCIN20": {
"direction": "IN"
},
"TESTSCANCLK3": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"TESTADCIN24": {
"direction": "IN"
},
"TESTADCCLK0": {
"direction": "IN"
},
"VAUXN6": {
"direction": "IN"
},
"TESTDB10": {
"direction": "OUT"
},
"VAUXP3": {
"direction": "IN"
},
"TESTADCIN213": {
"direction": "IN"
},
"TESTADCIN12": {
"direction": "IN"
},
"TESTADCIN25": {
"direction": "IN"
},
"TESTSO4": {
"direction": "OUT"
},
"MUXADDR4": {
"direction": "OUT"
},
"JTAGLOCKED": {
"direction": "OUT"
},
"TESTADCCLK2": {
"direction": "IN"
},
"TESTDB1": {
"direction": "OUT"
},
"TESTDB7": {
"direction": "OUT"
},
"TESTADCIN23": {
"direction": "IN"
},
"DADDR4": {
"direction": "IN"
},
"VAUXN11": {
"direction": "IN"
},
"DO5": {
"direction": "OUT"
},
"TESTSO0": {
"direction": "OUT"
},
"TESTADCIN10": {
"direction": "IN"
},
"DO9": {
"direction": "OUT"
},
"TESTADCIN219": {
"direction": "IN"
},
"TESTADCIN27": {
"direction": "IN"
},
"TESTADCIN210": {
"direction": "IN"
},
"TESTADCIN215": {
"direction": "IN"
},
"TESTADCIN5": {
"direction": "IN"
},
"TESTSCANCLK0": {
"direction": "IN"
},
"TESTDB8": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"VAUXP10": {
"direction": "IN"
},
"VAUXP12": {
"direction": "IN"
},
"VAUXP7": {
"direction": "IN"
},
"DADDR1": {
"direction": "IN"
},
"VAUXP13": {
"direction": "IN"
},
"TESTDRCK": {
"direction": "IN"
},
"TESTSO2": {
"direction": "OUT"
},
"TESTADCOUT15": {
"direction": "OUT"
},
"RESET": {
"direction": "IN"
},
"TESTDB13": {
"direction": "OUT"
},
"TESTADCIN22": {
"direction": "IN"
},
"ALM6": {
"direction": "OUT"
},
"VP": {
"direction": "IN"
},
"TESTADCIN9": {
"direction": "IN"
},
"VAUXP5": {
"direction": "IN"
},
"TESTADCIN11": {
"direction": "IN"
},
"VAUXN14": {
"direction": "IN"
},
"TESTDB5": {
"direction": "OUT"
},
"MUXADDR1": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"DI15": {
"direction": "IN"
},
"TESTADCIN214": {
"direction": "IN"
},
"TESTSI3": {
"direction": "IN"
},
"DO14": {
"direction": "OUT"
},
"VAUXP11": {
"direction": "IN"
},
"TESTADCOUT13": {
"direction": "OUT"
},
"DI7": {
"direction": "IN"
},
"DO8": {
"direction": "OUT"
},
"VN": {
"direction": "IN"
},
"TESTSCANMODE0": {
"direction": "IN"
},
"ALM1": {
"direction": "OUT"
},
"ALM0": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"VAUXP9": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"CHANNEL2": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"TESTADCOUT14": {
"direction": "OUT"
},
"CHANNEL3": {
"direction": "OUT"
},
"DI11": {
"direction": "IN"
},
"VAUXN10": {
"direction": "IN"
},
"VAUXP0": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"TESTADCIN26": {
"direction": "IN"
},
"DO15": {
"direction": "OUT"
},
"TESTRST": {
"direction": "IN"
},
"TESTADCIN1": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"VAUXN8": {
"direction": "IN"
},
"TESTADCIN0": {
"direction": "IN"
},
"VAUXP4": {
"direction": "IN"
},
"TESTADCOUT11": {
"direction": "OUT"
},
"TESTADCOUT0": {
"direction": "OUT"
},
"TESTADCOUT4": {
"direction": "OUT"
},
"CHANNEL4": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"DI9": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"ALM5": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DADDR3": {
"direction": "IN"
},
"TESTDB0": {
"direction": "OUT"
},
"TESTSE2": {
"direction": "IN"
},
"JTAGBUSY": {
"direction": "OUT"
},
"VAUXP15": {
"direction": "IN"
},
"OT": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"TESTADCIN217": {
"direction": "IN"
},
"TESTADCIN2": {
"direction": "IN"
},
"TESTADCIN19": {
"direction": "IN"
},
"DI4": {
"direction": "IN"
},
"TESTDB3": {
"direction": "OUT"
},
"TESTTDO": {
"direction": "OUT"
},
"TESTDB6": {
"direction": "OUT"
},
"TESTENJTAG": {
"direction": "IN"
},
"DO12": {
"direction": "OUT"
},
"DI2": {
"direction": "IN"
},
"TESTDB11": {
"direction": "OUT"
},
"TESTCAPTURE": {
"direction": "IN"
},
"TESTADCIN17": {
"direction": "IN"
},
"TESTSI0": {
"direction": "IN"
},
"ALM4": {
"direction": "OUT"
},
"TESTADCOUT17": {
"direction": "OUT"
},
"TESTADCIN216": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"TESTADCOUT6": {
"direction": "OUT"
},
"TESTADCIN18": {
"direction": "IN"
},
"TESTSCANMODE2": {
"direction": "IN"
},
"VAUXN12": {
"direction": "IN"
},
"DO13": {
"direction": "OUT"
},
"VAUXN2": {
"direction": "IN"
},
"VAUXP14": {
"direction": "IN"
},
"MUXADDR0": {
"direction": "OUT"
},
"CONVST": {
"direction": "IN"
},
"VAUXN15": {
"direction": "IN"
},
"TESTSEL": {
"direction": "IN"
},
"EOC": {
"direction": "OUT"
},
"TESTADCCLK1": {
"direction": "IN"
},
"VAUXN13": {
"direction": "IN"
},
"MUXADDR3": {
"direction": "OUT"
},
"TESTDB9": {
"direction": "OUT"
},
"TESTADCOUT1": {
"direction": "OUT"
},
"VAUXN1": {
"direction": "IN"
},
"TESTADCOUT5": {
"direction": "OUT"
},
"TESTADCIN6": {
"direction": "IN"
},
"JTAGMODIFIED": {
"direction": "OUT"
},
"VAUXP8": {
"direction": "IN"
},
"TESTADCIN8": {
"direction": "IN"
},
"DI3": {
"direction": "IN"
},
"TESTADCOUT3": {
"direction": "OUT"
},
"TESTADCIN4": {
"direction": "IN"
},
"TESTADCIN28": {
"direction": "IN"
},
"TESTSCANMODE3": {
"direction": "IN"
},
"TESTADCOUT18": {
"direction": "OUT"
},
"DI8": {
"direction": "IN"
},
"TESTSI1": {
"direction": "IN"
},
"TESTADCCLK3": {
"direction": "IN"
},
"VAUXN5": {
"direction": "IN"
},
"TESTSCANCLK1": {
"direction": "IN"
},
"TESTDB14": {
"direction": "OUT"
},
"TESTSI4": {
"direction": "IN"
}
},
"site_pips": {
"DCLKINV:DCLK": {
"from_pin": "DCLK",
"to_pin": "OUT"
},
"DCLKINV:DCLK_B": {
"from_pin": "DCLK_B",
"to_pin": "OUT"
},
"CONVSTCLKINV:CONVSTCLK_B": {
"from_pin": "CONVSTCLK_B",
"to_pin": "OUT"
},
"CONVSTCLKINV:CONVSTCLK": {
"from_pin": "CONVSTCLK",
"to_pin": "OUT"
}
},
"type": "XADC"
}

476
artix7/tile_type_BRAM_INT_INTERFACE_L.json Normal file
View File

@ -0,0 +1,476 @@
{
"tile_type": "BRAM_INT_INTERFACE_L",
"pips": {
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
"is_directional": "1",
"can_invert": "0"
}
},
"wires": [
"INT_INTERFACE_BRAM_UTURN_IMUX31",
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_BRAM_UTURN_IMUX17",
"INT_INTERFACE_BRAM_UTURN_IMUX44",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_LH4",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_LOGIC_OUTS_L16",
"INT_INTERFACE_LOGIC_OUTS_L19",
"INT_INTERFACE_BRAM_UTURN_IMUX2",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_BRAM_UTURN_IMUX37",
"INT_INTERFACE_BRAM_UTURN_IMUX33",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_BRAM_UTURN_IMUX42",
"INT_INTERFACE_BRAM_UTURN_IMUX8",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_BRAM_UTURN_IMUX29",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_LOGIC_OUTS_L_B14",
"INT_INTERFACE_BRAM_UTURN_IMUX41",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_LOGIC_OUTS_L14",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_BRAM_UTURN_IMUX39",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_LOGIC_OUTS_L4",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_BLOCK_OUTS_L_B0",
"INT_INTERFACE_LH7",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_BRAM_UTURN_IMUX30",
"INT_INTERFACE_LOGIC_OUTS_L9",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_LOGIC_OUTS_L_B22",
"INT_INTERFACE_LOGIC_OUTS_L12",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_BRAM_UTURN_IMUX28",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_LOGIC_OUTS_L_B10",
"INT_INTERFACE_BRAM_UTURN_IMUX45",
"INT_INTERFACE_LH10",
"INT_INTERFACE_LH3",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_BRAM_UTURN_IMUX15",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_LOGIC_OUTS_L_B8",
"INT_INTERFACE_BRAM_UTURN_IMUX16",
"INT_INTERFACE_BRAM_UTURN_IMUX43",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_BRAM_UTURN_IMUX47",
"INT_INTERFACE_BRAM_UTURN_IMUX1",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_BRAM_UTURN_IMUX32",
"INT_INTERFACE_BRAM_UTURN_IMUX10",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_LOGIC_OUTS_L_B1",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_LOGIC_OUTS_L11",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_BRAM_UTURN_IMUX0",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_LOGIC_OUTS_L_B17",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_LOGIC_OUTS_L_B18",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_LOGIC_OUTS_L15",
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_LOGIC_OUTS_L_B20",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_BRAM_UTURN_IMUX3",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_LOGIC_OUTS_L3",
"INT_INTERFACE_BRAM_UTURN_IMUX38",
"INT_INTERFACE_BRAM_UTURN_IMUX35",
"INT_INTERFACE_LOGIC_OUTS_L_B3",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_LOGIC_OUTS_L2",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_LH12",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_LH6",
"INT_INTERFACE_LOGIC_OUTS_L_B23",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_BLOCK_OUTS_L_B1",
"INT_INTERFACE_BRAM_UTURN_IMUX9",
"INT_INTERFACE_LOGIC_OUTS_L_B7",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_LOGIC_OUTS_L21",
"INT_INTERFACE_BRAM_UTURN_IMUX36",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_LOGIC_OUTS_L13",
"INT_INTERFACE_BRAM_UTURN_IMUX12",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_BRAM_UTURN_IMUX23",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_LOGIC_OUTS_L_B6",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_LOGIC_OUTS_L_B4",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_LOGIC_OUTS_L_B9",
"INT_INTERFACE_LOGIC_OUTS_L_B16",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_BRAM_UTURN_IMUX4",
"INT_INTERFACE_BRAM_UTURN_IMUX7",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_LH8",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_LH2",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_BRAM_UTURN_IMUX40",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_LOGIC_OUTS_L5",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_LOGIC_OUTS_L_B13",
"INT_INTERFACE_LOGIC_OUTS_L22",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_BRAM_UTURN_IMUX24",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_BLOCK_OUTS_L_B3",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_BRAM_UTURN_IMUX27",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_BRAM_UTURN_IMUX34",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_LOGIC_OUTS_L7",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_BLOCK_OUTS_L_B2",
"INT_INTERFACE_LOGIC_OUTS_L_B5",
"INT_INTERFACE_LH5",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_BRAM_IMUX1",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_BRAM_IMUX19",
"L_INT_INTER_DQS_IOTOPHASER",
"INT_INTERFACE_BRAM_UTURN_IMUX19",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_LOGIC_OUTS_L8",
"INT_INTERFACE_LOGIC_OUTS_L17",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_LOGIC_OUTS_L_B2",
"INT_INTERFACE_BRAM_UTURN_IMUX13",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_BRAM_UTURN_IMUX21",
"INT_INTERFACE_BRAM_UTURN_IMUX25",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_LOGIC_OUTS_L_B21",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_BRAM_UTURN_IMUX26",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_LOGIC_OUTS_L1",
"INT_INTERFACE_LOGIC_OUTS_L0",
"INT_INTERFACE_BRAM_UTURN_IMUX14",
"INT_INTERFACE_LOGIC_OUTS_L_B19",
"INT_INTERFACE_WW4END3",
"INT_INTERFACE_BRAM_UTURN_IMUX20",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_LOGIC_OUTS_L_B11",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_LOGIC_OUTS_L_B15",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_LOGIC_OUTS_L10",
"INT_INTERFACE_BRAM_UTURN_IMUX11",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_BRAM_UTURN_IMUX6",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_LOGIC_OUTS_L23",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_LOGIC_OUTS_L20",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_BRAM_UTURN_IMUX5",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_BRAM_UTURN_IMUX22",
"INT_INTERFACE_LH1",
"INT_INTERFACE_LH9",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_LH11",
"INT_INTERFACE_LOGIC_OUTS_L18",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_LOGIC_OUTS_L_B12",
"INT_INTERFACE_LOGIC_OUTS_L_B0",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_BRAM_UTURN_IMUX18",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_LOGIC_OUTS_L6",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_BRAM_UTURN_IMUX46",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_BRAM_IMUX32"
],
"sites": []
}

476
artix7/tile_type_BRAM_INT_INTERFACE_R.json Normal file
View File

@ -0,0 +1,476 @@
{
"tile_type": "BRAM_INT_INTERFACE_R",
"pips": {
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
"is_directional": "1",
"can_invert": "0"
}
},
"wires": [
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_LH4",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_LOGIC_OUTS0",
"INT_INTERFACE_LOGIC_OUTS_B15",
"INT_INTERFACE_LOGIC_OUTS4",
"INT_INTERFACE_LOGIC_OUTS1",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_LOGIC_OUTS13",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_LOGIC_OUTS18",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_LOGIC_OUTS_B4",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
"INT_INTERFACE_LH7",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_LOGIC_OUTS10",
"INT_INTERFACE_LH10",
"INT_INTERFACE_LH3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_LOGIC_OUTS_B23",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_LOGIC_OUTS_B9",
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
"INT_INTERFACE_LOGIC_OUTS_B1",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_BRAM_IMUX32",
"INT_INTERFACE_LOGIC_OUTS_B0",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_LOGIC_OUTS_B13",
"INT_INTERFACE_LOGIC_OUTS11",
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
"INT_INTERFACE_BLOCK_OUTS_B0",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_LOGIC_OUTS_B3",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_LOGIC_OUTS15",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_LOGIC_OUTS5",
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_LOGIC_OUTS12",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_LOGIC_OUTS_B18",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_LOGIC_OUTS3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
"INT_INTERFACE_LOGIC_OUTS9",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_LOGIC_OUTS20",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_LOGIC_OUTS_B12",
"INT_INTERFACE_LOGIC_OUTS17",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_LOGIC_OUTS6",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_LOGIC_OUTS8",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_LH12",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_LH6",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_LOGIC_OUTS16",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
"INT_INTERFACE_LOGIC_OUTS_B8",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_LOGIC_OUTS_B2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_LOGIC_OUTS22",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_LOGIC_OUTS14",
"INT_INTERFACE_BLOCK_OUTS_B2",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_LH8",
"INT_INTERFACE_LOGIC_OUTS_B20",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_LH2",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_LOGIC_OUTS_B16",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_LOGIC_OUTS_B10",
"INT_INTERFACE_LOGIC_OUTS_B19",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_LOGIC_OUTS_B17",
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
"INT_INTERFACE_LOGIC_OUTS_B22",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_LOGIC_OUTS_B5",
"INT_INTERFACE_LH5",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_BRAM_IMUX1",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_BRAM_IMUX19",
"L_INT_INTER_DQS_IOTOPHASER",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
"INT_INTERFACE_LOGIC_OUTS_B6",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_LOGIC_OUTS21",
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_LOGIC_OUTS_B11",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
"INT_INTERFACE_WW4END3",
"INT_INTERFACE_LOGIC_OUTS_B14",
"INT_INTERFACE_BLOCK_OUTS_B1",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
"INT_INTERFACE_BLOCK_OUTS_B3",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_LOGIC_OUTS_B21",
"INT_INTERFACE_LH1",
"INT_INTERFACE_LH9",
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_LH11",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
"INT_INTERFACE_LOGIC_OUTS23",
"INT_INTERFACE_LOGIC_OUTS2",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_LOGIC_OUTS7",
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_LOGIC_OUTS19",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_LOGIC_OUTS_B7",
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
"INT_INTERFACE_BRAM_UTURN_R_IMUX17"
],
"sites": []
}

9834
artix7/tile_type_BRAM_L.json Normal file
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9834
artix7/tile_type_BRAM_R.json Normal file
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71
artix7/tile_type_BRKH_BRAM.json Normal file
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{
"tile_type": "BRKH_BRAM",
"pips": {},
"wires": [
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCADEA_L",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCADEA_R",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCADEB_L",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCADEB_R",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4"
],
"sites": []
}

125
artix7/tile_type_BRKH_B_TERM_INT.json Normal file
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{
"tile_type": "BRKH_B_TERM_INT",
"pips": {},
"wires": [
"B_TERM_UTURN_INT_SS6C3",
"B_TERM_UTURN_INT_SE6C0",
"B_TERM_UTURN_INT_FAN_BOUNCE6",
"B_TERM_UTURN_INT_FAN_BOUNCE0",
"B_TERM_UTURN_INT_SW6D3",
"B_TERM_UTURN_INT_LV5",
"B_TERM_UTURN_INT_LVB1",
"B_TERM_UTURN_INT_SS6B2",
"B_TERM_UTURN_INT_FAN_BOUNCE4",
"B_TERM_UTURN_INT_SS2BEG2",
"B_TERM_UTURN_INT_SW6D1",
"B_TERM_UTURN_INT_LV4",
"B_TERM_UTURN_INT_LVB0",
"B_TERM_UTURN_INT_ER1END_N3_3",
"B_TERM_UTURN_INT_SW6D0",
"B_TERM_UTURN_INT_SS6B1",
"B_TERM_UTURN_INT_SS2A1",
"B_TERM_UTURN_INT_SW2BEG3",
"B_TERM_UTURN_INT_SW6C2",
"B_TERM_UTURN_INT_SE6A2",
"B_TERM_UTURN_INT_SW2BEG0",
"B_TERM_UTURN_INT_SW6B1",
"B_TERM_UTURN_INT_LV_L8",
"B_TERM_UTURN_INT_SR1BEG2",
"B_TERM_UTURN_INT_SS6BEG0",
"B_TERM_UTURN_INT_LV9",
"B_TERM_UTURN_INT_LV_L4",
"B_TERM_UTURN_INT_SW6B3",
"B_TERM_UTURN_INT_SL1BEG2",
"B_TERM_UTURN_INT_SW2BEG1",
"B_TERM_UTURN_INT_SS2BEG1",
"B_TERM_UTURN_INT_SL1BEG3",
"B_TERM_UTURN_INT_SE6A3",
"B_TERM_UTURN_INT_ER1BEG0",
"B_TERM_UTURN_INT_SS6D1",
"B_TERM_UTURN_INT_SS6BEG1",
"B_TERM_UTURN_INT_SW6A3",
"B_TERM_UTURN_INT_LV8",
"B_TERM_UTURN_INT_SW6D2",
"B_TERM_UTURN_INT_SW6B0",
"B_TERM_UTURN_INT_SE6D3",
"B_TERM_UTURN_INT_SW6C3",
"B_TERM_UTURN_INT_LVB_L5",
"B_TERM_UTURN_INT_SW2BEG2",
"B_TERM_UTURN_INT_SR1BEG1",
"B_TERM_UTURN_INT_SE6B1",
"B_TERM_UTURN_INT_LVB4",
"B_TERM_UTURN_INT_SS6A0",
"B_TERM_UTURN_INT_SS2A2",
"B_TERM_UTURN_INT_SS2BEG0",
"B_TERM_UTURN_INT_SW6C1",
"B_TERM_UTURN_INT_SE6B3",
"B_TERM_UTURN_INT_LV3",
"B_TERM_UTURN_INT_SL1BEG0",
"B_TERM_UTURN_INT_SW6C0",
"B_TERM_UTURN_INT_SS6E2",
"B_TERM_UTURN_INT_LV_L5",
"B_TERM_UTURN_INT_LV_L18",
"B_TERM_UTURN_INT_SS6A2",
"B_TERM_UTURN_INT_SE6C1",
"B_TERM_UTURN_INT_SS6E1",
"B_TERM_UTURN_INT_SE6A1",
"B_TERM_UTURN_INT_SW6A0",
"B_TERM_UTURN_INT_LV_L7",
"B_TERM_UTURN_INT_SS6E3",
"B_TERM_UTURN_INT_LVB2",
"B_TERM_UTURN_INT_SS6D2",
"B_TERM_UTURN_INT_LV_L3",
"B_TERM_UTURN_INT_SS2A0",
"B_TERM_UTURN_INT_LVB_L2",
"B_TERM_UTURN_INT_SE6D1",
"B_TERM_UTURN_INT_SS6E0",
"B_TERM_UTURN_INT_LV7",
"B_TERM_UTURN_INT_SE6B0",
"B_TERM_UTURN_INT_SS6B3",
"B_TERM_UTURN_INT_SE2BEG3",
"B_TERM_UTURN_INT_SW6END_N0_3",
"B_TERM_UTURN_INT_SS6C1",
"B_TERM_UTURN_INT_SW6A2",
"B_TERM_UTURN_INT_LVB_L0",
"B_TERM_UTURN_INT_SS6BEG3",
"B_TERM_UTURN_INT_LV_L2",
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_LVB5",
"B_TERM_UTURN_INT_SS2BEG3",
"B_TERM_UTURN_INT_LVB_L3",
"B_TERM_UTURN_INT_SS6A1",
"B_TERM_UTURN_INT_LVB3",
"B_TERM_UTURN_INT_LV_L6",
"B_TERM_UTURN_INT_SS6D3",
"B_TERM_UTURN_INT_LV_L9",
"B_TERM_UTURN_INT_LVB_L1",
"B_TERM_UTURN_INT_SE2BEG2",
"B_TERM_UTURN_INT_SE6B2",
"B_TERM_UTURN_INT_SS6BEG2",
"B_TERM_UTURN_INT_SE2BEG1",
"B_TERM_UTURN_INT_FAN_BOUNCE2",
"B_TERM_UTURN_INT_SE6C2",
"B_TERM_UTURN_INT_SS2A3",
"B_TERM_UTURN_INT_LVB_L4",
"B_TERM_UTURN_INT_LV2",
"B_TERM_UTURN_INT_SS6B0",
"B_TERM_UTURN_INT_LV18",
"B_TERM_UTURN_INT_LV6",
"B_TERM_UTURN_INT_SS6C0",
"B_TERM_UTURN_INT_SE6A0",
"B_TERM_UTURN_INT_SS6C2",
"B_TERM_UTURN_INT_SW6A1",
"B_TERM_UTURN_INT_SE6D0",
"B_TERM_UTURN_INT_SE2BEG0",
"B_TERM_UTURN_INT_SS6D0",
"B_TERM_UTURN_INT_SR1BEG3",
"B_TERM_UTURN_INT_SW6B2",
"B_TERM_UTURN_INT_SE6C3",
"B_TERM_UTURN_INT_SL1BEG1",
"B_TERM_UTURN_INT_WR1END0",
"B_TERM_UTURN_INT_SS6A3",
"B_TERM_UTURN_INT_SE6D2"
],
"sites": []
}

11
artix7/tile_type_BRKH_CLB.json Normal file
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{
"tile_type": "BRKH_CLB",
"pips": {},
"wires": [
"BRKH_CLB_COUT1_L",
"BRKH_CLB_COUT0_L",
"BRKH_CLB_COUT1_R",
"BRKH_CLB_COUT0_R"
],
"sites": []
}

135
artix7/tile_type_BRKH_CLK.json Normal file
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{
"tile_type": "BRKH_CLK",
"pips": {},
"wires": [
"BRKH_CLK_R_CK_BUFG_CASC13",
"BRKH_CLK_R_CK_BUFG_CASC12",
"BRKH_CLK_R_CK_GCLK2",
"BRKH_CLK_CK_GCLK20",
"BRKH_CLK_CK_GCLK30",
"BRKH_CLK_R_CK_BUFG_CASC15",
"BRKH_CLK_R_CK_BUFG_CASC30",
"BRKH_CLK_R_CK_BUFG_CASC2",
"BRKH_CLK_R_CK_BUFG_CASC4",
"BRKH_CLK_R_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_GCLK3",
"BRKH_CLK_CK_GCLK24",
"BRKH_CLK_CK_GCLK9",
"BRKH_CLK_CK_GCLK25",
"BRKH_CLK_R_CK_BUFG_CASC25",
"BRKH_CLK_R_CK_BUFG_CASC26",
"BRKH_CLK_CK_GCLK5",
"BRKH_CLK_CK_GCLK0",
"BRKH_CLK_R_CK_BUFG_CASC9",
"BRKH_CLK_CK_BUFG_CASC11",
"BRKH_CLK_CK_BUFG_CASC4",
"BRKH_CLK_CK_GCLK12",
"BRKH_CLK_CK_GCLK17",
"BRKH_CLK_CK_GCLK14",
"BRKH_CLK_R_CK_BUFG_CASC28",
"BRKH_CLK_CK_GCLK31",
"BRKH_CLK_R_CK_BUFG_CASC10",
"BRKH_CLK_CK_BUFG_CASC0",
"BRKH_CLK_CK_GCLK2",
"BRKH_CLK_CK_BUFG_CASC14",
"BRKH_CLK_CK_GCLK18",
"BRKH_CLK_R_CK_BUFG_CASC24",
"BRKH_CLK_CK_BUFG_CASC18",
"BRKH_CLK_CK_GCLK28",
"BRKH_CLK_CK_BUFG_CASC15",
"BRKH_CLK_CK_GCLK4",
"BRKH_CLK_CK_BUFG_CASC21",
"BRKH_CLK_R_CK_BUFG_CASC29",
"BRKH_CLK_R_CK_GCLK1",
"BRKH_CLK_R_CK_GCLK21",
"BRKH_CLK_CK_BUFG_CASC28",
"BRKH_CLK_CK_GCLK3",
"BRKH_CLK_R_CK_GCLK17",
"BRKH_CLK_R_CK_GCLK27",
"BRKH_CLK_R_CK_GCLK25",
"BRKH_CLK_R_CK_GCLK7",
"BRKH_CLK_R_CK_BUFG_CASC11",
"BRKH_CLK_R_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_BUFG_CASC20",
"BRKH_CLK_CK_BUFG_CASC12",
"BRKH_CLK_CK_BUFG_CASC2",
"BRKH_CLK_R_CK_BUFG_CASC3",
"BRKH_CLK_CK_BUFG_CASC29",
"BRKH_CLK_CK_GCLK27",
"BRKH_CLK_CK_GCLK21",
"BRKH_CLK_CK_GCLK15",
"BRKH_CLK_CK_BUFG_CASC26",
"BRKH_CLK_R_CK_GCLK28",
"BRKH_CLK_CK_GCLK16",
"BRKH_CLK_CK_GCLK22",
"BRKH_CLK_CK_BUFG_CASC25",
"BRKH_CLK_CK_GCLK10",
"BRKH_CLK_CK_BUFG_CASC3",
"BRKH_CLK_R_CK_GCLK14",
"BRKH_CLK_R_CK_GCLK19",
"BRKH_CLK_CK_GCLK19",
"BRKH_CLK_CK_GCLK23",
"BRKH_CLK_R_CK_GCLK24",
"BRKH_CLK_CK_GCLK13",
"BRKH_CLK_R_CK_GCLK31",
"BRKH_CLK_R_CK_GCLK8",
"BRKH_CLK_R_CK_BUFG_CASC21",
"BRKH_CLK_CK_GCLK7",
"BRKH_CLK_R_CK_GCLK0",
"BRKH_CLK_R_CK_BUFG_CASC6",
"BRKH_CLK_CK_BUFG_CASC23",
"BRKH_CLK_CK_GCLK26",
"BRKH_CLK_CK_BUFG_CASC30",
"BRKH_CLK_R_CK_GCLK18",
"BRKH_CLK_R_CK_GCLK29",
"BRKH_CLK_R_CK_BUFG_CASC7",
"BRKH_CLK_CK_BUFG_CASC22",
"BRKH_CLK_R_CK_BUFG_CASC16",
"BRKH_CLK_CK_BUFG_CASC1",
"BRKH_CLK_R_CK_GCLK12",
"BRKH_CLK_R_CK_GCLK11",
"BRKH_CLK_CK_GCLK8",
"BRKH_CLK_CK_BUFG_CASC16",
"BRKH_CLK_R_CK_BUFG_CASC18",
"BRKH_CLK_CK_BUFG_CASC7",
"BRKH_CLK_CK_BUFG_CASC31",
"BRKH_CLK_R_CK_GCLK4",
"BRKH_CLK_CK_GCLK11",
"BRKH_CLK_R_CK_GCLK26",
"BRKH_CLK_CK_BUFG_CASC17",
"BRKH_CLK_CK_BUFG_CASC9",
"BRKH_CLK_CK_GCLK6",
"BRKH_CLK_CK_BUFG_CASC24",
"BRKH_CLK_R_CK_BUFG_CASC5",
"BRKH_CLK_CK_BUFG_CASC19",
"BRKH_CLK_R_CK_GCLK23",
"BRKH_CLK_R_CK_BUFG_CASC22",
"BRKH_CLK_CK_GCLK1",
"BRKH_CLK_R_CK_BUFG_CASC17",
"BRKH_CLK_R_CK_GCLK22",
"BRKH_CLK_R_CK_GCLK9",
"BRKH_CLK_CK_BUFG_CASC13",
"BRKH_CLK_CK_BUFG_CASC10",
"BRKH_CLK_R_CK_BUFG_CASC0",
"BRKH_CLK_R_CK_GCLK20",
"BRKH_CLK_R_CK_GCLK5",
"BRKH_CLK_CK_BUFG_CASC20",
"BRKH_CLK_R_CK_BUFG_CASC23",
"BRKH_CLK_R_CK_GCLK6",
"BRKH_CLK_R_CK_GCLK15",
"BRKH_CLK_R_CK_BUFG_CASC1",
"BRKH_CLK_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_BUFG_CASC31",
"BRKH_CLK_R_CK_BUFG_CASC14",
"BRKH_CLK_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_GCLK30",
"BRKH_CLK_CK_GCLK29",
"BRKH_CLK_R_CK_GCLK10",
"BRKH_CLK_CK_BUFG_CASC5",
"BRKH_CLK_CK_BUFG_CASC6",
"BRKH_CLK_R_CK_GCLK13",
"BRKH_CLK_R_CK_GCLK16",
"BRKH_CLK_R_CK_BUFG_CASC19"
],
"sites": []
}

16
artix7/tile_type_BRKH_CMT.json Normal file
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{
"tile_type": "BRKH_CMT",
"pips": {},
"wires": [
"BRKH_CMT_FREQ_REF_NS3",
"BRKH_CMT_PHASEREF1",
"BRKH_CMT_FREQ_REF_NS2",
"BRKH_CMT_FREQ_REF_NS0",
"BRKH_CMT_PHASEREF_BELOW1",
"BRKH_CMT_PHYCTRL_SYNC_BB",
"BRKH_CMT_PHASEREF0",
"BRKH_CMT_FREQ_REF_NS1",
"BRKH_CMT_PHASEREF_BELOW0"
],
"sites": []
}

105
artix7/tile_type_BRKH_DSP_L.json Normal file
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{
"tile_type": "BRKH_DSP_L",
"pips": {},
"wires": [
"BRKH_DSP_ACIN2",
"BRKH_DSP_PCIN35",
"BRKH_DSP_PCIN20",
"BRKH_DSP_BCIN15",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN9",
"BRKH_DSP_ACIN14",
"BRKH_DSP_PCIN45",
"BRKH_DSP_PCIN12",
"BRKH_DSP_BCIN16",
"BRKH_DSP_PCIN30",
"BRKH_DSP_PCIN31",
"BRKH_DSP_PCIN29",
"BRKH_DSP_ACIN5",
"BRKH_DSP_PCIN21",
"BRKH_DSP_ACIN3",
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN3",
"BRKH_DSP_PCIN46",
"BRKH_DSP_BCIN4",
"BRKH_DSP_BCIN13",
"BRKH_DSP_PCIN18",
"BRKH_DSP_ACIN24",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN4",
"BRKH_DSP_BCIN0",
"BRKH_DSP_PCIN44",
"BRKH_DSP_BCIN17",
"BRKH_DSP_ACIN15",
"BRKH_DSP_PCIN34",
"BRKH_DSP_ACIN17",
"BRKH_DSP_BCIN14",
"BRKH_DSP_PCIN27",
"BRKH_DSP_BCIN8",
"BRKH_DSP_PCIN2",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN16",
"BRKH_DSP_ACIN12",
"BRKH_DSP_PCIN39",
"BRKH_DSP_ACIN23",
"BRKH_DSP_BCIN3",
"BRKH_DSP_PCIN37",
"BRKH_DSP_PCIN32",
"BRKH_DSP_ACIN6",
"BRKH_DSP_PCIN14",
"BRKH_DSP_ACIN25",
"BRKH_DSP_BCIN1",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN33",
"BRKH_DSP_ACIN16",
"BRKH_DSP_PCIN7",
"BRKH_DSP_ACIN26",
"BRKH_DSP_BCIN10",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN21",
"BRKH_DSP_PCIN38",
"BRKH_DSP_PCIN22",
"BRKH_DSP_PCIN1",
"BRKH_DSP_BCIN11",
"BRKH_DSP_BCIN5",
"BRKH_DSP_ACIN10",
"BRKH_DSP_PCIN43",
"BRKH_DSP_PCIN15",
"BRKH_DSP_PCIN36",
"BRKH_DSP_PCIN26",
"BRKH_DSP_ACIN29",
"BRKH_DSP_PCIN24",
"BRKH_DSP_ACIN19",
"BRKH_DSP_BCIN7",
"BRKH_DSP_PCIN25",
"BRKH_DSP_ACIN8",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN5",
"BRKH_DSP_BCIN2",
"BRKH_DSP_BCIN9",
"BRKH_DSP_PCIN13",
"BRKH_DSP_ACIN7",
"BRKH_DSP_PCIN19",
"BRKH_DSP_PCIN11",
"BRKH_DSP_ACIN0",
"BRKH_DSP_BCIN12",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN9",
"BRKH_DSP_ACIN20",
"BRKH_DSP_ACIN27",
"BRKH_DSP_ACIN13",
"BRKH_DSP_ACIN22",
"BRKH_DSP_ACIN28",
"BRKH_DSP_PCIN10",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_ACIN1",
"BRKH_DSP_BCIN6",
"BRKH_DSP_ACIN18",
"BRKH_DSP_PCIN28"
],
"sites": []
}

105
artix7/tile_type_BRKH_DSP_R.json Normal file
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{
"tile_type": "BRKH_DSP_R",
"pips": {},
"wires": [
"BRKH_DSP_ACIN2",
"BRKH_DSP_PCIN35",
"BRKH_DSP_PCIN20",
"BRKH_DSP_BCIN15",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN9",
"BRKH_DSP_ACIN14",
"BRKH_DSP_PCIN45",
"BRKH_DSP_PCIN12",
"BRKH_DSP_BCIN16",
"BRKH_DSP_PCIN30",
"BRKH_DSP_PCIN31",
"BRKH_DSP_PCIN29",
"BRKH_DSP_ACIN5",
"BRKH_DSP_PCIN21",
"BRKH_DSP_ACIN3",
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN3",
"BRKH_DSP_PCIN46",
"BRKH_DSP_BCIN4",
"BRKH_DSP_BCIN13",
"BRKH_DSP_PCIN18",
"BRKH_DSP_ACIN24",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN4",
"BRKH_DSP_BCIN0",
"BRKH_DSP_PCIN44",
"BRKH_DSP_BCIN17",
"BRKH_DSP_ACIN15",
"BRKH_DSP_PCIN34",
"BRKH_DSP_ACIN17",
"BRKH_DSP_BCIN14",
"BRKH_DSP_PCIN27",
"BRKH_DSP_BCIN8",
"BRKH_DSP_PCIN2",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN16",
"BRKH_DSP_ACIN12",
"BRKH_DSP_PCIN39",
"BRKH_DSP_ACIN23",
"BRKH_DSP_BCIN3",
"BRKH_DSP_PCIN37",
"BRKH_DSP_PCIN32",
"BRKH_DSP_ACIN6",
"BRKH_DSP_PCIN14",
"BRKH_DSP_ACIN25",
"BRKH_DSP_BCIN1",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN33",
"BRKH_DSP_ACIN16",
"BRKH_DSP_PCIN7",
"BRKH_DSP_ACIN26",
"BRKH_DSP_BCIN10",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN21",
"BRKH_DSP_PCIN38",
"BRKH_DSP_PCIN22",
"BRKH_DSP_PCIN1",
"BRKH_DSP_BCIN11",
"BRKH_DSP_BCIN5",
"BRKH_DSP_ACIN10",
"BRKH_DSP_PCIN43",
"BRKH_DSP_PCIN15",
"BRKH_DSP_PCIN36",
"BRKH_DSP_PCIN26",
"BRKH_DSP_ACIN29",
"BRKH_DSP_PCIN24",
"BRKH_DSP_ACIN19",
"BRKH_DSP_BCIN7",
"BRKH_DSP_PCIN25",
"BRKH_DSP_ACIN8",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN5",
"BRKH_DSP_BCIN2",
"BRKH_DSP_BCIN9",
"BRKH_DSP_PCIN13",
"BRKH_DSP_ACIN7",
"BRKH_DSP_PCIN19",
"BRKH_DSP_PCIN11",
"BRKH_DSP_ACIN0",
"BRKH_DSP_BCIN12",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN9",
"BRKH_DSP_ACIN20",
"BRKH_DSP_ACIN27",
"BRKH_DSP_ACIN13",
"BRKH_DSP_ACIN22",
"BRKH_DSP_ACIN28",
"BRKH_DSP_PCIN10",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_ACIN1",
"BRKH_DSP_BCIN6",
"BRKH_DSP_ACIN18",
"BRKH_DSP_PCIN28"
],
"sites": []
}

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artix7/tile_type_BRKH_GTX.json Normal file
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{
"tile_type": "BRKH_GTX",
"pips": {
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
"is_directional": "1",
"is_pseudo": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"can_invert": "0",
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
"is_directional": "1",
"is_pseudo": "0"
}
},
"wires": [
"BRKH_GTX_REFCLK0_LOWER",
"BRKH_GTX_NORTHREFCLK1_LOWER",
"BRKH_GTX_NORTHREFCLK1_UPPER",
"BRKH_GTX_SOUTHREFCLK0_LOWER",
"BRKH_GTX_REFCLK1_LOWER",
"BRKH_GTX_NORTHREFCLK0_UPPER",
"BRKH_GTX_REFCLK1_UPPER",
"BRKH_GTX_NORTHREFCLK0_LOWER",
"BRKH_GTX_SOUTHREFCLK1_LOWER",
"BRKH_GTX_SOUTHREFCLK0_UPPER",
"BRKH_GTX_REFCLK0_UPPER",
"BRKH_GTX_SOUTHREFCLK1_UPPER"
],
"sites": []
}

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{
"tile_type": "BRKH_INT",
"pips": {
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG2",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG3",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
"dst_wire": "BRKH_INT_SR1END1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END1_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
"dst_wire": "BRKH_INT_SL1END2",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END2_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
"dst_wire": "BRKH_INT_SL1END3",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END3_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG2",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG0",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
"dst_wire": "BRKH_INT_SL1END1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END1_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
"dst_wire": "BRKH_INT_SL1END0",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END0_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG1",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG1",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
"dst_wire": "BRKH_INT_SR1END2",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END2_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG0",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
"dst_wire": "BRKH_INT_SR1END3",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END3_SLOW",
"is_directional": "1",
"can_invert": "0"
}
},
"wires": [
"BRKH_INT_SW2A0",
"BRKH_INT_SS6END0",
"BRKH_INT_SS6D1",
"BRKH_INT_SS6END_N0_3",
"BRKH_INT_NN2A2",
"BRKH_INT_LV8",
"BRKH_INT_SL1END2_SLOW",
"BRKH_INT_SE2A1",
"BRKH_INT_FAN_BOUNCE_S3_4",
"BRKH_INT_NN6BEG3",
"BRKH_INT_SW6D3",
"BRKH_INT_NN6D2",
"BRKH_INT_NE6C3",
"BRKH_INT_SE6B3",
"BRKH_INT_SL1END1",
"BRKH_INT_NW6A0",
"BRKH_INT_NW6C0",
"BRKH_INT_SW6C1",
"BRKH_INT_NR1BEG3_SLOW",
"BRKH_INT_SS2END1",
"BRKH_INT_SR1END1_SLOW",
"BRKH_INT_LVB_L4",
"BRKH_INT_SW6END3",
"BRKH_INT_L_LV5",
"BRKH_INT_LVB_L3",
"BRKH_INT_SR1END2_SLOW",
"BRKH_INT_L_LV12",
"BRKH_INT_SE6D1",
"BRKH_INT_SE6C1",
"BRKH_INT_SE6C0",
"BRKH_INT_NW6B0",
"BRKH_INT_NE6A1",
"BRKH_INT_SL1END0",
"BRKH_INT_SW6C2",
"BRKH_INT_NE6D0",
"BRKH_INT_EL1BEG3",
"BRKH_INT_NW6D0",
"BRKH_INT_SE6E2",
"BRKH_INT_SL1END3",
"BRKH_INT_WR1BEG_S0",
"BRKH_INT_SW2END3",
"BRKH_INT_SS6A1",
"BRKH_INT_LVB_L2",
"BRKH_INT_LVB_L9",
"BRKH_INT_LV9",
"BRKH_INT_FAN_BOUNCE_S3_0",
"BRKH_INT_L_LV8",
"BRKH_INT_SS2END2",
"BRKH_INT_SS6E1",
"BRKH_INT_NW6B1",
"BRKH_INT_NN6E3",
"BRKH_INT_NN6A0",
"BRKH_INT_SE6C2",
"BRKH_INT_SW6D2",
"BRKH_INT_LV12",
"BRKH_INT_L_LV0",
"BRKH_INT_NE6B0",
"BRKH_INT_BYP_BOUNCE2",
"BRKH_INT_SW6B2",
"BRKH_INT_SE6B2",
"BRKH_INT_LVB11",
"BRKH_INT_NL1END_S3_0",
"BRKH_INT_NR1BEG3",
"BRKH_INT_NE2BEG2",
"BRKH_INT_LVB6",
"BRKH_INT_NE6B3",
"BRKH_INT_NN6D3",
"BRKH_INT_L_LV3",
"BRKH_INT_NR1BEG1",
"BRKH_INT_NN6BEG1",
"BRKH_INT_SW6B3",
"BRKH_INT_SS6A3",
"BRKH_INT_LVB7",
"BRKH_INT_L_LV6",
"BRKH_INT_SE6E3",
"BRKH_INT_SL1END1_SLOW",
"BRKH_INT_NW6D1",
"BRKH_INT_NN2A0",
"BRKH_INT_NN2A1",
"BRKH_INT_SS6D3",
"BRKH_INT_SS6B3",
"BRKH_INT_NE6C0",
"BRKH_INT_SR1END1",
"BRKH_INT_SW2A1",
"BRKH_INT_NE2END_S3_0",
"BRKH_INT_NL1BEG0",
"BRKH_INT_NN6BEG0",
"BRKH_INT_NN6A3",
"BRKH_INT_L_LV2",
"BRKH_INT_NE6D3",
"BRKH_INT_NE6B1",
"BRKH_INT_NN2BEG3",
"BRKH_INT_LVB_L6",
"BRKH_INT_L_LV10",
"BRKH_INT_NE2BEG3",
"BRKH_INT_ER1BEG_S0",
"BRKH_INT_NN6C1",
"BRKH_INT_NE6A2",
"BRKH_INT_LV2",
"BRKH_INT_FAN_BOUNCE_S3_6",
"BRKH_INT_SW6D1",
"BRKH_INT_NN6C3",
"BRKH_INT_EL1END_S3_0",
"BRKH_INT_LVB_L1",
"BRKH_INT_NN6C2",
"BRKH_INT_NN6B2",
"BRKH_INT_SE2A2",
"BRKH_INT_SS2A0",
"BRKH_INT_SL1END0_SLOW",
"BRKH_INT_LVB5",
"BRKH_INT_BYP_BOUNCE3",
"BRKH_INT_NW6A2",
"BRKH_INT_NE6A0",
"BRKH_INT_SS6END3",
"BRKH_INT_NE2BEG0",
"BRKH_INT_LV16",
"BRKH_INT_SS6C2",
"BRKH_INT_SS6C3",
"BRKH_INT_LVB_L12",
"BRKH_INT_NW6END_S0_0",
"BRKH_INT_LV11",
"BRKH_INT_SS6A2",
"BRKH_INT_NR1BEG2_SLOW",
"BRKH_INT_LV6",
"BRKH_INT_SW6E1",
"BRKH_INT_SW6B0",
"BRKH_INT_SW6B1",
"BRKH_INT_LVB1",
"BRKH_INT_WL1BEG3",
"BRKH_INT_LVB12",
"BRKH_INT_L_LV16",
"BRKH_INT_NL1BEG2",
"BRKH_INT_SS2END_N0_3",
"BRKH_INT_BYP_BOUNCE6",
"BRKH_INT_NE6D2",
"BRKH_INT_NE6C1",
"BRKH_INT_SL1END2",
"BRKH_INT_SS6B0",
"BRKH_INT_LV0",
"BRKH_INT_NW6B3",
"BRKH_INT_NN6B0",
"BRKH_INT_LV15",
"BRKH_INT_NN6E2",
"BRKH_INT_SS2A2",
"BRKH_INT_BYP_BOUNCE7",
"BRKH_INT_SS2END3",
"BRKH_INT_NN2BEG2",
"BRKH_INT_LVB_L11",
"BRKH_INT_NR1BEG0",
"BRKH_INT_L_LV11",
"BRKH_INT_NE6D1",
"BRKH_INT_L_LV15",
"BRKH_INT_SS6E0",
"BRKH_INT_SS6E2",
"BRKH_INT_SE6D0",
"BRKH_INT_NW2BEG2",
"BRKH_INT_SS6D2",
"BRKH_INT_LV10",
"BRKH_INT_NN2BEG0",
"BRKH_INT_WW4END_S0_0",
"BRKH_INT_NN6C0",
"BRKH_INT_SE6B1",
"BRKH_INT_NR1BEG1_SLOW",
"BRKH_INT_FAN_BOUNCE_S3_2",
"BRKH_INT_NW6B2",
"BRKH_INT_L_LV7",
"BRKH_INT_LVB_L7",
"BRKH_INT_LVB4",
"BRKH_INT_NW6A1",
"BRKH_INT_SS6B2",
"BRKH_INT_WW2END3",
"BRKH_INT_WR1END_S1_0",
"BRKH_INT_NW2BEG1",
"BRKH_INT_LV5",
"BRKH_INT_LV13",
"BRKH_INT_NN6END_S1_0",
"BRKH_INT_SE6E1",
"BRKH_INT_NN6E0",
"BRKH_INT_LVB2",
"BRKH_INT_NE6B2",
"BRKH_INT_SE2A0",
"BRKH_INT_NN6BEG2",
"BRKH_INT_SE6D3",
"BRKH_INT_NW6A3",
"BRKH_INT_SS6END1",
"BRKH_INT_L_LV13",
"BRKH_INT_NL1BEG0_SLOW",
"BRKH_INT_SS6C0",
"BRKH_INT_SS6C1",
"BRKH_INT_NN6B3",
"BRKH_INT_SW6C3",
"BRKH_INT_NN2A3",
"BRKH_INT_SE6C3",
"BRKH_INT_LVB_L5",
"BRKH_INT_LV7",
"BRKH_INT_SE6D2",
"BRKH_INT_NR1BEG0_SLOW",
"BRKH_INT_WL1END3",
"BRKH_INT_NE6C2",
"BRKH_INT_NW6C1",
"BRKH_INT_SS6E3",
"BRKH_INT_LVB8",
"BRKH_INT_LVB10",
"BRKH_INT_SR1END_N3_3",
"BRKH_INT_LV14",
"BRKH_INT_NW2BEG3",
"BRKH_INT_L_LV4",
"BRKH_INT_L_LV1",
"BRKH_INT_LV1",
"BRKH_INT_LV3",
"BRKH_INT_SS6D0",
"BRKH_INT_SE6B0",
"BRKH_INT_NN6B1",
"BRKH_INT_SR1END2",
"BRKH_INT_SW2A3",
"BRKH_INT_LV4",
"BRKH_INT_SW2A2",
"BRKH_INT_NN6E1",
"BRKH_INT_NW2END_S0_0",
"BRKH_INT_SL1END3_SLOW",
"BRKH_INT_NR1BEG2",
"BRKH_INT_SW6E2",
"BRKH_INT_SE6E0",
"BRKH_INT_NN6A1",
"BRKH_INT_NL1BEG1",
"BRKH_INT_NW6D3",
"BRKH_INT_L_LV17",
"BRKH_INT_SS6A0",
"BRKH_INT_LVB9",
"BRKH_INT_LV17",
"BRKH_INT_NL1BEG2_SLOW",
"BRKH_INT_SE2A3",
"BRKH_INT_L_LV9",
"BRKH_INT_NN6A2",
"BRKH_INT_SW6E3",
"BRKH_INT_ER1END3",
"BRKH_INT_SW6E0",
"BRKH_INT_NN2BEG1",
"BRKH_INT_LVB3",
"BRKH_INT_NW2BEG0",
"BRKH_INT_SS2END0",
"BRKH_INT_NW6C3",
"BRKH_INT_NN2END_S2_0",
"BRKH_INT_SW6D0",
"BRKH_INT_NN6D0",
"BRKH_INT_L_LV14",
"BRKH_INT_LVB_L10",
"BRKH_INT_SR1END3",
"BRKH_INT_NL1BEG1_SLOW",
"BRKH_INT_SS2A1",
"BRKH_INT_LVB_L8",
"BRKH_INT_NN6D1",
"BRKH_INT_SS6END2",
"BRKH_INT_SS6B1",
"BRKH_INT_NW6C2",
"BRKH_INT_NW6D2",
"BRKH_INT_SR1END3_SLOW",
"BRKH_INT_SS2A3",
"BRKH_INT_NE6A3",
"BRKH_INT_SW6C0",
"BRKH_INT_NE2BEG1"
],
"sites": []
}

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artix7/tile_type_BRKH_TERM_INT.json Normal file
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{
"tile_type": "BRKH_TERM_INT",
"pips": {},
"wires": [
"T_TERM_UTURN_INT_LVB_L0",
"T_TERM_UTURN_INT_SS6E2",
"T_TERM_UTURN_INT_SS6A2",
"T_TERM_UTURN_INT_SR1END2_SLOW",
"T_TERM_UTURN_INT_SS6C2",
"T_TERM_UTURN_INT_SE2A3",
"T_TERM_UTURN_INT_SW6E3",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
"T_TERM_UTURN_INT_SS6B0",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
"T_TERM_UTURN_INT_LV_L16",
"T_TERM_UTURN_INT_SS6C0",
"T_TERM_UTURN_INT_SS6D3",
"T_TERM_UTURN_INT_SW6B2",
"T_TERM_UTURN_INT_LV_L7",
"T_TERM_INT_UTURN_LV_R9",
"T_TERM_UTURN_INT_SW2A3",
"T_TERM_UTURN_INT_SS6END1",
"T_TERM_UTURN_INT_SS6B1",
"T_TERM_UTURN_INT_SS6C1",
"T_TERM_UTURN_INT_SS6B3",
"T_TERM_UTURN_INT_SE6E0",
"T_TERM_UTURN_INT_SW2A0",
"T_TERM_UTURN_INT_SW6E0",
"T_TERM_INT_UTURN_LV_R16",
"T_TERM_UTURN_INT_SE2A2",
"T_TERM_UTURN_INT_SE6D2",
"T_TERM_UTURN_INT_LVB4",
"T_TERM_UTURN_INT_SS6END0",
"T_TERM_INT_UTURN_LV_R3",
"T_TERM_UTURN_INT_LVB_L3",
"T_TERM_UTURN_INT_SR1END3_SLOW",
"T_TERM_UTURN_INT_SW2A1",
"T_TERM_INT_UTURN_LV_R6",
"T_TERM_UTURN_INT_SE6B3",
"T_TERM_UTURN_INT_LV_L5",
"T_TERM_UTURN_INT_SS6END2",
"T_TERM_UTURN_INT_LVB5",
"T_TERM_UTURN_INT_SS6C3",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
"T_TERM_UTURN_INT_LVB_L2",
"T_TERM_INT_UTURN_LV_R17",
"T_TERM_UTURN_INT_SE6C2",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
"T_TERM_UTURN_INT_SS6D0",
"T_TERM_UTURN_INT_LV_L3",
"T_TERM_UTURN_INT_SS2A0",
"T_TERM_UTURN_INT_SW2A2",
"T_TERM_UTURN_INT_LV_L17",
"T_TERM_UTURN_INT_SR1END1_SLOW",
"T_TERM_UTURN_INT_LV_L4",
"T_TERM_UTURN_INT_WR1BEG_S0",
"T_TERM_UTURN_INT_SW6D2",
"T_TERM_UTURN_INT_LVB0",
"T_TERM_UTURN_INT_SW6C0",
"T_TERM_UTURN_INT_SW6E1",
"T_TERM_UTURN_INT_SW6D0",
"T_TERM_UTURN_INT_SS6A0",
"T_TERM_UTURN_INT_SW6C3",
"T_TERM_UTURN_INT_SL1END0_SLOW",
"T_TERM_UTURN_INT_SS6D1",
"T_TERM_UTURN_INT_SE2A0",
"T_TERM_UTURN_INT_SS2A2",
"T_TERM_UTURN_INT_SW6D1",
"T_TERM_UTURN_INT_SS6A1",
"T_TERM_UTURN_INT_SS6E3",
"T_TERM_UTURN_INT_LV_L9",
"T_TERM_UTURN_INT_SS6A3",
"T_TERM_UTURN_INT_SW6C1",
"T_TERM_UTURN_INT_SL1END3_SLOW",
"T_TERM_UTURN_INT_SS2END3",
"T_TERM_UTURN_INT_LV_L2",
"T_TERM_UTURN_INT_SS2END0",
"T_TERM_UTURN_INT_ER1BEG_S0",
"T_TERM_UTURN_INT_LV_L6",
"T_TERM_UTURN_INT_LVB1",
"T_TERM_UTURN_INT_SE6B1",
"T_TERM_UTURN_INT_LVB_L4",
"T_TERM_UTURN_INT_SL1END2_SLOW",
"T_TERM_UTURN_INT_SE6E2",
"T_TERM_UTURN_INT_WR1END_S1_0",
"T_TERM_UTURN_INT_LVB2",
"T_TERM_UTURN_INT_SL1END1_SLOW",
"T_TERM_UTURN_INT_SS6E0",
"T_TERM_UTURN_INT_SW6B1",
"T_TERM_UTURN_INT_ER1END3",
"T_TERM_INT_UTURN_LV_R4",
"T_TERM_INT_UTURN_LV_R5",
"T_TERM_UTURN_INT_SS6E1",
"T_TERM_UTURN_INT_SW6B3",
"T_TERM_UTURN_INT_SE6E1",
"T_TERM_UTURN_INT_SW6B0",
"T_TERM_UTURN_INT_SS6END3",
"T_TERM_UTURN_INT_LVB_L1",
"T_TERM_UTURN_INT_LVB_L5",
"T_TERM_UTURN_INT_SS6B2",
"T_TERM_UTURN_INT_SS6D2",
"T_TERM_INT_UTURN_LV_R2",
"T_TERM_UTURN_INT_SE6B2",
"T_TERM_UTURN_INT_SE6B0",
"T_TERM_UTURN_INT_SW6D3",
"T_TERM_UTURN_INT_SE6D1",
"T_TERM_UTURN_INT_SS2A1",
"T_TERM_UTURN_INT_SE6D0",
"T_TERM_UTURN_INT_SE6D3",
"T_TERM_UTURN_INT_SS2END2",
"T_TERM_UTURN_INT_SE6C3",
"T_TERM_UTURN_INT_SE6C0",
"T_TERM_UTURN_INT_SS2A3",
"T_TERM_INT_UTURN_LV_R7",
"T_TERM_UTURN_INT_LVB3",
"T_TERM_UTURN_INT_SE6E3",
"T_TERM_UTURN_INT_SW6E2",
"T_TERM_UTURN_INT_SE2A1",
"T_TERM_UTURN_INT_SS2END1",
"T_TERM_UTURN_INT_SW6C2",
"T_TERM_UTURN_INT_SE6C1"
],
"sites": []
}

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artix7/tile_type_B_TERM_INT.json Normal file
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{
"tile_type": "B_TERM_INT",
"pips": {},
"wires": [
"B_TERM_UTURN_INT_SS6C3",
"B_TERM_UTURN_INT_SE6C0",
"B_TERM_UTURN_INT_FAN_BOUNCE6",
"B_TERM_UTURN_INT_FAN_BOUNCE0",
"B_TERM_UTURN_INT_SW6D3",
"B_TERM_UTURN_INT_LV5",
"B_TERM_UTURN_INT_LVB1",
"B_TERM_UTURN_INT_SS6B2",
"B_TERM_UTURN_INT_FAN_BOUNCE4",
"B_TERM_UTURN_INT_SS2BEG2",
"B_TERM_UTURN_INT_SW6D1",
"B_TERM_UTURN_INT_LV4",
"B_TERM_UTURN_INT_LVB0",
"B_TERM_UTURN_INT_ER1END_N3_3",
"B_TERM_UTURN_INT_SW6D0",
"B_TERM_UTURN_INT_SS6B1",
"B_TERM_UTURN_INT_SS2A1",
"B_TERM_UTURN_INT_SW2BEG3",
"B_TERM_UTURN_INT_SW6C2",
"B_TERM_UTURN_INT_SE6A2",
"B_TERM_UTURN_INT_SW2BEG0",
"B_TERM_UTURN_INT_SW6B1",
"B_TERM_UTURN_INT_LV_L8",
"B_TERM_UTURN_INT_SR1BEG2",
"B_TERM_UTURN_INT_SS6BEG0",
"B_TERM_UTURN_INT_LV9",
"B_TERM_UTURN_INT_LV_L4",
"B_TERM_UTURN_INT_SW6B3",
"B_TERM_UTURN_INT_SL1BEG2",
"B_TERM_UTURN_INT_SW2BEG1",
"B_TERM_UTURN_INT_SS2BEG1",
"B_TERM_UTURN_INT_SL1BEG3",
"B_TERM_UTURN_INT_SE6A3",
"B_TERM_UTURN_INT_ER1BEG0",
"B_TERM_UTURN_INT_SS6D1",
"B_TERM_UTURN_INT_SS6BEG1",
"B_TERM_UTURN_INT_SW6A3",
"B_TERM_UTURN_INT_LV8",
"B_TERM_UTURN_INT_SW6D2",
"B_TERM_UTURN_INT_SW6B0",
"B_TERM_UTURN_INT_SE6D3",
"B_TERM_UTURN_INT_SW6C3",
"B_TERM_UTURN_INT_LVB_L5",
"B_TERM_UTURN_INT_SW2BEG2",
"B_TERM_UTURN_INT_SR1BEG1",
"B_TERM_UTURN_INT_SE6B1",
"B_TERM_UTURN_INT_LVB4",
"B_TERM_UTURN_INT_SS6A0",
"B_TERM_UTURN_INT_SS2A2",
"B_TERM_UTURN_INT_SS2BEG0",
"B_TERM_UTURN_INT_SW6C1",
"B_TERM_UTURN_INT_SE6B3",
"B_TERM_UTURN_INT_LV3",
"B_TERM_UTURN_INT_SL1BEG0",
"B_TERM_UTURN_INT_SW6C0",
"B_TERM_UTURN_INT_SS6E2",
"B_TERM_UTURN_INT_LV_L5",
"B_TERM_UTURN_INT_LV_L18",
"B_TERM_UTURN_INT_SS6A2",
"B_TERM_UTURN_INT_SE6C1",
"B_TERM_UTURN_INT_SS6E1",
"B_TERM_UTURN_INT_SE6A1",
"B_TERM_UTURN_INT_SW6A0",
"B_TERM_UTURN_INT_LV_L7",
"B_TERM_UTURN_INT_SS6E3",
"B_TERM_UTURN_INT_LVB2",
"B_TERM_UTURN_INT_SS6D2",
"B_TERM_UTURN_INT_LV_L3",
"B_TERM_UTURN_INT_SS2A0",
"B_TERM_UTURN_INT_LVB_L2",
"B_TERM_UTURN_INT_SE6D1",
"B_TERM_UTURN_INT_SS6E0",
"B_TERM_UTURN_INT_LV7",
"B_TERM_UTURN_INT_SE6B0",
"B_TERM_UTURN_INT_SS6B3",
"B_TERM_UTURN_INT_SE2BEG3",
"B_TERM_UTURN_INT_SW6END_N0_3",
"B_TERM_UTURN_INT_SS6C1",
"B_TERM_UTURN_INT_SW6A2",
"B_TERM_UTURN_INT_LVB_L0",
"B_TERM_UTURN_INT_SS6BEG3",
"B_TERM_UTURN_INT_LV_L2",
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_LVB5",
"B_TERM_UTURN_INT_SS2BEG3",
"B_TERM_UTURN_INT_LVB_L3",
"B_TERM_UTURN_INT_SS6A1",
"B_TERM_UTURN_INT_LVB3",
"B_TERM_UTURN_INT_LV_L6",
"B_TERM_UTURN_INT_SS6D3",
"B_TERM_UTURN_INT_LV_L9",
"B_TERM_UTURN_INT_LVB_L1",
"B_TERM_UTURN_INT_SE2BEG2",
"B_TERM_UTURN_INT_SE6B2",
"B_TERM_UTURN_INT_SS6BEG2",
"B_TERM_UTURN_INT_SE2BEG1",
"B_TERM_UTURN_INT_FAN_BOUNCE2",
"B_TERM_UTURN_INT_SE6C2",
"B_TERM_UTURN_INT_SS2A3",
"B_TERM_UTURN_INT_LVB_L4",
"B_TERM_UTURN_INT_LV2",
"B_TERM_UTURN_INT_SS6B0",
"B_TERM_UTURN_INT_LV18",
"B_TERM_UTURN_INT_LV6",
"B_TERM_UTURN_INT_SS6C0",
"B_TERM_UTURN_INT_SE6A0",
"B_TERM_UTURN_INT_SS6C2",
"B_TERM_UTURN_INT_SW6A1",
"B_TERM_UTURN_INT_SE6D0",
"B_TERM_UTURN_INT_SE2BEG0",
"B_TERM_UTURN_INT_SS6D0",
"B_TERM_UTURN_INT_SR1BEG3",
"B_TERM_UTURN_INT_SW6B2",
"B_TERM_UTURN_INT_SE6C3",
"B_TERM_UTURN_INT_SL1BEG1",
"B_TERM_UTURN_INT_WR1END0",
"B_TERM_UTURN_INT_SS6A3",
"B_TERM_UTURN_INT_SE6D2"
],
"sites": []
}

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artix7/tile_type_CFG_CENTER_BOT.json Normal file
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artix7/tile_type_CFG_CENTER_MID.json Normal file
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artix7/tile_type_CFG_CENTER_TOP.json Normal file
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artix7/tile_type_CLBLL_L.json Normal file
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artix7/tile_type_CLBLL_R.json Normal file
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artix7/tile_type_CLBLM_L.json Normal file
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artix7/tile_type_CLBLM_R.json Normal file
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artix7/tile_type_CLK_BUFG_BOT_R.json Normal file
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artix7/tile_type_CLK_BUFG_REBUF.json Normal file
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artix7/tile_type_CLK_BUFG_TOP_R.json Normal file
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artix7/tile_type_CLK_FEED.json Normal file
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{
"tile_type": "CLK_FEED",
"pips": {},
"wires": [
"CLK_FEED_LH4",
"CLK_FEED_NE4C2",
"CLK_FEED_EL1BEG2",
"CLK_FEED_LH3",
"CLK_FEED_WW4END3",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_FEED_WW4B0",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_EE2A0",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_FEED_R_CK_GCLK1",
"CLK_FEED_NE4BEG0",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_FEED_WW4B2",
"CLK_FEED_EE2A2",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_SW4END1",
"CLK_FEED_SE2A0",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_LH6",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_NW4END1",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_FEED_NW4A1",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_EE2A3",
"CLK_FEED_NE2A0",
"CLK_FEED_EE4C2",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4BEG3",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_NW2A0",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_FEED_R_CK_GCLK2",
"CLK_FEED_NE4BEG1",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_WW4END2",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_EE4B1",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_SE2A2",
"CLK_FEED_WW4C2",
"CLK_FEED_NE4BEG2",
"CLK_FEED_SE4C2",
"CLK_FEED_WW4A2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_NW2A2",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_LH10",
"CLK_FEED_EL1BEG0",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_WW4B3",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_FEED_R_CK_GCLK23",
"CLK_FEED_SE4C0",
"CLK_FEED_WW2A2",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_NE4C0",
"CLK_FEED_NW4END2",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_WL1END0",
"CLK_FEED_WW2END2",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_WW4B1",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_WL1END2",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_ER1BEG2",
"CLK_FEED_R_CK_GCLK31",
"CLK_FEED_SE4BEG3",
"CLK_FEED_LH7",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_FEED_WW2A0",
"CLK_FEED_EE4B2",
"CLK_FEED_SW2A3",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_EE2A1",
"CLK_FEED_EE4C1",
"CLK_FEED_SW4END3",
"CLK_FEED_WR1END3",
"CLK_FEED_EE4C3",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_SW4A2",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_WW4A0",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_FEED_WW2A3",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_EE2BEG2",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_EE2BEG0",
"CLK_FEED_LH1",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_FEED_SE4C1",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_NE4C3",
"CLK_FEED_SE2A1",
"CLK_FEED_NE2A1",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_FEED_WW2END3",
"CLK_FEED_MONITOR_N",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_ER1BEG1",
"CLK_FEED_EE4BEG1",
"CLK_FEED_WR1END1",
"CLK_FEED_R_CK_GCLK26",
"CLK_FEED_R_CK_GCLK16",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_EE4BEG2",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_WW4C3",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_FEED_LH2",
"CLK_FEED_SW4END2",
"CLK_FEED_WW4END0",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_LH9",
"CLK_FEED_NW2A1",
"CLK_FEED_WW2END0",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_R_CK_GCLK22",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_EE4BEG0",
"CLK_FEED_NW4END0",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_EE2BEG1",
"CLK_FEED_SE4BEG0",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_SE2A3",
"CLK_FEED_SW2A2",
"CLK_FEED_NE4C1",
"CLK_FEED_SE4BEG1",
"CLK_FEED_ER1BEG0",
"CLK_FEED_EE4A1",
"CLK_FEED_WW4C0",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_NE2A3",
"CLK_FEED_SW4A3",
"CLK_FEED_NW4A2",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_NE4BEG3",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_SW4A1",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_LH8",
"CLK_FEED_MONITOR_P",
"CLK_FEED_WL1END3",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_WW4END1",
"CLK_FEED_LH5",
"CLK_FEED_SW4END0",
"CLK_FEED_WW4A1",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_ER1BEG3",
"CLK_FEED_SE4BEG2",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_NW4A3",
"CLK_FEED_WR1END2",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_EE4A3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_FEED_R_CK_GCLK12",
"CLK_FEED_CK_GCLK14",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4B3",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_EE4A2",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_NW4END3",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_FEED_WW4C1",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_SE4C3",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_SW4A0",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_FEED_NE2A2",
"CLK_FEED_SW2A1",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_SW2A0",
"CLK_FEED_CK_GCLK11",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK25",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_WL1END1",
"CLK_FEED_R_CK_GCLK14",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_WW2END1",
"CLK_FEED_WW4A3",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_EL1BEG1",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_FEED_LH12",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_WR1END0",
"CLK_FEED_LH11",
"CLK_FEED_WW2A1",
"CLK_FEED_EL1BEG3",
"CLK_FEED_EE4B0",
"CLK_FEED_EE2BEG3",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC12"
],
"sites": []
}

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artix7/tile_type_CLK_HROW_BOT_R.json Normal file
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artix7/tile_type_CLK_HROW_TOP_R.json Normal file
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artix7/tile_type_CLK_MTBF2.json Normal file
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{
"tile_type": "CLK_MTBF2",
"pips": {},
"wires": [
"CLK_FEED_LH4",
"CLK_FEED_NE4C2",
"CLK_PMV_CLK0_0",
"CLK_FEED_EL1BEG2",
"CLK_FEED_LH3",
"CLK_FEED_WW4END3",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_PMV_FAN0_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_FEED_WW4B0",
"CLK_PMV_BYP5_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_EE2A0",
"CLK_PMV_IMUX34_0",
"CLK_MTBF2_Q2B",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_PMV_IMUX3_0",
"CLK_FEED_R_CK_GCLK1",
"CLK_PMV_BYP4_0",
"CLK_FEED_NE4BEG0",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_FEED_WW4B2",
"CLK_FEED_EE2A2",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_SW4END1",
"CLK_FEED_SE2A0",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_PMV_IMUX41_0",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_LH6",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_NW4END1",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_PMV_IMUX25_0",
"CLK_FEED_NW4A1",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_EE2A3",
"CLK_FEED_NE2A0",
"CLK_FEED_EE4C2",
"CLK_PMV_IMUX15_0",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4BEG3",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_NW2A0",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_FEED_R_CK_GCLK2",
"CLK_MTBF2_Q3B",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX2_0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX16_0",
"CLK_FEED_R_CK_GCLK5",
"CLK_MTBF2_Q4B",
"CLK_FEED_WW4END2",
"CLK_PMV_CTRL0_0",
"CLK_PMV_IMUX31_0",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_EE4B1",
"CLK_FEED_SE2A2",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_WW4C2",
"CLK_FEED_NE4BEG2",
"CLK_FEED_SE4C2",
"CLK_FEED_WW4A2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_NW2A2",
"CLK_PMV_IMUX33_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_LH10",
"CLK_FEED_EL1BEG0",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_PMV_LOGIC_OUTS9_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_WW4B3",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX37_0",
"CLK_FEED_R_CK_GCLK23",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_FEED_SE4C0",
"CLK_FEED_WW2A2",
"CLK_PMV_IMUX1_0",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_NE4C0",
"CLK_FEED_NW4END2",
"CLK_FEED_CK_GCLK29",
"CLK_MTBF2_Q0B",
"CLK_FEED_WL1END0",
"CLK_PMV_IMUX36_0",
"CLK_FEED_WW2END2",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_WW4B1",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_WL1END2",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_ER1BEG2",
"CLK_FEED_R_CK_GCLK31",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_FEED_SE4BEG3",
"CLK_PMV_IMUX20_0",
"CLK_FEED_LH7",
"CLK_FEED_NW4A0",
"CLK_FEED_NW2A3",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX4_0",
"CLK_FEED_WW2A0",
"CLK_FEED_EE4B2",
"CLK_FEED_SW2A3",
"CLK_PMV_IMUX45_0",
"CLK_FEED_EE2A1",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_EE4C1",
"CLK_FEED_SW4END3",
"CLK_FEED_WR1END3",
"CLK_FEED_EE4C3",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_SW4A2",
"CLK_PMV_FAN1_0",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_WW4A0",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_PMV_IMUX7_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_FEED_WW2A3",
"CLK_PMV_FAN2_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_IMUX23_0",
"CLK_FEED_EE2BEG0",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_EE2BEG2",
"CLK_FEED_LH1",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_PMV_IMUX11_0",
"CLK_FEED_SE4C1",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_NE4C3",
"CLK_PMV_FAN3_0",
"CLK_FEED_SE2A1",
"CLK_FEED_NE2A1",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_FEED_WW2END3",
"CLK_FEED_MONITOR_N",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_ER1BEG1",
"CLK_FEED_EE4BEG1",
"CLK_PMV_IMUX35_0",
"CLK_FEED_WR1END1",
"CLK_FEED_R_CK_GCLK26",
"CLK_PMV_IMUX19_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_FEED_R_CK_GCLK16",
"CLK_PMV_FAN5_0",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_EE4BEG2",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_BYP3_0",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_WW4C3",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_PMV_IMUX43_0",
"CLK_FEED_LH2",
"CLK_FEED_SW4END2",
"CLK_FEED_WW4END0",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_NW2A1",
"CLK_FEED_LH9",
"CLK_FEED_WW2END0",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_R_CK_GCLK22",
"CLK_PMV_IMUX24_0",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_EE4BEG0",
"CLK_PMV_IMUX10_0",
"CLK_FEED_NW4END0",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_EE2BEG1",
"CLK_FEED_SE4BEG0",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_MTBF2_Q6B",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_PMV_IMUX28_0",
"CLK_MTBF2_Q7B",
"CLK_PMV_BYP6_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_SE2A3",
"CLK_PMV_IMUX40_0",
"CLK_FEED_SW2A2",
"CLK_FEED_NE4C1",
"CLK_FEED_SE4BEG1",
"CLK_FEED_ER1BEG0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_IMUX42_0",
"CLK_FEED_EE4A1",
"CLK_FEED_WW4C0",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_NE2A3",
"CLK_FEED_SW4A3",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_IMUX27_0",
"CLK_FEED_NW4A2",
"CLK_PMV_IMUX38_0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_IMUX30_0",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_NE4BEG3",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_SW4A1",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_MONITOR_P",
"CLK_FEED_LH8",
"CLK_FEED_WL1END3",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_WW4END1",
"CLK_FEED_LH5",
"CLK_FEED_SW4END0",
"CLK_FEED_WW4A1",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_ER1BEG3",
"CLK_FEED_SE4BEG2",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_WR1END2",
"CLK_FEED_NW4A3",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_EE4A3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_FEED_R_CK_GCLK12",
"CLK_PMV_CTRL1_0",
"CLK_FEED_CK_GCLK14",
"CLK_PMV_FAN4_0",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4B3",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_EE4A2",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX21_0",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_NW4END3",
"CLK_PMV_BYP0_0",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_PMV_IMUX47_0",
"CLK_FEED_WW4C1",
"CLK_PMV_IMUX32_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_MTBF2_Q1B",
"CLK_FEED_SE4C3",
"CLK_PMV_IMUX26_0",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_SW4A0",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_PMV_IMUX17_0",
"CLK_FEED_NE2A2",
"CLK_FEED_SW2A1",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_SW2A0",
"CLK_FEED_CK_GCLK11",
"CLK_PMV_IMUX46_0",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_PMV_IMUX12_0",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK25",
"CLK_PMV_IMUX14_0",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_WL1END1",
"CLK_FEED_R_CK_GCLK14",
"CLK_PMV_IMUX0_0",
"CLK_FEED_CK_GCLK10",
"CLK_MTBF2_Q5B",
"CLK_FEED_WW2END1",
"CLK_FEED_WW4A3",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_EL1BEG1",
"CLK_MTBF2_RESET",
"CLK_MTBF2_CLK",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_PMV_IMUX5_0",
"CLK_FEED_LH12",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_WR1END0",
"CLK_FEED_LH11",
"CLK_MTBF2_DIN",
"CLK_PMV_BYP2_0",
"CLK_FEED_WW2A1",
"CLK_PMV_IMUX8_0",
"CLK_FEED_EL1BEG3",
"CLK_PMV_IMUX39_0",
"CLK_PMV_FAN6_0",
"CLK_MTBF2_EN",
"CLK_FEED_EE4B0",
"CLK_PMV_IMUX29_0",
"CLK_FEED_EE2BEG3",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC12"
],
"sites": []
}

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artix7/tile_type_CLK_PMV.json Normal file
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artix7/tile_type_CLK_PMV2.json Normal file
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{
"tile_type": "CLK_PMV2",
"pips": {},
"wires": [
"CLK_FEED_LH4",
"CLK_FEED_NE4C2",
"CLK_PMV_CLK0_0",
"CLK_FEED_EL1BEG2",
"CLK_FEED_LH3",
"CLK_FEED_WW4END3",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_PMV_FAN0_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_FEED_WW4B0",
"CLK_PMV_BYP5_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_EE2A0",
"CLK_PMV_IMUX34_0",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_PMV_IMUX3_0",
"CLK_FEED_R_CK_GCLK1",
"CLK_PMV_BYP4_0",
"CLK_FEED_NE4BEG0",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_FEED_WW4B2",
"CLK_FEED_EE2A2",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_SW4END1",
"CLK_FEED_SE2A0",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_PMV_IMUX41_0",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_LH6",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_NW4END1",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_PMV_IMUX25_0",
"CLK_FEED_NW4A1",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_EE2A3",
"CLK_FEED_NE2A0",
"CLK_PMV2_ODIV4",
"CLK_FEED_EE4C2",
"CLK_PMV_IMUX15_0",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4BEG3",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_NW2A0",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_PMV2_EN",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_FEED_R_CK_GCLK2",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX2_0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX16_0",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_WW4END2",
"CLK_PMV_CTRL0_0",
"CLK_PMV_IMUX31_0",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_EE4B1",
"CLK_FEED_SE2A2",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_WW4C2",
"CLK_FEED_NE4BEG2",
"CLK_FEED_SE4C2",
"CLK_FEED_WW4A2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_NW2A2",
"CLK_PMV_IMUX33_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_LH10",
"CLK_FEED_EL1BEG0",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_PMV_LOGIC_OUTS9_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_WW4B3",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX37_0",
"CLK_FEED_R_CK_GCLK23",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_FEED_SE4C0",
"CLK_FEED_WW2A2",
"CLK_PMV_IMUX1_0",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_NE4C0",
"CLK_FEED_NW4END2",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_WL1END0",
"CLK_PMV_IMUX36_0",
"CLK_FEED_WW2END2",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_WW4B1",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_WL1END2",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_ER1BEG2",
"CLK_FEED_R_CK_GCLK31",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_FEED_SE4BEG3",
"CLK_PMV_IMUX20_0",
"CLK_FEED_LH7",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX4_0",
"CLK_FEED_WW2A0",
"CLK_FEED_EE4B2",
"CLK_PMV2_A0",
"CLK_FEED_SW2A3",
"CLK_PMV_IMUX45_0",
"CLK_FEED_EE2A1",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_EE4C1",
"CLK_FEED_SW4END3",
"CLK_FEED_WR1END3",
"CLK_FEED_EE4C3",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_SW4A2",
"CLK_PMV_FAN1_0",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_WW4A0",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_PMV_IMUX7_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_FEED_WW2A3",
"CLK_PMV_FAN2_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_IMUX23_0",
"CLK_FEED_EE2BEG0",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_EE2BEG2",
"CLK_FEED_LH1",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_PMV_IMUX11_0",
"CLK_FEED_SE4C1",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_NE4C3",
"CLK_PMV_FAN3_0",
"CLK_FEED_SE2A1",
"CLK_FEED_NE2A1",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_FEED_WW2END3",
"CLK_FEED_MONITOR_N",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_ER1BEG1",
"CLK_FEED_EE4BEG1",
"CLK_PMV_IMUX35_0",
"CLK_FEED_WR1END1",
"CLK_FEED_R_CK_GCLK26",
"CLK_PMV_IMUX19_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_FEED_R_CK_GCLK16",
"CLK_PMV_FAN5_0",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_EE4BEG2",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_BYP3_0",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_WW4C3",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_PMV_IMUX43_0",
"CLK_FEED_LH2",
"CLK_FEED_SW4END2",
"CLK_FEED_WW4END0",
"CLK_PMV2_A1",
"CLK_PMV2_ODIV2",
"CLK_FEED_CK_GCLK12",
"CLK_PMV2_O",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_NW2A1",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_LH9",
"CLK_FEED_WW2END0",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_R_CK_GCLK22",
"CLK_PMV_IMUX24_0",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_EE4BEG0",
"CLK_PMV_IMUX10_0",
"CLK_FEED_NW4END0",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_EE2BEG1",
"CLK_FEED_SE4BEG0",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_PMV_IMUX28_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_SE2A3",
"CLK_PMV_IMUX40_0",
"CLK_FEED_SW2A2",
"CLK_FEED_NE4C1",
"CLK_FEED_SE4BEG1",
"CLK_FEED_ER1BEG0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_IMUX42_0",
"CLK_FEED_EE4A1",
"CLK_FEED_WW4C0",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_NE2A3",
"CLK_FEED_SW4A3",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_IMUX27_0",
"CLK_FEED_NW4A2",
"CLK_PMV_IMUX38_0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_PMV_IMUX30_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_NE4BEG3",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_SW4A1",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_MONITOR_P",
"CLK_FEED_LH8",
"CLK_FEED_WL1END3",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_WW4END1",
"CLK_FEED_LH5",
"CLK_FEED_SW4END0",
"CLK_FEED_WW4A1",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_ER1BEG3",
"CLK_FEED_SE4BEG2",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_WR1END2",
"CLK_FEED_NW4A3",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_EE4A3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_FEED_R_CK_GCLK12",
"CLK_PMV_CTRL1_0",
"CLK_FEED_CK_GCLK14",
"CLK_PMV_FAN4_0",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4B3",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_EE4A2",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX21_0",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_NW4END3",
"CLK_PMV_BYP0_0",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_PMV_IMUX47_0",
"CLK_FEED_WW4C1",
"CLK_PMV_IMUX32_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_SE4C3",
"CLK_PMV_IMUX26_0",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_SW4A0",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_PMV_IMUX17_0",
"CLK_FEED_NE2A2",
"CLK_FEED_SW2A1",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_SW2A0",
"CLK_FEED_CK_GCLK11",
"CLK_PMV_IMUX46_0",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_PMV_IMUX12_0",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK25",
"CLK_PMV_IMUX14_0",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_CK_GCLK3",
"CLK_PMV2_A2",
"CLK_FEED_WL1END1",
"CLK_FEED_R_CK_GCLK14",
"CLK_PMV_IMUX0_0",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_WW2END1",
"CLK_FEED_WW4A3",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_EL1BEG1",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_PMV_IMUX5_0",
"CLK_FEED_LH12",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_WR1END0",
"CLK_FEED_LH11",
"CLK_PMV_BYP2_0",
"CLK_FEED_WW2A1",
"CLK_PMV_IMUX8_0",
"CLK_FEED_EL1BEG3",
"CLK_PMV_IMUX39_0",
"CLK_PMV_FAN6_0",
"CLK_FEED_EE4B0",
"CLK_PMV_IMUX29_0",
"CLK_FEED_EE2BEG3",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC12"
],
"sites": [
{
"type": "PMV2",
"y_coord": 0,
"name": "X0Y0",
"prefix": "PMV",
"x_coord": 0,
"site_pins": {
"A0": "CLK_PMV2_A0",
"O": "CLK_PMV2_O",
"A2": "CLK_PMV2_A2",
"ODIV4": "CLK_PMV2_ODIV4",
"EN": "CLK_PMV2_EN",
"ODIV2": "CLK_PMV2_ODIV2",
"A1": "CLK_PMV2_A1"
}
}
]
}

360
artix7/tile_type_CLK_PMV2_SVT.json Normal file
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{
"tile_type": "CLK_PMV2_SVT",
"pips": {},
"wires": [
"CLK_FEED_LH4",
"CLK_FEED_NE4C2",
"CLK_PMV_CLK0_0",
"CLK_FEED_EL1BEG2",
"CLK_FEED_LH3",
"CLK_FEED_WW4END3",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_PMV_FAN0_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_FEED_WW4B0",
"CLK_PMV_BYP5_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_EE2A0",
"CLK_PMV_IMUX34_0",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_PMV_IMUX3_0",
"CLK_FEED_R_CK_GCLK1",
"CLK_PMV_BYP4_0",
"CLK_FEED_NE4BEG0",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_FEED_WW4B2",
"CLK_FEED_EE2A2",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_SW4END1",
"CLK_FEED_SE2A0",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_PMV_IMUX41_0",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_LH6",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_NW4END1",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_PMV_IMUX25_0",
"CLK_FEED_NW4A1",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_EE2A3",
"CLK_FEED_NE2A0",
"CLK_PMV2_ODIV4",
"CLK_FEED_EE4C2",
"CLK_PMV_IMUX15_0",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4BEG3",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_NW2A0",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_PMV2_EN",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_FEED_R_CK_GCLK2",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX2_0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX16_0",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_WW4END2",
"CLK_PMV_CTRL0_0",
"CLK_PMV_IMUX31_0",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_EE4B1",
"CLK_FEED_SE2A2",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_WW4C2",
"CLK_FEED_NE4BEG2",
"CLK_FEED_SE4C2",
"CLK_FEED_WW4A2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_NW2A2",
"CLK_PMV_IMUX33_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_LH10",
"CLK_FEED_EL1BEG0",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_PMV_LOGIC_OUTS9_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_WW4B3",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX37_0",
"CLK_FEED_R_CK_GCLK23",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_FEED_SE4C0",
"CLK_FEED_WW2A2",
"CLK_PMV_IMUX1_0",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_NE4C0",
"CLK_FEED_NW4END2",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_WL1END0",
"CLK_PMV_IMUX36_0",
"CLK_FEED_WW2END2",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_WW4B1",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_WL1END2",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_ER1BEG2",
"CLK_FEED_R_CK_GCLK31",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_FEED_SE4BEG3",
"CLK_PMV_IMUX20_0",
"CLK_FEED_LH7",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_PMV_IMUX22_0",
"CLK_PMV_IMUX4_0",
"CLK_FEED_WW2A0",
"CLK_FEED_EE4B2",
"CLK_PMV2_A0",
"CLK_FEED_SW2A3",
"CLK_PMV_IMUX45_0",
"CLK_FEED_EE2A1",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_EE4C1",
"CLK_FEED_SW4END3",
"CLK_FEED_WR1END3",
"CLK_FEED_EE4C3",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_SW4A2",
"CLK_PMV_FAN1_0",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_WW4A0",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_PMV_IMUX7_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_FEED_WW2A3",
"CLK_PMV_FAN2_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_IMUX23_0",
"CLK_FEED_EE2BEG0",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_EE2BEG2",
"CLK_FEED_LH1",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_PMV_IMUX11_0",
"CLK_FEED_SE4C1",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_NE4C3",
"CLK_PMV_FAN3_0",
"CLK_FEED_SE2A1",
"CLK_FEED_NE2A1",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_FEED_WW2END3",
"CLK_FEED_MONITOR_N",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_ER1BEG1",
"CLK_FEED_EE4BEG1",
"CLK_PMV_IMUX35_0",
"CLK_FEED_WR1END1",
"CLK_FEED_R_CK_GCLK26",
"CLK_PMV_IMUX19_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_FEED_R_CK_GCLK16",
"CLK_PMV_FAN5_0",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_EE4BEG2",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_BYP3_0",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_WW4C3",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_PMV_IMUX43_0",
"CLK_FEED_LH2",
"CLK_FEED_SW4END2",
"CLK_FEED_WW4END0",
"CLK_PMV2_A1",
"CLK_PMV2_ODIV2",
"CLK_FEED_CK_GCLK12",
"CLK_PMV2_O",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_NW2A1",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_LH9",
"CLK_FEED_WW2END0",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_R_CK_GCLK22",
"CLK_PMV_IMUX24_0",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_EE4BEG0",
"CLK_PMV_IMUX10_0",
"CLK_FEED_NW4END0",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_EE2BEG1",
"CLK_FEED_SE4BEG0",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_PMV_IMUX28_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_SE2A3",
"CLK_PMV_IMUX40_0",
"CLK_FEED_SW2A2",
"CLK_FEED_NE4C1",
"CLK_FEED_SE4BEG1",
"CLK_FEED_ER1BEG0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_IMUX42_0",
"CLK_FEED_EE4A1",
"CLK_FEED_WW4C0",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_NE2A3",
"CLK_FEED_SW4A3",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_IMUX27_0",
"CLK_FEED_NW4A2",
"CLK_PMV_IMUX38_0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_PMV_IMUX30_0",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_NE4BEG3",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_SW4A1",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_MONITOR_P",
"CLK_FEED_LH8",
"CLK_FEED_WL1END3",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_WW4END1",
"CLK_FEED_LH5",
"CLK_FEED_SW4END0",
"CLK_FEED_WW4A1",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_ER1BEG3",
"CLK_FEED_SE4BEG2",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_WR1END2",
"CLK_FEED_NW4A3",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_EE4A3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_FEED_R_CK_GCLK12",
"CLK_PMV_CTRL1_0",
"CLK_FEED_CK_GCLK14",
"CLK_PMV_FAN4_0",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4B3",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_EE4A2",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX21_0",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_NW4END3",
"CLK_PMV_BYP0_0",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_PMV_IMUX47_0",
"CLK_FEED_WW4C1",
"CLK_PMV_IMUX32_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_SE4C3",
"CLK_PMV_IMUX26_0",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_SW4A0",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_PMV_IMUX17_0",
"CLK_FEED_NE2A2",
"CLK_FEED_SW2A1",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_SW2A0",
"CLK_FEED_CK_GCLK11",
"CLK_PMV_IMUX46_0",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_PMV_IMUX12_0",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK25",
"CLK_PMV_IMUX14_0",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_CK_GCLK3",
"CLK_PMV2_A2",
"CLK_FEED_WL1END1",
"CLK_FEED_R_CK_GCLK14",
"CLK_PMV_IMUX0_0",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_WW2END1",
"CLK_FEED_WW4A3",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_EL1BEG1",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_PMV_IMUX5_0",
"CLK_FEED_LH12",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_WR1END0",
"CLK_FEED_LH11",
"CLK_PMV_BYP2_0",
"CLK_FEED_WW2A1",
"CLK_PMV_IMUX8_0",
"CLK_FEED_EL1BEG3",
"CLK_PMV_IMUX39_0",
"CLK_PMV_FAN6_0",
"CLK_FEED_EE4B0",
"CLK_PMV_IMUX29_0",
"CLK_FEED_EE2BEG3",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC12"
],
"sites": []
}

359
artix7/tile_type_CLK_PMVIOB.json Normal file
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{
"tile_type": "CLK_PMVIOB",
"pips": {},
"wires": [
"CLK_FEED_LH4",
"CLK_FEED_NE4C2",
"CLK_PMV_CLK0_0",
"CLK_FEED_EL1BEG2",
"CLK_FEED_LH3",
"CLK_FEED_WW4END3",
"CLK_FEED_CK_BUFG_CASC29",
"CLK_PMV_FAN0_0",
"CLK_PMV_LOGIC_OUTS17_0",
"CLK_FEED_WW4B0",
"CLK_PMV_BYP5_0",
"CLK_PMV_LOGIC_OUTS21_0",
"CLK_FEED_R_CK_BUFG_CASC22",
"CLK_PMV_LOGIC_OUTS4_0",
"CLK_FEED_R_CK_BUFG_CASC4",
"CLK_FEED_R_CK_BUFG_CASC30",
"CLK_FEED_EE2A0",
"CLK_PMV_IMUX34_0",
"CLK_FEED_CK_BUFG_CASC5",
"CLK_PMV_IMUX3_0",
"CLK_FEED_R_CK_GCLK1",
"CLK_PMV_BYP4_0",
"CLK_FEED_NE4BEG0",
"CLK_FEED_CK_BUFG_CASC30",
"CLK_PMVIOB_ODIV2",
"CLK_PMV_LOGIC_OUTS15_0",
"CLK_FEED_WW4B2",
"CLK_FEED_EE2A2",
"CLK_FEED_CK_GCLK28",
"CLK_FEED_R_CK_GCLK13",
"CLK_FEED_CK_GCLK26",
"CLK_FEED_SW4END1",
"CLK_FEED_SE2A0",
"CLK_FEED_R_CK_BUFG_CASC27",
"CLK_PMV_IMUX41_0",
"CLK_FEED_CK_GCLK13",
"CLK_FEED_CK_GCLK19",
"CLK_FEED_LH6",
"CLK_PMVIOB_ODIV4",
"CLK_FEED_R_CK_BUFG_CASC29",
"CLK_FEED_NW4END1",
"CLK_PMVIOB_A0",
"CLK_FEED_R_CK_BUFG_CASC2",
"CLK_FEED_R_CK_BUFG_CASC15",
"CLK_PMV_IMUX25_0",
"CLK_FEED_NW4A1",
"CLK_FEED_CK_GCLK22",
"CLK_FEED_EE2A3",
"CLK_FEED_NE2A0",
"CLK_FEED_EE4C2",
"CLK_PMV_IMUX15_0",
"CLK_FEED_EE4A0",
"CLK_FEED_EE4BEG3",
"CLK_FEED_CK_GCLK6",
"CLK_FEED_NW2A0",
"CLK_FEED_R_CK_GCLK25",
"CLK_FEED_R_CK_BUFG_CASC28",
"CLK_PMV_LOGIC_OUTS3_0",
"CLK_FEED_R_CK_GCLK2",
"CLK_PMV_FAN7_0",
"CLK_PMV_IMUX2_0",
"CLK_FEED_NE4BEG1",
"CLK_FEED_CK_BUFG_CASC7",
"CLK_PMV_IMUX13_0",
"CLK_PMV_IMUX16_0",
"CLK_FEED_R_CK_GCLK5",
"CLK_FEED_WW4END2",
"CLK_PMV_CTRL0_0",
"CLK_PMV_IMUX31_0",
"CLK_FEED_CK_GCLK8",
"CLK_FEED_EE4B1",
"CLK_FEED_SE2A2",
"CLK_FEED_R_CK_GCLK21",
"CLK_FEED_WW4C2",
"CLK_FEED_NE4BEG2",
"CLK_FEED_SE4C2",
"CLK_FEED_WW4A2",
"CLK_FEED_CK_GCLK20",
"CLK_FEED_NW2A2",
"CLK_PMV_IMUX33_0",
"CLK_PMV_CLK1_0",
"CLK_PMV_IMUX9_0",
"CLK_PMV_LOGIC_OUTS10_0",
"CLK_FEED_CK_BUFG_CASC15",
"CLK_FEED_LH10",
"CLK_FEED_EL1BEG0",
"CLK_FEED_CK_BUFG_CASC9",
"CLK_PMV_LOGIC_OUTS9_0",
"CLK_PMV_LOGIC_OUTS20_0",
"CLK_FEED_CK_BUFG_CASC17",
"CLK_FEED_CK_BUFG_CASC3",
"CLK_FEED_WW4B3",
"CLK_FEED_R_CK_BUFG_CASC3",
"CLK_FEED_CK_BUFG_CASC14",
"CLK_PMV_IMUX18_0",
"CLK_PMV_IMUX37_0",
"CLK_FEED_R_CK_GCLK23",
"CLK_PMV_LOGIC_OUTS8_0",
"CLK_FEED_SE4C0",
"CLK_PMV_IMUX1_0",
"CLK_FEED_WW2A2",
"CLK_FEED_CK_GCLK17",
"CLK_FEED_NE4C0",
"CLK_FEED_NW4END2",
"CLK_FEED_CK_GCLK29",
"CLK_FEED_WL1END0",
"CLK_PMV_IMUX36_0",
"CLK_FEED_WW2END2",
"CLK_FEED_CK_BUFG_CASC26",
"CLK_FEED_R_CK_BUFG_CASC26",
"CLK_PMV_LOGIC_OUTS11_0",
"CLK_FEED_CK_BUFG_CASC0",
"CLK_FEED_WW4B1",
"CLK_FEED_CK_GCLK0",
"CLK_FEED_R_CK_BUFG_CASC19",
"CLK_FEED_WL1END2",
"CLK_FEED_CK_BUFG_CASC23",
"CLK_FEED_R_CK_GCLK6",
"CLK_FEED_ER1BEG2",
"CLK_FEED_R_CK_GCLK31",
"CLK_PMV_LOGIC_OUTS13_0",
"CLK_FEED_SE4BEG3",
"CLK_PMV_IMUX20_0",
"CLK_FEED_LH7",
"CLK_FEED_NW2A3",
"CLK_FEED_NW4A0",
"CLK_PMV_IMUX22_0",
"CLK_FEED_WW2A0",
"CLK_PMV_IMUX4_0",
"CLK_FEED_EE4B2",
"CLK_FEED_SW2A3",
"CLK_PMV_IMUX45_0",
"CLK_FEED_EE2A1",
"CLK_FEED_CK_BUFG_CASC21",
"CLK_FEED_R_CK_GCLK3",
"CLK_FEED_EE4C1",
"CLK_FEED_SW4END3",
"CLK_FEED_WR1END3",
"CLK_FEED_EE4C3",
"CLK_FEED_R_CK_GCLK8",
"CLK_FEED_CK_BUFG_CASC1",
"CLK_FEED_R_CK_GCLK10",
"CLK_FEED_SW4A2",
"CLK_PMV_FAN1_0",
"CLK_FEED_R_CK_GCLK7",
"CLK_FEED_R_CK_GCLK4",
"CLK_FEED_WW4A0",
"CLK_FEED_CK_BUFG_CASC28",
"CLK_FEED_CK_GCLK31",
"CLK_FEED_R_CK_BUFG_CASC11",
"CLK_PMV_IMUX7_0",
"CLK_PMV_BYP7_0",
"CLK_PMV_BYP1_0",
"CLK_PMV_LOGIC_OUTS7_0",
"CLK_FEED_WW2A3",
"CLK_PMV_FAN2_0",
"CLK_PMV_LOGIC_OUTS2_0",
"CLK_PMV_IMUX6_0",
"CLK_PMV_LOGIC_OUTS22_0",
"CLK_PMV_IMUX23_0",
"CLK_FEED_EE2BEG0",
"CLK_FEED_CK_BUFG_CASC2",
"CLK_FEED_CK_BUFG_CASC24",
"CLK_FEED_EE2BEG2",
"CLK_FEED_LH1",
"CLK_FEED_CK_BUFG_CASC22",
"CLK_PMV_IMUX11_0",
"CLK_FEED_SE4C1",
"CLK_PMV_LOGIC_OUTS23_0",
"CLK_FEED_R_CK_BUFG_CASC25",
"CLK_FEED_NE4C3",
"CLK_PMV_FAN3_0",
"CLK_FEED_SE2A1",
"CLK_FEED_NE2A1",
"CLK_FEED_R_CK_BUFG_CASC18",
"CLK_PMV_LOGIC_OUTS19_0",
"CLK_FEED_WW2END3",
"CLK_FEED_MONITOR_N",
"CLK_FEED_R_CK_BUFG_CASC17",
"CLK_FEED_ER1BEG1",
"CLK_FEED_EE4BEG1",
"CLK_PMV_IMUX35_0",
"CLK_FEED_WR1END1",
"CLK_FEED_R_CK_GCLK26",
"CLK_PMV_IMUX19_0",
"CLK_PMV_LOGIC_OUTS0_0",
"CLK_FEED_R_CK_GCLK16",
"CLK_PMV_FAN5_0",
"CLK_FEED_R_CK_BUFG_CASC9",
"CLK_FEED_EE4BEG2",
"CLK_PMV_LOGIC_OUTS12_0",
"CLK_PMV_BYP3_0",
"CLK_FEED_R_CK_BUFG_CASC7",
"CLK_FEED_WW4C3",
"CLK_FEED_R_CK_GCLK29",
"CLK_FEED_CK_BUFG_CASC6",
"CLK_PMV_IMUX43_0",
"CLK_FEED_LH2",
"CLK_FEED_SW4END2",
"CLK_FEED_WW4END0",
"CLK_FEED_CK_GCLK12",
"CLK_FEED_CK_BUFG_CASC31",
"CLK_FEED_R_CK_GCLK9",
"CLK_FEED_CK_BUFG_CASC11",
"CLK_FEED_NW2A1",
"CLK_FEED_LH9",
"CLK_FEED_WW2END0",
"CLK_FEED_CK_GCLK9",
"CLK_FEED_R_CK_GCLK22",
"CLK_PMV_IMUX24_0",
"CLK_FEED_R_CK_BUFG_CASC10",
"CLK_FEED_EE4BEG0",
"CLK_PMV_IMUX10_0",
"CLK_FEED_NW4END0",
"CLK_FEED_CK_GCLK7",
"CLK_FEED_CK_BUFG_CASC19",
"CLK_FEED_EE2BEG1",
"CLK_FEED_SE4BEG0",
"CLK_FEED_R_CK_GCLK27",
"CLK_FEED_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC12",
"CLK_FEED_CK_BUFG_CASC4",
"CLK_FEED_CK_BUFG_CASC20",
"CLK_PMV_IMUX28_0",
"CLK_PMV_BYP6_0",
"CLK_PMV_LOGIC_OUTS5_0",
"CLK_FEED_R_CK_GCLK20",
"CLK_FEED_SE2A3",
"CLK_PMV_IMUX40_0",
"CLK_FEED_SW2A2",
"CLK_FEED_NE4C1",
"CLK_FEED_SE4BEG1",
"CLK_FEED_ER1BEG0",
"CLK_PMV_LOGIC_OUTS16_0",
"CLK_PMV_IMUX42_0",
"CLK_FEED_EE4A1",
"CLK_FEED_WW4C0",
"CLK_PMVIOB_A1",
"CLK_FEED_R_CK_GCLK11",
"CLK_FEED_NE2A3",
"CLK_FEED_SW4A3",
"CLK_PMV_LOGIC_OUTS6_0",
"CLK_PMV_IMUX27_0",
"CLK_FEED_NW4A2",
"CLK_PMV_IMUX38_0",
"CLK_FEED_R_CK_BUFG_CASC1",
"CLK_PMVIOB_O",
"CLK_PMV_LOGIC_OUTS14_0",
"CLK_PMV_IMUX30_0",
"CLK_FEED_CK_GCLK23",
"CLK_FEED_CK_GCLK18",
"CLK_FEED_R_CK_BUFG_CASC20",
"CLK_FEED_NE4BEG3",
"CLK_FEED_CK_GCLK16",
"CLK_FEED_SW4A1",
"CLK_FEED_R_CK_BUFG_CASC23",
"CLK_FEED_CK_GCLK21",
"CLK_FEED_MONITOR_P",
"CLK_FEED_LH8",
"CLK_FEED_WL1END3",
"CLK_FEED_R_CK_GCLK18",
"CLK_FEED_WW4END1",
"CLK_FEED_LH5",
"CLK_FEED_SW4END0",
"CLK_FEED_WW4A1",
"CLK_FEED_R_CK_GCLK15",
"CLK_FEED_CK_BUFG_CASC18",
"CLK_FEED_R_CK_BUFG_CASC6",
"CLK_FEED_ER1BEG3",
"CLK_FEED_SE4BEG2",
"CLK_FEED_CK_GCLK1",
"CLK_FEED_WR1END2",
"CLK_FEED_NW4A3",
"CLK_FEED_CK_GCLK24",
"CLK_FEED_EE4A3",
"CLK_FEED_R_CK_BUFG_CASC0",
"CLK_PMV_LOGIC_OUTS18_0",
"CLK_FEED_R_CK_GCLK12",
"CLK_PMV_CTRL1_0",
"CLK_FEED_CK_GCLK14",
"CLK_PMV_FAN4_0",
"CLK_FEED_CK_GCLK4",
"CLK_FEED_EE4C0",
"CLK_FEED_EE4B3",
"CLK_FEED_R_CK_GCLK24",
"CLK_FEED_EE4A2",
"CLK_PMV_IMUX44_0",
"CLK_PMV_IMUX21_0",
"CLK_FEED_R_CK_GCLK30",
"CLK_FEED_R_CK_BUFG_CASC24",
"CLK_FEED_CK_BUFG_CASC13",
"CLK_FEED_R_CK_BUFG_CASC5",
"CLK_FEED_NW4END3",
"CLK_PMV_BYP0_0",
"CLK_FEED_R_CK_BUFG_CASC21",
"CLK_PMV_IMUX47_0",
"CLK_FEED_WW4C1",
"CLK_PMV_IMUX32_0",
"CLK_PMV_LOGIC_OUTS1_0",
"CLK_FEED_R_CK_BUFG_CASC8",
"CLK_FEED_SE4C3",
"CLK_PMV_IMUX26_0",
"CLK_FEED_CK_BUFG_CASC10",
"CLK_FEED_SW4A0",
"CLK_FEED_CK_BUFG_CASC27",
"CLK_FEED_R_CK_BUFG_CASC13",
"CLK_PMV_IMUX17_0",
"CLK_FEED_NE2A2",
"CLK_FEED_SW2A1",
"CLK_FEED_CK_GCLK15",
"CLK_FEED_SW2A0",
"CLK_FEED_CK_GCLK11",
"CLK_PMV_IMUX46_0",
"CLK_FEED_CK_BUFG_CASC25",
"CLK_PMV_IMUX12_0",
"CLK_FEED_CK_GCLK2",
"CLK_FEED_CK_GCLK25",
"CLK_PMV_IMUX14_0",
"CLK_FEED_R_CK_GCLK0",
"CLK_FEED_CK_GCLK3",
"CLK_FEED_WL1END1",
"CLK_FEED_R_CK_GCLK14",
"CLK_PMV_IMUX0_0",
"CLK_FEED_CK_GCLK10",
"CLK_FEED_WW2END1",
"CLK_FEED_WW4A3",
"CLK_FEED_R_CK_BUFG_CASC31",
"CLK_FEED_CK_GCLK5",
"CLK_FEED_CK_GCLK27",
"CLK_FEED_CK_BUFG_CASC16",
"CLK_FEED_R_CK_GCLK28",
"CLK_FEED_EL1BEG1",
"CLK_PMVIOB_EN",
"CLK_FEED_R_CK_GCLK19",
"CLK_FEED_CK_BUFG_CASC8",
"CLK_PMV_IMUX5_0",
"CLK_FEED_LH12",
"CLK_FEED_R_CK_GCLK17",
"CLK_FEED_WR1END0",
"CLK_FEED_LH11",
"CLK_PMV_BYP2_0",
"CLK_FEED_WW2A1",
"CLK_PMV_IMUX8_0",
"CLK_FEED_EL1BEG3",
"CLK_PMV_IMUX39_0",
"CLK_PMV_FAN6_0",
"CLK_FEED_EE4B0",
"CLK_PMV_IMUX29_0",
"CLK_FEED_EE2BEG3",
"CLK_FEED_R_CK_BUFG_CASC14",
"CLK_FEED_R_CK_BUFG_CASC16",
"CLK_FEED_CK_BUFG_CASC12"
],
"sites": []
}

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artix7/tile_type_CLK_TERM.json Normal file
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{
"tile_type": "CLK_TERM",
"pips": {},
"wires": [
"CLK_TERM_R_GCLK6",
"CLK_TERM_R_GCLK28",
"CLK_TERM_GCLK15",
"CLK_TERM_R_GCLK12",
"CLK_TERM_R_GCLK23",
"CLK_TERM_R_GCLK20",
"CLK_TERM_GCLK1",
"CLK_TERM_R_GCLK14",
"CLK_TERM_GCLK28",
"CLK_TERM_R_GCLK3",
"CLK_TERM_R_GCLK30",
"CLK_TERM_GCLK13",
"CLK_TERM_GCLK21",
"CLK_TERM_GCLK14",
"CLK_TERM_GCLK0",
"CLK_TERM_GCLK26",
"CLK_TERM_R_GCLK4",
"CLK_TERM_R_GCLK5",
"CLK_TERM_R_GCLK18",
"CLK_TERM_R_GCLK31",
"CLK_TERM_GCLK10",
"CLK_TERM_R_GCLK8",
"CLK_TERM_R_GCLK22",
"CLK_TERM_GCLK22",
"CLK_TERM_GCLK24",
"CLK_TERM_R_GCLK1",
"CLK_TERM_GCLK17",
"CLK_TERM_GCLK9",
"CLK_TERM_GCLK3",
"CLK_TERM_R_GCLK26",
"CLK_TERM_GCLK25",
"CLK_TERM_R_GCLK19",
"CLK_TERM_GCLK19",
"CLK_TERM_GCLK30",
"CLK_TERM_R_GCLK15",
"CLK_TERM_GCLK29",
"CLK_TERM_GCLK5",
"CLK_TERM_R_GCLK17",
"CLK_TERM_GCLK7",
"CLK_TERM_R_GCLK21",
"CLK_TERM_GCLK18",
"CLK_TERM_R_GCLK24",
"CLK_TERM_R_GCLK7",
"CLK_TERM_GCLK8",
"CLK_TERM_GCLK12",
"CLK_TERM_R_GCLK13",
"CLK_TERM_GCLK2",
"CLK_TERM_R_GCLK2",
"CLK_TERM_R_GCLK0",
"CLK_TERM_R_GCLK9",
"CLK_TERM_R_GCLK16",
"CLK_TERM_R_GCLK27",
"CLK_TERM_R_GCLK11",
"CLK_TERM_GCLK6",
"CLK_TERM_R_GCLK10",
"CLK_TERM_GCLK20",
"CLK_TERM_GCLK23",
"CLK_TERM_GCLK16",
"CLK_TERM_R_GCLK25",
"CLK_TERM_GCLK11",
"CLK_TERM_GCLK27",
"CLK_TERM_GCLK31",
"CLK_TERM_R_GCLK29",
"CLK_TERM_GCLK4"
],
"sites": []
}

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artix7/tile_type_CMT_FIFO_L.json Normal file
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artix7/tile_type_CMT_FIFO_R.json Normal file
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artix7/tile_type_CMT_PMV.json Normal file
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{
"tile_type": "CMT_PMV",
"pips": {},
"wires": [
"CMT_PMV_IMUX37",
"CMT_PMV_IMUX42",
"CMT_PMV_WW4END1",
"CMT_PMV_WW4A1",
"CMT_PMV_FAN1",
"CMT_PMV_IMUX38",
"CMT_PMV_LOGIC_OUTS3",
"CMT_PMV_SW4A1",
"CMT_PMV_SE4C2",
"CMT_PMV_FAN6",
"CMT_PMV_WL1END2",
"CMT_PMV_EE4C3",
"CMT_PMV_SW2A0",
"CMT_PMV_LOGIC_OUTS4",
"CMT_PMV_MONITOR_N",
"CMT_PMV_NW4END1",
"CMT_PMV_NW2A0",
"CMT_PMV_EE4C1",
"CMT_PMV_LOGIC_OUTS11",
"CMT_PMV_EE2A1",
"CMT_PMV_IMUX46",
"CMT_PMV_LOGIC_OUTS7",
"CMT_PMV_WL1END0",
"CMT_PMV_IMUX6",
"CMT_PMV_NW4A3",
"CMT_PMV_WW4B3",
"CMT_PMV_SW2A2",
"CMT_PMV_IMUX47",
"CMT_PMV_SE2A2",
"CMT_PMV_NE4C2",
"CMT_PMV_NE4C1",
"CMT_PMV_EE4B3",
"CMT_PMV_WW2A1",
"CMT_PMV_NE4BEG0",
"CMT_PMV_SW2A3",
"CMT_PMV_EE2BEG3",
"CMT_PMV_IMUX15",
"CMT_PMV_FAN4",
"CMT_PMV_WW4C1",
"CMT_PMV_EE2BEG0",
"CMT_PMV_EE4C2",
"CMT_PMV_LOGIC_OUTS8",
"CMT_PMV_LOGIC_OUTS2",
"CMT_PMV_NW4A0",
"CMT_PMV_WW4B0",
"CMT_PMV_WW4B2",
"CMT_PMV_BYP4",
"CMT_PMV_IMUX20",
"CMT_PMV_IMUX7",
"CMT_PMV_WW4C2",
"CMT_PMV_NW4A1",
"CMT_PMV_LOGIC_OUTS16",
"CMT_PMV_WW4END2",
"CMT_PMV_IMUX25",
"CMT_PMV_SW4END3",
"CMT_PMV_LOGIC_OUTS23",
"CMT_PMV_WW4END0",
"CMT_PMV_IMUX39",
"CMT_PMV_IMUX9",
"CMT_PMV_SE2A0",
"CMT_PMV_LOGIC_OUTS22",
"CMT_PMV_BYP6",
"CMT_PMV_LH9",
"CMT_PMV_LOGIC_OUTS10",
"CMT_PMV_IMUX31",
"CMT_PMV_EE4B1",
"CMT_PMV_LOGIC_OUTS1",
"CMT_PMV_SW4A2",
"CMT_PMV_WL1END1",
"CMT_PMV_IMUX28",
"CMT_PMV_IMUX27",
"CMT_PMV_LOGIC_OUTS5",
"CMT_PMV_SE2A3",
"CMT_PMV_WR1END0",
"CMT_PMV_SW4END1",
"CMT_PMV_SW4END2",
"CMT_PMV_IMUX23",
"CMT_PMV_NW4END0",
"CMT_PMV_EE4A3",
"CMT_PMV_EE4A1",
"CMT_PMV_NW2A3",
"CMT_PMV_IMUX30",
"CMT_PMV_SE4BEG3",
"CMT_PMV_CTRL0",
"CMT_PMV_IMUX3",
"CMT_PMV_NW2A2",
"CMT_PMV_ER1BEG2",
"CMT_PMV_IMUX26",
"CMT_PMV_NE4BEG3",
"CMT_PMV_EE4A0",
"CMT_PMV_LH6",
"CMT_PMV_NE2A0",
"CMT_PMV_WW2END3",
"CMT_PMV_FAN7",
"CMT_PMV_LOGIC_OUTS13",
"CMT_PMV_IMUX10",
"CMT_PMV_SE4C1",
"CMT_PMV_NE4C3",
"CMT_PMV_LH1",
"CMT_PMV_EE4A2",
"CMT_PMV_FAN3",
"CMT_PMV_WW2END2",
"CMT_PMV_LOGIC_OUTS15",
"CMT_PMV_SW4END0",
"CMT_PMV_IMUX29",
"CMT_PMV_NE2A2",
"CMT_PMV_BYP5",
"CMT_PMV_MONITOR_P",
"CMT_PMV_SE2A1",
"CMT_PMV_EE4B2",
"CMT_PMV_LH8",
"CMT_PMV_NW4END3",
"CMT_PMV_NE2A1",
"CMT_PMV_SE4BEG2",
"CMT_PMV_IMUX8",
"CMT_PMV_IMUX24",
"CMT_PMV_IMUX18",
"CMT_PMV_WW2END1",
"CMT_PMV_WW2END0",
"CMT_PMV_SE4C0",
"L_TERM_INT_PHASER_TO_IO_OCLK",
"CMT_PMV_WW2A2",
"CMT_PMV_EL1BEG2",
"CMT_PMV_SE4BEG0",
"CMT_PMV_LOGIC_OUTS21",
"CMT_PMV_IMUX22",
"CMT_PMV_LOGIC_OUTS12",
"CMT_PMV_WW4B1",
"CMT_PMV_FAN0",
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
"CMT_PMV_WW2A3",
"L_TERM_INT_PHASER_TO_IO_ICLK",
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
"CMT_PMV_WW4C3",
"CMT_PMV_CLK0",
"CMT_PMV_WR1END2",
"CMT_PMV_LH10",
"CMT_PMV_EE2A0",
"CMT_PMV_IMUX32",
"CMT_PMV_EE4B0",
"CMT_PMV_IMUX12",
"CMT_PMV_IMUX19",
"CMT_PMV_SW4A3",
"CMT_PMV_LH3",
"CMT_PMV_BYP2",
"CMT_PMV_LH2",
"CMT_PMV_LH11",
"CMT_PMV_LOGIC_OUTS19",
"CMT_PMV_IMUX41",
"CMT_PMV_NE4BEG1",
"CMT_PMV_LOGIC_OUTS9",
"CMT_PMV_SW2A1",
"CMT_PMV_EE4C0",
"CMT_PMV_EE2BEG1",
"CMT_PMV_WW4A2",
"CMT_PMV_IMUX45",
"CMT_PMV_BYP0",
"CMT_PMV_WW4C0",
"CMT_PMV_EE4BEG1",
"CMT_PMV_NW4END2",
"CMT_PMV_SE4BEG1",
"CMT_PMV_EL1BEG0",
"CMT_PMV_IMUX13",
"CMT_PMV_NW4A2",
"CMT_PMV_EL1BEG1",
"CMT_PMV_LH7",
"CMT_PMV_NE2A3",
"CMT_PMV_EL1BEG3",
"CMT_PMV_EE2BEG2",
"CMT_PMV_IMUX21",
"CMT_PMV_CLK1",
"CMT_PMV_WL1END3",
"CMT_PMV_EE2A2",
"CMT_PMV_IMUX34",
"CMT_PMV_FAN2",
"CMT_PMV_IMUX14",
"CMT_PMV_LH12",
"CMT_PMV_IMUX4",
"CMT_PMV_LOGIC_OUTS0",
"CMT_PMV_LOGIC_OUTS17",
"CMT_PMV_LOGIC_OUTS6",
"CMT_PMV_BYP1",
"CMT_PMV_NE4BEG2",
"CMT_PMV_SW4A0",
"CMT_PMV_LOGIC_OUTS20",
"CMT_PMV_LH4",
"CMT_PMV_IMUX40",
"CMT_PMV_IMUX17",
"CMT_PMV_IMUX2",
"CMT_PMV_WW4END3",
"CMT_PMV_IMUX35",
"CMT_PMV_IMUX43",
"CMT_PMV_EE2A3",
"CMT_PMV_EE4BEG3",
"CMT_PMV_LOGIC_OUTS14",
"CMT_PMV_WW2A0",
"CMT_PMV_IMUX33",
"CMT_PMV_WW4A0",
"CMT_PMV_EE4BEG0",
"CMT_PMV_SE4C3",
"CMT_PMV_BYP3",
"CMT_PMV_EE4BEG2",
"CMT_PMV_BYP7",
"CMT_PMV_IMUX1",
"CMT_PMV_FAN5",
"CMT_PMV_LH5",
"CMT_PMV_NW2A1",
"CMT_PMV_IMUX16",
"CMT_PMV_NE4C0",
"CMT_PMV_IMUX11",
"CMT_PMV_ER1BEG3",
"CMT_PMV_LOGIC_OUTS18",
"CMT_PMV_WW4A3",
"CMT_PMV_IMUX36",
"CMT_PMV_IMUX0",
"CMT_PMV_ER1BEG0",
"CMT_PMV_IMUX5",
"CMT_PMV_ER1BEG1",
"CMT_PMV_WR1END3",
"CMT_PMV_IMUX44",
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
"CMT_PMV_CTRL1",
"CMT_PMV_WR1END1"
],
"sites": []
}

230
artix7/tile_type_CMT_PMV_L.json Normal file
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@ -0,0 +1,230 @@
{
"tile_type": "CMT_PMV_L",
"pips": {},
"wires": [
"CMT_PMV_IMUX37",
"CMT_PMV_IMUX42",
"CMT_PMV_WW4END1",
"CMT_PMV_WW4A1",
"CMT_PMV_FAN1",
"CMT_PMV_IMUX38",
"CMT_PMV_LOGIC_OUTS3",
"CMT_PMV_SW4A1",
"CMT_PMV_SE4C2",
"CMT_PMV_FAN6",
"CMT_PMV_WL1END2",
"CMT_PMV_EE4C3",
"CMT_PMV_SW2A0",
"CMT_PMV_LOGIC_OUTS4",
"CMT_PMV_MONITOR_N",
"CMT_PMV_NW4END1",
"CMT_PMV_NW2A0",
"CMT_PMV_EE4C1",
"CMT_PMV_LOGIC_OUTS11",
"CMT_PMV_EE2A1",
"CMT_PMV_IMUX46",
"CMT_PMV_LOGIC_OUTS7",
"CMT_PMV_WL1END0",
"CMT_PMV_IMUX6",
"CMT_PMV_NW4A3",
"CMT_PMV_WW4B3",
"CMT_PMV_SW2A2",
"CMT_PMV_IMUX47",
"CMT_PMV_SE2A2",
"CMT_PMV_NE4C2",
"CMT_PMV_NE4C1",
"CMT_PMV_EE4B3",
"CMT_PMV_WW2A1",
"CMT_PMV_NE4BEG0",
"CMT_PMV_SW2A3",
"CMT_PMV_EE2BEG3",
"CMT_PMV_IMUX15",
"CMT_PMV_FAN4",
"CMT_PMV_WW4C1",
"CMT_PMV_EE2BEG0",
"CMT_PMV_EE4C2",
"CMT_PMV_LOGIC_OUTS8",
"CMT_PMV_LOGIC_OUTS2",
"CMT_PMV_NW4A0",
"CMT_PMV_WW4B0",
"CMT_PMV_WW4B2",
"CMT_PMV_BYP4",
"CMT_PMV_IMUX20",
"CMT_PMV_IMUX7",
"CMT_PMV_WW4C2",
"CMT_PMV_NW4A1",
"CMT_PMV_LOGIC_OUTS16",
"CMT_PMV_WW4END2",
"CMT_PMV_IMUX25",
"CMT_PMV_SW4END3",
"CMT_PMV_LOGIC_OUTS23",
"CMT_PMV_WW4END0",
"CMT_PMV_IMUX39",
"CMT_PMV_IMUX9",
"CMT_PMV_SE2A0",
"CMT_PMV_LOGIC_OUTS22",
"CMT_PMV_BYP6",
"CMT_PMV_LH9",
"CMT_PMV_LOGIC_OUTS10",
"CMT_PMV_IMUX31",
"CMT_PMV_EE4B1",
"CMT_PMV_LOGIC_OUTS1",
"CMT_PMV_SW4A2",
"CMT_PMV_WL1END1",
"CMT_PMV_IMUX28",
"CMT_PMV_IMUX27",
"CMT_PMV_LOGIC_OUTS5",
"CMT_PMV_SE2A3",
"CMT_PMV_WR1END0",
"CMT_PMV_SW4END1",
"CMT_PMV_SW4END2",
"CMT_PMV_IMUX23",
"CMT_PMV_NW4END0",
"CMT_PMV_EE4A3",
"CMT_PMV_EE4A1",
"CMT_PMV_NW2A3",
"CMT_PMV_IMUX30",
"CMT_PMV_SE4BEG3",
"CMT_PMV_CTRL0",
"CMT_PMV_IMUX3",
"CMT_PMV_NW2A2",
"CMT_PMV_ER1BEG2",
"CMT_PMV_IMUX26",
"CMT_PMV_NE4BEG3",
"CMT_PMV_EE4A0",
"CMT_PMV_LH6",
"CMT_PMV_NE2A0",
"CMT_PMV_WW2END3",
"CMT_PMV_FAN7",
"CMT_PMV_LOGIC_OUTS13",
"CMT_PMV_IMUX10",
"CMT_PMV_SE4C1",
"CMT_PMV_NE4C3",
"CMT_PMV_LH1",
"CMT_PMV_EE4A2",
"CMT_PMV_FAN3",
"CMT_PMV_WW2END2",
"CMT_PMV_LOGIC_OUTS15",
"CMT_PMV_SW4END0",
"CMT_PMV_IMUX29",
"CMT_PMV_NE2A2",
"CMT_PMV_BYP5",
"CMT_PMV_MONITOR_P",
"CMT_PMV_SE2A1",
"CMT_PMV_EE4B2",
"CMT_PMV_LH8",
"CMT_PMV_NW4END3",
"CMT_PMV_NE2A1",
"CMT_PMV_SE4BEG2",
"CMT_PMV_IMUX8",
"CMT_PMV_IMUX24",
"CMT_PMV_IMUX18",
"CMT_PMV_WW2END1",
"CMT_PMV_WW2END0",
"CMT_PMV_SE4C0",
"L_TERM_INT_PHASER_TO_IO_OCLK",
"CMT_PMV_WW2A2",
"CMT_PMV_EL1BEG2",
"CMT_PMV_SE4BEG0",
"CMT_PMV_LOGIC_OUTS21",
"CMT_PMV_IMUX22",
"CMT_PMV_LOGIC_OUTS12",
"CMT_PMV_WW4B1",
"CMT_PMV_FAN0",
"L_TERM_INT_PHASER_TO_IO_ICLKDIV",
"CMT_PMV_WW2A3",
"L_TERM_INT_PHASER_TO_IO_ICLK",
"L_TERM_INT_PHASER_TO_IO_OCLK1X_90",
"CMT_PMV_WW4C3",
"CMT_PMV_CLK0",
"CMT_PMV_WR1END2",
"CMT_PMV_LH10",
"CMT_PMV_EE2A0",
"CMT_PMV_IMUX32",
"CMT_PMV_EE4B0",
"CMT_PMV_IMUX12",
"CMT_PMV_IMUX19",
"CMT_PMV_SW4A3",
"CMT_PMV_LH3",
"CMT_PMV_BYP2",
"CMT_PMV_LH2",
"CMT_PMV_LH11",
"CMT_PMV_LOGIC_OUTS19",
"CMT_PMV_IMUX41",
"CMT_PMV_NE4BEG1",
"CMT_PMV_LOGIC_OUTS9",
"CMT_PMV_SW2A1",
"CMT_PMV_EE4C0",
"CMT_PMV_EE2BEG1",
"CMT_PMV_WW4A2",
"CMT_PMV_IMUX45",
"CMT_PMV_BYP0",
"CMT_PMV_WW4C0",
"CMT_PMV_EE4BEG1",
"CMT_PMV_NW4END2",
"CMT_PMV_SE4BEG1",
"CMT_PMV_EL1BEG0",
"CMT_PMV_IMUX13",
"CMT_PMV_NW4A2",
"CMT_PMV_EL1BEG1",
"CMT_PMV_LH7",
"CMT_PMV_NE2A3",
"CMT_PMV_EL1BEG3",
"CMT_PMV_EE2BEG2",
"CMT_PMV_IMUX21",
"CMT_PMV_CLK1",
"CMT_PMV_WL1END3",
"CMT_PMV_EE2A2",
"CMT_PMV_IMUX34",
"CMT_PMV_FAN2",
"CMT_PMV_IMUX14",
"CMT_PMV_LH12",
"CMT_PMV_IMUX4",
"CMT_PMV_LOGIC_OUTS0",
"CMT_PMV_LOGIC_OUTS17",
"CMT_PMV_LOGIC_OUTS6",
"CMT_PMV_BYP1",
"CMT_PMV_NE4BEG2",
"CMT_PMV_SW4A0",
"CMT_PMV_LOGIC_OUTS20",
"CMT_PMV_LH4",
"CMT_PMV_IMUX40",
"CMT_PMV_IMUX17",
"CMT_PMV_IMUX2",
"CMT_PMV_WW4END3",
"CMT_PMV_IMUX35",
"CMT_PMV_IMUX43",
"CMT_PMV_EE2A3",
"CMT_PMV_EE4BEG3",
"CMT_PMV_LOGIC_OUTS14",
"CMT_PMV_WW2A0",
"CMT_PMV_IMUX33",
"CMT_PMV_WW4A0",
"CMT_PMV_EE4BEG0",
"CMT_PMV_SE4C3",
"CMT_PMV_BYP3",
"CMT_PMV_EE4BEG2",
"CMT_PMV_BYP7",
"CMT_PMV_IMUX1",
"CMT_PMV_FAN5",
"CMT_PMV_LH5",
"CMT_PMV_NW2A1",
"CMT_PMV_IMUX16",
"CMT_PMV_NE4C0",
"CMT_PMV_IMUX11",
"CMT_PMV_ER1BEG3",
"CMT_PMV_LOGIC_OUTS18",
"CMT_PMV_WW4A3",
"CMT_PMV_IMUX36",
"CMT_PMV_IMUX0",
"CMT_PMV_ER1BEG0",
"CMT_PMV_IMUX5",
"CMT_PMV_ER1BEG1",
"CMT_PMV_WR1END3",
"CMT_PMV_IMUX44",
"L_TERM_INT_PHASER_TO_IO_OCLKDIV",
"CMT_PMV_CTRL1",
"CMT_PMV_WR1END1"
],
"sites": []
}

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