luke
/
prjxray-db
mirror of https://github.com/openXC7/prjxray-db.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updating info based on "Merge pull request #659 from litghost/restore_iob_fuzzer". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-02-20 00:46:23 +00:00
parent d37cdf2a91
commit effb484aa9
56 changed files with 186301 additions and 40818 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
Info.md
View File

@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Mon Feb 18 10:17:51 UTC 2019 (2019-02-18T10:17:51+00:00).
Last updated on Wed Feb 20 00:46:22 UTC 2019 (2019-02-20T00:46:22+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [9e4c6f1](https://github.com/SymbiFlow/prjxray/commit/9e4c6f1bb55e9e68266396bae169f0c5d05bdc0d).
@ -366,32 +366,56 @@ source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
Results have checksums;
* [`d154b5fc62e0ae17091b880050a7302f4f75fed1008967eb88e2c1e3f13f4792 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv)
* [`2f2a37cca066562d79b6a7ecc89ff750c30db2cb355c0665379b356c7c8d41bd ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`2f2a37cca066562d79b6a7ecc89ff750c30db2cb355c0665379b356c7c8d41bd ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`48d52092f62239a82141b89539c690a405a54822ba04d0e284d9ffd300811d8c ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_l.block_ram.db`](./kintex7/mask_bram_l.block_ram.db)
* [`0a1777c5cbab388741934b51a2a2b57ffe450200df1d4d2f7051d2680b6c0a83 ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_r.block_ram.db`](./kintex7/mask_bram_r.block_ram.db)
* [`0a1777c5cbab388741934b51a2a2b57ffe450200df1d4d2f7051d2680b6c0a83 ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`ca5d5c0a53c60ea40f75fac03269a5d3722b6c56b8395002453bec5024557e54 ./kintex7/mask_clk_bufg_bot_r.db`](./kintex7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./kintex7/mask_clk_bufg_rebuf.db`](./kintex7/mask_clk_bufg_rebuf.db)
* [`ca5d5c0a53c60ea40f75fac03269a5d3722b6c56b8395002453bec5024557e54 ./kintex7/mask_clk_bufg_top_r.db`](./kintex7/mask_clk_bufg_top_r.db)
* [`35706a9a25d1213c7143628e41ca5bf3633f37925b20b2f00b1f94a80e879115 ./kintex7/mask_clk_hrow_bot_r.db`](./kintex7/mask_clk_hrow_bot_r.db)
* [`35706a9a25d1213c7143628e41ca5bf3633f37925b20b2f00b1f94a80e879115 ./kintex7/mask_clk_hrow_top_r.db`](./kintex7/mask_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./kintex7/ppips_bram_l.db`](./kintex7/ppips_bram_l.db)
* [`e58acdfa3cc740d2346dcb5d3a4c13434d459ebdc2ceb655dcb65fd631da4e4d ./kintex7/ppips_bram_r.db`](./kintex7/ppips_bram_r.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`292b55e44a2c49d9a7fc961ba37761ee8a29e50c790ef9da5e8c0d1c6c142b2f ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`60c352d2d6124ad3260ae0c3c151effa29aaad4c32fa2cee7787bfc43ca6aa89 ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_dsp_l.db`](./kintex7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_dsp_r.db`](./kintex7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`4b616026c8d3cb1e4e61e5e5e5abdfa381e66ac6583cacc5262c69273ff813f0 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`f61ce3972e8a3db9dd090a626c018c247788b5ba0946968b641d108de325a0a1 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`fb840f2f70f9203652d00f3b1dd5ea57e1b30d6ef49cb8c940b0f197b03ee5fe ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`83c126d6bf0a40f5438026a1c8572b7f408a91011d89750315c72cf8e337fc9e ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`78179d7f80769785b1d02c1b50994f6a801d3178a977205eb4376aeee680b160 ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`b253e0c8547109c27087f829b5652d647ea1969d8fc460518ebefa1d32a48ae9 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`5b0a0f277b5a915c9f9d5a27a2cc6c8cf90bca15e6c6aa2a8ed2147010fd4741 ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`d675f037111e500b21acb0b455d77f3b972de1f68643d69a842ea8ffb44db65a ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`cd6ce69c10e481f329308c6ec3d011ca2325a91a27c3567d53de19f7f4bc0229 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`6a620f430bcfc6b197da7dd9e9660ac06ef35744b752fe495277915b23198a73 ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./kintex7/segbits_clk_bufg_rebuf.db`](./kintex7/segbits_clk_bufg_rebuf.db)
* [`7618b3f1691081ec0d37e32c2533c8b6b637395d7a1779a708637ca547ee4c1b ./kintex7/segbits_clk_bufg_top_r.db`](./kintex7/segbits_clk_bufg_top_r.db)
* [`b90a415459e35584e0a5e59d54a882750d774fcd27921e69f929dcea939e8656 ./kintex7/segbits_clk_hrow_bot_r.db`](./kintex7/segbits_clk_hrow_bot_r.db)
* [`ed55b0098519109e38c9eaf9f47079925c3bcc0c721918efc254e358000b6d06 ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`23d2bec81339b3fcead640cba87c202edc0b5d9686a88abf586d41bdbf828569 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`a4290f6ff4b0dbc60ea7e276eb871b2f4450f2cc7d75adf8824802f1ff3c8d86 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
@ -446,8 +470,8 @@ Results have checksums;
* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`eb70fc5b8f16c680ceb6fb8797305c44a7f300cddcb9e679273984f8001e9420 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
* [`3594ba76355caa26c7ae1ffad782b03737a5fa257cb23945a4f3daf0dc5c4bb4 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
* [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
* [`3f080d03ca1d85aa81c2bae209cb401b8dcddd6e115ea8d16d735f2b4e6fc892 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
* [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json)
* [`fccd1abee620b9dc48534d82af9c84d7e4fb9f2fbeaa0d8bbef1ddab5d2d91c5 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json)
* [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json)
@ -484,19 +508,19 @@ Results have checksums;
* [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json)
* [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`3196f3226311d6da93de4941e326367c75d2433dcda15df9d1ca9a361f57b297 ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`3c645c7e32529af66b278c8c06734bb052d1be00ff801772d28147b1e62da2ff ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`5b45ef7b0d9a366440da629a02330f51b6210652842fe723369e88f31df5d732 ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json)
* [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json)
* [`c12d02118db07c8703fe07d9592cf8f1672389bd2bde3a82e67e41d961bbb171 ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`526212df7cbe1dbc56b70ac0dc0e93823cb238fcbf0c223dd82e88fac47e329f ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json)
* [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json)
* [`2911d44d3955c49dcad765b66aee65d1938224bb0a5cfe657b0061003cbaf154 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
* [`06802112ab5ed24674380cf08a8c3287dfb3a1d939664362f29892807a91b69a ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
* [`61667549d4262e9cbda59fe2eb9a87a61594b0bf722f3ba8f0f85a4ff077c7cd ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
* [`aa472cce57a7ddfd06831483ee4d0b09d30b644ad8d45e0a4cb8e82e7950472b ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
* [`cae21c2a995cd8c8e6b0001bbb5641d113007f7e4b5ce3b9b62b48fe07f8874d ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
* [`e62f84821d99fd43f58b9a144eb48e013519824dfce6e1bb056f0f0a7c0b969b ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
* [`4f86506406294db9f5fe6fae8f7ebf22e762f0e10a985b1bbf7c8b1c91b0dcc0 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
* [`4ddd2c3e96995a4acf4320877f3ab6ade22d9b475eb8b2e46cb64c325b92e386 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json)
* [`b7f2ec5fcaf13becd7a73baa9271370dd80ccc24a1dc52bbe4ec2a450aabd7ad ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json)
* [`664e29cdabfbec863560328a0833a91459c17dc70ea679128d602c805825ccd7 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json)
* [`073c39fafe9d8dacb4e002d50832d5978ca20f4503434fdee83c7132cd338128 ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json)
* [`11692719d238fce3ad91ba0ba92a0d4216b24eb6da2f17e988f3145b08c11ddf ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json)
* [`06f886342ce6151e496b553027ec5930c28f972f6cfa4edf669ef46cb7958843 ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json)
* [`124ad9e96a57e9f949a9525366f0f2c497ef20f14e0848b465aa3215556c7825 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json)
* [`b015248899232a2c9213742d7f44c597b75bb58e5f4edf03ef71119e003958d4 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json)
* [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json)
* [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json)
@ -510,8 +534,8 @@ Results have checksums;
* [`7897a72ad8df7a9561af0cd339d07b78fda2d8978771ca314edb158eb6bf21d5 ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json)
* [`a614c05f6190160ffe2178fe0a8bf52b351b429a2468217236b29e0c44344eaf ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
* [`e57958223bc67dcba0e52050d88164b60b2f25c689a6eed89718935b0c4c4557 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
* [`ac2bda946bf493ddaa51c21c4cec8295317ce822692f8276725a4bc36618c0f1 ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
* [`5e15b63a15fd7864d838d448599718e5f82e8caafa8fd316eb19374e20c0d89c ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
* [`4270980b733f54a17a34b5259579fd2e42d38efeeb42518967362c599def37c2 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json)
@ -535,7 +559,7 @@ Results have checksums;
* [`b69c2ea84f06bfed085b2f50e1f4dd43033dd5f34ca19e67da42d6c80317cd23 ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
* [`44cf5e287a63932e7b6809f4fc3245ff380ae8ad24ed9b53b8cee45b719517b6 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
* [`5c6ddebe6aef58fa126d2f1121f2c415737d513b90169c393dfcbe2655251716 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
* [`492e354568a279eb9b4d45a38a8e99a7971d02dad9d7db9979a115ee775f7b57 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
* [`0ba8ee53d9143f34acda567dc07fe65317ced21eac6b84223de2620630c285fa ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
* [`ecd8853d71cb85a9234f41c12f81e22a91dc2623947c07c9ad5d6a07a1d4e9b7 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
* [`687681f194bdd1c2642f07d0ef1e95fa1f4de557bc4ea3d098b8224e982eda69 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
* [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
@ -558,7 +582,7 @@ Results have checksums;
* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`b870a0225ffe1b5b9729fbfea3925ad3c24ea7b9fa7ebc8665368f00a2743781 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`fc7d6eb90cb54117f3a92e52394ddb8525cc0b4f3098efa9d1f92a384fea44f1 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)

36864
kintex7/mask_bram_l.block_ram.db Normal file
View File

File diff suppressed because it is too large Load Diff

2377
kintex7/mask_bram_l.db Normal file
View File

File diff suppressed because it is too large Load Diff

36864
kintex7/mask_bram_r.block_ram.db Normal file
View File

File diff suppressed because it is too large Load Diff

2377
kintex7/mask_bram_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

37
kintex7/mask_clbll_l.db
View File

@ -11,17 +11,24 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -38,11 +45,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -55,15 +71,22 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -83,11 +106,19 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1878,6 +1909,7 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1922,8 +1954,6 @@ bit 31_12
bit 31_13
bit 31_14
bit 31_15
bit 31_16
bit 31_17
bit 31_18
bit 31_19
bit 31_20
@ -1937,6 +1967,7 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35
@ -1950,8 +1981,6 @@ bit 31_42
bit 31_43
bit 31_44
bit 31_45
bit 31_46
bit 31_47
bit 31_48
bit 31_49
bit 31_50

38
kintex7/mask_clbll_r.db
View File

@ -11,17 +11,24 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -38,11 +45,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -55,15 +71,22 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -79,15 +102,24 @@ bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1877,6 +1909,7 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1921,8 +1954,6 @@ bit 31_12
bit 31_13
bit 31_14
bit 31_15
bit 31_16
bit 31_17
bit 31_18
bit 31_19
bit 31_20
@ -1936,6 +1967,7 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35
@ -1949,8 +1981,6 @@ bit 31_42
bit 31_43
bit 31_44
bit 31_45
bit 31_46
bit 31_47
bit 31_48
bit 31_49
bit 31_50

39
kintex7/mask_clblm_l.db
View File

@ -11,17 +11,24 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -30,6 +37,7 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -38,11 +46,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -55,15 +72,23 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -83,11 +108,19 @@ bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1865,6 +1898,8 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1878,6 +1913,7 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1891,6 +1927,8 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1937,6 +1975,7 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

40
kintex7/mask_clblm_r.db
View File

@ -11,17 +11,24 @@ bit 00_09
bit 00_10
bit 00_11
bit 00_12
bit 00_13
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
bit 00_33
bit 00_34
@ -30,6 +37,7 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -38,11 +46,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -55,15 +72,23 @@ bit 01_08
bit 01_09
bit 01_10
bit 01_11
bit 01_12
bit 01_13
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_18
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
bit 01_32
@ -79,15 +104,24 @@ bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1864,6 +1898,8 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1877,6 +1913,7 @@ bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
@ -1890,6 +1927,8 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1936,6 +1975,7 @@ bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35

1381
kintex7/mask_clk_bufg_bot_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

128
kintex7/mask_clk_bufg_rebuf.db Normal file
View File

@ -0,0 +1,128 @@
bit 26_00
bit 26_01
bit 26_02
bit 26_03
bit 26_12
bit 26_13
bit 26_14
bit 26_15
bit 26_16
bit 26_17
bit 26_18
bit 26_19
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_32
bit 26_33
bit 26_34
bit 26_35
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_48
bit 26_49
bit 26_50
bit 26_51
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_64
bit 26_65
bit 26_66
bit 26_67
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_80
bit 26_81
bit 26_82
bit 26_83
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_96
bit 26_97
bit 26_98
bit 26_99
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_112
bit 26_113
bit 26_114
bit 26_115
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 27_00
bit 27_01
bit 27_02
bit 27_03
bit 27_12
bit 27_13
bit 27_14
bit 27_15
bit 27_16
bit 27_17
bit 27_18
bit 27_19
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_32
bit 27_33
bit 27_34
bit 27_35
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_48
bit 27_49
bit 27_50
bit 27_51
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_64
bit 27_65
bit 27_66
bit 27_67
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_80
bit 27_81
bit 27_82
bit 27_83
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_96
bit 27_97
bit 27_98
bit 27_99
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_114
bit 27_115
bit 27_124
bit 27_125
bit 27_126
bit 27_127

1381
kintex7/mask_clk_bufg_top_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

568
kintex7/mask_clk_hrow_bot_r.db Normal file
View File

@ -0,0 +1,568 @@
bit 00_49
bit 00_57
bit 00_58
bit 00_59
bit 00_145
bit 00_150
bit 00_153
bit 00_154
bit 00_155
bit 01_45
bit 01_53
bit 01_56
bit 01_57
bit 01_58
bit 01_141
bit 01_149
bit 01_152
bit 01_153
bit 11_143
bit 13_143
bit 21_72
bit 21_168
bit 25_72
bit 25_168
bit 26_03
bit 26_08
bit 26_09
bit 26_10
bit 26_11
bit 26_12
bit 26_13
bit 26_14
bit 26_15
bit 26_19
bit 26_24
bit 26_25
bit 26_26
bit 26_27
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_35
bit 26_40
bit 26_41
bit 26_42
bit 26_43
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_51
bit 26_56
bit 26_57
bit 26_58
bit 26_59
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_67
bit 26_72
bit 26_73
bit 26_74
bit 26_75
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_80
bit 26_81
bit 26_83
bit 26_88
bit 26_89
bit 26_90
bit 26_91
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_114
bit 26_115
bit 26_116
bit 26_117
bit 26_118
bit 26_119
bit 26_120
bit 26_121
bit 26_122
bit 26_123
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_131
bit 26_136
bit 26_137
bit 26_138
bit 26_139
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_147
bit 26_152
bit 26_153
bit 26_154
bit 26_155
bit 26_156
bit 26_157
bit 26_158
bit 26_159
bit 26_163
bit 26_168
bit 26_169
bit 26_170
bit 26_171
bit 26_172
bit 26_173
bit 26_174
bit 26_175
bit 26_179
bit 26_184
bit 26_185
bit 26_186
bit 26_187
bit 26_188
bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_200
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_206
bit 26_207
bit 26_211
bit 26_216
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_223
bit 27_03
bit 27_06
bit 27_07
bit 27_08
bit 27_09
bit 27_10
bit 27_11
bit 27_12
bit 27_13
bit 27_14
bit 27_15
bit 27_19
bit 27_22
bit 27_23
bit 27_24
bit 27_25
bit 27_26
bit 27_27
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_35
bit 27_38
bit 27_39
bit 27_40
bit 27_41
bit 27_42
bit 27_43
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_51
bit 27_54
bit 27_55
bit 27_56
bit 27_57
bit 27_58
bit 27_59
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_67
bit 27_70
bit 27_71
bit 27_72
bit 27_73
bit 27_74
bit 27_75
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_80
bit 27_81
bit 27_83
bit 27_86
bit 27_87
bit 27_88
bit 27_89
bit 27_90
bit 27_91
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_114
bit 27_115
bit 27_116
bit 27_117
bit 27_118
bit 27_119
bit 27_120
bit 27_121
bit 27_122
bit 27_123
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_131
bit 27_134
bit 27_135
bit 27_136
bit 27_137
bit 27_138
bit 27_139
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_147
bit 27_150
bit 27_151
bit 27_152
bit 27_153
bit 27_154
bit 27_155
bit 27_156
bit 27_157
bit 27_158
bit 27_159
bit 27_163
bit 27_166
bit 27_167
bit 27_168
bit 27_169
bit 27_170
bit 27_171
bit 27_172
bit 27_173
bit 27_174
bit 27_175
bit 27_179
bit 27_182
bit 27_183
bit 27_184
bit 27_185
bit 27_186
bit 27_187
bit 27_188
bit 27_189
bit 27_190
bit 27_191
bit 27_195
bit 27_198
bit 27_199
bit 27_200
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_211
bit 27_214
bit 27_215
bit 27_216
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 28_03
bit 28_08
bit 28_09
bit 28_10
bit 28_11
bit 28_12
bit 28_13
bit 28_14
bit 28_15
bit 28_19
bit 28_24
bit 28_25
bit 28_26
bit 28_27
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_35
bit 28_40
bit 28_41
bit 28_42
bit 28_43
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_51
bit 28_56
bit 28_57
bit 28_58
bit 28_59
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_67
bit 28_72
bit 28_73
bit 28_74
bit 28_75
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_80
bit 28_81
bit 28_83
bit 28_88
bit 28_89
bit 28_90
bit 28_91
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 28_114
bit 28_115
bit 28_116
bit 28_117
bit 28_118
bit 28_119
bit 28_120
bit 28_121
bit 28_122
bit 28_123
bit 28_124
bit 28_125
bit 28_126
bit 28_127
bit 28_131
bit 28_136
bit 28_137
bit 28_138
bit 28_139
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_147
bit 28_152
bit 28_153
bit 28_154
bit 28_155
bit 28_156
bit 28_157
bit 28_158
bit 28_159
bit 28_163
bit 28_168
bit 28_169
bit 28_170
bit 28_171
bit 28_172
bit 28_173
bit 28_174
bit 28_175
bit 28_179
bit 28_184
bit 28_185
bit 28_186
bit 28_187
bit 28_188
bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_200
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_206
bit 28_207
bit 28_211
bit 28_216
bit 28_217
bit 28_218
bit 28_219
bit 28_220
bit 28_221
bit 28_222
bit 28_223
bit 29_03
bit 29_06
bit 29_07
bit 29_08
bit 29_09
bit 29_10
bit 29_11
bit 29_12
bit 29_13
bit 29_14
bit 29_15
bit 29_19
bit 29_22
bit 29_23
bit 29_24
bit 29_25
bit 29_26
bit 29_27
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_35
bit 29_38
bit 29_39
bit 29_40
bit 29_41
bit 29_42
bit 29_43
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_51
bit 29_54
bit 29_55
bit 29_56
bit 29_57
bit 29_58
bit 29_59
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_67
bit 29_70
bit 29_71
bit 29_72
bit 29_73
bit 29_74
bit 29_75
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_80
bit 29_81
bit 29_83
bit 29_86
bit 29_87
bit 29_88
bit 29_89
bit 29_90
bit 29_91
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 29_114
bit 29_115
bit 29_116
bit 29_117
bit 29_118
bit 29_119
bit 29_120
bit 29_121
bit 29_122
bit 29_123
bit 29_124
bit 29_125
bit 29_126
bit 29_127
bit 29_131
bit 29_134
bit 29_135
bit 29_136
bit 29_137
bit 29_138
bit 29_139
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_147
bit 29_150
bit 29_151
bit 29_152
bit 29_153
bit 29_154
bit 29_155
bit 29_156
bit 29_157
bit 29_158
bit 29_159
bit 29_163
bit 29_166
bit 29_167
bit 29_168
bit 29_169
bit 29_170
bit 29_171
bit 29_172
bit 29_173
bit 29_174
bit 29_175
bit 29_179
bit 29_182
bit 29_183
bit 29_184
bit 29_185
bit 29_186
bit 29_187
bit 29_188
bit 29_189
bit 29_190
bit 29_191
bit 29_195
bit 29_198
bit 29_199
bit 29_200
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_211
bit 29_214
bit 29_215
bit 29_216
bit 29_217
bit 29_218
bit 29_219
bit 29_220
bit 29_221
bit 29_222
bit 29_223

568
kintex7/mask_clk_hrow_top_r.db Normal file
View File

@ -0,0 +1,568 @@
bit 00_49
bit 00_57
bit 00_58
bit 00_59
bit 00_145
bit 00_150
bit 00_153
bit 00_154
bit 00_155
bit 01_45
bit 01_53
bit 01_56
bit 01_57
bit 01_58
bit 01_141
bit 01_149
bit 01_152
bit 01_153
bit 11_143
bit 13_143
bit 21_72
bit 21_168
bit 25_72
bit 25_168
bit 26_03
bit 26_08
bit 26_09
bit 26_10
bit 26_11
bit 26_12
bit 26_13
bit 26_14
bit 26_15
bit 26_19
bit 26_24
bit 26_25
bit 26_26
bit 26_27
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_35
bit 26_40
bit 26_41
bit 26_42
bit 26_43
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_51
bit 26_56
bit 26_57
bit 26_58
bit 26_59
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_67
bit 26_72
bit 26_73
bit 26_74
bit 26_75
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_80
bit 26_81
bit 26_83
bit 26_88
bit 26_89
bit 26_90
bit 26_91
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_114
bit 26_115
bit 26_116
bit 26_117
bit 26_118
bit 26_119
bit 26_120
bit 26_121
bit 26_122
bit 26_123
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_131
bit 26_136
bit 26_137
bit 26_138
bit 26_139
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_147
bit 26_152
bit 26_153
bit 26_154
bit 26_155
bit 26_156
bit 26_157
bit 26_158
bit 26_159
bit 26_163
bit 26_168
bit 26_169
bit 26_170
bit 26_171
bit 26_172
bit 26_173
bit 26_174
bit 26_175
bit 26_179
bit 26_184
bit 26_185
bit 26_186
bit 26_187
bit 26_188
bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_200
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_206
bit 26_207
bit 26_211
bit 26_216
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_223
bit 27_03
bit 27_06
bit 27_07
bit 27_08
bit 27_09
bit 27_10
bit 27_11
bit 27_12
bit 27_13
bit 27_14
bit 27_15
bit 27_19
bit 27_22
bit 27_23
bit 27_24
bit 27_25
bit 27_26
bit 27_27
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_35
bit 27_38
bit 27_39
bit 27_40
bit 27_41
bit 27_42
bit 27_43
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_51
bit 27_54
bit 27_55
bit 27_56
bit 27_57
bit 27_58
bit 27_59
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_67
bit 27_70
bit 27_71
bit 27_72
bit 27_73
bit 27_74
bit 27_75
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_80
bit 27_81
bit 27_83
bit 27_86
bit 27_87
bit 27_88
bit 27_89
bit 27_90
bit 27_91
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_114
bit 27_115
bit 27_116
bit 27_117
bit 27_118
bit 27_119
bit 27_120
bit 27_121
bit 27_122
bit 27_123
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_131
bit 27_134
bit 27_135
bit 27_136
bit 27_137
bit 27_138
bit 27_139
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_147
bit 27_150
bit 27_151
bit 27_152
bit 27_153
bit 27_154
bit 27_155
bit 27_156
bit 27_157
bit 27_158
bit 27_159
bit 27_163
bit 27_166
bit 27_167
bit 27_168
bit 27_169
bit 27_170
bit 27_171
bit 27_172
bit 27_173
bit 27_174
bit 27_175
bit 27_179
bit 27_182
bit 27_183
bit 27_184
bit 27_185
bit 27_186
bit 27_187
bit 27_188
bit 27_189
bit 27_190
bit 27_191
bit 27_195
bit 27_198
bit 27_199
bit 27_200
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_211
bit 27_214
bit 27_215
bit 27_216
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 28_03
bit 28_08
bit 28_09
bit 28_10
bit 28_11
bit 28_12
bit 28_13
bit 28_14
bit 28_15
bit 28_19
bit 28_24
bit 28_25
bit 28_26
bit 28_27
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_35
bit 28_40
bit 28_41
bit 28_42
bit 28_43
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_51
bit 28_56
bit 28_57
bit 28_58
bit 28_59
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_67
bit 28_72
bit 28_73
bit 28_74
bit 28_75
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_80
bit 28_81
bit 28_83
bit 28_88
bit 28_89
bit 28_90
bit 28_91
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 28_114
bit 28_115
bit 28_116
bit 28_117
bit 28_118
bit 28_119
bit 28_120
bit 28_121
bit 28_122
bit 28_123
bit 28_124
bit 28_125
bit 28_126
bit 28_127
bit 28_131
bit 28_136
bit 28_137
bit 28_138
bit 28_139
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_147
bit 28_152
bit 28_153
bit 28_154
bit 28_155
bit 28_156
bit 28_157
bit 28_158
bit 28_159
bit 28_163
bit 28_168
bit 28_169
bit 28_170
bit 28_171
bit 28_172
bit 28_173
bit 28_174
bit 28_175
bit 28_179
bit 28_184
bit 28_185
bit 28_186
bit 28_187
bit 28_188
bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_200
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_206
bit 28_207
bit 28_211
bit 28_216
bit 28_217
bit 28_218
bit 28_219
bit 28_220
bit 28_221
bit 28_222
bit 28_223
bit 29_03
bit 29_06
bit 29_07
bit 29_08
bit 29_09
bit 29_10
bit 29_11
bit 29_12
bit 29_13
bit 29_14
bit 29_15
bit 29_19
bit 29_22
bit 29_23
bit 29_24
bit 29_25
bit 29_26
bit 29_27
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_35
bit 29_38
bit 29_39
bit 29_40
bit 29_41
bit 29_42
bit 29_43
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_51
bit 29_54
bit 29_55
bit 29_56
bit 29_57
bit 29_58
bit 29_59
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_67
bit 29_70
bit 29_71
bit 29_72
bit 29_73
bit 29_74
bit 29_75
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_80
bit 29_81
bit 29_83
bit 29_86
bit 29_87
bit 29_88
bit 29_89
bit 29_90
bit 29_91
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 29_114
bit 29_115
bit 29_116
bit 29_117
bit 29_118
bit 29_119
bit 29_120
bit 29_121
bit 29_122
bit 29_123
bit 29_124
bit 29_125
bit 29_126
bit 29_127
bit 29_131
bit 29_134
bit 29_135
bit 29_136
bit 29_137
bit 29_138
bit 29_139
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_147
bit 29_150
bit 29_151
bit 29_152
bit 29_153
bit 29_154
bit 29_155
bit 29_156
bit 29_157
bit 29_158
bit 29_159
bit 29_163
bit 29_166
bit 29_167
bit 29_168
bit 29_169
bit 29_170
bit 29_171
bit 29_172
bit 29_173
bit 29_174
bit 29_175
bit 29_179
bit 29_182
bit 29_183
bit 29_184
bit 29_185
bit 29_186
bit 29_187
bit 29_188
bit 29_189
bit 29_190
bit 29_191
bit 29_195
bit 29_198
bit 29_199
bit 29_200
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_211
bit 29_214
bit 29_215
bit 29_216
bit 29_217
bit 29_218
bit 29_219
bit 29_220
bit 29_221
bit 29_222
bit 29_223

0
kintex7/mask_dsp_l.db Normal file
View File

0
kintex7/mask_dsp_r.db Normal file
View File

24
kintex7/ppips_bram_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
kintex7/ppips_bram_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

794
kintex7/ppips_bram_l.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_L.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_L.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_L.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_L.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_L.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_L.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_L.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_L.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_L.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_L.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_L.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_L.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_L.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_L.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_L.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_L.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_L.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_L.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_L.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_L.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_L.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_L.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_L.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_L.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_L.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_L.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_L.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_L.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_L.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_L.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_L.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_L.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_L.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_L.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_L.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_L.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_L.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_L.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_L.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_L.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_L.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_L.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_L.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_L.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_L.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_L.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_L.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_L.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_L.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_L.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_L.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_L.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_L.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_L.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_L.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_L.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_L.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_L.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_L.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_L.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_L.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_L.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_L.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_L.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_L.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_L.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_L.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_L.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_L.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_L.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_L.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_L.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_L.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_L.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_L.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_L.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_L.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_L.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_L.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_L.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_L.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_L.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_L.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_L.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_L.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_L.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_L.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_L.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_L.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_L.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_L.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_L.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_L.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_L.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_L.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_L.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_L.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_L.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_L.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_L.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_L.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_L.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_L.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_L.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_L.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_L.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_L.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_L.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_L.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_L.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_L.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_L.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_L.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_L.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_L.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_L.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_L.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_L.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_L.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_L.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_L.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_L.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_L.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_L.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_L.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_L.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_L.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_L.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_L.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_L.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_L.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_L.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_L.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_L.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_L.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_L.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_L.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_L.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_L.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_L.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_L.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_L.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_L.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_L.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_L.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_L.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_L.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_L.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_L.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_L.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_L.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_L.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_L.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_L.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_L.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

794
kintex7/ppips_bram_r.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_R.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_R.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_R.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_R.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_R.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_R.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_R.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_R.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_R.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_R.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_R.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_R.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_R.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_R.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_R.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_R.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_R.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_R.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_R.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_R.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_R.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_R.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_R.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_R.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_R.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_R.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_R.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_R.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_R.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_R.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_R.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_R.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_R.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_R.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_R.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_R.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_R.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_R.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_R.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_R.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_R.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_R.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_R.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_R.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_R.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_R.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_R.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_R.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_R.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_R.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_R.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_R.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_R.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_R.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_R.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_R.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_R.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_R.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_R.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_R.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_R.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_R.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_R.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_R.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_R.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_R.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_R.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_R.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_R.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_R.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_R.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_R.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_R.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_R.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_R.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_R.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_R.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_R.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_R.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_R.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_R.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_R.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_R.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_R.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_R.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_R.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_R.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_R.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_R.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_R.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_R.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_R.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_R.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_R.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_R.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_R.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_R.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_R.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_R.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_R.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_R.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_R.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_R.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_R.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_R.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_R.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_R.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_R.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_R.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_R.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_R.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_R.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_R.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_R.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_R.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_R.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_R.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_R.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_R.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_R.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_R.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_R.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_R.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_R.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_R.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_R.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_R.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_R.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_R.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_R.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_R.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_R.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_R.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_R.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_R.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_R.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_R.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_R.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_R.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_R.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_R.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_R.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_R.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_R.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_R.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_R.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_R.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_R.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_R.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_R.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_R.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_R.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_R.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_R.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_R.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

0
kintex7/ppips_dsp_l.db Normal file
View File

0
kintex7/ppips_dsp_r.db Normal file
View File

8
kintex7/ppips_hclk_l.db
View File

@ -1,8 +0,0 @@
HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always

8
kintex7/ppips_hclk_r.db
View File

@ -1,8 +0,0 @@
HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always

64
kintex7/ppips_int_l.db
View File

@ -1,3 +1,11 @@
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
@ -14,6 +22,14 @@ INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
@ -42,3 +58,51 @@ INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default

64
kintex7/ppips_int_r.db
View File

@ -1,3 +1,11 @@
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
@ -6,6 +14,14 @@ INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
@ -42,3 +58,51 @@ INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default

246
kintex7/segbits_bram_l.db
View File

@ -1,3 +1,215 @@
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 26_64 !26_65 26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 26_64 26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2 !26_64 !26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 26_192 !26_193 26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 26_192 26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3 !26_192 !26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 26_96 !26_97 26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 26_96 26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4 !26_96 !26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 26_224 !26_225 26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 26_224 26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5 !26_224 !26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 26_160 !26_161 26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 26_160 26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6 !26_160 !26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 26_176 !26_177 26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 26_176 26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7 !26_176 !26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 26_80 !26_81 26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 26_80 26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 26_69 !26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 !26_69 26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 !26_69 !26_70 !26_71
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 26_197 !26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 !26_197 26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 !26_197 !26_198 !26_199
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 26_101 !26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 !26_101 26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 !26_101 !26_102 !26_103
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 26_229 !26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 !26_229 26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 !26_229 !26_230 !26_231
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 26_165 !26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 !26_165 26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6 !26_165 !26_166 !26_167
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 26_181 !26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 !26_181 26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 !26_181 !26_182 !26_183
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 26_85 !26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 !26_85 26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_72 !26_73 26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 26_72 26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_IMUX_ADDRBWRADDRL2 !26_72 !26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_200 !26_201 26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 26_200 26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_IMUX_ADDRBWRADDRL3 !26_200 !26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_104 !26_105 26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 26_104 26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_IMUX_ADDRBWRADDRL4 !26_104 !26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_232 !26_233 26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 26_232 26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_IMUX_ADDRBWRADDRL5 !26_232 !26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_168 !26_169 26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 26_168 26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_IMUX_ADDRBWRADDRL6 !26_168 !26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_184 !26_185 26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 26_184 26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 !26_184 !26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_88 !26_89 26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 26_88 26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_77 !26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 !26_77 26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 !26_77 !26_78 !26_79
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_205 !26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 !26_205 26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 !26_205 !26_206 !26_207
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_109 !26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 !26_109 26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 !26_109 !26_110 !26_111
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_237 !26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 !26_237 26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 !26_237 !26_238 !26_239
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_173 !26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 !26_173 26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 !26_173 !26_174 !26_175
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_189 !26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 !26_189 26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 !26_189 !26_190 !26_191
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_93 !26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 !26_93 26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.EN_SYN 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_L.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_L.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_L.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_L.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 27_150
BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
@ -34,14 +246,22 @@ BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
@ -82,10 +302,12 @@ BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
@ -94,10 +316,16 @@ BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_L.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_L.RAMB18_Y0.ZINV_REGCLKARDRCLK 27_104
BRAM_L.RAMB18_Y0.ZINV_REGCLKB 27_108
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
@ -134,14 +362,22 @@ BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
@ -182,10 +418,12 @@ BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
@ -194,7 +432,15 @@ BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_L.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_L.RAMB18_Y1.ZINV_REGCLKARDRCLK 27_216
BRAM_L.RAMB18_Y1.ZINV_REGCLKB 27_212
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187

246
kintex7/segbits_bram_r.db
View File

@ -1,3 +1,215 @@
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 26_64 !26_65 26_67
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 26_64 26_65 !26_67
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_R_IMUX_ADDRARDADDRL2 !26_64 !26_65 !26_67
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 26_192 !26_193 26_195
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 26_192 26_193 !26_195
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_R_IMUX_ADDRARDADDRL3 !26_192 !26_193 !26_195
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 26_96 !26_97 26_99
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 26_96 26_97 !26_99
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_R_IMUX_ADDRARDADDRL4 !26_96 !26_97 !26_99
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 26_224 !26_225 26_227
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 26_224 26_225 !26_227
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_R_IMUX_ADDRARDADDRL5 !26_224 !26_225 !26_227
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 26_160 !26_161 26_163
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 26_160 26_161 !26_163
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_R_IMUX_ADDRARDADDRL6 !26_160 !26_161 !26_163
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 26_176 !26_177 26_179
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 26_176 26_177 !26_179
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_R_IMUX_ADDRARDADDRL7 !26_176 !26_177 !26_179
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 26_80 !26_81 26_83
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 26_80 26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_R_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 26_69 !26_70 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 !26_69 26_70 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_R_IMUX_ADDRARDADDRU2 !26_69 !26_70 !26_71
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 26_197 !26_198 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 !26_197 26_198 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_R_IMUX_ADDRARDADDRU3 !26_197 !26_198 !26_199
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 26_101 !26_102 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 !26_101 26_102 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_R_IMUX_ADDRARDADDRU4 !26_101 !26_102 !26_103
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 26_229 !26_230 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 !26_229 26_230 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_R_IMUX_ADDRARDADDRU5 !26_229 !26_230 !26_231
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 26_165 !26_166 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 !26_165 26_166 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_R_IMUX_ADDRARDADDRU6 !26_165 !26_166 !26_167
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 26_181 !26_182 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 !26_181 26_182 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_R_IMUX_ADDRARDADDRU7 !26_181 !26_182 !26_183
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 26_85 !26_86 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 !26_85 26_86 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_R_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_R_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_R_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_72 !26_73 26_75
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 26_72 26_73 !26_75
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_R_IMUX_ADDRBWRADDRL2 !26_72 !26_73 !26_75
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_200 !26_201 26_203
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 26_200 26_201 !26_203
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_R_IMUX_ADDRBWRADDRL3 !26_200 !26_201 !26_203
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_104 !26_105 26_107
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 26_104 26_105 !26_107
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_R_IMUX_ADDRBWRADDRL4 !26_104 !26_105 !26_107
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_232 !26_233 26_235
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 26_232 26_233 !26_235
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_R_IMUX_ADDRBWRADDRL5 !26_232 !26_233 !26_235
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_168 !26_169 26_171
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 26_168 26_169 !26_171
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_R_IMUX_ADDRBWRADDRL6 !26_168 !26_169 !26_171
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_184 !26_185 26_187
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 26_184 26_185 !26_187
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_R_IMUX_ADDRBWRADDRL7 !26_184 !26_185 !26_187
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_88 !26_89 26_91
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 26_88 26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_77 !26_78 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 !26_77 26_78 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_R_IMUX_ADDRBWRADDRU2 !26_77 !26_78 !26_79
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_205 !26_206 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 !26_205 26_206 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_R_IMUX_ADDRBWRADDRU3 !26_205 !26_206 !26_207
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_109 !26_110 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 !26_109 26_110 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_R_IMUX_ADDRBWRADDRU4 !26_109 !26_110 !26_111
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_237 !26_238 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 !26_237 26_238 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_R_IMUX_ADDRBWRADDRU5 !26_237 !26_238 !26_239
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_173 !26_174 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 !26_173 26_174 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_R_IMUX_ADDRBWRADDRU6 !26_173 !26_174 !26_175
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_189 !26_190 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 !26_189 26_190 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_R_IMUX_ADDRBWRADDRU7 !26_189 !26_190 !26_191
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_93 !26_94 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 !26_93 26_94 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.EN_SYN 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_R.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_R.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_R.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_R.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 27_150
BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
@ -34,14 +246,22 @@ BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
@ -82,10 +302,12 @@ BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
@ -94,10 +316,16 @@ BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_R.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_R.RAMB18_Y0.ZINV_REGCLKARDRCLK 27_104
BRAM_R.RAMB18_Y0.ZINV_REGCLKB 27_108
BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
@ -134,14 +362,22 @@ BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
@ -182,10 +418,12 @@ BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
@ -194,7 +432,15 @@ BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_R.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_R.RAMB18_Y1.ZINV_REGCLKARDRCLK 27_216
BRAM_R.RAMB18_Y1.ZINV_REGCLKB 27_212
BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187

77
kintex7/segbits_clbll_l.db
View File

@ -4,12 +4,6 @@ CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -74,9 +68,6 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.ALUT.RAM 31_16
CLBLL_L.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_L.SLICEL_X0.ALUT.SRL 30_16
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
@ -89,12 +80,6 @@ CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -159,9 +144,6 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BLUT.RAM 31_17
CLBLL_L.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_L.SLICEL_X0.BLUT.SRL 30_17
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
@ -175,12 +157,6 @@ CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -246,9 +222,6 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.CLUT.RAM 31_46
CLBLL_L.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_L.SLICEL_X0.CLUT.SRL 30_46
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
@ -258,14 +231,9 @@ CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -330,9 +298,6 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DLUT.RAM 31_47
CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
@ -340,14 +305,12 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.WA7USED 00_40
CLBLL_L.SLICEL_X0.WA8USED 01_27
CLBLL_L.SLICEL_X0.WEMUX.CE 01_23
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
@ -357,12 +320,6 @@ CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -439,12 +396,6 @@ CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -522,12 +473,6 @@ CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -602,14 +547,9 @@ CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -681,11 +621,12 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

31
kintex7/segbits_clbll_r.db
View File

@ -74,9 +74,6 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.ALUT.RAM 31_16
CLBLL_R.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_R.SLICEL_X0.ALUT.SRL 30_16
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
@ -159,9 +156,6 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BLUT.RAM 31_17
CLBLL_R.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_R.SLICEL_X0.BLUT.SRL 30_17
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
@ -246,9 +240,6 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.CLUT.RAM 31_46
CLBLL_R.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_R.SLICEL_X0.CLUT.SRL 30_46
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
@ -258,7 +249,7 @@ CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
@ -330,9 +321,6 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DLUT.RAM 31_47
CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
@ -340,14 +328,12 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.WA7USED 00_40
CLBLL_R.SLICEL_X0.WA8USED 01_27
CLBLL_R.SLICEL_X0.WEMUX.CE 01_23
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
@ -602,7 +588,7 @@ CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
@ -681,11 +667,12 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

16
kintex7/segbits_clblm_l.db
View File

@ -249,7 +249,7 @@ CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
@ -328,12 +328,13 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
@ -599,7 +600,7 @@ CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
@ -681,14 +682,15 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49

16
kintex7/segbits_clblm_r.db
View File

@ -249,7 +249,7 @@ CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 25_63 31_54
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
@ -328,12 +328,13 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08 31_27 31_29 31_30
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
@ -599,7 +600,7 @@ CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 21_55 25_55 30_54
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
@ -681,14 +682,15 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_01 30_12 30_15 31_03
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49

160
kintex7/segbits_clk_bufg_bot_r.db Normal file
View File

@ -0,0 +1,160 @@
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT 27_13
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED 26_01
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED 27_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 26_12
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 27_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 27_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 27_03
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 26_11
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 26_02
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT 27_173
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED 26_161
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED 27_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 26_172
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 27_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 27_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 27_163
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 26_171
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 26_162
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT 27_189
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED 26_177
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED 27_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 26_188
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 27_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 27_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 27_179
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 26_187
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 26_178
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT 27_205
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED 26_193
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED 27_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 26_204
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 27_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 27_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 27_195
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 26_203
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 26_194
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT 27_221
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED 26_209
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED 27_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 26_220
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 27_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 27_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 27_211
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 26_219
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 26_210
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT 27_237
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED 26_225
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED 27_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 26_236
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 27_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 27_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 27_227
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 26_235
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 26_226
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 07_118 26_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 27_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 26_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 26_242

128
kintex7/segbits_clk_bufg_rebuf.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT.CLK_BUFG_REBUF_R_CK_GCLK0_TOP 27_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT 27_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP 27_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT 27_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP 27_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT 27_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP 27_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT 27_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP 27_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT 27_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP 27_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT 27_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP 27_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT 27_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP 27_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT 27_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP 26_15
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT 26_13
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP 26_31
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT 26_29
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT.CLK_BUFG_REBUF_R_CK_GCLK10_TOP 26_47
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_TOP.CLK_BUFG_REBUF_R_CK_GCLK10_BOT 26_45
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT.CLK_BUFG_REBUF_R_CK_GCLK11_TOP 26_63
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP.CLK_BUFG_REBUF_R_CK_GCLK11_BOT 26_61
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT.CLK_BUFG_REBUF_R_CK_GCLK12_TOP 26_79
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_TOP.CLK_BUFG_REBUF_R_CK_GCLK12_BOT 26_77
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT.CLK_BUFG_REBUF_R_CK_GCLK13_TOP 26_95
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP.CLK_BUFG_REBUF_R_CK_GCLK13_BOT 26_93
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT.CLK_BUFG_REBUF_R_CK_GCLK14_TOP 26_111
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_TOP.CLK_BUFG_REBUF_R_CK_GCLK14_BOT 26_109
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT.CLK_BUFG_REBUF_R_CK_GCLK15_TOP 26_127
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP.CLK_BUFG_REBUF_R_CK_GCLK15_BOT 26_125
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT.CLK_BUFG_REBUF_R_CK_GCLK16_TOP 27_14
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT 27_12
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT.CLK_BUFG_REBUF_R_CK_GCLK17_TOP 27_30
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP.CLK_BUFG_REBUF_R_CK_GCLK17_BOT 27_28
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT.CLK_BUFG_REBUF_R_CK_GCLK18_TOP 27_46
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_TOP.CLK_BUFG_REBUF_R_CK_GCLK18_BOT 27_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT.CLK_BUFG_REBUF_R_CK_GCLK19_TOP 27_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP.CLK_BUFG_REBUF_R_CK_GCLK19_BOT 27_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT.CLK_BUFG_REBUF_R_CK_GCLK20_TOP 27_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_TOP.CLK_BUFG_REBUF_R_CK_GCLK20_BOT 27_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT.CLK_BUFG_REBUF_R_CK_GCLK21_TOP 27_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP.CLK_BUFG_REBUF_R_CK_GCLK21_BOT 27_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT.CLK_BUFG_REBUF_R_CK_GCLK22_TOP 27_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_TOP.CLK_BUFG_REBUF_R_CK_GCLK22_BOT 27_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT.CLK_BUFG_REBUF_R_CK_GCLK23_TOP 27_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP.CLK_BUFG_REBUF_R_CK_GCLK23_BOT 27_124
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT.CLK_BUFG_REBUF_R_CK_GCLK24_TOP 26_14
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_TOP.CLK_BUFG_REBUF_R_CK_GCLK24_BOT 26_12
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT.CLK_BUFG_REBUF_R_CK_GCLK25_TOP 26_30
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP.CLK_BUFG_REBUF_R_CK_GCLK25_BOT 26_28
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT.CLK_BUFG_REBUF_R_CK_GCLK26_TOP 26_46
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_TOP.CLK_BUFG_REBUF_R_CK_GCLK26_BOT 26_44
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT.CLK_BUFG_REBUF_R_CK_GCLK27_TOP 26_62
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP.CLK_BUFG_REBUF_R_CK_GCLK27_BOT 26_60
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT.CLK_BUFG_REBUF_R_CK_GCLK28_TOP 26_78
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_TOP.CLK_BUFG_REBUF_R_CK_GCLK28_BOT 26_76
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT.CLK_BUFG_REBUF_R_CK_GCLK29_TOP 26_94
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP.CLK_BUFG_REBUF_R_CK_GCLK29_BOT 26_92
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT.CLK_BUFG_REBUF_R_CK_GCLK30_TOP 26_110
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_TOP.CLK_BUFG_REBUF_R_CK_GCLK30_BOT 26_108
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT.CLK_BUFG_REBUF_R_CK_GCLK31_TOP 26_126
CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP.CLK_BUFG_REBUF_R_CK_GCLK31_BOT 26_124
CLK_BUFG_REBUF.GCLK0_ENABLE_ABOVE 27_03
CLK_BUFG_REBUF.GCLK0_ENABLE_BELOW 27_01
CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE 27_19
CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW 27_17
CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE 27_35
CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW 27_33
CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE 27_51
CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW 27_49
CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE 27_67
CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW 27_65
CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE 27_83
CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW 27_81
CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE 27_99
CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW 27_97
CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE 27_115
CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW 27_113
CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE 26_03
CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW 26_01
CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE 26_19
CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW 26_17
CLK_BUFG_REBUF.GCLK10_ENABLE_ABOVE 26_35
CLK_BUFG_REBUF.GCLK10_ENABLE_BELOW 26_33
CLK_BUFG_REBUF.GCLK11_ENABLE_ABOVE 26_51
CLK_BUFG_REBUF.GCLK11_ENABLE_BELOW 26_49
CLK_BUFG_REBUF.GCLK12_ENABLE_ABOVE 26_67
CLK_BUFG_REBUF.GCLK12_ENABLE_BELOW 26_65
CLK_BUFG_REBUF.GCLK13_ENABLE_ABOVE 26_83
CLK_BUFG_REBUF.GCLK13_ENABLE_BELOW 26_81
CLK_BUFG_REBUF.GCLK14_ENABLE_ABOVE 26_99
CLK_BUFG_REBUF.GCLK14_ENABLE_BELOW 26_97
CLK_BUFG_REBUF.GCLK15_ENABLE_ABOVE 26_115
CLK_BUFG_REBUF.GCLK15_ENABLE_BELOW 26_113
CLK_BUFG_REBUF.GCLK16_ENABLE_ABOVE 27_02
CLK_BUFG_REBUF.GCLK16_ENABLE_BELOW 27_00
CLK_BUFG_REBUF.GCLK17_ENABLE_ABOVE 27_18
CLK_BUFG_REBUF.GCLK17_ENABLE_BELOW 27_16
CLK_BUFG_REBUF.GCLK18_ENABLE_ABOVE 27_34
CLK_BUFG_REBUF.GCLK18_ENABLE_BELOW 27_32
CLK_BUFG_REBUF.GCLK19_ENABLE_ABOVE 27_50
CLK_BUFG_REBUF.GCLK19_ENABLE_BELOW 27_48
CLK_BUFG_REBUF.GCLK20_ENABLE_ABOVE 27_66
CLK_BUFG_REBUF.GCLK20_ENABLE_BELOW 27_64
CLK_BUFG_REBUF.GCLK21_ENABLE_ABOVE 27_82
CLK_BUFG_REBUF.GCLK21_ENABLE_BELOW 27_80
CLK_BUFG_REBUF.GCLK22_ENABLE_ABOVE 27_98
CLK_BUFG_REBUF.GCLK22_ENABLE_BELOW 27_96
CLK_BUFG_REBUF.GCLK23_ENABLE_ABOVE 27_114
CLK_BUFG_REBUF.GCLK23_ENABLE_BELOW 27_112
CLK_BUFG_REBUF.GCLK24_ENABLE_ABOVE 26_02
CLK_BUFG_REBUF.GCLK24_ENABLE_BELOW 26_00
CLK_BUFG_REBUF.GCLK25_ENABLE_ABOVE 26_18
CLK_BUFG_REBUF.GCLK25_ENABLE_BELOW 26_16
CLK_BUFG_REBUF.GCLK26_ENABLE_ABOVE 26_34
CLK_BUFG_REBUF.GCLK26_ENABLE_BELOW 26_32
CLK_BUFG_REBUF.GCLK27_ENABLE_ABOVE 26_50
CLK_BUFG_REBUF.GCLK27_ENABLE_BELOW 26_48
CLK_BUFG_REBUF.GCLK28_ENABLE_ABOVE 26_66
CLK_BUFG_REBUF.GCLK28_ENABLE_BELOW 26_64
CLK_BUFG_REBUF.GCLK29_ENABLE_ABOVE 26_82
CLK_BUFG_REBUF.GCLK29_ENABLE_BELOW 26_80
CLK_BUFG_REBUF.GCLK30_ENABLE_ABOVE 26_98
CLK_BUFG_REBUF.GCLK30_ENABLE_BELOW 26_96
CLK_BUFG_REBUF.GCLK31_ENABLE_ABOVE 26_114
CLK_BUFG_REBUF.GCLK31_ENABLE_BELOW 26_112

160
kintex7/segbits_clk_bufg_top_r.db Normal file
View File

@ -0,0 +1,160 @@
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE 27_00 27_15
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT 27_13
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED 26_01
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED 27_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 26_12
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 27_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 27_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 27_03
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 26_11
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 26_02
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE 27_16 27_31
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT 27_29
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED 26_17
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED 27_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 26_28
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 27_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 27_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 27_19
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 26_27
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 26_18
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE 27_32 27_47
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT 27_45
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED 26_33
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED 27_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 26_44
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 27_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 27_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 27_35
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 26_43
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 26_34
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE 27_48 27_63
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT 27_61
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED 26_49
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED 27_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 26_60
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 27_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 27_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 27_51
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 26_59
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 26_50
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE 27_64 27_79
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT 27_77
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED 26_65
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED 27_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 26_76
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 27_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 27_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 27_67
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 26_75
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 26_66
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE 27_80 27_95
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT 27_93
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED 26_81
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED 27_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 26_92
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 27_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 27_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 27_83
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 26_91
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 26_82
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE 27_96 27_111
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT 27_109
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED 26_97
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED 27_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 26_108
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 27_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 27_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 27_99
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 26_107
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 26_98
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE 27_112 27_127
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT 27_125
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED 26_113
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED 27_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 26_124
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 27_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 27_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 27_115
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 26_123
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 26_114
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE 27_128 27_143
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT 27_141
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED 26_129
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED 27_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 26_140
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 27_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 27_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 27_131
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 26_139
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 26_130
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE 27_144 27_159
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT 27_157
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED 26_145
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED 27_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 26_156
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 27_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 27_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 27_147
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 26_155
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 26_146
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE 27_160 27_175
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT 27_173
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED 26_161
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED 27_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 26_172
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 27_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 27_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 27_163
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 26_171
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 26_162
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE 27_176 27_191
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT 27_189
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED 26_177
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED 27_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 26_188
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 27_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 27_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 27_179
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 26_187
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 26_178
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE 27_192 27_207
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT 27_205
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED 26_193
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED 27_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 26_204
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 27_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 27_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 27_195
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 26_203
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 26_194
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE 27_208 27_223
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT 27_221
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED 26_209
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED 27_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 26_220
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 27_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 27_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 27_211
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 26_219
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 26_210
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE 27_224 27_239
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT 27_237
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED 26_225
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED 27_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 26_236
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 27_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 27_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 27_227
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 26_235
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 26_226
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 07_118 26_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 27_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 26_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 26_242

1644
kintex7/segbits_clk_hrow_bot_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

1644
kintex7/segbits_clk_hrow_top_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

0
kintex7/segbits_dsp_l.db Normal file
View File

0
kintex7/segbits_dsp_r.db Normal file
View File

10
kintex7/segbits_int_l.db
View File

@ -6,7 +6,6 @@ INT_L.BYP_ALT0.LOGIC_OUTS_L0 20_07 !22_07 23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L12 20_07 22_07 !23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L22 20_07 !22_07 !23_07 !24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 18_06 !22_07 23_07 24_07 25_07
INT_L.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WW2END_N0_3 17_07 !22_07 !23_07 24_07 !25_07
INT_L.BYP_ALT0.EE2END0 18_06 !22_07 !23_07 24_07 !25_07
INT_L.BYP_ALT0.EL1END0 16_07 22_07 !23_07 24_07 25_07
@ -31,7 +30,6 @@ INT_L.BYP_ALT1.LOGIC_OUTS_L4 20_15 !22_15 23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L8 20_15 22_15 !23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L18 20_15 !22_15 !23_15 !24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 18_14 !22_15 23_15 24_15 25_15
INT_L.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.EE2END0 17_15 !22_15 !23_15 24_15 !25_15
INT_L.BYP_ALT1.EL1END1 17_15 22_15 !23_15 24_15 25_15
INT_L.BYP_ALT1.ER1END0 16_15 !22_15 23_15 24_15 25_15
@ -331,7 +329,7 @@ INT_L.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
INT_L.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
INT_L.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
INT_L.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_L.FAN_ALT1.GFAN1 21_48 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
INT_L.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
INT_L.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
@ -380,7 +378,7 @@ INT_L.FAN_ALT3.NW2END_S0_0 19_57 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.EE2END3 16_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.EL1END3 16_56 !22_56 23_56 24_56 25_56
INT_L.FAN_ALT3.ER1END3 17_56 22_56 !23_56 24_56 25_56
INT_L.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
INT_L.FAN_ALT3.GFAN1 21_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.NE2END3 17_56 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.NN2END3 17_56 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT3.NR1END3 18_57 22_56 !23_56 24_56 25_56
@ -392,7 +390,7 @@ INT_L.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
INT_L.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
INT_L.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
INT_L.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 !22_08 !23_08 !24_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
@ -427,7 +425,7 @@ INT_L.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
INT_L.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
INT_L.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
INT_L.FAN_ALT5.GFAN1 21_40 25_40
INT_L.FAN_ALT5.GFAN1 21_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
INT_L.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
INT_L.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40

12
kintex7/segbits_int_r.db
View File

@ -6,7 +6,6 @@ INT_R.BYP_ALT0.LOGIC_OUTS0 20_07 !22_07 23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS12 20_07 22_07 !23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS22 20_07 !22_07 !23_07 !24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 18_06 !22_07 23_07 24_07 25_07
INT_R.BYP_ALT0.VCC_WIRE 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WW2END_N0_3 17_07 !22_07 !23_07 24_07 !25_07
INT_R.BYP_ALT0.EE2END0 18_06 !22_07 !23_07 24_07 !25_07
INT_R.BYP_ALT0.EL1END0 16_07 22_07 !23_07 24_07 25_07
@ -31,7 +30,6 @@ INT_R.BYP_ALT1.LOGIC_OUTS4 20_15 !22_15 23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS8 20_15 22_15 !23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS18 20_15 !22_15 !23_15 !24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 18_14 !22_15 23_15 24_15 25_15
INT_R.BYP_ALT1.VCC_WIRE 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.EE2END0 17_15 !22_15 !23_15 24_15 !25_15
INT_R.BYP_ALT1.EL1END1 17_15 22_15 !23_15 24_15 25_15
INT_R.BYP_ALT1.ER1END0 16_15 !22_15 23_15 24_15 25_15
@ -267,7 +265,7 @@ INT_R.FAN_ALT1.NL1BEG_N3 19_49 !22_48 23_48 24_48 25_48
INT_R.FAN_ALT1.EE2END3 19_49 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.EL1END3 17_48 !22_48 23_48 24_48 25_48
INT_R.FAN_ALT1.ER1END2 16_48 22_48 !23_48 24_48 25_48
INT_R.FAN_ALT1.GFAN1 00_14 00_17 21_48 25_48
INT_R.FAN_ALT1.GFAN1 21_48 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.NE2END3 18_49 !22_48 !23_48 24_48 !25_48
INT_R.FAN_ALT1.NN2END3 18_49 !22_48 !23_48 !24_48 25_48
INT_R.FAN_ALT1.NR1END3 18_49 22_48 !23_48 24_48 25_48
@ -316,7 +314,7 @@ INT_R.FAN_ALT3.NW2END_S0_0 19_57 !22_56 !23_56 24_56 !25_56
INT_R.FAN_ALT3.EE2END3 16_56 !22_56 !23_56 !24_56 25_56
INT_R.FAN_ALT3.EL1END3 16_56 !22_56 23_56 24_56 25_56
INT_R.FAN_ALT3.ER1END3 17_56 22_56 !23_56 24_56 25_56
INT_R.FAN_ALT3.GFAN1 00_14 00_17 21_56 25_56
INT_R.FAN_ALT3.GFAN1 21_56 !22_56 !23_56 !24_56 25_56
INT_R.FAN_ALT3.NE2END3 17_56 !22_56 !23_56 24_56 !25_56
INT_R.FAN_ALT3.NN2END3 17_56 !22_56 !23_56 !24_56 25_56
INT_R.FAN_ALT3.NR1END3 18_57 22_56 !23_56 24_56 25_56
@ -328,7 +326,7 @@ INT_R.FAN_ALT3.SW2END3 18_57 !22_56 !23_56 24_56 !25_56
INT_R.FAN_ALT3.WL1END3 17_56 !22_56 23_56 24_56 25_56
INT_R.FAN_ALT3.WR1END3 16_56 22_56 !23_56 24_56 25_56
INT_R.FAN_ALT3.WW2END3 19_57 !22_56 !23_56 !24_56 25_56
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 20_08 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 20_08 !22_08 !23_08 24_08 !25_08
INT_R.FAN_ALT4.FAN_BOUNCE2 20_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 20_08 !22_08 23_08 24_08 25_08
@ -352,7 +350,7 @@ INT_R.FAN_ALT4.SW2END0 18_09 !22_08 !23_08 24_08 !25_08
INT_R.FAN_ALT4.WL1END0 17_08 !22_08 23_08 24_08 25_08
INT_R.FAN_ALT4.WR1END0 16_08 22_08 !23_08 24_08 25_08
INT_R.FAN_ALT4.WW2END0 19_09 !22_08 !23_08 !24_08 25_08
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 24_40
INT_R.FAN_ALT5.BYP_BOUNCE1 20_40 !22_40 !23_40 24_40 !25_40
INT_R.FAN_ALT5.BYP_BOUNCE5 20_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 20_40 22_40 !23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 20_40 !22_40 23_40 24_40 25_40
@ -363,7 +361,7 @@ INT_R.FAN_ALT5.NL1BEG_N3 19_41 !22_40 23_40 24_40 25_40
INT_R.FAN_ALT5.EE2END2 16_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.EL1END2 16_40 !22_40 23_40 24_40 25_40
INT_R.FAN_ALT5.ER1END2 17_40 22_40 !23_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 00_14 00_17 21_40 25_40
INT_R.FAN_ALT5.GFAN1 21_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.NE2END2 17_40 !22_40 !23_40 24_40 !25_40
INT_R.FAN_ALT5.NN2END2 17_40 !22_40 !23_40 !24_40 25_40
INT_R.FAN_ALT5.NR1END2 18_41 22_40 !23_40 24_40 25_40

8
kintex7/tile_type_BRAM_L.json
View File

@ -7186,7 +7186,7 @@
"y_coord": 0
},
{
"name": "X0Y39",
"name": "X0Y0",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
@ -7350,10 +7350,10 @@
},
"type": "FIFO18E1",
"x_coord": 0,
"y_coord": 39
"y_coord": 0
},
{
"name": "X0Y40",
"name": "X0Y1",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
@ -7517,7 +7517,7 @@
},
"type": "RAMB18E1",
"x_coord": 0,
"y_coord": 40
"y_coord": 1
}
],
"tile_type": "BRAM_L",

8
kintex7/tile_type_BRAM_R.json
View File

@ -6821,7 +6821,7 @@
},
"sites": [
{
"name": "X0Y39",
"name": "X0Y0",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0",
@ -6985,10 +6985,10 @@
},
"type": "FIFO18E1",
"x_coord": 0,
"y_coord": 39
"y_coord": 0
},
{
"name": "X0Y40",
"name": "X0Y1",
"prefix": "RAMB18",
"site_pins": {
"ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0",
@ -7152,7 +7152,7 @@
},
"type": "RAMB18E1",
"x_coord": 0,
"y_coord": 40
"y_coord": 1
},
{
"name": "X0Y0",

16
kintex7/tile_type_CMT_TOP_L_UPPER_B.json
View File

@ -2856,7 +2856,7 @@
"y_coord": 0
},
{
"name": "X0Y5",
"name": "X0Y0",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING",
@ -2939,10 +2939,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 0
},
{
"name": "X0Y5",
"name": "X0Y0",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING",
@ -3040,10 +3040,10 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 5
"y_coord": 0
},
{
"name": "X0Y6",
"name": "X0Y1",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING",
@ -3126,10 +3126,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 1
},
{
"name": "X0Y6",
"name": "X0Y1",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING",
@ -3227,7 +3227,7 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 6
"y_coord": 1
}
],
"tile_type": "CMT_TOP_L_UPPER_B",

16
kintex7/tile_type_CMT_TOP_R_UPPER_B.json
View File

@ -2856,7 +2856,7 @@
"y_coord": 0
},
{
"name": "X0Y11",
"name": "X0Y0",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING",
@ -2939,10 +2939,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 11
"y_coord": 0
},
{
"name": "X0Y11",
"name": "X0Y0",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING",
@ -3040,10 +3040,10 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 11
"y_coord": 0
},
{
"name": "X0Y12",
"name": "X0Y1",
"prefix": "PHASER_OUT_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING",
@ -3126,10 +3126,10 @@
},
"type": "PHASER_OUT_PHY",
"x_coord": 0,
"y_coord": 12
"y_coord": 1
},
{
"name": "X0Y12",
"name": "X0Y1",
"prefix": "PHASER_IN_PHY",
"site_pins": {
"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING",
@ -3227,7 +3227,7 @@
},
"type": "PHASER_IN_PHY",
"x_coord": 0,
"y_coord": 12
"y_coord": 1
}
],
"tile_type": "CMT_TOP_R_UPPER_B",

6
kintex7/tile_type_DSP_L.json
View File

@ -6413,15 +6413,15 @@
"y_coord": 1
},
{
"name": "X14Y117",
"name": "X0Y0",
"prefix": "TIEOFF",
"site_pins": {
"HARD0": "DSP_GND_L",
"HARD1": "DSP_VCC_L"
},
"type": "TIEOFF",
"x_coord": 14,
"y_coord": 117
"x_coord": 0,
"y_coord": 0
}
],
"tile_type": "DSP_L",

6
kintex7/tile_type_DSP_R.json
View File

@ -6413,15 +6413,15 @@
"y_coord": 1
},
{
"name": "X10Y117",
"name": "X0Y0",
"prefix": "TIEOFF",
"site_pins": {
"HARD0": "DSP_GND_R",
"HARD1": "DSP_VCC_R"
},
"type": "TIEOFF",
"x_coord": 10,
"y_coord": 117
"x_coord": 0,
"y_coord": 0
}
],
"tile_type": "DSP_R",

16
kintex7/tile_type_GTX_CHANNEL_0.json
View File

@ -5092,44 +5092,44 @@
"y_coord": 0
},
{
"name": "X0Y26",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXN_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 26
"y_coord": 0
},
{
"name": "X0Y27",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXP_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 27
"y_coord": 1
},
{
"name": "X0Y4",
"name": "X0Y0",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXN_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 4
"y_coord": 0
},
{
"name": "X0Y5",
"name": "X0Y1",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXP_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 5
"y_coord": 1
}
],
"tile_type": "GTX_CHANNEL_0",

16
kintex7/tile_type_GTX_CHANNEL_1.json
View File

@ -5092,44 +5092,44 @@
"y_coord": 0
},
{
"name": "X0Y31",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXN_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 31
"y_coord": 0
},
{
"name": "X0Y32",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXP_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 32
"y_coord": 1
},
{
"name": "X0Y5",
"name": "X0Y0",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXN_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 5
"y_coord": 0
},
{
"name": "X0Y6",
"name": "X0Y1",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXP_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 6
"y_coord": 1
}
],
"tile_type": "GTX_CHANNEL_1",

16
kintex7/tile_type_GTX_CHANNEL_2.json
View File

@ -5092,44 +5092,44 @@
"y_coord": 0
},
{
"name": "X0Y42",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXN_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 42
"y_coord": 0
},
{
"name": "X0Y43",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXP_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 43
"y_coord": 1
},
{
"name": "X0Y6",
"name": "X0Y0",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXN_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 6
"y_coord": 0
},
{
"name": "X0Y7",
"name": "X0Y1",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXP_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 7
"y_coord": 1
}
],
"tile_type": "GTX_CHANNEL_2",

16
kintex7/tile_type_GTX_CHANNEL_3.json
View File

@ -5092,44 +5092,44 @@
"y_coord": 0
},
{
"name": "X0Y47",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXN_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 47
"y_coord": 0
},
{
"name": "X0Y48",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "GTXE2_CHANNEL_RXP_PAD"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 48
"y_coord": 1
},
{
"name": "X0Y7",
"name": "X0Y0",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXN_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 7
"y_coord": 0
},
{
"name": "X0Y8",
"name": "X0Y1",
"prefix": "OPAD",
"site_pins": {
"I": "GTXE2_CHANNEL_TXP_PAD"
},
"type": "OPAD",
"x_coord": 0,
"y_coord": 8
"y_coord": 1
}
],
"tile_type": "GTX_CHANNEL_3",

24
kintex7/tile_type_GTX_COMMON.json
View File

@ -1071,47 +1071,47 @@
"y_coord": 0
},
{
"name": "X0Y38",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "IBUFDS_GTE2_0_IB"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 38
"y_coord": 1
},
{
"name": "X0Y37",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "IBUFDS_GTE2_0_I"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 37
"y_coord": 0
},
{
"name": "X0Y40",
"name": "X0Y3",
"prefix": "IPAD",
"site_pins": {
"O": "IBUFDS_GTE2_1_IB"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 40
"y_coord": 3
},
{
"name": "X0Y39",
"name": "X0Y2",
"prefix": "IPAD",
"site_pins": {
"O": "IBUFDS_GTE2_1_I"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 39
"y_coord": 2
},
{
"name": "X0Y1",
"name": "X0Y0",
"prefix": "IBUFDS_GTE2",
"site_pins": {
"CEB": "IBUFDS_GTE2_0_CEB",
@ -1123,10 +1123,10 @@
},
"type": "IBUFDS_GTE2",
"x_coord": 0,
"y_coord": 1
"y_coord": 0
},
{
"name": "X0Y2",
"name": "X0Y1",
"prefix": "IBUFDS_GTE2",
"site_pins": {
"CEB": "IBUFDS_GTE2_1_CEB",
@ -1138,7 +1138,7 @@
},
"type": "IBUFDS_GTE2",
"x_coord": 0,
"y_coord": 2
"y_coord": 1
}
],
"tile_type": "GTX_COMMON",

32
kintex7/tile_type_HCLK_IOI.json
View File

@ -1711,7 +1711,7 @@
},
"sites": [
{
"name": "X0Y4",
"name": "X0Y1",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK3",
@ -1719,10 +1719,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 4
"y_coord": 1
},
{
"name": "X0Y3",
"name": "X0Y0",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK2",
@ -1730,10 +1730,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 3
"y_coord": 0
},
{
"name": "X0Y6",
"name": "X0Y3",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK1",
@ -1741,10 +1741,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 6
"y_coord": 3
},
{
"name": "X0Y5",
"name": "X0Y2",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK0",
@ -1752,10 +1752,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 5
"y_coord": 2
},
{
"name": "X0Y4",
"name": "X0Y1",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR3_CE",
@ -1765,10 +1765,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 4
"y_coord": 1
},
{
"name": "X0Y3",
"name": "X0Y0",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR2_CE",
@ -1778,10 +1778,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 3
"y_coord": 0
},
{
"name": "X0Y6",
"name": "X0Y3",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR1_CE",
@ -1791,10 +1791,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 6
"y_coord": 3
},
{
"name": "X0Y5",
"name": "X0Y2",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR0_CE",
@ -1804,7 +1804,7 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 5
"y_coord": 2
},
{
"name": "X0Y0",

32
kintex7/tile_type_HCLK_IOI3.json
View File

@ -1711,7 +1711,7 @@
},
"sites": [
{
"name": "X0Y10",
"name": "X0Y1",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK3",
@ -1719,10 +1719,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 10
"y_coord": 1
},
{
"name": "X0Y9",
"name": "X0Y0",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK2",
@ -1730,10 +1730,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 9
"y_coord": 0
},
{
"name": "X0Y12",
"name": "X0Y3",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK1",
@ -1741,10 +1741,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 12
"y_coord": 3
},
{
"name": "X0Y11",
"name": "X0Y2",
"prefix": "BUFIO",
"site_pins": {
"I": "HCLK_IOI_IO_PLL_CLK0",
@ -1752,10 +1752,10 @@
},
"type": "BUFIO",
"x_coord": 0,
"y_coord": 11
"y_coord": 2
},
{
"name": "X0Y10",
"name": "X0Y1",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR3_CE",
@ -1765,10 +1765,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 10
"y_coord": 1
},
{
"name": "X0Y9",
"name": "X0Y0",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR2_CE",
@ -1778,10 +1778,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 9
"y_coord": 0
},
{
"name": "X0Y12",
"name": "X0Y3",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR1_CE",
@ -1791,10 +1791,10 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 12
"y_coord": 3
},
{
"name": "X0Y11",
"name": "X0Y2",
"prefix": "BUFR",
"site_pins": {
"CE": "HCLK_IOI_BUFR0_CE",
@ -1804,7 +1804,7 @@
},
"type": "BUFR",
"x_coord": 0,
"y_coord": 11
"y_coord": 2
},
{
"name": "X0Y0",

8
kintex7/tile_type_MONITOR_BOT_FUJI2.json
View File

@ -738,24 +738,24 @@
},
"sites": [
{
"name": "X0Y67",
"name": "X0Y1",
"prefix": "IPAD",
"site_pins": {
"O": "MONITOR_SEG_VN"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 67
"y_coord": 1
},
{
"name": "X0Y66",
"name": "X0Y0",
"prefix": "IPAD",
"site_pins": {
"O": "MONITOR_SEG_VP"
},
"type": "IPAD",
"x_coord": 0,
"y_coord": 66
"y_coord": 0
},
{
"name": "X0Y0",

137979
kintex7/tilegrid.json
View File

File diff suppressed because it is too large Load Diff