Updating all based on "Merge pull request #1558 from antmicro/add-gtp-channel-conf"

See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
2021-01-25 12:16:13 -08:00 · 2021-01-25 12:16:13 -08:00 · e7663ba6eb
parent 6f476da67d
commit e7663ba6eb
58 changed files with 86323 additions and 89 deletions
--- a/Info.md
+++ b/Info.md
@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).

 # Details

-Last updated on Mon 25 Jan 2021 08:13:26 PM UTC (2021-01-25T20:13:26+00:00).
+Last updated on Mon 25 Jan 2021 08:15:39 PM UTC (2021-01-25T20:15:39+00:00).

-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [30890e0e](https://github.com/SymbiFlow/prjxray/commit/30890e0e041f7533ee669da5b88f99b4932a6e42).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6e3f0537](https://github.com/SymbiFlow/prjxray/commit/6e3f05370102d3b93760120741ca75c14599e7e2).

 Latest commit was;
 ```
-commit 30890e0e041f7533ee669da5b88f99b4932a6e42
-Merge: 905a6b5b b8ff7326
+commit 6e3f05370102d3b93760120741ca75c14599e7e2
+Merge: 14d2c2b9 b81df3fe
 Author: litghost <537074+litghost@users.noreply.github.com>
-Date:   Thu Jan 14 08:16:43 2021 -0800
+Date:   Fri Jan 22 12:36:55 2021 -0800

-    Merge pull request #1539 from dnltz/WIP/dnltz/refactory_database
+    Merge pull request #1558 from antmicro/add-gtp-channel-conf
    
-    Refactor fabric data in database
+    Add GTP_CHANNEL fuzzer
 ```


@ -59,7 +59,7 @@ Date:   Thu Jan 14 08:16:43 2021 -0800

 ### Settings

-Created using following [settings/artix7.sh (sha256: 98f0e8a28de014f0e40c23763e053c55d789770a5850dc591d7aef73f9c64204)](https://github.com/SymbiFlow/prjxray/blob/30890e0e041f7533ee669da5b88f99b4932a6e42/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/6e3f05370102d3b93760120741ca75c14599e7e2/settings/artix7.sh)
 ```shell
 #!/bin/bash
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
@ -96,6 +96,8 @@ export XRAY_ROI_GRID_Y2="51"

 source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh

+eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py)
+
 ```

 ### [Results](artix7/)
@ -150,6 +152,21 @@ Results have checksums;
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/mask_dsp_l.origin_info.db`](./artix7/mask_dsp_l.origin_info.db)
 * [`0ea9fc3ec271604c27b850f84ec3811fd366c0897dfb8728bdb96d7f170a8a27  ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
 * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/mask_dsp_r.origin_info.db`](./artix7/mask_dsp_r.origin_info.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_0.db`](./artix7/mask_gtp_channel_0.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_0_mid_left.db`](./artix7/mask_gtp_channel_0_mid_left.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_0_mid_right.db`](./artix7/mask_gtp_channel_0_mid_right.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_1.db`](./artix7/mask_gtp_channel_1.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_1_mid_left.db`](./artix7/mask_gtp_channel_1_mid_left.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_1_mid_right.db`](./artix7/mask_gtp_channel_1_mid_right.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_2.db`](./artix7/mask_gtp_channel_2.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_2_mid_left.db`](./artix7/mask_gtp_channel_2_mid_left.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_2_mid_right.db`](./artix7/mask_gtp_channel_2_mid_right.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_3.db`](./artix7/mask_gtp_channel_3.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_3_mid_left.db`](./artix7/mask_gtp_channel_3_mid_left.db)
+ * [`2ad5834b0de909d9645f57caa13bbe7a8a2d68ad36adeda8ef8f59ecaa6f92bf  ./artix7/mask_gtp_channel_3_mid_right.db`](./artix7/mask_gtp_channel_3_mid_right.db)
+ * [`5a3a0bab93d2e2df22e1245c38d2e1a62f6d6cb1d6ad358099402d9c89aa13bc  ./artix7/mask_gtp_common.db`](./artix7/mask_gtp_common.db)
+ * [`60e4aed5bb9e864d2cd815281cf2bcf296b462d5e0982eabf9c582a4e2f89afc  ./artix7/mask_gtp_common_mid_left.db`](./artix7/mask_gtp_common_mid_left.db)
+ * [`60e4aed5bb9e864d2cd815281cf2bcf296b462d5e0982eabf9c582a4e2f89afc  ./artix7/mask_gtp_common_mid_right.db`](./artix7/mask_gtp_common_mid_right.db)
 * [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404  ./artix7/mask_hclk_cmt.db`](./artix7/mask_hclk_cmt.db)
 * [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404  ./artix7/mask_hclk_cmt_l.db`](./artix7/mask_hclk_cmt_l.db)
 * [`d0914443ac28056e840aee431bd51933a7cdc6504eefb052113d7e33e8b08e83  ./artix7/mask_hclk_ioi.db`](./artix7/mask_hclk_ioi.db)
@ -162,6 +179,7 @@ Results have checksums;
 * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
 * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
 * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
+ * [`454a16b8e9d2e0d38ee8c4af979a7bb1dd0757e5edb90d7b4f9489f094e7b162  ./artix7/mask_pcie_bot.db`](./artix7/mask_pcie_bot.db)
 * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
 * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
 * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
@ -261,6 +279,36 @@ Results have checksums;
 * [`10a6e47f7b26f0d21cf0a011d4a5f2a4266538bb8d028a07fd981323dc1f0da0  ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
 * [`f81459ae1c84e0e73815c4577a7d0b19b497dd7f16029763c3fc4f3b8410dcc2  ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
 * [`76965c2e6ba2acab8f809a3d947b100fd322ba5b6d88c358bf816699348b07bf  ./artix7/segbits_dsp_r.origin_info.db`](./artix7/segbits_dsp_r.origin_info.db)
+ * [`43e958853f10cd658ae0af26f78469bdac9b2bd1abb5dbee83f4e9dfad40eaeb  ./artix7/segbits_gtp_channel_0.db`](./artix7/segbits_gtp_channel_0.db)
+ * [`23f87065aec5f4f22dd0c3c0b5e73a50e13e28b3c494f07becf435f219030b30  ./artix7/segbits_gtp_channel_0.origin_info.db`](./artix7/segbits_gtp_channel_0.origin_info.db)
+ * [`fffd49cbef2952247233e2128b2752bf28f91f05e194495c6b044d125902191e  ./artix7/segbits_gtp_channel_0_mid_left.db`](./artix7/segbits_gtp_channel_0_mid_left.db)
+ * [`3c51cce7195efee2655f0d8bdddbcebd9f7424fc531958a503ce700a209833f4  ./artix7/segbits_gtp_channel_0_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_left.origin_info.db)
+ * [`cf590acfaf96e259c464dd05b6d9728724941aff4926bf8bd57794c07c6931b7  ./artix7/segbits_gtp_channel_0_mid_right.db`](./artix7/segbits_gtp_channel_0_mid_right.db)
+ * [`a9c772ded5981040e503509abde4e9dc48619655c4dc75eb6950ca7641a70af3  ./artix7/segbits_gtp_channel_0_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_0_mid_right.origin_info.db)
+ * [`ed22f29d7ea7180e50160b86da8c10e081ed9c3c399b7ff5b11f5e3c272d11a3  ./artix7/segbits_gtp_channel_1.db`](./artix7/segbits_gtp_channel_1.db)
+ * [`4c212e5ad3ac869e0b8e9927a97f32b75d5f5b166eb4a37af83738cb4ea2e95d  ./artix7/segbits_gtp_channel_1.origin_info.db`](./artix7/segbits_gtp_channel_1.origin_info.db)
+ * [`efc28e01454541111a2517802814f6afd6c8d6f44d9ed9bbd79923e547cd2668  ./artix7/segbits_gtp_channel_1_mid_left.db`](./artix7/segbits_gtp_channel_1_mid_left.db)
+ * [`e3ff98c549a159a928e34d7bccca8a5c513401019d0f2c3f476f56322db4bd3e  ./artix7/segbits_gtp_channel_1_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_left.origin_info.db)
+ * [`0d004b9755465b0d0c937f06d8ee3cfe83b6651810f766e8d2e63fbbccb6cab3  ./artix7/segbits_gtp_channel_1_mid_right.db`](./artix7/segbits_gtp_channel_1_mid_right.db)
+ * [`f15d88b953d32c73fbebe87a72bbae9a89b7e9f1e8fb53c45898a08f8c390dbc  ./artix7/segbits_gtp_channel_1_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_1_mid_right.origin_info.db)
+ * [`9a689135198dfacb307687415b086aef5a49e69eb39e331b6238e802907e3088  ./artix7/segbits_gtp_channel_2.db`](./artix7/segbits_gtp_channel_2.db)
+ * [`f5801a6809eb80627a630a988bc319d65e6b2fa2e56b2d612f07d98060cf6105  ./artix7/segbits_gtp_channel_2.origin_info.db`](./artix7/segbits_gtp_channel_2.origin_info.db)
+ * [`697dda8e24472fdfc92a94a31f9b6abac78e41b25fcb46303db9cef0016778f5  ./artix7/segbits_gtp_channel_2_mid_left.db`](./artix7/segbits_gtp_channel_2_mid_left.db)
+ * [`2fa375cc1c9b59a885e4c42764ac7fe816ec550df1dd694dbe55550e9ac495f5  ./artix7/segbits_gtp_channel_2_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_left.origin_info.db)
+ * [`e4eaec32de51c26916143be6fb83d005652b2dbdc82083f6dbfd6837dd8e6a46  ./artix7/segbits_gtp_channel_2_mid_right.db`](./artix7/segbits_gtp_channel_2_mid_right.db)
+ * [`d5bcd83a26fcc62bda3d7dffc5e54813fca2098c1a6c2294300f94c5f20b86ee  ./artix7/segbits_gtp_channel_2_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_2_mid_right.origin_info.db)
+ * [`7e13681d1a2435db935e800c9e8db3e17e1922c167cf470dc2172af733bc95ef  ./artix7/segbits_gtp_channel_3.db`](./artix7/segbits_gtp_channel_3.db)
+ * [`2b7728a26ab3a151e08f27cfa88582d661fc96900c227d5ab6ab6a4ff362e358  ./artix7/segbits_gtp_channel_3.origin_info.db`](./artix7/segbits_gtp_channel_3.origin_info.db)
+ * [`2d8634163b632d2030104a8c090e0dd935cdd5afd78b7491d3bfd83e1e81887d  ./artix7/segbits_gtp_channel_3_mid_left.db`](./artix7/segbits_gtp_channel_3_mid_left.db)
+ * [`290ca89106b61311978f9b7a9650fddb4dd5fb2b249612f66abdbe5a0a102f75  ./artix7/segbits_gtp_channel_3_mid_left.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_left.origin_info.db)
+ * [`4cda734eeec2bfdcd7eab62628b5577277f820aae7ba01c85fa7dbe2389ada1d  ./artix7/segbits_gtp_channel_3_mid_right.db`](./artix7/segbits_gtp_channel_3_mid_right.db)
+ * [`e8357be2f52886f7160aafa6495791ab890808f99a1e396077e17c30e49e6700  ./artix7/segbits_gtp_channel_3_mid_right.origin_info.db`](./artix7/segbits_gtp_channel_3_mid_right.origin_info.db)
+ * [`eca0e9e36b3e9f6e2584ee31e10a4104d5e128aac610da8236c94d49ebd02b3c  ./artix7/segbits_gtp_common.db`](./artix7/segbits_gtp_common.db)
+ * [`ddfdf641009197804217c42635638c4d797355684584051939ed9b48558b4494  ./artix7/segbits_gtp_common.origin_info.db`](./artix7/segbits_gtp_common.origin_info.db)
+ * [`0e52cfd32e766dafe42f2d2c7a2ff5c4a9195dce8a1d7cd019f49dd01d0ce818  ./artix7/segbits_gtp_common_mid_left.db`](./artix7/segbits_gtp_common_mid_left.db)
+ * [`225f0089d42a1d565d8335a053998a98a11120535255834c259df5cf2e921c85  ./artix7/segbits_gtp_common_mid_left.origin_info.db`](./artix7/segbits_gtp_common_mid_left.origin_info.db)
+ * [`c4b5b9477acc4e6220cb4e28604eecf205b2864cfd310edd9246f9182c90f451  ./artix7/segbits_gtp_common_mid_right.db`](./artix7/segbits_gtp_common_mid_right.db)
+ * [`1371addf23574533d237282c8651987089d3fa705fb7c7192dc5567ac80db8d6  ./artix7/segbits_gtp_common_mid_right.origin_info.db`](./artix7/segbits_gtp_common_mid_right.origin_info.db)
 * [`5d9063c8d4a35b5458573358459ec5e273cf242a97e5d7f1f0c1bf351edf2c63  ./artix7/segbits_hclk_cmt.db`](./artix7/segbits_hclk_cmt.db)
 * [`01b36f7757bee52cd1bdd78ecefed58b8215732678cef9eec629c21e4e89d7c5  ./artix7/segbits_hclk_cmt.origin_info.db`](./artix7/segbits_hclk_cmt.origin_info.db)
 * [`92eab3f79b39609fcd131300a63ddca51200ff4bd23b7b759d1e9bbf99543862  ./artix7/segbits_hclk_cmt_l.db`](./artix7/segbits_hclk_cmt_l.db)
@ -272,9 +320,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
- * [`32c3c91fc4dd17387aa991aa76276fb3e9932625cdcabc4e591eff388171d705  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
+ * [`6afcb554d32a59c99417f454c93d1b38b4b7fe17e0c2822f8d04b81fc0c2225f  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
 * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`ede9d35118f59bd01258a97af53288963a33afaec1000bc6c1f04bc88e5daf70  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`ced6c489ab1bae4823f259b65c90453d753b6b05c1ab8c00b959e2ca86504a8d  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
 * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
 * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@ -283,6 +331,8 @@ Results have checksums;
 * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c  ./artix7/segbits_lioi3_tbytesrc.origin_info.db`](./artix7/segbits_lioi3_tbytesrc.origin_info.db)
 * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b  ./artix7/segbits_lioi3_tbyteterm.db`](./artix7/segbits_lioi3_tbyteterm.db)
 * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250  ./artix7/segbits_lioi3_tbyteterm.origin_info.db`](./artix7/segbits_lioi3_tbyteterm.origin_info.db)
+ * [`5d3619d34977c6fc9a2e25e0b7db002af348bf35747b99fba89072778c943c5c  ./artix7/segbits_pcie_bot.db`](./artix7/segbits_pcie_bot.db)
+ * [`f2a3c7410f318cb6906c49916104864894d0d2daba55a2173dc2033c8037bae7  ./artix7/segbits_pcie_bot.origin_info.db`](./artix7/segbits_pcie_bot.origin_info.db)
 * [`ded5f7b0cdadb7558470dbca9102d7293e4237ecb563b5f69821e01b41e4aad1  ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
 * [`49456622ba534f8a616fe6e8bb0e3006c3ca292f2439f190ef07f82743f09613  ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
 * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a  ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db)
@ -516,7 +566,7 @@ Results have checksums;
 * [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e  ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
 * [`9aaa711d29833f53f765caa74f1e43ac288803d9af8030ce1694b3e3137c4078  ./artix7/xc7a100t/node_wires.json`](./artix7/xc7a100t/node_wires.json)
 * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391  ./artix7/xc7a100t/tileconn.json`](./artix7/xc7a100t/tileconn.json)
- * [`4adf96ae90772ca15b796b453dc5cde970f6dea1ced130271fe042e6993ba085  ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json)
+ * [`7af806f357beceb592e1ada7f4c582a5bef2e5ac708779e5813fa3f49ffa2a63  ./artix7/xc7a100t/tilegrid.json`](./artix7/xc7a100t/tilegrid.json)
 * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa  ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv)
 * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02  ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json)
 * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92  ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml)
@ -525,7 +575,7 @@ Results have checksums;
 * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92  ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml)
 * [`f25057c3f5f1273ab0e21bddafcb4499e219d84f7b5a00764b48bcb64dcd4bd2  ./artix7/xc7a200t/node_wires.json`](./artix7/xc7a200t/node_wires.json)
 * [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617  ./artix7/xc7a200t/tileconn.json`](./artix7/xc7a200t/tileconn.json)
- * [`9e8dc925a9534e26596989b489ccafa82ce8995c1ddbd507b57f6600936a5315  ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json)
+ * [`9a88cc6c4a07e1ebed4ffcd1d7683a1f9394a68567b4f90c5c236ad9c670ba03  ./artix7/xc7a200t/tilegrid.json`](./artix7/xc7a200t/tilegrid.json)
 * [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3  ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv)
 * [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42  ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json)
 * [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97  ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml)
@ -543,7 +593,7 @@ Results have checksums;
 * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d  ./artix7/xc7a35tftg256-1/part.yaml`](./artix7/xc7a35tftg256-1/part.yaml)
 * [`b60e01fef4c8c8d47fc646190d2d17fc63210cd0e82613624761e7463a7c35a6  ./artix7/xc7a50t/node_wires.json`](./artix7/xc7a50t/node_wires.json)
 * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b  ./artix7/xc7a50t/tileconn.json`](./artix7/xc7a50t/tileconn.json)
- * [`20ace148a3ee47cdb0d14bb0c35ef0aa426bf411d8f8b60f3fa5677fbbce83a8  ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json)
+ * [`5a3025cb7acf62e401c8b0a29e8f61cf35239574acdb4671157a27716f749fb4  ./artix7/xc7a50t/tilegrid.json`](./artix7/xc7a50t/tilegrid.json)
 * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805  ./artix7/xc7a50tfgg484-1/package_pins.csv`](./artix7/xc7a50tfgg484-1/package_pins.csv)
 * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae  ./artix7/xc7a50tfgg484-1/part.json`](./artix7/xc7a50tfgg484-1/part.json)
 * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3  ./artix7/xc7a50tfgg484-1/part.yaml`](./artix7/xc7a50tfgg484-1/part.yaml)
@ -553,7 +603,7 @@ Results have checksums;

 ### Settings

-Created using following [settings/kintex7.sh (sha256: 98cd036b10e049706983791abd2817952b0e0d379f848e24a341169844b98790)](https://github.com/SymbiFlow/prjxray/blob/30890e0e041f7533ee669da5b88f99b4932a6e42/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/6e3f05370102d3b93760120741ca75c14599e7e2/settings/kintex7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@ -584,6 +634,8 @@ export XRAY_ROI_GRID_Y2="156"

 source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh

+eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py)
+
 ```

 ### [Results](kintex7/)
@ -734,9 +786,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
- * [`66c9451631fbcde9a417fa19168a60a8bae3a991823d6773ffa1543396dde30e  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
+ * [`b635b86e0c7171123c853dee145cf57f7a1f411b82d7a368ed69f659f765b54b  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
 * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
- * [`f074bf5dcf90a014cd2534b21677c94550baa64bbce918e12fb3d370210e33c2  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
+ * [`0fc9c0513eb861f945057bf695b6b4e3026bd1b5a38953872b1c7ae3ab6f3468  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
 * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
 * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
@ -930,7 +982,7 @@ Results have checksums;

 ### Settings

-Created using following [settings/zynq7.sh (sha256: d043754dce270046665b600960905864cd490ca1e1aea2dbc0bbd113d0901433)](https://github.com/SymbiFlow/prjxray/blob/30890e0e041f7533ee669da5b88f99b4932a6e42/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/6e3f05370102d3b93760120741ca75c14599e7e2/settings/zynq7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@ -963,6 +1015,8 @@ export XRAY_ROI_GRID_Y2="155"

 source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh

+eval $(python3 ${XRAY_UTILS_DIR}/create_environment.py)
+
 ```

 ### [Results](zynq7/)
@ -1129,9 +1183,9 @@ Results have checksums;
 * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
 * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
 * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`9f1bc39f477dc15719584221debbc0b3ebfc45541fb510d8c52d7d4875d3ba66  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`505898cbef5f62b7e4d1274c49dad1a373bae12af7825b14e52f053bf42217fe  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
 * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`1b8775f4768d295252094ab935632665a8ce1d50a2077685c3ac74d796425958  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`769ba4269774fca078ed64a0acaf380ae9532753b6cfb9378457e6485adbe15c  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
 * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
 * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
 * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
--- a/artix7/mask_gtp_channel_0.db
+++ b/artix7/mask_gtp_channel_0.db
--- a/artix7/mask_gtp_channel_0_mid_left.db
+++ b/artix7/mask_gtp_channel_0_mid_left.db
--- a/artix7/mask_gtp_channel_0_mid_right.db
+++ b/artix7/mask_gtp_channel_0_mid_right.db
--- a/artix7/mask_gtp_channel_1.db
+++ b/artix7/mask_gtp_channel_1.db
--- a/artix7/mask_gtp_channel_1_mid_left.db
+++ b/artix7/mask_gtp_channel_1_mid_left.db
--- a/artix7/mask_gtp_channel_1_mid_right.db
+++ b/artix7/mask_gtp_channel_1_mid_right.db
--- a/artix7/mask_gtp_channel_2.db
+++ b/artix7/mask_gtp_channel_2.db
--- a/artix7/mask_gtp_channel_2_mid_left.db
+++ b/artix7/mask_gtp_channel_2_mid_left.db
--- a/artix7/mask_gtp_channel_2_mid_right.db
+++ b/artix7/mask_gtp_channel_2_mid_right.db
--- a/artix7/mask_gtp_channel_3.db
+++ b/artix7/mask_gtp_channel_3.db
--- a/artix7/mask_gtp_channel_3_mid_left.db
+++ b/artix7/mask_gtp_channel_3_mid_left.db
--- a/artix7/mask_gtp_channel_3_mid_right.db
+++ b/artix7/mask_gtp_channel_3_mid_right.db
--- a/artix7/mask_gtp_common.db
+++ b/artix7/mask_gtp_common.db
@ -0,0 +1,282 @@
+bit 28_1424
+bit 28_1425
+bit 28_1426
+bit 28_1427
+bit 28_1428
+bit 28_1429
+bit 28_1430
+bit 28_1431
+bit 28_1432
+bit 28_1433
+bit 28_1434
+bit 28_1435
+bit 28_1436
+bit 28_1437
+bit 28_1440
+bit 28_1442
+bit 28_1448
+bit 28_1449
+bit 28_1450
+bit 28_1451
+bit 28_1452
+bit 28_1456
+bit 28_1457
+bit 28_1458
+bit 28_1459
+bit 28_1460
+bit 28_1461
+bit 28_1462
+bit 28_1463
+bit 28_1464
+bit 28_1465
+bit 28_1466
+bit 28_1467
+bit 28_1488
+bit 28_1489
+bit 28_1490
+bit 28_1491
+bit 28_1492
+bit 28_1493
+bit 28_1494
+bit 28_1495
+bit 28_1512
+bit 28_1514
+bit 28_1516
+bit 28_1528
+bit 28_1544
+bit 28_1545
+bit 28_1546
+bit 28_1547
+bit 28_1548
+bit 28_1549
+bit 28_1550
+bit 28_1551
+bit 28_1552
+bit 28_1553
+bit 28_1554
+bit 28_1555
+bit 28_1556
+bit 28_1557
+bit 28_1558
+bit 28_1559
+bit 28_1560
+bit 28_1561
+bit 28_1562
+bit 28_1563
+bit 28_1576
+bit 28_1578
+bit 28_1579
+bit 28_1580
+bit 28_1582
+bit 28_1584
+bit 28_1640
+bit 28_1641
+bit 28_1642
+bit 28_1643
+bit 28_1644
+bit 28_1645
+bit 28_1646
+bit 28_1647
+bit 28_1648
+bit 28_1649
+bit 28_1650
+bit 28_1651
+bit 28_1652
+bit 28_1653
+bit 28_1654
+bit 28_1655
+bit 28_1656
+bit 28_1657
+bit 28_1658
+bit 28_1659
+bit 28_1660
+bit 28_1661
+bit 28_1662
+bit 28_1663
+bit 28_1664
+bit 28_1665
+bit 28_1666
+bit 28_1667
+bit 28_1668
+bit 28_1669
+bit 28_1670
+bit 28_1671
+bit 28_1728
+bit 28_1729
+bit 28_1730
+bit 28_1731
+bit 28_1732
+bit 28_1733
+bit 28_1734
+bit 28_1735
+bit 28_1760
+bit 28_1761
+bit 28_1762
+bit 28_1763
+bit 28_1764
+bit 28_1765
+bit 28_1766
+bit 28_1767
+bit 28_1768
+bit 28_1769
+bit 28_1770
+bit 28_1771
+bit 28_1776
+bit 28_1777
+bit 28_1778
+bit 28_1779
+bit 28_1780
+bit 28_1784
+bit 28_1786
+bit 28_1792
+bit 28_1793
+bit 28_1794
+bit 28_1795
+bit 28_1796
+bit 28_1797
+bit 28_1798
+bit 28_1799
+bit 28_1800
+bit 28_1801
+bit 28_1802
+bit 28_1803
+bit 28_1804
+bit 28_1805
+bit 29_1424
+bit 29_1425
+bit 29_1426
+bit 29_1427
+bit 29_1428
+bit 29_1429
+bit 29_1430
+bit 29_1431
+bit 29_1432
+bit 29_1433
+bit 29_1434
+bit 29_1435
+bit 29_1436
+bit 29_1440
+bit 29_1443
+bit 29_1446
+bit 29_1448
+bit 29_1449
+bit 29_1450
+bit 29_1451
+bit 29_1456
+bit 29_1457
+bit 29_1458
+bit 29_1459
+bit 29_1460
+bit 29_1461
+bit 29_1462
+bit 29_1463
+bit 29_1464
+bit 29_1465
+bit 29_1466
+bit 29_1467
+bit 29_1488
+bit 29_1489
+bit 29_1490
+bit 29_1491
+bit 29_1492
+bit 29_1493
+bit 29_1494
+bit 29_1495
+bit 29_1512
+bit 29_1516
+bit 29_1528
+bit 29_1544
+bit 29_1545
+bit 29_1546
+bit 29_1547
+bit 29_1548
+bit 29_1549
+bit 29_1550
+bit 29_1551
+bit 29_1552
+bit 29_1553
+bit 29_1554
+bit 29_1555
+bit 29_1556
+bit 29_1557
+bit 29_1558
+bit 29_1559
+bit 29_1560
+bit 29_1561
+bit 29_1562
+bit 29_1563
+bit 29_1576
+bit 29_1580
+bit 29_1581
+bit 29_1640
+bit 29_1641
+bit 29_1642
+bit 29_1643
+bit 29_1644
+bit 29_1645
+bit 29_1646
+bit 29_1647
+bit 29_1648
+bit 29_1649
+bit 29_1650
+bit 29_1651
+bit 29_1652
+bit 29_1653
+bit 29_1654
+bit 29_1655
+bit 29_1656
+bit 29_1657
+bit 29_1658
+bit 29_1659
+bit 29_1660
+bit 29_1661
+bit 29_1662
+bit 29_1663
+bit 29_1664
+bit 29_1665
+bit 29_1666
+bit 29_1667
+bit 29_1668
+bit 29_1669
+bit 29_1670
+bit 29_1671
+bit 29_1728
+bit 29_1729
+bit 29_1730
+bit 29_1731
+bit 29_1732
+bit 29_1733
+bit 29_1734
+bit 29_1735
+bit 29_1760
+bit 29_1761
+bit 29_1762
+bit 29_1763
+bit 29_1764
+bit 29_1765
+bit 29_1766
+bit 29_1767
+bit 29_1768
+bit 29_1769
+bit 29_1770
+bit 29_1771
+bit 29_1776
+bit 29_1777
+bit 29_1778
+bit 29_1779
+bit 29_1784
+bit 29_1787
+bit 29_1790
+bit 29_1792
+bit 29_1793
+bit 29_1794
+bit 29_1795
+bit 29_1796
+bit 29_1797
+bit 29_1798
+bit 29_1799
+bit 29_1800
+bit 29_1801
+bit 29_1802
+bit 29_1803
+bit 29_1804
--- a/artix7/mask_gtp_common_mid_left.db
+++ b/artix7/mask_gtp_common_mid_left.db
@ -0,0 +1,282 @@
+bit 00_1424
+bit 00_1425
+bit 00_1426
+bit 00_1427
+bit 00_1428
+bit 00_1429
+bit 00_1430
+bit 00_1431
+bit 00_1432
+bit 00_1433
+bit 00_1434
+bit 00_1435
+bit 00_1436
+bit 00_1437
+bit 00_1440
+bit 00_1442
+bit 00_1448
+bit 00_1449
+bit 00_1450
+bit 00_1451
+bit 00_1452
+bit 00_1456
+bit 00_1457
+bit 00_1458
+bit 00_1459
+bit 00_1460
+bit 00_1461
+bit 00_1462
+bit 00_1463
+bit 00_1464
+bit 00_1465
+bit 00_1466
+bit 00_1467
+bit 00_1488
+bit 00_1489
+bit 00_1490
+bit 00_1491
+bit 00_1492
+bit 00_1493
+bit 00_1494
+bit 00_1495
+bit 00_1512
+bit 00_1514
+bit 00_1516
+bit 00_1528
+bit 00_1544
+bit 00_1545
+bit 00_1546
+bit 00_1547
+bit 00_1548
+bit 00_1549
+bit 00_1550
+bit 00_1551
+bit 00_1552
+bit 00_1553
+bit 00_1554
+bit 00_1555
+bit 00_1556
+bit 00_1557
+bit 00_1558
+bit 00_1559
+bit 00_1560
+bit 00_1561
+bit 00_1562
+bit 00_1563
+bit 00_1576
+bit 00_1578
+bit 00_1579
+bit 00_1580
+bit 00_1582
+bit 00_1584
+bit 00_1640
+bit 00_1641
+bit 00_1642
+bit 00_1643
+bit 00_1644
+bit 00_1645
+bit 00_1646
+bit 00_1647
+bit 00_1648
+bit 00_1649
+bit 00_1650
+bit 00_1651
+bit 00_1652
+bit 00_1653
+bit 00_1654
+bit 00_1655
+bit 00_1656
+bit 00_1657
+bit 00_1658
+bit 00_1659
+bit 00_1660
+bit 00_1661
+bit 00_1662
+bit 00_1663
+bit 00_1664
+bit 00_1665
+bit 00_1666
+bit 00_1667
+bit 00_1668
+bit 00_1669
+bit 00_1670
+bit 00_1671
+bit 00_1728
+bit 00_1729
+bit 00_1730
+bit 00_1731
+bit 00_1732
+bit 00_1733
+bit 00_1734
+bit 00_1735
+bit 00_1760
+bit 00_1761
+bit 00_1762
+bit 00_1763
+bit 00_1764
+bit 00_1765
+bit 00_1766
+bit 00_1767
+bit 00_1768
+bit 00_1769
+bit 00_1770
+bit 00_1771
+bit 00_1776
+bit 00_1777
+bit 00_1778
+bit 00_1779
+bit 00_1780
+bit 00_1784
+bit 00_1786
+bit 00_1792
+bit 00_1793
+bit 00_1794
+bit 00_1795
+bit 00_1796
+bit 00_1797
+bit 00_1798
+bit 00_1799
+bit 00_1800
+bit 00_1801
+bit 00_1802
+bit 00_1803
+bit 00_1804
+bit 00_1805
+bit 01_1424
+bit 01_1425
+bit 01_1426
+bit 01_1427
+bit 01_1428
+bit 01_1429
+bit 01_1430
+bit 01_1431
+bit 01_1432
+bit 01_1433
+bit 01_1434
+bit 01_1435
+bit 01_1436
+bit 01_1440
+bit 01_1443
+bit 01_1446
+bit 01_1448
+bit 01_1449
+bit 01_1450
+bit 01_1451
+bit 01_1456
+bit 01_1457
+bit 01_1458
+bit 01_1459
+bit 01_1460
+bit 01_1461
+bit 01_1462
+bit 01_1463
+bit 01_1464
+bit 01_1465
+bit 01_1466
+bit 01_1467
+bit 01_1488
+bit 01_1489
+bit 01_1490
+bit 01_1491
+bit 01_1492
+bit 01_1493
+bit 01_1494
+bit 01_1495
+bit 01_1512
+bit 01_1516
+bit 01_1528
+bit 01_1544
+bit 01_1545
+bit 01_1546
+bit 01_1547
+bit 01_1548
+bit 01_1549
+bit 01_1550
+bit 01_1551
+bit 01_1552
+bit 01_1553
+bit 01_1554
+bit 01_1555
+bit 01_1556
+bit 01_1557
+bit 01_1558
+bit 01_1559
+bit 01_1560
+bit 01_1561
+bit 01_1562
+bit 01_1563
+bit 01_1576
+bit 01_1580
+bit 01_1581
+bit 01_1640
+bit 01_1641
+bit 01_1642
+bit 01_1643
+bit 01_1644
+bit 01_1645
+bit 01_1646
+bit 01_1647
+bit 01_1648
+bit 01_1649
+bit 01_1650
+bit 01_1651
+bit 01_1652
+bit 01_1653
+bit 01_1654
+bit 01_1655
+bit 01_1656
+bit 01_1657
+bit 01_1658
+bit 01_1659
+bit 01_1660
+bit 01_1661
+bit 01_1662
+bit 01_1663
+bit 01_1664
+bit 01_1665
+bit 01_1666
+bit 01_1667
+bit 01_1668
+bit 01_1669
+bit 01_1670
+bit 01_1671
+bit 01_1728
+bit 01_1729
+bit 01_1730
+bit 01_1731
+bit 01_1732
+bit 01_1733
+bit 01_1734
+bit 01_1735
+bit 01_1760
+bit 01_1761
+bit 01_1762
+bit 01_1763
+bit 01_1764
+bit 01_1765
+bit 01_1766
+bit 01_1767
+bit 01_1768
+bit 01_1769
+bit 01_1770
+bit 01_1771
+bit 01_1776
+bit 01_1777
+bit 01_1778
+bit 01_1779
+bit 01_1784
+bit 01_1787
+bit 01_1790
+bit 01_1792
+bit 01_1793
+bit 01_1794
+bit 01_1795
+bit 01_1796
+bit 01_1797
+bit 01_1798
+bit 01_1799
+bit 01_1800
+bit 01_1801
+bit 01_1802
+bit 01_1803
+bit 01_1804
--- a/artix7/mask_gtp_common_mid_right.db
+++ b/artix7/mask_gtp_common_mid_right.db
@ -0,0 +1,282 @@
+bit 00_1424
+bit 00_1425
+bit 00_1426
+bit 00_1427
+bit 00_1428
+bit 00_1429
+bit 00_1430
+bit 00_1431
+bit 00_1432
+bit 00_1433
+bit 00_1434
+bit 00_1435
+bit 00_1436
+bit 00_1437
+bit 00_1440
+bit 00_1442
+bit 00_1448
+bit 00_1449
+bit 00_1450
+bit 00_1451
+bit 00_1452
+bit 00_1456
+bit 00_1457
+bit 00_1458
+bit 00_1459
+bit 00_1460
+bit 00_1461
+bit 00_1462
+bit 00_1463
+bit 00_1464
+bit 00_1465
+bit 00_1466
+bit 00_1467
+bit 00_1488
+bit 00_1489
+bit 00_1490
+bit 00_1491
+bit 00_1492
+bit 00_1493
+bit 00_1494
+bit 00_1495
+bit 00_1512
+bit 00_1514
+bit 00_1516
+bit 00_1528
+bit 00_1544
+bit 00_1545
+bit 00_1546
+bit 00_1547
+bit 00_1548
+bit 00_1549
+bit 00_1550
+bit 00_1551
+bit 00_1552
+bit 00_1553
+bit 00_1554
+bit 00_1555
+bit 00_1556
+bit 00_1557
+bit 00_1558
+bit 00_1559
+bit 00_1560
+bit 00_1561
+bit 00_1562
+bit 00_1563
+bit 00_1576
+bit 00_1578
+bit 00_1579
+bit 00_1580
+bit 00_1582
+bit 00_1584
+bit 00_1640
+bit 00_1641
+bit 00_1642
+bit 00_1643
+bit 00_1644
+bit 00_1645
+bit 00_1646
+bit 00_1647
+bit 00_1648
+bit 00_1649
+bit 00_1650
+bit 00_1651
+bit 00_1652
+bit 00_1653
+bit 00_1654
+bit 00_1655
+bit 00_1656
+bit 00_1657
+bit 00_1658
+bit 00_1659
+bit 00_1660
+bit 00_1661
+bit 00_1662
+bit 00_1663
+bit 00_1664
+bit 00_1665
+bit 00_1666
+bit 00_1667
+bit 00_1668
+bit 00_1669
+bit 00_1670
+bit 00_1671
+bit 00_1728
+bit 00_1729
+bit 00_1730
+bit 00_1731
+bit 00_1732
+bit 00_1733
+bit 00_1734
+bit 00_1735
+bit 00_1760
+bit 00_1761
+bit 00_1762
+bit 00_1763
+bit 00_1764
+bit 00_1765
+bit 00_1766
+bit 00_1767
+bit 00_1768
+bit 00_1769
+bit 00_1770
+bit 00_1771
+bit 00_1776
+bit 00_1777
+bit 00_1778
+bit 00_1779
+bit 00_1780
+bit 00_1784
+bit 00_1786
+bit 00_1792
+bit 00_1793
+bit 00_1794
+bit 00_1795
+bit 00_1796
+bit 00_1797
+bit 00_1798
+bit 00_1799
+bit 00_1800
+bit 00_1801
+bit 00_1802
+bit 00_1803
+bit 00_1804
+bit 00_1805
+bit 01_1424
+bit 01_1425
+bit 01_1426
+bit 01_1427
+bit 01_1428
+bit 01_1429
+bit 01_1430
+bit 01_1431
+bit 01_1432
+bit 01_1433
+bit 01_1434
+bit 01_1435
+bit 01_1436
+bit 01_1440
+bit 01_1443
+bit 01_1446
+bit 01_1448
+bit 01_1449
+bit 01_1450
+bit 01_1451
+bit 01_1456
+bit 01_1457
+bit 01_1458
+bit 01_1459
+bit 01_1460
+bit 01_1461
+bit 01_1462
+bit 01_1463
+bit 01_1464
+bit 01_1465
+bit 01_1466
+bit 01_1467
+bit 01_1488
+bit 01_1489
+bit 01_1490
+bit 01_1491
+bit 01_1492
+bit 01_1493
+bit 01_1494
+bit 01_1495
+bit 01_1512
+bit 01_1516
+bit 01_1528
+bit 01_1544
+bit 01_1545
+bit 01_1546
+bit 01_1547
+bit 01_1548
+bit 01_1549
+bit 01_1550
+bit 01_1551
+bit 01_1552
+bit 01_1553
+bit 01_1554
+bit 01_1555
+bit 01_1556
+bit 01_1557
+bit 01_1558
+bit 01_1559
+bit 01_1560
+bit 01_1561
+bit 01_1562
+bit 01_1563
+bit 01_1576
+bit 01_1580
+bit 01_1581
+bit 01_1640
+bit 01_1641
+bit 01_1642
+bit 01_1643
+bit 01_1644
+bit 01_1645
+bit 01_1646
+bit 01_1647
+bit 01_1648
+bit 01_1649
+bit 01_1650
+bit 01_1651
+bit 01_1652
+bit 01_1653
+bit 01_1654
+bit 01_1655
+bit 01_1656
+bit 01_1657
+bit 01_1658
+bit 01_1659
+bit 01_1660
+bit 01_1661
+bit 01_1662
+bit 01_1663
+bit 01_1664
+bit 01_1665
+bit 01_1666
+bit 01_1667
+bit 01_1668
+bit 01_1669
+bit 01_1670
+bit 01_1671
+bit 01_1728
+bit 01_1729
+bit 01_1730
+bit 01_1731
+bit 01_1732
+bit 01_1733
+bit 01_1734
+bit 01_1735
+bit 01_1760
+bit 01_1761
+bit 01_1762
+bit 01_1763
+bit 01_1764
+bit 01_1765
+bit 01_1766
+bit 01_1767
+bit 01_1768
+bit 01_1769
+bit 01_1770
+bit 01_1771
+bit 01_1776
+bit 01_1777
+bit 01_1778
+bit 01_1779
+bit 01_1784
+bit 01_1787
+bit 01_1790
+bit 01_1792
+bit 01_1793
+bit 01_1794
+bit 01_1795
+bit 01_1796
+bit 01_1797
+bit 01_1798
+bit 01_1799
+bit 01_1800
+bit 01_1801
+bit 01_1802
+bit 01_1803
+bit 01_1804
--- a/artix7/mask_pcie_bot.db
+++ b/artix7/mask_pcie_bot.db
--- a/artix7/segbits_gtp_channel_0.db
+++ b/artix7/segbits_gtp_channel_0.db
--- a/artix7/segbits_gtp_channel_0.origin_info.db
+++ b/artix7/segbits_gtp_channel_0.origin_info.db
--- a/artix7/segbits_gtp_channel_0_mid_left.db
+++ b/artix7/segbits_gtp_channel_0_mid_left.db
--- a/artix7/segbits_gtp_channel_0_mid_left.origin_info.db
+++ b/artix7/segbits_gtp_channel_0_mid_left.origin_info.db
--- a/artix7/segbits_gtp_channel_0_mid_right.db
+++ b/artix7/segbits_gtp_channel_0_mid_right.db
--- a/artix7/segbits_gtp_channel_0_mid_right.origin_info.db
+++ b/artix7/segbits_gtp_channel_0_mid_right.origin_info.db
--- a/artix7/segbits_gtp_channel_1.db
+++ b/artix7/segbits_gtp_channel_1.db
--- a/artix7/segbits_gtp_channel_1.origin_info.db
+++ b/artix7/segbits_gtp_channel_1.origin_info.db
--- a/artix7/segbits_gtp_channel_1_mid_left.db
+++ b/artix7/segbits_gtp_channel_1_mid_left.db
--- a/artix7/segbits_gtp_channel_1_mid_left.origin_info.db
+++ b/artix7/segbits_gtp_channel_1_mid_left.origin_info.db
--- a/artix7/segbits_gtp_channel_1_mid_right.db
+++ b/artix7/segbits_gtp_channel_1_mid_right.db
--- a/artix7/segbits_gtp_channel_1_mid_right.origin_info.db
+++ b/artix7/segbits_gtp_channel_1_mid_right.origin_info.db
--- a/artix7/segbits_gtp_channel_2.db
+++ b/artix7/segbits_gtp_channel_2.db
--- a/artix7/segbits_gtp_channel_2.origin_info.db
+++ b/artix7/segbits_gtp_channel_2.origin_info.db
--- a/artix7/segbits_gtp_channel_2_mid_left.db
+++ b/artix7/segbits_gtp_channel_2_mid_left.db
--- a/artix7/segbits_gtp_channel_2_mid_left.origin_info.db
+++ b/artix7/segbits_gtp_channel_2_mid_left.origin_info.db
--- a/artix7/segbits_gtp_channel_2_mid_right.db
+++ b/artix7/segbits_gtp_channel_2_mid_right.db
--- a/artix7/segbits_gtp_channel_2_mid_right.origin_info.db
+++ b/artix7/segbits_gtp_channel_2_mid_right.origin_info.db
--- a/artix7/segbits_gtp_channel_3.db
+++ b/artix7/segbits_gtp_channel_3.db
--- a/artix7/segbits_gtp_channel_3.origin_info.db
+++ b/artix7/segbits_gtp_channel_3.origin_info.db
--- a/artix7/segbits_gtp_channel_3_mid_left.db
+++ b/artix7/segbits_gtp_channel_3_mid_left.db
--- a/artix7/segbits_gtp_channel_3_mid_left.origin_info.db
+++ b/artix7/segbits_gtp_channel_3_mid_left.origin_info.db
--- a/artix7/segbits_gtp_channel_3_mid_right.db
+++ b/artix7/segbits_gtp_channel_3_mid_right.db
--- a/artix7/segbits_gtp_channel_3_mid_right.origin_info.db
+++ b/artix7/segbits_gtp_channel_3_mid_right.origin_info.db
--- a/artix7/segbits_gtp_common.db
+++ b/artix7/segbits_gtp_common.db
@ -0,0 +1,282 @@
+GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] 29_1581
+GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] 28_1582
+GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG 28_1580
+GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST 28_1576
+GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE 28_1578
+GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG 29_1580
+GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST 29_1576
+GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE 28_1579
+GTP_COMMON.GTPE2.BIAS_CFG[0] 28_1640
+GTP_COMMON.GTPE2.BIAS_CFG[1] 29_1640
+GTP_COMMON.GTPE2.BIAS_CFG[2] 28_1641
+GTP_COMMON.GTPE2.BIAS_CFG[3] 29_1641
+GTP_COMMON.GTPE2.BIAS_CFG[4] 28_1642
+GTP_COMMON.GTPE2.BIAS_CFG[5] 29_1642
+GTP_COMMON.GTPE2.BIAS_CFG[6] 28_1643
+GTP_COMMON.GTPE2.BIAS_CFG[7] 29_1643
+GTP_COMMON.GTPE2.BIAS_CFG[8] 28_1644
+GTP_COMMON.GTPE2.BIAS_CFG[9] 29_1644
+GTP_COMMON.GTPE2.BIAS_CFG[10] 28_1645
+GTP_COMMON.GTPE2.BIAS_CFG[11] 29_1645
+GTP_COMMON.GTPE2.BIAS_CFG[12] 28_1646
+GTP_COMMON.GTPE2.BIAS_CFG[13] 29_1646
+GTP_COMMON.GTPE2.BIAS_CFG[14] 28_1647
+GTP_COMMON.GTPE2.BIAS_CFG[15] 29_1647
+GTP_COMMON.GTPE2.BIAS_CFG[16] 28_1648
+GTP_COMMON.GTPE2.BIAS_CFG[17] 29_1648
+GTP_COMMON.GTPE2.BIAS_CFG[18] 28_1649
+GTP_COMMON.GTPE2.BIAS_CFG[19] 29_1649
+GTP_COMMON.GTPE2.BIAS_CFG[20] 28_1650
+GTP_COMMON.GTPE2.BIAS_CFG[21] 29_1650
+GTP_COMMON.GTPE2.BIAS_CFG[22] 28_1651
+GTP_COMMON.GTPE2.BIAS_CFG[23] 29_1651
+GTP_COMMON.GTPE2.BIAS_CFG[24] 28_1652
+GTP_COMMON.GTPE2.BIAS_CFG[25] 29_1652
+GTP_COMMON.GTPE2.BIAS_CFG[26] 28_1653
+GTP_COMMON.GTPE2.BIAS_CFG[27] 29_1653
+GTP_COMMON.GTPE2.BIAS_CFG[28] 28_1654
+GTP_COMMON.GTPE2.BIAS_CFG[29] 29_1654
+GTP_COMMON.GTPE2.BIAS_CFG[30] 28_1655
+GTP_COMMON.GTPE2.BIAS_CFG[31] 29_1655
+GTP_COMMON.GTPE2.BIAS_CFG[32] 28_1656
+GTP_COMMON.GTPE2.BIAS_CFG[33] 29_1656
+GTP_COMMON.GTPE2.BIAS_CFG[34] 28_1657
+GTP_COMMON.GTPE2.BIAS_CFG[35] 29_1657
+GTP_COMMON.GTPE2.BIAS_CFG[36] 28_1658
+GTP_COMMON.GTPE2.BIAS_CFG[37] 29_1658
+GTP_COMMON.GTPE2.BIAS_CFG[38] 28_1659
+GTP_COMMON.GTPE2.BIAS_CFG[39] 29_1659
+GTP_COMMON.GTPE2.BIAS_CFG[40] 28_1660
+GTP_COMMON.GTPE2.BIAS_CFG[41] 29_1660
+GTP_COMMON.GTPE2.BIAS_CFG[42] 28_1661
+GTP_COMMON.GTPE2.BIAS_CFG[43] 29_1661
+GTP_COMMON.GTPE2.BIAS_CFG[44] 28_1662
+GTP_COMMON.GTPE2.BIAS_CFG[45] 29_1662
+GTP_COMMON.GTPE2.BIAS_CFG[46] 28_1663
+GTP_COMMON.GTPE2.BIAS_CFG[47] 29_1663
+GTP_COMMON.GTPE2.BIAS_CFG[48] 28_1664
+GTP_COMMON.GTPE2.BIAS_CFG[49] 29_1664
+GTP_COMMON.GTPE2.BIAS_CFG[50] 28_1665
+GTP_COMMON.GTPE2.BIAS_CFG[51] 29_1665
+GTP_COMMON.GTPE2.BIAS_CFG[52] 28_1666
+GTP_COMMON.GTPE2.BIAS_CFG[53] 29_1666
+GTP_COMMON.GTPE2.BIAS_CFG[54] 28_1667
+GTP_COMMON.GTPE2.BIAS_CFG[55] 29_1667
+GTP_COMMON.GTPE2.BIAS_CFG[56] 28_1668
+GTP_COMMON.GTPE2.BIAS_CFG[57] 29_1668
+GTP_COMMON.GTPE2.BIAS_CFG[58] 28_1669
+GTP_COMMON.GTPE2.BIAS_CFG[59] 29_1669
+GTP_COMMON.GTPE2.BIAS_CFG[60] 28_1670
+GTP_COMMON.GTPE2.BIAS_CFG[61] 29_1670
+GTP_COMMON.GTPE2.BIAS_CFG[62] 28_1671
+GTP_COMMON.GTPE2.BIAS_CFG[63] 29_1671
+GTP_COMMON.GTPE2.COMMON_CFG[0] 28_1544
+GTP_COMMON.GTPE2.COMMON_CFG[1] 29_1544
+GTP_COMMON.GTPE2.COMMON_CFG[2] 28_1545
+GTP_COMMON.GTPE2.COMMON_CFG[3] 29_1545
+GTP_COMMON.GTPE2.COMMON_CFG[4] 28_1546
+GTP_COMMON.GTPE2.COMMON_CFG[5] 29_1546
+GTP_COMMON.GTPE2.COMMON_CFG[6] 28_1547
+GTP_COMMON.GTPE2.COMMON_CFG[7] 29_1547
+GTP_COMMON.GTPE2.COMMON_CFG[8] 28_1548
+GTP_COMMON.GTPE2.COMMON_CFG[9] 29_1548
+GTP_COMMON.GTPE2.COMMON_CFG[10] 28_1549
+GTP_COMMON.GTPE2.COMMON_CFG[11] 29_1549
+GTP_COMMON.GTPE2.COMMON_CFG[12] 28_1550
+GTP_COMMON.GTPE2.COMMON_CFG[13] 29_1550
+GTP_COMMON.GTPE2.COMMON_CFG[14] 28_1551
+GTP_COMMON.GTPE2.COMMON_CFG[15] 29_1551
+GTP_COMMON.GTPE2.COMMON_CFG[16] 28_1552
+GTP_COMMON.GTPE2.COMMON_CFG[17] 29_1552
+GTP_COMMON.GTPE2.COMMON_CFG[18] 28_1553
+GTP_COMMON.GTPE2.COMMON_CFG[19] 29_1553
+GTP_COMMON.GTPE2.COMMON_CFG[20] 28_1554
+GTP_COMMON.GTPE2.COMMON_CFG[21] 29_1554
+GTP_COMMON.GTPE2.COMMON_CFG[22] 28_1555
+GTP_COMMON.GTPE2.COMMON_CFG[23] 29_1555
+GTP_COMMON.GTPE2.COMMON_CFG[24] 28_1556
+GTP_COMMON.GTPE2.COMMON_CFG[25] 29_1556
+GTP_COMMON.GTPE2.COMMON_CFG[26] 28_1557
+GTP_COMMON.GTPE2.COMMON_CFG[27] 29_1557
+GTP_COMMON.GTPE2.COMMON_CFG[28] 28_1558
+GTP_COMMON.GTPE2.COMMON_CFG[29] 29_1558
+GTP_COMMON.GTPE2.COMMON_CFG[30] 28_1559
+GTP_COMMON.GTPE2.COMMON_CFG[31] 29_1559
+GTP_COMMON.GTPE2.IN_USE 28_1584
+GTP_COMMON.GTPE2.INV_GTGREFCLK0 29_1516
+GTP_COMMON.GTPE2.INV_GTGREFCLK1 28_1514
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] 28_1560
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] 29_1560
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] 28_1561
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] 29_1561
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] 28_1562
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] 29_1562
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] 28_1563
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] 29_1563
+GTP_COMMON.GTPE2.RSVD_ATTR0[0] 28_1488
+GTP_COMMON.GTPE2.RSVD_ATTR0[1] 29_1488
+GTP_COMMON.GTPE2.RSVD_ATTR0[2] 28_1489
+GTP_COMMON.GTPE2.RSVD_ATTR0[3] 29_1489
+GTP_COMMON.GTPE2.RSVD_ATTR0[4] 28_1490
+GTP_COMMON.GTPE2.RSVD_ATTR0[5] 29_1490
+GTP_COMMON.GTPE2.RSVD_ATTR0[6] 28_1491
+GTP_COMMON.GTPE2.RSVD_ATTR0[7] 29_1491
+GTP_COMMON.GTPE2.RSVD_ATTR0[8] 28_1492
+GTP_COMMON.GTPE2.RSVD_ATTR0[9] 29_1492
+GTP_COMMON.GTPE2.RSVD_ATTR0[10] 28_1493
+GTP_COMMON.GTPE2.RSVD_ATTR0[11] 29_1493
+GTP_COMMON.GTPE2.RSVD_ATTR0[12] 28_1494
+GTP_COMMON.GTPE2.RSVD_ATTR0[13] 29_1494
+GTP_COMMON.GTPE2.RSVD_ATTR0[14] 28_1495
+GTP_COMMON.GTPE2.RSVD_ATTR0[15] 29_1495
+GTP_COMMON.GTPE2.RSVD_ATTR1[0] 28_1728
+GTP_COMMON.GTPE2.RSVD_ATTR1[1] 29_1728
+GTP_COMMON.GTPE2.RSVD_ATTR1[2] 28_1729
+GTP_COMMON.GTPE2.RSVD_ATTR1[3] 29_1729
+GTP_COMMON.GTPE2.RSVD_ATTR1[4] 28_1730
+GTP_COMMON.GTPE2.RSVD_ATTR1[5] 29_1730
+GTP_COMMON.GTPE2.RSVD_ATTR1[6] 28_1731
+GTP_COMMON.GTPE2.RSVD_ATTR1[7] 29_1731
+GTP_COMMON.GTPE2.RSVD_ATTR1[8] 28_1732
+GTP_COMMON.GTPE2.RSVD_ATTR1[9] 29_1732
+GTP_COMMON.GTPE2.RSVD_ATTR1[10] 28_1733
+GTP_COMMON.GTPE2.RSVD_ATTR1[11] 29_1733
+GTP_COMMON.GTPE2.RSVD_ATTR1[12] 28_1734
+GTP_COMMON.GTPE2.RSVD_ATTR1[13] 29_1734
+GTP_COMMON.GTPE2.RSVD_ATTR1[14] 28_1735
+GTP_COMMON.GTPE2.RSVD_ATTR1[15] 29_1735
+GTP_COMMON.GTPE2.ZINV_DRPCLK 28_1516
+GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK 29_1512
+GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK 28_1512
+GTP_COMMON.GTPE2.PLL0_CFG[0] 28_1424
+GTP_COMMON.GTPE2.PLL0_CFG[1] 29_1424
+GTP_COMMON.GTPE2.PLL0_CFG[2] 28_1425
+GTP_COMMON.GTPE2.PLL0_CFG[3] 29_1425
+GTP_COMMON.GTPE2.PLL0_CFG[4] 28_1426
+GTP_COMMON.GTPE2.PLL0_CFG[5] 29_1426
+GTP_COMMON.GTPE2.PLL0_CFG[6] 28_1427
+GTP_COMMON.GTPE2.PLL0_CFG[7] 29_1427
+GTP_COMMON.GTPE2.PLL0_CFG[8] 28_1428
+GTP_COMMON.GTPE2.PLL0_CFG[9] 29_1428
+GTP_COMMON.GTPE2.PLL0_CFG[10] 28_1429
+GTP_COMMON.GTPE2.PLL0_CFG[11] 29_1429
+GTP_COMMON.GTPE2.PLL0_CFG[12] 28_1430
+GTP_COMMON.GTPE2.PLL0_CFG[13] 29_1430
+GTP_COMMON.GTPE2.PLL0_CFG[14] 28_1431
+GTP_COMMON.GTPE2.PLL0_CFG[15] 29_1431
+GTP_COMMON.GTPE2.PLL0_CFG[16] 28_1432
+GTP_COMMON.GTPE2.PLL0_CFG[17] 29_1432
+GTP_COMMON.GTPE2.PLL0_CFG[18] 28_1433
+GTP_COMMON.GTPE2.PLL0_CFG[19] 29_1433
+GTP_COMMON.GTPE2.PLL0_CFG[20] 28_1434
+GTP_COMMON.GTPE2.PLL0_CFG[21] 29_1434
+GTP_COMMON.GTPE2.PLL0_CFG[22] 28_1435
+GTP_COMMON.GTPE2.PLL0_CFG[23] 29_1435
+GTP_COMMON.GTPE2.PLL0_CFG[24] 28_1436
+GTP_COMMON.GTPE2.PLL0_CFG[25] 29_1436
+GTP_COMMON.GTPE2.PLL0_CFG[26] 28_1437
+GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] 28_1528
+GTP_COMMON.GTPE2.PLL0_FBDIV[0] 28_1440
+GTP_COMMON.GTPE2.PLL0_FBDIV[1] 29_1440
+GTP_COMMON.GTPE2.PLL0_FBDIV[4] 28_1442
+GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] 29_1443
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] 28_1456
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] 29_1456
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] 28_1457
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] 29_1457
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] 28_1458
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] 29_1458
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] 28_1459
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] 29_1459
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] 28_1460
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] 29_1460
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] 28_1461
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] 29_1461
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] 28_1462
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] 29_1462
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] 28_1463
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] 29_1463
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] 28_1464
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] 29_1464
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] 28_1465
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] 29_1465
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] 28_1466
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] 29_1466
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] 28_1467
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] 29_1467
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] 28_1448
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] 29_1448
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] 28_1449
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] 29_1449
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] 28_1450
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] 29_1450
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] 28_1451
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] 29_1451
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] 28_1452
+GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] 29_1446
+GTP_COMMON.GTPE2.PLL1_CFG[0] 28_1792
+GTP_COMMON.GTPE2.PLL1_CFG[1] 29_1792
+GTP_COMMON.GTPE2.PLL1_CFG[2] 28_1793
+GTP_COMMON.GTPE2.PLL1_CFG[3] 29_1793
+GTP_COMMON.GTPE2.PLL1_CFG[4] 28_1794
+GTP_COMMON.GTPE2.PLL1_CFG[5] 29_1794
+GTP_COMMON.GTPE2.PLL1_CFG[6] 28_1795
+GTP_COMMON.GTPE2.PLL1_CFG[7] 29_1795
+GTP_COMMON.GTPE2.PLL1_CFG[8] 28_1796
+GTP_COMMON.GTPE2.PLL1_CFG[9] 29_1796
+GTP_COMMON.GTPE2.PLL1_CFG[10] 28_1797
+GTP_COMMON.GTPE2.PLL1_CFG[11] 29_1797
+GTP_COMMON.GTPE2.PLL1_CFG[12] 28_1798
+GTP_COMMON.GTPE2.PLL1_CFG[13] 29_1798
+GTP_COMMON.GTPE2.PLL1_CFG[14] 28_1799
+GTP_COMMON.GTPE2.PLL1_CFG[15] 29_1799
+GTP_COMMON.GTPE2.PLL1_CFG[16] 28_1800
+GTP_COMMON.GTPE2.PLL1_CFG[17] 29_1800
+GTP_COMMON.GTPE2.PLL1_CFG[18] 28_1801
+GTP_COMMON.GTPE2.PLL1_CFG[19] 29_1801
+GTP_COMMON.GTPE2.PLL1_CFG[20] 28_1802
+GTP_COMMON.GTPE2.PLL1_CFG[21] 29_1802
+GTP_COMMON.GTPE2.PLL1_CFG[22] 28_1803
+GTP_COMMON.GTPE2.PLL1_CFG[23] 29_1803
+GTP_COMMON.GTPE2.PLL1_CFG[24] 28_1804
+GTP_COMMON.GTPE2.PLL1_CFG[25] 29_1804
+GTP_COMMON.GTPE2.PLL1_CFG[26] 28_1805
+GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] 29_1528
+GTP_COMMON.GTPE2.PLL1_FBDIV[0] 28_1784
+GTP_COMMON.GTPE2.PLL1_FBDIV[1] 29_1784
+GTP_COMMON.GTPE2.PLL1_FBDIV[4] 28_1786
+GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] 29_1787
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] 28_1760
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] 29_1760
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] 28_1761
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] 29_1761
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] 28_1762
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] 29_1762
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] 28_1763
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] 29_1763
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] 28_1764
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] 29_1764
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] 28_1765
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] 29_1765
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] 28_1766
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] 29_1766
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] 28_1767
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] 29_1767
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] 28_1768
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] 29_1768
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] 28_1769
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] 29_1769
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] 28_1770
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] 29_1770
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] 28_1771
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] 29_1771
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] 28_1776
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] 29_1776
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] 28_1777
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] 29_1777
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] 28_1778
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] 29_1778
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] 28_1779
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] 29_1779
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] 28_1780
+GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] 29_1790
--- a/artix7/segbits_gtp_common.origin_info.db
+++ b/artix7/segbits_gtp_common.origin_info.db
@ -0,0 +1,282 @@
+GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 29_1581
+GTP_COMMON.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 28_1582
+GTP_COMMON.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 28_1580
+GTP_COMMON.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 28_1576
+GTP_COMMON.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 28_1578
+GTP_COMMON.IBUFDS_GTE2_Y1.CLKCM_CFG origin:063-gtp-common-conf 29_1580
+GTP_COMMON.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 29_1576
+GTP_COMMON.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 28_1579
+GTP_COMMON.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 28_1640
+GTP_COMMON.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 29_1640
+GTP_COMMON.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 28_1641
+GTP_COMMON.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 29_1641
+GTP_COMMON.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 28_1642
+GTP_COMMON.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 29_1642
+GTP_COMMON.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 28_1643
+GTP_COMMON.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 29_1643
+GTP_COMMON.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 28_1644
+GTP_COMMON.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 29_1644
+GTP_COMMON.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 28_1645
+GTP_COMMON.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 29_1645
+GTP_COMMON.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 28_1646
+GTP_COMMON.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 29_1646
+GTP_COMMON.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 28_1647
+GTP_COMMON.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 29_1647
+GTP_COMMON.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 28_1648
+GTP_COMMON.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 29_1648
+GTP_COMMON.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 28_1649
+GTP_COMMON.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 29_1649
+GTP_COMMON.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 28_1650
+GTP_COMMON.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 29_1650
+GTP_COMMON.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 28_1651
+GTP_COMMON.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 29_1651
+GTP_COMMON.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 28_1652
+GTP_COMMON.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 29_1652
+GTP_COMMON.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 28_1653
+GTP_COMMON.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 29_1653
+GTP_COMMON.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 28_1654
+GTP_COMMON.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 29_1654
+GTP_COMMON.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 28_1655
+GTP_COMMON.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 29_1655
+GTP_COMMON.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 28_1656
+GTP_COMMON.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 29_1656
+GTP_COMMON.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 28_1657
+GTP_COMMON.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 29_1657
+GTP_COMMON.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 28_1658
+GTP_COMMON.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 29_1658
+GTP_COMMON.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 28_1659
+GTP_COMMON.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 29_1659
+GTP_COMMON.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 28_1660
+GTP_COMMON.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 29_1660
+GTP_COMMON.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 28_1661
+GTP_COMMON.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 29_1661
+GTP_COMMON.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 28_1662
+GTP_COMMON.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 29_1662
+GTP_COMMON.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 28_1663
+GTP_COMMON.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 29_1663
+GTP_COMMON.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 28_1664
+GTP_COMMON.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 29_1664
+GTP_COMMON.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 28_1665
+GTP_COMMON.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 29_1665
+GTP_COMMON.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 28_1666
+GTP_COMMON.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 29_1666
+GTP_COMMON.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 28_1667
+GTP_COMMON.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 29_1667
+GTP_COMMON.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 28_1668
+GTP_COMMON.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 29_1668
+GTP_COMMON.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 28_1669
+GTP_COMMON.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 29_1669
+GTP_COMMON.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 28_1670
+GTP_COMMON.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 29_1670
+GTP_COMMON.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 28_1671
+GTP_COMMON.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 29_1671
+GTP_COMMON.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 28_1544
+GTP_COMMON.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 29_1544
+GTP_COMMON.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 28_1545
+GTP_COMMON.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 29_1545
+GTP_COMMON.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 28_1546
+GTP_COMMON.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 29_1546
+GTP_COMMON.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 28_1547
+GTP_COMMON.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 29_1547
+GTP_COMMON.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 28_1548
+GTP_COMMON.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 29_1548
+GTP_COMMON.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 28_1549
+GTP_COMMON.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 29_1549
+GTP_COMMON.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 28_1550
+GTP_COMMON.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 29_1550
+GTP_COMMON.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 28_1551
+GTP_COMMON.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 29_1551
+GTP_COMMON.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 28_1552
+GTP_COMMON.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 29_1552
+GTP_COMMON.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 28_1553
+GTP_COMMON.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 29_1553
+GTP_COMMON.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 28_1554
+GTP_COMMON.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 29_1554
+GTP_COMMON.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 28_1555
+GTP_COMMON.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 29_1555
+GTP_COMMON.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 28_1556
+GTP_COMMON.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 29_1556
+GTP_COMMON.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 28_1557
+GTP_COMMON.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 29_1557
+GTP_COMMON.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 28_1558
+GTP_COMMON.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 29_1558
+GTP_COMMON.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 28_1559
+GTP_COMMON.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 29_1559
+GTP_COMMON.GTPE2.IN_USE origin:063-gtp-common-conf 28_1584
+GTP_COMMON.GTPE2.INV_GTGREFCLK0 origin:063-gtp-common-conf 29_1516
+GTP_COMMON.GTPE2.INV_GTGREFCLK1 origin:063-gtp-common-conf 28_1514
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 28_1560
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 29_1560
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 28_1561
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 29_1561
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 28_1562
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 29_1562
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 28_1563
+GTP_COMMON.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 29_1563
+GTP_COMMON.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 28_1488
+GTP_COMMON.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 29_1488
+GTP_COMMON.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 28_1489
+GTP_COMMON.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 29_1489
+GTP_COMMON.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 28_1490
+GTP_COMMON.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 29_1490
+GTP_COMMON.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 28_1491
+GTP_COMMON.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 29_1491
+GTP_COMMON.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 28_1492
+GTP_COMMON.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 29_1492
+GTP_COMMON.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 28_1493
+GTP_COMMON.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 29_1493
+GTP_COMMON.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 28_1494
+GTP_COMMON.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 29_1494
+GTP_COMMON.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 28_1495
+GTP_COMMON.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 29_1495
+GTP_COMMON.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 28_1728
+GTP_COMMON.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 29_1728
+GTP_COMMON.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 28_1729
+GTP_COMMON.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 29_1729
+GTP_COMMON.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 28_1730
+GTP_COMMON.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 29_1730
+GTP_COMMON.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 28_1731
+GTP_COMMON.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 29_1731
+GTP_COMMON.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 28_1732
+GTP_COMMON.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 29_1732
+GTP_COMMON.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 28_1733
+GTP_COMMON.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 29_1733
+GTP_COMMON.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 28_1734
+GTP_COMMON.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 29_1734
+GTP_COMMON.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 28_1735
+GTP_COMMON.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 29_1735
+GTP_COMMON.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 28_1516
+GTP_COMMON.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 29_1512
+GTP_COMMON.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 28_1512
+GTP_COMMON.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 28_1424
+GTP_COMMON.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 29_1424
+GTP_COMMON.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 28_1425
+GTP_COMMON.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 29_1425
+GTP_COMMON.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 28_1426
+GTP_COMMON.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 29_1426
+GTP_COMMON.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 28_1427
+GTP_COMMON.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 29_1427
+GTP_COMMON.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 28_1428
+GTP_COMMON.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 29_1428
+GTP_COMMON.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 28_1429
+GTP_COMMON.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 29_1429
+GTP_COMMON.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 28_1430
+GTP_COMMON.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 29_1430
+GTP_COMMON.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 28_1431
+GTP_COMMON.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 29_1431
+GTP_COMMON.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 28_1432
+GTP_COMMON.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 29_1432
+GTP_COMMON.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 28_1433
+GTP_COMMON.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 29_1433
+GTP_COMMON.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 28_1434
+GTP_COMMON.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 29_1434
+GTP_COMMON.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 28_1435
+GTP_COMMON.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 29_1435
+GTP_COMMON.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 28_1436
+GTP_COMMON.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 29_1436
+GTP_COMMON.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 28_1437
+GTP_COMMON.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 28_1528
+GTP_COMMON.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 28_1440
+GTP_COMMON.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 29_1440
+GTP_COMMON.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 28_1442
+GTP_COMMON.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 29_1443
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 28_1456
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 29_1456
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 28_1457
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 29_1457
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 28_1458
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 29_1458
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 28_1459
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 29_1459
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 28_1460
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 29_1460
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 28_1461
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 29_1461
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 28_1462
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 29_1462
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 28_1463
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 29_1463
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 28_1464
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 29_1464
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 28_1465
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 29_1465
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 28_1466
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 29_1466
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 28_1467
+GTP_COMMON.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 29_1467
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 28_1448
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 29_1448
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 28_1449
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 29_1449
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 28_1450
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 29_1450
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 28_1451
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 29_1451
+GTP_COMMON.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 28_1452
+GTP_COMMON.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1446
+GTP_COMMON.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 28_1792
+GTP_COMMON.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 29_1792
+GTP_COMMON.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 28_1793
+GTP_COMMON.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 29_1793
+GTP_COMMON.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 28_1794
+GTP_COMMON.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 29_1794
+GTP_COMMON.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 28_1795
+GTP_COMMON.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 29_1795
+GTP_COMMON.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 28_1796
+GTP_COMMON.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 29_1796
+GTP_COMMON.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 28_1797
+GTP_COMMON.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 29_1797
+GTP_COMMON.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 28_1798
+GTP_COMMON.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 29_1798
+GTP_COMMON.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 28_1799
+GTP_COMMON.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 29_1799
+GTP_COMMON.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 28_1800
+GTP_COMMON.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 29_1800
+GTP_COMMON.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 28_1801
+GTP_COMMON.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 29_1801
+GTP_COMMON.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 28_1802
+GTP_COMMON.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 29_1802
+GTP_COMMON.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 28_1803
+GTP_COMMON.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 29_1803
+GTP_COMMON.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 28_1804
+GTP_COMMON.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 29_1804
+GTP_COMMON.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 28_1805
+GTP_COMMON.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 29_1528
+GTP_COMMON.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 28_1784
+GTP_COMMON.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 29_1784
+GTP_COMMON.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 28_1786
+GTP_COMMON.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 29_1787
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 28_1760
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 29_1760
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 28_1761
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 29_1761
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 28_1762
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 29_1762
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 28_1763
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 29_1763
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 28_1764
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 29_1764
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 28_1765
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 29_1765
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 28_1766
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 29_1766
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 28_1767
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 29_1767
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 28_1768
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 29_1768
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 28_1769
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 29_1769
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 28_1770
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 29_1770
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 28_1771
+GTP_COMMON.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 29_1771
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 28_1776
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 29_1776
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 28_1777
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 29_1777
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 28_1778
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 29_1778
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 28_1779
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 29_1779
+GTP_COMMON.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 28_1780
+GTP_COMMON.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 29_1790
--- a/artix7/segbits_gtp_common_mid_left.db
+++ b/artix7/segbits_gtp_common_mid_left.db
@ -0,0 +1,282 @@
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE 00_1578
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKCM_CFG 01_1580
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE 00_1579
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] 00_1640
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] 01_1640
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] 00_1641
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] 01_1641
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] 00_1642
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] 01_1642
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] 00_1643
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] 01_1643
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] 00_1644
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] 01_1644
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] 00_1645
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] 01_1645
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] 00_1646
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] 01_1646
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] 00_1647
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] 01_1647
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] 00_1648
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] 01_1648
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] 00_1649
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] 01_1649
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] 00_1650
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] 01_1650
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] 00_1651
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] 01_1651
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] 00_1652
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] 01_1652
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] 00_1653
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] 01_1653
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] 00_1654
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] 01_1654
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] 00_1655
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] 01_1655
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] 00_1656
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] 01_1656
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] 00_1657
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] 01_1657
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] 00_1658
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] 01_1658
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] 00_1659
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] 01_1659
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] 00_1660
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] 01_1660
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] 00_1661
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] 01_1661
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] 00_1662
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[45] 01_1662
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[46] 00_1663
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[47] 01_1663
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[48] 00_1664
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[49] 01_1664
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[50] 00_1665
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[51] 01_1665
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[52] 00_1666
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[53] 01_1666
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[54] 00_1667
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[55] 01_1667
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[56] 00_1668
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[57] 01_1668
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[58] 00_1669
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[59] 01_1669
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[60] 00_1670
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[61] 01_1670
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[62] 00_1671
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[63] 01_1671
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[0] 00_1544
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[1] 01_1544
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[2] 00_1545
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[3] 01_1545
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[4] 00_1546
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[5] 01_1546
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[6] 00_1547
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[7] 01_1547
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[8] 00_1548
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[9] 01_1548
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[10] 00_1549
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[11] 01_1549
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[12] 00_1550
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[13] 01_1550
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[14] 00_1551
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[15] 01_1551
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[16] 00_1552
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[17] 01_1552
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[18] 00_1553
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[19] 01_1553
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[20] 00_1554
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[21] 01_1554
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[22] 00_1555
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[23] 01_1555
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[24] 00_1556
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[25] 01_1556
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[26] 00_1557
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[27] 01_1557
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[28] 00_1558
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[29] 01_1558
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[30] 00_1559
+GTP_COMMON_MID_LEFT.GTPE2.COMMON_CFG[31] 01_1559
+GTP_COMMON_MID_LEFT.GTPE2.IN_USE 00_1584
+GTP_COMMON_MID_LEFT.GTPE2.INV_GTGREFCLK0 01_1516
+GTP_COMMON_MID_LEFT.GTPE2.INV_GTGREFCLK1 00_1514
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563
+GTP_COMMON_MID_LEFT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[0] 00_1488
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[1] 01_1488
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[2] 00_1489
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[3] 01_1489
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[4] 00_1490
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[5] 01_1490
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[6] 00_1491
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[7] 01_1491
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[8] 00_1492
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[9] 01_1492
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[10] 00_1493
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[11] 01_1493
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[12] 00_1494
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[13] 01_1494
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[14] 00_1495
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR0[15] 01_1495
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[0] 00_1728
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[1] 01_1728
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[2] 00_1729
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[3] 01_1729
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[4] 00_1730
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[5] 01_1730
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[6] 00_1731
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[7] 01_1731
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[8] 00_1732
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[9] 01_1732
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[10] 00_1733
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[11] 01_1733
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[12] 00_1734
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[13] 01_1734
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[14] 00_1735
+GTP_COMMON_MID_LEFT.GTPE2.RSVD_ATTR1[15] 01_1735
+GTP_COMMON_MID_LEFT.GTPE2.ZINV_DRPCLK 00_1516
+GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512
+GTP_COMMON_MID_LEFT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[0] 00_1424
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[1] 01_1424
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[2] 00_1425
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[3] 01_1425
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[4] 00_1426
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[5] 01_1426
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[6] 00_1427
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[7] 01_1427
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[8] 00_1428
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[9] 01_1428
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[10] 00_1429
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[11] 01_1429
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[12] 00_1430
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[13] 01_1430
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[14] 00_1431
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[15] 01_1431
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[16] 00_1432
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[17] 01_1432
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[18] 00_1433
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[19] 01_1433
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[20] 00_1434
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[21] 01_1434
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[22] 00_1435
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[23] 01_1435
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[24] 00_1436
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[25] 01_1436
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_CFG[26] 00_1437
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_DMON_CFG[0] 00_1528
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[0] 00_1440
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[1] 01_1440
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV[4] 00_1442
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_FBDIV_45[0] 01_1443
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[0] 00_1456
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[1] 01_1456
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[2] 00_1457
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[3] 01_1457
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[4] 00_1458
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[5] 01_1458
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[6] 00_1459
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[7] 01_1459
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[8] 00_1460
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[9] 01_1460
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[10] 00_1461
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[11] 01_1461
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[12] 00_1462
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[13] 01_1462
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[14] 00_1463
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[15] 01_1463
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[16] 00_1464
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[17] 01_1464
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[18] 00_1465
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[19] 01_1465
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[20] 00_1466
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[21] 01_1466
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[22] 00_1467
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_INIT_CFG[23] 01_1467
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[0] 00_1448
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[1] 01_1448
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[2] 00_1449
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[3] 01_1449
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[4] 00_1450
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[5] 01_1450
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[6] 00_1451
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[7] 01_1451
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_LOCK_CFG[8] 00_1452
+GTP_COMMON_MID_LEFT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[0] 00_1792
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[1] 01_1792
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[2] 00_1793
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[3] 01_1793
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[4] 00_1794
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[5] 01_1794
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[6] 00_1795
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[7] 01_1795
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[8] 00_1796
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[9] 01_1796
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[10] 00_1797
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[11] 01_1797
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[12] 00_1798
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[13] 01_1798
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[14] 00_1799
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[15] 01_1799
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[16] 00_1800
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[17] 01_1800
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[18] 00_1801
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[19] 01_1801
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[20] 00_1802
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[21] 01_1802
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[22] 00_1803
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[23] 01_1803
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[24] 00_1804
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[25] 01_1804
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_CFG[26] 00_1805
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_DMON_CFG[0] 01_1528
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[0] 00_1784
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[1] 01_1784
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV[4] 00_1786
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_FBDIV_45[0] 01_1787
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[0] 00_1760
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[1] 01_1760
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[2] 00_1761
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[3] 01_1761
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[4] 00_1762
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[5] 01_1762
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] 00_1763
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] 01_1763
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] 00_1764
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] 01_1764
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] 00_1765
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] 01_1765
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] 00_1766
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] 01_1766
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] 00_1767
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] 01_1767
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] 00_1768
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] 01_1768
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] 00_1769
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] 01_1769
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] 00_1770
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] 01_1770
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] 00_1771
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] 01_1771
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] 00_1776
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] 01_1776
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] 00_1777
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] 01_1777
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] 00_1778
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] 01_1778
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] 00_1779
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] 01_1779
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] 00_1780
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790
--- a/artix7/segbits_gtp_common_mid_left.origin_info.db
+++ b/artix7/segbits_gtp_common_mid_left.origin_info.db
@ -0,0 +1,282 @@
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKCM_CFG origin:063-gtp-common-conf 01_1580
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_1576
+GTP_COMMON_MID_LEFT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
+GTP_COMMON_MID_LEFT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
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+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
+GTP_COMMON_MID_LEFT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790
--- a/artix7/segbits_gtp_common_mid_right.db
+++ b/artix7/segbits_gtp_common_mid_right.db
@ -0,0 +1,282 @@
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] 01_1581
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] 00_1582
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG 00_1580
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST 00_1576
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE 00_1578
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKCM_CFG 01_1580
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST 01_1576
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE 00_1579
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] 00_1640
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] 01_1640
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] 00_1641
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] 01_1641
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] 00_1642
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] 01_1642
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] 00_1643
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] 01_1643
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] 00_1644
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] 01_1644
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] 00_1645
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] 01_1645
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] 00_1646
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] 01_1646
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] 00_1647
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] 01_1647
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] 00_1648
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] 01_1648
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] 00_1649
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] 01_1649
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] 00_1650
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] 01_1650
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] 00_1651
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] 01_1651
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] 00_1652
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] 01_1652
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] 00_1653
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] 01_1653
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] 00_1654
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] 01_1654
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] 00_1655
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] 01_1655
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] 00_1656
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] 01_1656
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] 00_1657
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] 01_1657
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] 00_1658
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] 01_1658
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] 00_1659
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] 01_1659
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] 00_1660
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] 01_1660
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] 00_1661
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] 01_1661
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] 00_1662
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] 01_1662
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] 00_1663
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] 01_1663
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] 00_1664
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] 01_1664
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] 00_1665
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] 01_1665
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] 00_1666
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] 01_1666
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] 00_1667
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] 01_1667
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] 00_1668
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] 01_1668
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] 00_1669
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] 01_1669
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] 00_1670
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] 01_1670
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] 00_1671
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] 01_1671
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] 00_1544
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] 01_1544
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] 00_1545
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] 01_1545
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] 00_1546
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] 01_1546
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] 00_1547
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] 01_1547
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] 00_1548
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] 01_1548
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] 00_1549
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] 01_1549
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] 00_1550
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] 01_1550
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] 00_1551
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] 01_1551
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] 00_1552
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] 01_1552
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] 00_1553
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] 01_1553
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] 00_1554
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] 01_1554
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] 00_1555
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] 01_1555
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] 00_1556
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] 01_1556
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] 00_1557
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] 01_1557
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] 00_1558
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] 01_1558
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] 00_1559
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] 01_1559
+GTP_COMMON_MID_RIGHT.GTPE2.IN_USE 00_1584
+GTP_COMMON_MID_RIGHT.GTPE2.INV_GTGREFCLK0 01_1516
+GTP_COMMON_MID_RIGHT.GTPE2.INV_GTGREFCLK1 00_1514
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] 00_1560
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] 01_1560
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] 00_1561
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] 01_1561
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] 00_1562
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] 01_1562
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] 00_1563
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] 01_1563
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] 00_1488
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] 01_1488
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] 00_1489
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] 01_1489
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] 00_1490
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] 01_1490
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] 00_1491
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] 01_1491
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] 00_1492
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] 01_1492
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] 00_1493
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] 01_1493
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] 00_1494
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] 01_1494
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] 00_1495
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] 01_1495
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] 00_1728
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] 01_1728
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] 00_1729
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] 01_1729
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] 00_1730
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] 01_1730
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] 00_1731
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] 01_1731
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] 00_1732
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] 01_1732
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] 00_1733
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] 01_1733
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] 00_1734
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] 01_1734
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] 00_1735
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] 01_1735
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK 00_1516
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK 01_1512
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK 00_1512
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] 00_1424
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] 01_1424
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] 00_1425
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] 01_1425
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] 00_1426
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] 01_1426
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] 00_1427
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] 01_1427
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] 00_1428
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] 01_1428
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] 00_1429
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] 01_1429
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] 00_1430
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] 01_1430
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] 00_1431
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] 01_1431
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] 00_1432
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] 01_1432
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] 00_1433
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] 01_1433
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] 00_1434
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] 01_1434
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] 00_1435
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] 01_1435
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] 00_1436
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] 01_1436
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] 00_1437
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] 00_1528
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] 00_1440
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] 01_1440
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] 00_1442
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] 01_1443
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] 00_1456
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] 01_1456
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] 00_1457
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] 01_1457
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] 00_1458
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] 01_1458
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] 00_1459
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] 01_1459
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] 00_1460
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] 01_1460
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] 00_1461
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] 01_1461
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] 00_1462
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] 01_1462
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] 00_1463
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] 01_1463
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] 00_1464
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] 01_1464
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] 00_1465
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] 01_1465
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] 00_1466
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] 01_1466
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] 00_1467
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] 01_1467
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] 00_1448
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] 01_1448
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] 00_1449
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] 01_1449
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] 00_1450
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] 01_1450
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] 00_1451
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] 01_1451
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] 00_1452
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] 01_1446
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] 00_1792
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] 01_1792
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] 00_1793
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] 01_1793
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] 00_1794
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] 01_1794
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] 00_1795
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] 01_1795
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] 00_1796
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] 01_1796
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] 00_1797
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] 01_1797
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] 00_1798
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] 01_1798
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] 00_1799
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] 01_1799
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] 00_1800
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] 01_1800
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] 00_1801
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] 01_1801
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] 00_1802
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] 01_1802
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] 00_1803
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] 01_1803
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] 00_1804
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] 01_1804
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] 00_1805
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] 01_1528
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] 00_1784
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] 01_1784
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] 00_1786
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] 01_1787
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] 00_1760
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] 01_1760
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] 00_1761
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] 01_1761
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] 00_1762
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] 01_1762
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] 00_1763
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] 01_1763
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] 00_1764
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] 01_1764
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] 00_1765
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] 01_1765
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] 00_1766
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] 01_1766
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] 00_1767
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] 01_1767
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] 00_1768
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] 01_1768
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] 00_1769
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] 01_1769
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] 00_1770
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] 01_1770
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] 00_1771
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] 01_1771
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] 00_1776
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] 01_1776
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] 00_1777
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] 01_1777
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] 00_1778
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] 01_1778
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] 00_1779
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] 01_1779
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] 00_1780
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] 01_1790
--- a/artix7/segbits_gtp_common_mid_right.origin_info.db
+++ b/artix7/segbits_gtp_common_mid_right.origin_info.db
@ -0,0 +1,282 @@
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[0] origin:063-gtp-common-conf 01_1581
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2.CLKCM_CFG[1] origin:063-gtp-common-conf 00_1582
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKCM_CFG origin:063-gtp-common-conf 00_1580
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.CLKRCV_TRST origin:063-gtp-common-conf 00_1576
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y0.IN_USE origin:063-gtp-common-conf 00_1578
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKCM_CFG origin:063-gtp-common-conf 01_1580
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.CLKRCV_TRST origin:063-gtp-common-conf 01_1576
+GTP_COMMON_MID_RIGHT.IBUFDS_GTE2_Y1.IN_USE origin:063-gtp-common-conf 00_1579
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[0] origin:063-gtp-common-conf 00_1640
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[1] origin:063-gtp-common-conf 01_1640
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[2] origin:063-gtp-common-conf 00_1641
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[3] origin:063-gtp-common-conf 01_1641
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[4] origin:063-gtp-common-conf 00_1642
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[5] origin:063-gtp-common-conf 01_1642
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[6] origin:063-gtp-common-conf 00_1643
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[7] origin:063-gtp-common-conf 01_1643
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[8] origin:063-gtp-common-conf 00_1644
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[9] origin:063-gtp-common-conf 01_1644
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[10] origin:063-gtp-common-conf 00_1645
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[11] origin:063-gtp-common-conf 01_1645
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[12] origin:063-gtp-common-conf 00_1646
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[13] origin:063-gtp-common-conf 01_1646
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[14] origin:063-gtp-common-conf 00_1647
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[15] origin:063-gtp-common-conf 01_1647
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[16] origin:063-gtp-common-conf 00_1648
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[17] origin:063-gtp-common-conf 01_1648
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[18] origin:063-gtp-common-conf 00_1649
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[19] origin:063-gtp-common-conf 01_1649
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[20] origin:063-gtp-common-conf 00_1650
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[21] origin:063-gtp-common-conf 01_1650
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[22] origin:063-gtp-common-conf 00_1651
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[23] origin:063-gtp-common-conf 01_1651
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[24] origin:063-gtp-common-conf 00_1652
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[25] origin:063-gtp-common-conf 01_1652
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[26] origin:063-gtp-common-conf 00_1653
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[27] origin:063-gtp-common-conf 01_1653
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[28] origin:063-gtp-common-conf 00_1654
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[29] origin:063-gtp-common-conf 01_1654
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[30] origin:063-gtp-common-conf 00_1655
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[31] origin:063-gtp-common-conf 01_1655
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[32] origin:063-gtp-common-conf 00_1656
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[33] origin:063-gtp-common-conf 01_1656
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[34] origin:063-gtp-common-conf 00_1657
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[35] origin:063-gtp-common-conf 01_1657
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[36] origin:063-gtp-common-conf 00_1658
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[37] origin:063-gtp-common-conf 01_1658
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[38] origin:063-gtp-common-conf 00_1659
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[39] origin:063-gtp-common-conf 01_1659
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[40] origin:063-gtp-common-conf 00_1660
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[41] origin:063-gtp-common-conf 01_1660
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[42] origin:063-gtp-common-conf 00_1661
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[43] origin:063-gtp-common-conf 01_1661
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[44] origin:063-gtp-common-conf 00_1662
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[45] origin:063-gtp-common-conf 01_1662
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[46] origin:063-gtp-common-conf 00_1663
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[47] origin:063-gtp-common-conf 01_1663
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[48] origin:063-gtp-common-conf 00_1664
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[49] origin:063-gtp-common-conf 01_1664
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[50] origin:063-gtp-common-conf 00_1665
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[51] origin:063-gtp-common-conf 01_1665
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[52] origin:063-gtp-common-conf 00_1666
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[53] origin:063-gtp-common-conf 01_1666
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[54] origin:063-gtp-common-conf 00_1667
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[55] origin:063-gtp-common-conf 01_1667
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[56] origin:063-gtp-common-conf 00_1668
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[57] origin:063-gtp-common-conf 01_1668
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[58] origin:063-gtp-common-conf 00_1669
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[59] origin:063-gtp-common-conf 01_1669
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[60] origin:063-gtp-common-conf 00_1670
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[61] origin:063-gtp-common-conf 01_1670
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[62] origin:063-gtp-common-conf 00_1671
+GTP_COMMON_MID_RIGHT.GTPE2.BIAS_CFG[63] origin:063-gtp-common-conf 01_1671
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[0] origin:063-gtp-common-conf 00_1544
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[1] origin:063-gtp-common-conf 01_1544
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[2] origin:063-gtp-common-conf 00_1545
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[3] origin:063-gtp-common-conf 01_1545
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[4] origin:063-gtp-common-conf 00_1546
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[5] origin:063-gtp-common-conf 01_1546
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[6] origin:063-gtp-common-conf 00_1547
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[7] origin:063-gtp-common-conf 01_1547
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[8] origin:063-gtp-common-conf 00_1548
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[9] origin:063-gtp-common-conf 01_1548
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[10] origin:063-gtp-common-conf 00_1549
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[11] origin:063-gtp-common-conf 01_1549
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[12] origin:063-gtp-common-conf 00_1550
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[13] origin:063-gtp-common-conf 01_1550
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[14] origin:063-gtp-common-conf 00_1551
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[15] origin:063-gtp-common-conf 01_1551
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[16] origin:063-gtp-common-conf 00_1552
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[17] origin:063-gtp-common-conf 01_1552
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[18] origin:063-gtp-common-conf 00_1553
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[19] origin:063-gtp-common-conf 01_1553
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[20] origin:063-gtp-common-conf 00_1554
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[21] origin:063-gtp-common-conf 01_1554
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[22] origin:063-gtp-common-conf 00_1555
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[23] origin:063-gtp-common-conf 01_1555
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[24] origin:063-gtp-common-conf 00_1556
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[25] origin:063-gtp-common-conf 01_1556
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[26] origin:063-gtp-common-conf 00_1557
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[27] origin:063-gtp-common-conf 01_1557
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[28] origin:063-gtp-common-conf 00_1558
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[29] origin:063-gtp-common-conf 01_1558
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[30] origin:063-gtp-common-conf 00_1559
+GTP_COMMON_MID_RIGHT.GTPE2.COMMON_CFG[31] origin:063-gtp-common-conf 01_1559
+GTP_COMMON_MID_RIGHT.GTPE2.IN_USE origin:063-gtp-common-conf 00_1584
+GTP_COMMON_MID_RIGHT.GTPE2.INV_GTGREFCLK0 origin:063-gtp-common-conf 01_1516
+GTP_COMMON_MID_RIGHT.GTPE2.INV_GTGREFCLK1 origin:063-gtp-common-conf 00_1514
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[0] origin:063-gtp-common-conf 00_1560
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[1] origin:063-gtp-common-conf 01_1560
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[2] origin:063-gtp-common-conf 00_1561
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[3] origin:063-gtp-common-conf 01_1561
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[4] origin:063-gtp-common-conf 00_1562
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[5] origin:063-gtp-common-conf 01_1562
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[6] origin:063-gtp-common-conf 00_1563
+GTP_COMMON_MID_RIGHT.GTPE2.PLL_CLKOUT_CFG[7] origin:063-gtp-common-conf 01_1563
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[0] origin:063-gtp-common-conf 00_1488
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[1] origin:063-gtp-common-conf 01_1488
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[2] origin:063-gtp-common-conf 00_1489
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[3] origin:063-gtp-common-conf 01_1489
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[4] origin:063-gtp-common-conf 00_1490
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[5] origin:063-gtp-common-conf 01_1490
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[6] origin:063-gtp-common-conf 00_1491
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[7] origin:063-gtp-common-conf 01_1491
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[8] origin:063-gtp-common-conf 00_1492
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[9] origin:063-gtp-common-conf 01_1492
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[10] origin:063-gtp-common-conf 00_1493
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[11] origin:063-gtp-common-conf 01_1493
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[12] origin:063-gtp-common-conf 00_1494
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[13] origin:063-gtp-common-conf 01_1494
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[14] origin:063-gtp-common-conf 00_1495
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR0[15] origin:063-gtp-common-conf 01_1495
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[0] origin:063-gtp-common-conf 00_1728
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[1] origin:063-gtp-common-conf 01_1728
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[2] origin:063-gtp-common-conf 00_1729
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[3] origin:063-gtp-common-conf 01_1729
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[4] origin:063-gtp-common-conf 00_1730
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[5] origin:063-gtp-common-conf 01_1730
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[6] origin:063-gtp-common-conf 00_1731
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[7] origin:063-gtp-common-conf 01_1731
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[8] origin:063-gtp-common-conf 00_1732
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[9] origin:063-gtp-common-conf 01_1732
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[10] origin:063-gtp-common-conf 00_1733
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[11] origin:063-gtp-common-conf 01_1733
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[12] origin:063-gtp-common-conf 00_1734
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[13] origin:063-gtp-common-conf 01_1734
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[14] origin:063-gtp-common-conf 00_1735
+GTP_COMMON_MID_RIGHT.GTPE2.RSVD_ATTR1[15] origin:063-gtp-common-conf 01_1735
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_DRPCLK origin:063-gtp-common-conf 00_1516
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL0LOCKDETCLK origin:063-gtp-common-conf 01_1512
+GTP_COMMON_MID_RIGHT.GTPE2.ZINV_PLL1LOCKDETCLK origin:063-gtp-common-conf 00_1512
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[0] origin:063-gtp-common-conf 00_1424
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[1] origin:063-gtp-common-conf 01_1424
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[2] origin:063-gtp-common-conf 00_1425
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[3] origin:063-gtp-common-conf 01_1425
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[4] origin:063-gtp-common-conf 00_1426
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[5] origin:063-gtp-common-conf 01_1426
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[6] origin:063-gtp-common-conf 00_1427
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[7] origin:063-gtp-common-conf 01_1427
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[8] origin:063-gtp-common-conf 00_1428
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[9] origin:063-gtp-common-conf 01_1428
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[10] origin:063-gtp-common-conf 00_1429
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[11] origin:063-gtp-common-conf 01_1429
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[12] origin:063-gtp-common-conf 00_1430
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[13] origin:063-gtp-common-conf 01_1430
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[14] origin:063-gtp-common-conf 00_1431
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[15] origin:063-gtp-common-conf 01_1431
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[16] origin:063-gtp-common-conf 00_1432
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[17] origin:063-gtp-common-conf 01_1432
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[18] origin:063-gtp-common-conf 00_1433
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[19] origin:063-gtp-common-conf 01_1433
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[20] origin:063-gtp-common-conf 00_1434
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[21] origin:063-gtp-common-conf 01_1434
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[22] origin:063-gtp-common-conf 00_1435
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[23] origin:063-gtp-common-conf 01_1435
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[24] origin:063-gtp-common-conf 00_1436
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[25] origin:063-gtp-common-conf 01_1436
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_CFG[26] origin:063-gtp-common-conf 00_1437
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_DMON_CFG[0] origin:063-gtp-common-conf 00_1528
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[0] origin:063-gtp-common-conf 00_1440
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[1] origin:063-gtp-common-conf 01_1440
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV[4] origin:063-gtp-common-conf 00_1442
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_FBDIV_45[0] origin:063-gtp-common-conf 01_1443
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[0] origin:063-gtp-common-conf 00_1456
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[1] origin:063-gtp-common-conf 01_1456
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[2] origin:063-gtp-common-conf 00_1457
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[3] origin:063-gtp-common-conf 01_1457
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[4] origin:063-gtp-common-conf 00_1458
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[5] origin:063-gtp-common-conf 01_1458
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[6] origin:063-gtp-common-conf 00_1459
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[7] origin:063-gtp-common-conf 01_1459
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[8] origin:063-gtp-common-conf 00_1460
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[9] origin:063-gtp-common-conf 01_1460
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[10] origin:063-gtp-common-conf 00_1461
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[11] origin:063-gtp-common-conf 01_1461
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[12] origin:063-gtp-common-conf 00_1462
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[13] origin:063-gtp-common-conf 01_1462
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[14] origin:063-gtp-common-conf 00_1463
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[15] origin:063-gtp-common-conf 01_1463
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[16] origin:063-gtp-common-conf 00_1464
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[17] origin:063-gtp-common-conf 01_1464
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[18] origin:063-gtp-common-conf 00_1465
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[19] origin:063-gtp-common-conf 01_1465
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[20] origin:063-gtp-common-conf 00_1466
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[21] origin:063-gtp-common-conf 01_1466
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[22] origin:063-gtp-common-conf 00_1467
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_INIT_CFG[23] origin:063-gtp-common-conf 01_1467
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[0] origin:063-gtp-common-conf 00_1448
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[1] origin:063-gtp-common-conf 01_1448
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[2] origin:063-gtp-common-conf 00_1449
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[3] origin:063-gtp-common-conf 01_1449
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[4] origin:063-gtp-common-conf 00_1450
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[5] origin:063-gtp-common-conf 01_1450
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[6] origin:063-gtp-common-conf 00_1451
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[7] origin:063-gtp-common-conf 01_1451
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_LOCK_CFG[8] origin:063-gtp-common-conf 00_1452
+GTP_COMMON_MID_RIGHT.GTPE2.PLL0_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1446
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[0] origin:063-gtp-common-conf 00_1792
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[1] origin:063-gtp-common-conf 01_1792
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[2] origin:063-gtp-common-conf 00_1793
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[3] origin:063-gtp-common-conf 01_1793
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[4] origin:063-gtp-common-conf 00_1794
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[5] origin:063-gtp-common-conf 01_1794
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[6] origin:063-gtp-common-conf 00_1795
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[7] origin:063-gtp-common-conf 01_1795
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[8] origin:063-gtp-common-conf 00_1796
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[9] origin:063-gtp-common-conf 01_1796
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[10] origin:063-gtp-common-conf 00_1797
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[11] origin:063-gtp-common-conf 01_1797
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[12] origin:063-gtp-common-conf 00_1798
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[13] origin:063-gtp-common-conf 01_1798
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[14] origin:063-gtp-common-conf 00_1799
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[15] origin:063-gtp-common-conf 01_1799
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[16] origin:063-gtp-common-conf 00_1800
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[17] origin:063-gtp-common-conf 01_1800
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[18] origin:063-gtp-common-conf 00_1801
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[19] origin:063-gtp-common-conf 01_1801
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[20] origin:063-gtp-common-conf 00_1802
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[21] origin:063-gtp-common-conf 01_1802
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[22] origin:063-gtp-common-conf 00_1803
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[23] origin:063-gtp-common-conf 01_1803
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[24] origin:063-gtp-common-conf 00_1804
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[25] origin:063-gtp-common-conf 01_1804
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_CFG[26] origin:063-gtp-common-conf 00_1805
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_DMON_CFG[0] origin:063-gtp-common-conf 01_1528
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[0] origin:063-gtp-common-conf 00_1784
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[1] origin:063-gtp-common-conf 01_1784
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV[4] origin:063-gtp-common-conf 00_1786
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_FBDIV_45[0] origin:063-gtp-common-conf 01_1787
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[0] origin:063-gtp-common-conf 00_1760
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[1] origin:063-gtp-common-conf 01_1760
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[2] origin:063-gtp-common-conf 00_1761
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[3] origin:063-gtp-common-conf 01_1761
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[4] origin:063-gtp-common-conf 00_1762
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[5] origin:063-gtp-common-conf 01_1762
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[6] origin:063-gtp-common-conf 00_1763
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[7] origin:063-gtp-common-conf 01_1763
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[8] origin:063-gtp-common-conf 00_1764
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[9] origin:063-gtp-common-conf 01_1764
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[10] origin:063-gtp-common-conf 00_1765
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[11] origin:063-gtp-common-conf 01_1765
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[12] origin:063-gtp-common-conf 00_1766
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[13] origin:063-gtp-common-conf 01_1766
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[14] origin:063-gtp-common-conf 00_1767
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[15] origin:063-gtp-common-conf 01_1767
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[16] origin:063-gtp-common-conf 00_1768
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[17] origin:063-gtp-common-conf 01_1768
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[18] origin:063-gtp-common-conf 00_1769
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[19] origin:063-gtp-common-conf 01_1769
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[20] origin:063-gtp-common-conf 00_1770
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[21] origin:063-gtp-common-conf 01_1770
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[22] origin:063-gtp-common-conf 00_1771
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_INIT_CFG[23] origin:063-gtp-common-conf 01_1771
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[0] origin:063-gtp-common-conf 00_1776
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[1] origin:063-gtp-common-conf 01_1776
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[2] origin:063-gtp-common-conf 00_1777
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[3] origin:063-gtp-common-conf 01_1777
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[4] origin:063-gtp-common-conf 00_1778
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[5] origin:063-gtp-common-conf 01_1778
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[6] origin:063-gtp-common-conf 00_1779
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[7] origin:063-gtp-common-conf 01_1779
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_LOCK_CFG[8] origin:063-gtp-common-conf 00_1780
+GTP_COMMON_MID_RIGHT.GTPE2.PLL1_REFCLK_DIV[4] origin:063-gtp-common-conf 01_1790
--- a/artix7/segbits_int_l.origin_info.db
+++ b/artix7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -301,7 +301,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00
 INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
 INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
 INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
 INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@ -1937,7 +1937,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@ -2253,7 +2253,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
 INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
 INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
 INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
+INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
 INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
 INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
 INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45
 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@ -3568,7 +3568,7 @@ INT_L.WW4BEG0.SW6END_N0_3 origin:050-pip-seed 04_01 05_00
 INT_L.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
 INT_L.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
 INT_L.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_L.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
+INT_L.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
 INT_L.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
 INT_L.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
 INT_L.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db
@ -2491,7 +2491,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
 INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
 INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
+INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS20 origin:050-pip-seed 04_34 06_32
 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
--- a/artix7/segbits_pcie_bot.db
+++ b/artix7/segbits_pcie_bot.db
--- a/artix7/segbits_pcie_bot.origin_info.db
+++ b/artix7/segbits_pcie_bot.origin_info.db
--- a/artix7/xc7a100t/tilegrid.json
+++ b/artix7/xc7a100t/tilegrid.json
@ -176433,7 +176433,14 @@
        "type": "DSP_R"
    },
    "GTP_CHANNEL_0_X130Y6": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00421980",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 130,
        "grid_y": 202,
@ -176454,7 +176461,14 @@
        "type": "GTP_CHANNEL_0"
    },
    "GTP_CHANNEL_0_X130Y162": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021980",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y3",
        "grid_x": 130,
        "grid_y": 46,
@ -176475,7 +176489,14 @@
        "type": "GTP_CHANNEL_0"
    },
    "GTP_CHANNEL_1_X130Y17": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00421980",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 130,
        "grid_y": 191,
@ -176496,7 +176517,14 @@
        "type": "GTP_CHANNEL_1"
    },
    "GTP_CHANNEL_1_X130Y173": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021980",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y3",
        "grid_x": 130,
        "grid_y": 35,
@ -176517,7 +176545,14 @@
        "type": "GTP_CHANNEL_1"
    },
    "GTP_CHANNEL_2_X130Y35": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00421980",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 130,
        "grid_y": 173,
@ -176538,7 +176573,14 @@
        "type": "GTP_CHANNEL_2"
    },
    "GTP_CHANNEL_2_X130Y191": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021980",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y3",
        "grid_x": 130,
        "grid_y": 17,
@ -176559,7 +176601,14 @@
        "type": "GTP_CHANNEL_2"
    },
    "GTP_CHANNEL_3_X130Y46": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00421980",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 130,
        "grid_y": 162,
@ -176580,7 +176629,14 @@
        "type": "GTP_CHANNEL_3"
    },
    "GTP_CHANNEL_3_X130Y202": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021980",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y3",
        "grid_x": 130,
        "grid_y": 6,
@ -176601,7 +176657,14 @@
        "type": "GTP_CHANNEL_3"
    },
    "GTP_COMMON_X130Y23": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00421980",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 130,
        "grid_y": 185,
@ -176624,7 +176687,14 @@
        "type": "GTP_COMMON"
    },
    "GTP_COMMON_X130Y179": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021980",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X1Y3",
        "grid_x": 130,
        "grid_y": 29,
--- a/artix7/xc7a200t/tilegrid.json
+++ b/artix7/xc7a200t/tilegrid.json
@ -381722,7 +381722,14 @@
        "type": "DSP_R"
    },
    "GTP_CHANNEL_0_MID_LEFT_X103Y6": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00441200",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y0",
        "grid_x": 103,
        "grid_y": 254,
@ -381743,7 +381750,14 @@
        "type": "GTP_CHANNEL_0_MID_LEFT"
    },
    "GTP_CHANNEL_0_MID_LEFT_X103Y214": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021200",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y4",
        "grid_x": 103,
        "grid_y": 46,
@ -381764,7 +381778,14 @@
        "type": "GTP_CHANNEL_0_MID_LEFT"
    },
    "GTP_CHANNEL_0_MID_RIGHT_X167Y6": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00442480",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 167,
        "grid_y": 254,
@ -381785,7 +381806,14 @@
        "type": "GTP_CHANNEL_0_MID_RIGHT"
    },
    "GTP_CHANNEL_0_MID_RIGHT_X167Y214": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00022480",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y4",
        "grid_x": 167,
        "grid_y": 46,
@ -381806,7 +381834,14 @@
        "type": "GTP_CHANNEL_0_MID_RIGHT"
    },
    "GTP_CHANNEL_1_MID_LEFT_X103Y17": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00441200",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y0",
        "grid_x": 103,
        "grid_y": 243,
@ -381827,7 +381862,14 @@
        "type": "GTP_CHANNEL_1_MID_LEFT"
    },
    "GTP_CHANNEL_1_MID_LEFT_X103Y225": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021200",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y4",
        "grid_x": 103,
        "grid_y": 35,
@ -381848,7 +381890,14 @@
        "type": "GTP_CHANNEL_1_MID_LEFT"
    },
    "GTP_CHANNEL_1_MID_RIGHT_X167Y17": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00442480",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 167,
        "grid_y": 243,
@ -381869,7 +381918,14 @@
        "type": "GTP_CHANNEL_1_MID_RIGHT"
    },
    "GTP_CHANNEL_1_MID_RIGHT_X167Y225": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00022480",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y4",
        "grid_x": 167,
        "grid_y": 35,
@ -381890,7 +381946,14 @@
        "type": "GTP_CHANNEL_1_MID_RIGHT"
    },
    "GTP_CHANNEL_2_MID_LEFT_X103Y35": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00441200",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y0",
        "grid_x": 103,
        "grid_y": 225,
@ -381911,7 +381974,14 @@
        "type": "GTP_CHANNEL_2_MID_LEFT"
    },
    "GTP_CHANNEL_2_MID_LEFT_X103Y243": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021200",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y4",
        "grid_x": 103,
        "grid_y": 17,
@ -381932,7 +382002,14 @@
        "type": "GTP_CHANNEL_2_MID_LEFT"
    },
    "GTP_CHANNEL_2_MID_RIGHT_X167Y35": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00442480",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 167,
        "grid_y": 225,
@ -381953,7 +382030,14 @@
        "type": "GTP_CHANNEL_2_MID_RIGHT"
    },
    "GTP_CHANNEL_2_MID_RIGHT_X167Y243": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00022480",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y4",
        "grid_x": 167,
        "grid_y": 17,
@ -381974,7 +382058,14 @@
        "type": "GTP_CHANNEL_2_MID_RIGHT"
    },
    "GTP_CHANNEL_3_MID_LEFT_X103Y46": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00441200",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y0",
        "grid_x": 103,
        "grid_y": 214,
@ -381995,7 +382086,14 @@
        "type": "GTP_CHANNEL_3_MID_LEFT"
    },
    "GTP_CHANNEL_3_MID_LEFT_X103Y254": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021200",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X0Y4",
        "grid_x": 103,
        "grid_y": 6,
@ -382016,7 +382114,14 @@
        "type": "GTP_CHANNEL_3_MID_LEFT"
    },
    "GTP_CHANNEL_3_MID_RIGHT_X167Y46": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00442480",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 167,
        "grid_y": 214,
@ -382037,7 +382142,14 @@
        "type": "GTP_CHANNEL_3_MID_RIGHT"
    },
    "GTP_CHANNEL_3_MID_RIGHT_X167Y254": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00022480",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y4",
        "grid_x": 167,
        "grid_y": 6,
@ -382058,7 +382170,14 @@
        "type": "GTP_CHANNEL_3_MID_RIGHT"
    },
    "GTP_COMMON_MID_LEFT_X103Y23": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00441200",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X0Y0",
        "grid_x": 103,
        "grid_y": 237,
@ -382081,7 +382200,14 @@
        "type": "GTP_COMMON_MID_LEFT"
    },
    "GTP_COMMON_MID_LEFT_X103Y231": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021200",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X0Y4",
        "grid_x": 103,
        "grid_y": 29,
@ -382104,7 +382230,14 @@
        "type": "GTP_COMMON_MID_LEFT"
    },
    "GTP_COMMON_MID_RIGHT_X167Y23": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00442480",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X1Y0",
        "grid_x": 167,
        "grid_y": 237,
@ -382127,7 +382260,14 @@
        "type": "GTP_COMMON_MID_RIGHT"
    },
    "GTP_COMMON_MID_RIGHT_X167Y231": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00022480",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X1Y4",
        "grid_x": 167,
        "grid_y": 29,
--- a/artix7/xc7a50t/tilegrid.json
+++ b/artix7/xc7a50t/tilegrid.json
@ -91749,7 +91749,14 @@
        "type": "DSP_R"
    },
    "GTP_CHANNEL_0_X97Y110": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021280",
+                "frames": 32,
+                "offset": 0,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y2",
        "grid_x": 97,
        "grid_y": 46,
@ -91770,7 +91777,14 @@
        "type": "GTP_CHANNEL_0"
    },
    "GTP_CHANNEL_1_X97Y121": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021280",
+                "frames": 32,
+                "offset": 22,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y2",
        "grid_x": 97,
        "grid_y": 35,
@ -91791,7 +91805,14 @@
        "type": "GTP_CHANNEL_1"
    },
    "GTP_CHANNEL_2_X97Y139": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021280",
+                "frames": 32,
+                "offset": 57,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y2",
        "grid_x": 97,
        "grid_y": 17,
@ -91812,7 +91833,14 @@
        "type": "GTP_CHANNEL_2"
    },
    "GTP_CHANNEL_3_X97Y150": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021280",
+                "frames": 32,
+                "offset": 79,
+                "words": 22
+            }
+        },
        "clock_region": "X1Y2",
        "grid_x": 97,
        "grid_y": 6,
@ -91833,7 +91861,14 @@
        "type": "GTP_CHANNEL_3"
    },
    "GTP_COMMON_X97Y127": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00021280",
+                "frames": 42,
+                "offset": 0,
+                "words": 101
+            }
+        },
        "clock_region": "X1Y2",
        "grid_x": 97,
        "grid_y": 29,
--- a/kintex7/segbits_int_l.origin_info.db
+++ b/kintex7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -2273,7 +2273,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@ -3345,7 +3345,7 @@ INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
 INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
 INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32
 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
@ -3623,7 +3623,7 @@ INT_L.WW4BEG3.LOGIC_OUTS_L21 origin:050-pip-seed 06_48 07_49
 INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49
 INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
 INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
 INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
 INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
 INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
--- a/kintex7/segbits_int_r.origin_info.db
+++ b/kintex7/segbits_int_r.origin_info.db
@ -329,7 +329,7 @@ INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@ -2273,7 +2273,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS21 origin:050-pip-seed 06_48 07_49
 INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
 INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
 INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
+INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
 INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
 INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
 INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db
@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -392,7 +392,7 @@ INT_L.FAN_ALT3.WR1END3 origin:050-pip-seed !23_56 16_56 22_56 24_56 25_56
 INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_L.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
@ -1937,7 +1937,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db
@ -328,11 +328,11 @@ INT_R.FAN_ALT3.WR1END3 origin:050-pip-seed !23_56 16_56 22_56 24_56 25_56
 INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_R.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
 INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
 INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
 INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@ -2471,7 +2471,7 @@ INT_R.NN6BEG2.NN6END2 origin:050-pip-seed 02_38 07_39
 INT_R.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
 INT_R.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
 INT_R.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_R.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
+INT_R.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
 INT_R.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
 INT_R.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
 INT_R.NN6BEG3.LOGIC_OUTS3 origin:050-pip-seed 03_54 06_54
@ -3321,7 +3321,7 @@ INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
+INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
@ -3568,7 +3568,7 @@ INT_R.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
 INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
 INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
 INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
+INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
 INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
 INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
 INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01