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artix7: Updating the harnesses. 

* Arty-A7
   - pmod
   - swbut
   - uart
 * Basys3
   - swbut

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-03-26 18:15:47 -07:00
parent 8ad991a195
commit e6837b7336
15 changed files with 2883 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Tue Mar 26 20:43:13 UTC 2019 (2019-03-26T20:43:13+00:00).
Last updated on Wed Mar 27 01:22:23 UTC 2019 (2019-03-27T01:22:23+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [c7d7e9d](https://github.com/SymbiFlow/prjxray/commit/c7d7e9d7ade70bd47f969f9713d9a6e4defbd53a).
@ -97,21 +97,21 @@ Results have checksums;
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
* [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
* [`0c0db34e2b1a0f38b05799ad7e042874d43443d79426e9f32f0b63c71a8c9d3d ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
* [`0df8a22d29a4425ee1da4363b8cdb56c82c1ab71913fbe36b4470b3ebc082c60 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`7f92af7280a5e8563dd764c52356e2f914a20b5d413ff1441c546da6101df21c ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
* [`78616f1443dcacb0af37f78ba507c81f0a6115770e538430d5c7382aa48edd6a ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
* [`8df57ddc871785ba1710beb4a14c6ceed706cfb48bfbc425182f2a96742fdd13 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`b270ca64ce9a15a0a2cde99523bab6e7ba748fbca804dd600ccb2c21a4224c85 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
* [`134f6438b4dbbd511c823e80548970359e9468b2509e6614732ef2d591613c53 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`39236ffb06698077ee3f06edd6d64c0167793cefab4acda71f219a5cf3a20f76 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
* [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
* [`5e4504596aaca26baf85309f7e223a9e45af410971af8c21b375f8151e9e6a53 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
* [`6c20fcdb578030f58da1082539828d2785065a598f8ca9c2d14b49d3a6ebe834 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`63af3a7ba401751dc4b03cd2db38d5a4c6d20279117307138fee3fcb92ab1119 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`7d2429e6bcedecaf6f0db4f2f04860b5b6dc4b036495815a70edc4a036361310 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`e492a4c97f0d0a10cd07e0badb0b81f084e2d1a88ba06ab5b705e90ef6003076 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
* [`e2dbcf498c7efe26d6a4ab14733bf3acfe51798bc1d2cd7f4e0e77fc95f40225 ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
* [`62586079b9ffd917ff5a5d4edcae802b161a7ed4f6af1c776731dcd10c87d096 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
* [`3e70378bc05fe32951fed4816f634ff35e5f1511d992ebf8e6718d6d8a65943f ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`2e19b7f8aaaf6fd6e891fa16ceb351eaf659202ef512598ec8f518c57d6ab484 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`4f590875a7851c6d036ab171421b12100f517af74229ad47d8e21fdb6e09b09e ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`0e48014931ae9a6010d6023b2a6e07e13ecf206be1076197b881161e67ced596 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`9bc42fedabb2f8ca69d0431b5e9c22f20c09b8fa5313dd252d0c32c32b6ad80b ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
* [`30b4cfe8b60ccde4423a0bd0d7ad5242bea58d54abf5d15601dd3f390465e821 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)

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@ -1,18 +1,18 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 G13 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
din[0] INT_R_X9Y102/NE2BEG3 E15 VBRK_X29Y108/VBRK_NE2A3
din[1] INT_R_X9Y105/NE2BEG3 E16 VBRK_X29Y111/VBRK_NE2A3
din[2] INT_R_X9Y108/NE2BEG3 D15 VBRK_X29Y114/VBRK_NE2A3
din[3] INT_R_X9Y111/NE2BEG3 C15 VBRK_X29Y117/VBRK_NE2A3
din[4] INT_R_X9Y114/NE2BEG3 J17 VBRK_X29Y120/VBRK_NE2A3
din[5] INT_R_X9Y117/NE2BEG3 J18 VBRK_X29Y123/VBRK_NE2A3
din[6] INT_R_X9Y120/NE2BEG3 K15 VBRK_X29Y126/VBRK_NE2A3
din[7] INT_R_X9Y123/NE2BEG3 J15 VBRK_X29Y129/VBRK_NE2A3
dout[0] INT_L_X10Y125/SW6BEG0 U12 VBRK_X29Y131/VBRK_SW4A0
dout[1] INT_L_X10Y128/SW6BEG0 V12 VBRK_X29Y134/VBRK_SW4A0
dout[2] INT_L_X10Y131/SW6BEG0 V10 VBRK_X29Y137/VBRK_SW4A0
dout[3] INT_L_X10Y134/SW6BEG0 V11 VBRK_X29Y140/VBRK_SW4A0
dout[4] INT_L_X10Y137/SW6BEG0 U14 VBRK_X29Y143/VBRK_SW4A0
dout[5] INT_L_X10Y140/SW6BEG0 V14 VBRK_X29Y146/VBRK_SW4A0
dout[6] INT_L_X10Y143/SW6BEG0 T13 VBRK_X29Y149/VBRK_SW4A0
dout[7] INT_L_X10Y146/SW6BEG0 U13 VBRK_X29Y152/VBRK_SW4A0
din[0] INT_L_X0Y102/EE2BEG2 E15 VBRK_X9Y107/VBRK_EE2A2
din[1] INT_L_X0Y104/EE2BEG2 E16 VBRK_X9Y109/VBRK_EE2A2
din[2] INT_L_X0Y106/EE2BEG2 D15 VBRK_X9Y111/VBRK_EE2A2
din[3] INT_L_X0Y108/EE2BEG2 C15 VBRK_X9Y113/VBRK_EE2A2
din[4] INT_L_X0Y110/EE2BEG2 J17 VBRK_X9Y115/VBRK_EE2A2
din[5] INT_L_X0Y112/EE2BEG2 J18 VBRK_X9Y117/VBRK_EE2A2
din[6] INT_L_X0Y114/EE2BEG2 K15 VBRK_X9Y119/VBRK_EE2A2
din[7] INT_L_X0Y116/EE2BEG2 J15 VBRK_X9Y121/VBRK_EE2A2
dout[0] INT_L_X2Y133/SW6BEG0 U12 VBRK_X9Y139/VBRK_SW4A0
dout[1] INT_L_X2Y135/SW6BEG0 V12 VBRK_X9Y141/VBRK_SW4A0
dout[2] INT_L_X2Y137/SW6BEG0 V10 VBRK_X9Y143/VBRK_SW4A0
dout[3] INT_L_X2Y139/SW6BEG0 V11 VBRK_X9Y145/VBRK_SW4A0
dout[4] INT_L_X2Y141/SW6BEG0 U14 VBRK_X9Y147/VBRK_SW4A0
dout[5] INT_L_X2Y143/SW6BEG0 V14 VBRK_X9Y149/VBRK_SW4A0
dout[6] INT_L_X2Y145/SW6BEG0 T13 VBRK_X9Y151/VBRK_SW4A0
dout[7] INT_L_X2Y147/SW6BEG0 U13 VBRK_X9Y153/VBRK_SW4A0

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@ -1,18 +1,18 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 E3 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
din[0] INT_R_X9Y102/NE2BEG3 A8 VBRK_X29Y108/VBRK_NE2A3
din[1] INT_R_X9Y105/NE2BEG3 C11 VBRK_X29Y111/VBRK_NE2A3
din[2] INT_R_X9Y108/NE2BEG3 C10 VBRK_X29Y114/VBRK_NE2A3
din[3] INT_R_X9Y111/NE2BEG3 A10 VBRK_X29Y117/VBRK_NE2A3
din[4] INT_R_X9Y114/NE2BEG3 D9 VBRK_X29Y120/VBRK_NE2A3
din[5] INT_R_X9Y117/NE2BEG3 C9 VBRK_X29Y123/VBRK_NE2A3
din[6] INT_R_X9Y120/NE2BEG3 B9 VBRK_X29Y126/VBRK_NE2A3
din[7] INT_R_X9Y123/NE2BEG3 B8 VBRK_X29Y129/VBRK_NE2A3
dout[0] INT_R_X17Y125/SE6BEG0 H5
dout[1] INT_R_X17Y128/SE6BEG0 J5
dout[2] INT_L_X10Y131/SW6BEG0 T9 VBRK_X29Y137/VBRK_SW4A0
dout[3] INT_L_X10Y134/SW6BEG0 T10 VBRK_X29Y140/VBRK_SW4A0
dout[4] INT_R_X17Y137/SE6BEG0 F6
dout[5] INT_R_X17Y140/SE6BEG0 J4
dout[6] INT_R_X17Y143/SE6BEG0 J2
dout[7] INT_R_X17Y146/SE6BEG0 H6
din[0] INT_L_X0Y102/EE2BEG2 A8 VBRK_X9Y107/VBRK_EE2A2
din[1] INT_L_X0Y104/EE2BEG2 C11 VBRK_X9Y109/VBRK_EE2A2
din[2] INT_L_X0Y106/EE2BEG2 C10 VBRK_X9Y111/VBRK_EE2A2
din[3] INT_L_X0Y108/EE2BEG2 A10 VBRK_X9Y113/VBRK_EE2A2
din[4] INT_L_X0Y110/EE2BEG2 D9 VBRK_X9Y115/VBRK_EE2A2
din[5] INT_L_X0Y112/EE2BEG2 C9 VBRK_X9Y117/VBRK_EE2A2
din[6] INT_L_X0Y114/EE2BEG2 B9 VBRK_X9Y119/VBRK_EE2A2
din[7] INT_L_X0Y116/EE2BEG2 B8 VBRK_X9Y121/VBRK_EE2A2
dout[0] INT_R_X23Y133/LH12 H5 VBRK_X61Y139/VBRK_LH12
dout[1] INT_R_X23Y135/LH12 J5 VBRK_X61Y141/VBRK_LH12
dout[2] INT_L_X2Y133/SW6BEG0 T9 VBRK_X9Y139/VBRK_SW4A0
dout[3] INT_L_X2Y135/SW6BEG0 T10 VBRK_X9Y141/VBRK_SW4A0
dout[4] INT_R_X23Y137/LH12 F6 VBRK_X61Y143/VBRK_LH12
dout[5] INT_R_X23Y139/LH12 J4 VBRK_X61Y145/VBRK_LH12
dout[6] INT_R_X23Y141/LH12 J2 VBRK_X61Y147/VBRK_LH12
dout[7] INT_R_X23Y143/LH12 H6 VBRK_X61Y149/VBRK_LH12

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@ -252,9 +252,143 @@
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y38.GCLK16_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
"CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
"CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_BELOW",
"CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
"CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
"CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
"CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
"CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE"
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE",
"CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_IN_R0_ACTIVE",
"CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
"CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
"HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
"HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
"HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
"INT_L_X0Y1.IMUX_L34.SL1END1",
"INT_L_X0Y102.EE2BEG2.SE2END2",
"INT_L_X0Y103.SW2BEG2.SE6END2",
"INT_L_X0Y105.LV_L18.LV_L0",
"INT_L_X0Y111.IMUX_L34.SL1END1",
"INT_L_X0Y112.SL1BEG1.SR1END1",
"INT_L_X0Y113.SR1BEG1.SS6END0",
"INT_L_X0Y119.SS6BEG0.SS6END0",
"INT_L_X0Y120.SE2BEG3.EL1END3",
"INT_L_X0Y121.WL1BEG_N3.LOGIC_OUTS_L18",
"INT_L_X0Y123.LV_L18.LV_L0",
"INT_L_X0Y125.SS6BEG0.LV_L0",
"INT_L_X0Y141.LV_L18.SW6END0",
"INT_L_X0Y143.LV_L18.SW6END0",
"INT_L_X0Y15.SS6BEG0.LV_L0",
"INT_L_X0Y2.SL1BEG1.SR1END1",
"INT_L_X0Y3.SR1BEG1.SS6END0",
"INT_L_X0Y33.LV_L18.LV_L0",
"INT_L_X0Y51.LV_L18.LV_L0",
"INT_L_X0Y69.LV_L18.LV_L0",
"INT_L_X0Y87.LV_L18.LV_L0",
"INT_L_X0Y9.SS6BEG0.SS6END0",
"INT_R_X1Y107.SW6BEG2.LVB0",
"INT_R_X1Y119.LVB12.SE2END3",
"INT_R_X25Y123.NL1BEG2.WW4END3",
"INT_R_X25Y124.NN2BEG2.NL1END2",
"INT_R_X25Y126.WW2BEG1.NN2END2",
"INT_R_X31Y105.LV0.LV18",
"INT_R_X31Y123.WW4BEG3.LV18",
"INT_R_X31Y87.LV0.LH12",
"INT_R_X43Y68.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y69.LV0.NR1END0",
"INT_R_X43Y87.LH0.LV18",
"LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y1.IOB_Y0.PULLTYPE.PULLDOWN",
"LIOB33_X0Y1.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y111.IOB_Y0.PULLTYPE.PULLDOWN",
"LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN",
"LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y121.IOB_Y1.IN_ONLY",
"LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y121.IOB_Y1.ZINV_D",
"LIOB33_X0Y43.IOB_Y0.IN_ONLY",
"LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
"LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
"LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y67.IOB_Y0.IN_ONLY",
"RIOB33_X43Y67.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y67.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y67.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y67.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y67.IOB_Y0.ZINV_D",
"RIOB33_X43Y67.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y67.IOB_Y1.PULLTYPE.PULLDOWN",
"RIOB33_X43Y67.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y75.IOB_Y0.IN_ONLY",
"RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y75.IOB_Y0.ZINV_D",
"RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
"RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
]
}

BIN
artix7/harness/basys3/swbut/design.bit
View File

Binary file not shown.

BIN
artix7/harness/basys3/swbut/design.dcp
View File

Binary file not shown.

619
artix7/harness/basys3/swbut/design.json
View File

@ -2,7 +2,7 @@
"info": {
"GRID_X_MAX": 58,
"GRID_X_MIN": 10,
"GRID_Y_MAX": 52,
"GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
@ -3060,13 +3060,628 @@
}
],
"required_features": [
"",
"CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
"CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
"CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
"CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
"CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O",
"CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
"CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y142.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y38.GCLK0_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
"CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
"CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_BOT_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_CK_IN_R0_ACTIVE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE"
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
"CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
"HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
"INT_L_X0Y0.IMUX_L34.SS2END1",
"INT_L_X0Y1.IMUX_L34.WW2END0",
"INT_L_X0Y10.LV_L0.NR1END0",
"INT_L_X0Y10.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y100.NN6BEG3.LV_L18",
"INT_L_X0Y101.LVB_L12.LV_L0",
"INT_L_X0Y101.NN6BEG3.LV_L18",
"INT_L_X0Y102.EE2BEG2.NN6END2",
"INT_L_X0Y103.LV_L18.LV_L0",
"INT_L_X0Y103.NR1BEG2.NN6END2",
"INT_L_X0Y104.EE2BEG2.NR1END2",
"INT_L_X0Y104.NN6BEG2.LVB_L12",
"INT_L_X0Y105.LV_L18.LV_L0",
"INT_L_X0Y105.NN6BEG3.NN6END3",
"INT_L_X0Y106.EE2BEG2.EL1END2",
"INT_L_X0Y106.NR1BEG3.NN6END3",
"INT_L_X0Y106.WL1BEG2.SR1END3",
"INT_L_X0Y107.LV_L18.LV_L0",
"INT_L_X0Y107.NL1BEG2.NR1END3",
"INT_L_X0Y107.SR1BEG3.NN6END3",
"INT_L_X0Y108.EE2BEG2.NL1END2",
"INT_L_X0Y108.NN6BEG2.LVB_L12",
"INT_L_X0Y109.LV_L18.LV_L0",
"INT_L_X0Y109.NN6BEG2.LVB_L12",
"INT_L_X0Y11.LV_L0.NR1END0",
"INT_L_X0Y11.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y110.EE2BEG2.NN6END2",
"INT_L_X0Y111.IMUX_L34.WR1END1",
"INT_L_X0Y111.LV_L18.SW6END0",
"INT_L_X0Y111.NL1BEG2.NN6END3",
"INT_L_X0Y111.WW2BEG0.SS6END0",
"INT_L_X0Y112.EE2BEG2.NL1END2",
"INT_L_X0Y112.NW6BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y113.LV_L18.SW6END0",
"INT_L_X0Y114.EE2BEG2.NN6END2",
"INT_L_X0Y115.LV_L18.SW6END0",
"INT_L_X0Y115.NR1BEG2.NN6END2",
"INT_L_X0Y116.EE2BEG2.NR1END2",
"INT_L_X0Y117.LV_L18.SW6END0",
"INT_L_X0Y117.SS6BEG0.SS6END0",
"INT_L_X0Y118.EE2BEG2.EL1END2",
"INT_L_X0Y118.WL1BEG2.NW2END_S0_0",
"INT_L_X0Y119.LV_L18.SW6END0",
"INT_L_X0Y12.LV_L0.NR1END0",
"INT_L_X0Y12.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y121.LV_L18.SW6END0",
"INT_L_X0Y123.LV_L18.SW6END0",
"INT_L_X0Y123.SS6BEG0.SS6END0",
"INT_L_X0Y125.LV_L18.SW6END0",
"INT_L_X0Y127.LV_L18.SW6END0",
"INT_L_X0Y129.SS6BEG0.SW6END0",
"INT_L_X0Y13.LV_L0.NR1END0",
"INT_L_X0Y13.SE6BEG0.SS2END0",
"INT_L_X0Y13.SS6BEG0.SS6END0",
"INT_L_X0Y15.SS2BEG0.SS6END0",
"INT_L_X0Y15.SS6BEG0.LV_L0",
"INT_L_X0Y17.NR1BEG1.EL1END1",
"INT_L_X0Y17.SE6BEG0.LV_L0",
"INT_L_X0Y17.WL1BEG1.SS6END2",
"INT_L_X0Y18.IMUX_L34.NR1END1",
"INT_L_X0Y19.FAN_ALT1.SS2END2",
"INT_L_X0Y19.IMUX_L34.FAN_BOUNCE1",
"INT_L_X0Y19.SS6BEG0.LV_L0",
"INT_L_X0Y2.IMUX_L34.SS2END1",
"INT_L_X0Y2.SS2BEG1.SR1END1",
"INT_L_X0Y20.FAN_ALT1.EL1END3",
"INT_L_X0Y20.IMUX_L34.FAN_BOUNCE1",
"INT_L_X0Y21.SS2BEG2.SS6END2",
"INT_L_X0Y21.SS6BEG0.LV_L0",
"INT_L_X0Y21.WL1BEG_N3.SS6END0",
"INT_L_X0Y23.SS6BEG2.SS6END2",
"INT_L_X0Y24.LV_L0.LV_L18",
"INT_L_X0Y25.LV_L0.LV_L18",
"INT_L_X0Y26.LV_L0.LV_L18",
"INT_L_X0Y27.LV_L0.LV_L18",
"INT_L_X0Y27.SS6BEG0.SS6END0",
"INT_L_X0Y27.SS6BEG2.SS6END2",
"INT_L_X0Y28.LV_L0.LV_L18",
"INT_L_X0Y29.LV_L0.LV_L18",
"INT_L_X0Y29.SS6BEG2.SS6END2",
"INT_L_X0Y3.IMUX_L34.WW2END0",
"INT_L_X0Y3.SR1BEG1.SS6END0",
"INT_L_X0Y30.LV_L0.LV_L18",
"INT_L_X0Y31.LV_L0.LV_L18",
"INT_L_X0Y33.LV_L18.LV_L0",
"INT_L_X0Y33.SS6BEG0.SS6END0",
"INT_L_X0Y33.SS6BEG2.SS6END2",
"INT_L_X0Y35.LV_L18.LV_L0",
"INT_L_X0Y35.SS6BEG2.SS6END2",
"INT_L_X0Y37.LV_L18.LV_L0",
"INT_L_X0Y39.LV_L18.LV_L0",
"INT_L_X0Y39.SS6BEG0.SS6END0",
"INT_L_X0Y39.SS6BEG2.SS6END2",
"INT_L_X0Y4.IMUX_L34.SR1BEG_S0",
"INT_L_X0Y4.SR1BEG_S0.WL1END3",
"INT_L_X0Y4.SS2BEG1.SR1END1",
"INT_L_X0Y41.SS6BEG2.SS6END2",
"INT_L_X0Y42.LV_L0.LV_L18",
"INT_L_X0Y43.IMUX_L34.WW2END0",
"INT_L_X0Y43.LV_L0.LV_L18",
"INT_L_X0Y44.LV_L0.LV_L18",
"INT_L_X0Y45.LV_L0.LV_L18",
"INT_L_X0Y45.SS6BEG0.SS6END0",
"INT_L_X0Y45.SS6BEG2.SS6END2",
"INT_L_X0Y46.LV_L0.LV_L18",
"INT_L_X0Y47.LV_L0.LV_L18",
"INT_L_X0Y47.SS6BEG2.SS6END2",
"INT_L_X0Y48.LV_L0.LV_L18",
"INT_L_X0Y49.LV_L0.LV_L18",
"INT_L_X0Y5.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y5.SR1BEG1.SS2END0",
"INT_L_X0Y51.LV_L18.LV_L0",
"INT_L_X0Y51.SS6BEG0.SS6END0",
"INT_L_X0Y51.SS6BEG2.SS6END2",
"INT_L_X0Y53.LV_L18.LV_L0",
"INT_L_X0Y53.SE6BEG0.SS6END0",
"INT_L_X0Y53.SS6BEG2.SS6END2",
"INT_L_X0Y55.LV_L18.LV_L0",
"INT_L_X0Y57.LV_L18.LV_L0",
"INT_L_X0Y57.SS6BEG0.SS6END0",
"INT_L_X0Y57.SS6BEG2.SS6END2",
"INT_L_X0Y59.SS6BEG0.LV_L0",
"INT_L_X0Y59.SS6BEG2.SS6END2",
"INT_L_X0Y6.LV_L0.NR1END0",
"INT_L_X0Y6.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y60.LV_L0.LV_L18",
"INT_L_X0Y61.LV_L0.LV_L18",
"INT_L_X0Y62.LV_L0.LV_L18",
"INT_L_X0Y63.LV_L0.LV_L18",
"INT_L_X0Y63.SS6BEG0.SS6END0",
"INT_L_X0Y63.SS6BEG2.SS6END2",
"INT_L_X0Y64.LV_L0.LV_L18",
"INT_L_X0Y65.LV_L0.LV_L18",
"INT_L_X0Y65.SS6BEG2.SS6END2",
"INT_L_X0Y66.LV_L0.LV_L18",
"INT_L_X0Y67.LV_L0.LV_L18",
"INT_L_X0Y69.LV_L18.LV_L0",
"INT_L_X0Y69.SS6BEG0.SS6END0",
"INT_L_X0Y69.SS6BEG2.SS6END2",
"INT_L_X0Y7.LV_L0.NR1END0",
"INT_L_X0Y7.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y7.SS2BEG0.SS6END0",
"INT_L_X0Y71.LV_L18.LV_L0",
"INT_L_X0Y71.SS6BEG2.SS6END2",
"INT_L_X0Y73.LV_L18.LV_L0",
"INT_L_X0Y75.LV_L18.LV_L0",
"INT_L_X0Y75.SS6BEG0.SS6END0",
"INT_L_X0Y75.SS6BEG2.LVB_L0",
"INT_L_X0Y77.LV_L18.LV_L0",
"INT_L_X0Y77.SS6BEG2.LVB_L0",
"INT_L_X0Y77.SW6BEG0.SW6END0",
"INT_L_X0Y78.LV_L0.LV_L18",
"INT_L_X0Y79.LV_L0.LV_L18",
"INT_L_X0Y8.LV_L0.NR1END0",
"INT_L_X0Y8.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y80.LVB_L0.LV_L18",
"INT_L_X0Y81.LV_L0.LV_L18",
"INT_L_X0Y81.SS6BEG0.SW6END0",
"INT_L_X0Y82.LV_L0.LV_L18",
"INT_L_X0Y83.LV_L0.LV_L18",
"INT_L_X0Y84.LVB_L0.LV_L18",
"INT_L_X0Y85.LVB_L0.LV_L18",
"INT_L_X0Y85.SE6BEG0.LV_L0",
"INT_L_X0Y87.LVB_L12.LVB_L0",
"INT_L_X0Y87.LV_L18.LV_L0",
"INT_L_X0Y89.LVB_L12.LVB_L0",
"INT_L_X0Y89.LV_L18.LV_L0",
"INT_L_X0Y89.SE6BEG0.SW6END0",
"INT_L_X0Y9.LV_L0.NR1END0",
"INT_L_X0Y9.NR1BEG0.LOGIC_OUTS_L18",
"INT_L_X0Y9.SS6BEG0.SS6END0",
"INT_L_X0Y91.LV_L18.LV_L0",
"INT_L_X0Y92.LVB_L0.LVB_L12",
"INT_L_X0Y93.LV_L18.LV_L0",
"INT_L_X0Y95.LV_L18.LV_L0",
"INT_L_X0Y96.LVB_L0.LV_L18",
"INT_L_X0Y96.NN6BEG2.LVB_L12",
"INT_L_X0Y97.LVB_L0.LV_L18",
"INT_L_X0Y97.NN6BEG2.LVB_L12",
"INT_L_X0Y97.SE6BEG0.LV_L0",
"INT_L_X0Y99.LVB_L12.LV_L0",
"INT_L_X0Y99.NN6BEG3.LV_L18",
"INT_L_X26Y140.WL1BEG1.NW2END3",
"INT_L_X2Y1.WW2BEG0.SS6END0",
"INT_L_X2Y13.SS6BEG0.SE6END0",
"INT_L_X2Y3.WW2BEG0.SS6END0",
"INT_L_X2Y43.WW2BEG0.SS6END0",
"INT_L_X2Y49.SS6BEG0.SE6END0",
"INT_L_X2Y7.SS6BEG0.SS6END0",
"INT_L_X2Y81.SW6BEG0.SE6END0",
"INT_L_X2Y85.SW6BEG0.SE6END0",
"INT_L_X2Y9.SS6BEG0.SE6END0",
"INT_L_X2Y93.SW6BEG0.SE6END0",
"INT_L_X40Y42.SE6BEG0.SE2END0",
"INT_L_X40Y62.EE4BEG0.SE2END0",
"INT_L_X40Y80.SE6BEG0.SE2END0",
"INT_L_X42Y32.ER1BEG1.SS6END0",
"INT_L_X42Y38.SS6BEG0.SE6END0",
"INT_L_X42Y39.SE2BEG1.ER1END1",
"INT_L_X42Y76.ER1BEG1.SE6END0",
"INT_L_X42Y77.SE2BEG1.ER1END1",
"INT_R_X1Y11.SS6BEG0.LV0",
"INT_R_X1Y111.WR1BEG1.EE2END0",
"INT_R_X1Y116.NN2BEG0.NE6END0",
"INT_R_X1Y118.NW2BEG0.NN2END0",
"INT_R_X1Y29.LV18.LV0",
"INT_R_X1Y47.LV18.LV0",
"INT_R_X1Y5.WL1BEG_N3.SS6END0",
"INT_R_X1Y65.LV18.SW6END0",
"INT_R_X1Y73.SE6BEG0.SE6END0",
"INT_R_X25Y126.WW2BEG1.WW4END2",
"INT_R_X25Y128.WW2BEG1.WW4END2",
"INT_R_X25Y130.WW2BEG1.WW4END2",
"INT_R_X25Y132.WW2BEG1.WW4END2",
"INT_R_X25Y134.WW2BEG1.WW4END2",
"INT_R_X25Y135.LV0.LH6",
"INT_R_X25Y136.WW2BEG1.WW2END1",
"INT_R_X25Y138.WW2BEG1.SS6END1",
"INT_R_X25Y140.WW2BEG1.WL1END1",
"INT_R_X25Y144.SS6BEG1.LV9",
"INT_R_X27Y136.WW2BEG1.NW6END2",
"INT_R_X27Y139.NW2BEG3.WW4END3",
"INT_R_X29Y126.WW4BEG2.NN6END2",
"INT_R_X29Y128.WW4BEG2.NW6END2",
"INT_R_X29Y129.LVB12.NW6END3",
"INT_R_X29Y129.SS6BEG1.NW6END2",
"INT_R_X29Y130.WW4BEG2.NW6END2",
"INT_R_X29Y132.NW6BEG2.NW6END2",
"INT_R_X29Y132.WW4BEG2.LVB12",
"INT_R_X29Y134.LVB12.NW6END3",
"INT_R_X29Y134.WW4BEG2.LVB12",
"INT_R_X31Y100.LVB0.LV18",
"INT_R_X31Y101.LV0.LV18",
"INT_R_X31Y102.LVB0.LV18",
"INT_R_X31Y103.LV0.LV18",
"INT_R_X31Y112.LV0.LV18",
"INT_R_X31Y112.LVB0.LVB12",
"INT_R_X31Y113.LVB0.LV18",
"INT_R_X31Y114.LVB0.LVB12",
"INT_R_X31Y116.LVB0.LV18",
"INT_R_X31Y117.LV0.LV18",
"INT_R_X31Y119.NN6BEG3.LV18",
"INT_R_X31Y121.LV0.LV18",
"INT_R_X31Y124.NW6BEG2.LVB12",
"INT_R_X31Y125.NW6BEG2.LVB12",
"INT_R_X31Y125.NW6BEG3.NN6END3",
"INT_R_X31Y126.NW6BEG2.LVB12",
"INT_R_X31Y128.NW6BEG2.LVB12",
"INT_R_X31Y130.NW6BEG3.LV18",
"INT_R_X31Y135.LH0.LV18",
"INT_R_X31Y139.WW4BEG3.LV18",
"INT_R_X31Y58.LV0.LH12",
"INT_R_X31Y59.LV0.LH12",
"INT_R_X31Y62.LV0.LH12",
"INT_R_X31Y63.LV0.LH12",
"INT_R_X31Y64.LV0.LH12",
"INT_R_X31Y65.LV0.LH12",
"INT_R_X31Y66.LV0.LH12",
"INT_R_X31Y67.LV0.LH12",
"INT_R_X31Y76.LV0.LV18",
"INT_R_X31Y77.LV0.LV18",
"INT_R_X31Y80.LV0.LV18",
"INT_R_X31Y81.LV0.LV18",
"INT_R_X31Y82.LV0.LV18",
"INT_R_X31Y83.LV0.LV18",
"INT_R_X31Y84.LV0.LV18",
"INT_R_X31Y85.LV0.LV18",
"INT_R_X31Y94.LV0.LV18",
"INT_R_X31Y95.LV0.LV18",
"INT_R_X31Y98.LV0.LV18",
"INT_R_X31Y99.LV0.LV18",
"INT_R_X35Y107.LV18.LV0",
"INT_R_X35Y109.SE6BEG0.LV0",
"INT_R_X35Y125.LV18.LH0",
"INT_R_X35Y127.LV18.LH0",
"INT_R_X35Y71.SE6BEG0.LV0",
"INT_R_X35Y89.LV18.LV0",
"INT_R_X37Y101.LV18.LV0",
"INT_R_X37Y103.LV18.LV0",
"INT_R_X37Y105.LV18.LV0",
"INT_R_X37Y105.SS6BEG0.SE6END0",
"INT_R_X37Y115.LV18.LH0",
"INT_R_X37Y117.LV18.LH0",
"INT_R_X37Y119.LV18.LH0",
"INT_R_X37Y121.LV18.LH0",
"INT_R_X37Y123.LV18.LH0",
"INT_R_X37Y43.SE6BEG0.LV0",
"INT_R_X37Y47.SE6BEG0.LV0",
"INT_R_X37Y61.LV18.LV0",
"INT_R_X37Y63.SE6BEG0.LV0",
"INT_R_X37Y65.LV18.LV0",
"INT_R_X37Y67.SE6BEG0.SE6END0",
"INT_R_X37Y79.LV18.LV0",
"INT_R_X37Y81.LV18.LV0",
"INT_R_X37Y83.LV18.LV0",
"INT_R_X37Y85.SE6BEG0.LV0",
"INT_R_X37Y87.SE6BEG0.LV0",
"INT_R_X37Y97.LV18.LV0",
"INT_R_X37Y99.LV18.LV0",
"INT_R_X37Y99.SE6BEG0.SS6END0",
"INT_R_X39Y39.EE2BEG0.SE6END0",
"INT_R_X39Y43.SE2BEG0.SE6END0",
"INT_R_X39Y59.SE6BEG0.SE6END0",
"INT_R_X39Y63.SE2BEG0.SE6END0",
"INT_R_X39Y77.EE2BEG0.SS6END0",
"INT_R_X39Y81.SE2BEG0.SE6END0",
"INT_R_X39Y83.SS6BEG0.SE6END0",
"INT_R_X39Y95.SE6BEG0.SE6END0",
"INT_R_X3Y69.SW6BEG0.SE6END0",
"INT_R_X41Y39.ER1BEG1.EE2END0",
"INT_R_X41Y49.SE6BEG0.SS6END0",
"INT_R_X41Y55.SS6BEG0.SE6END0",
"INT_R_X41Y77.ER1BEG1.EE2END0",
"INT_R_X41Y91.SE6BEG0.SE6END0",
"INT_R_X43Y32.IMUX34.ER1END1",
"INT_R_X43Y37.IMUX34.SL1END1",
"INT_R_X43Y38.IMUX34.SE2END1",
"INT_R_X43Y38.SL1BEG1.SR1END1",
"INT_R_X43Y39.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y39.SR1BEG1.SS6END0",
"INT_R_X43Y40.LV0.NR1END0",
"INT_R_X43Y40.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y41.LV0.NR1END0",
"INT_R_X43Y43.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y44.LV0.NR1END0",
"INT_R_X43Y44.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y45.LV0.NR1END0",
"INT_R_X43Y45.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y45.SS6BEG0.SE6END0",
"INT_R_X43Y46.LV0.NR1END0",
"INT_R_X43Y46.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y47.LV0.NR1END0",
"INT_R_X43Y47.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y48.LV0.NR1END0",
"INT_R_X43Y48.NR1BEG0.LOGIC_OUTS18",
"INT_R_X43Y49.LV0.NR1END0",
"INT_R_X43Y58.LH0.LV18",
"INT_R_X43Y59.LH0.LV18",
"INT_R_X43Y61.IMUX34.SR1BEG_S0",
"INT_R_X43Y61.SR1BEG_S0.WW4END_S0_0",
"INT_R_X43Y62.LH0.LV18",
"INT_R_X43Y63.LH0.LV18",
"INT_R_X43Y64.LH0.LV18",
"INT_R_X43Y65.LH0.LV18",
"INT_R_X43Y66.LH0.LV18",
"INT_R_X43Y67.LH0.LV18",
"INT_R_X43Y75.IMUX34.SL1END1",
"INT_R_X43Y76.IMUX34.SE2END1",
"INT_R_X43Y76.SL1BEG1.ER1END1",
"INT_R_X43Y87.ER1BEG1.SE6END0",
"INT_R_X43Y87.IMUX34.WR1END1",
"LIOB33_SING_X0Y0.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_SING_X0Y0.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_SING_X0Y0.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_SING_X0Y0.IOB_Y0.PULLTYPE.NONE",
"LIOB33_SING_X0Y0.IOB_Y0.SLEW.SLOW",
"LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
"LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y11.IOB_Y0.IN_ONLY",
"LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y11.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y11.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y11.IOB_Y0.ZINV_D",
"LIOB33_X0Y11.IOB_Y1.IN_ONLY",
"LIOB33_X0Y11.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y11.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y11.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y11.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y11.IOB_Y1.ZINV_D",
"LIOB33_X0Y111.IOB_Y0.IN_ONLY",
"LIOB33_X0Y111.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y111.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y111.IOB_Y0.ZINV_D",
"LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y17.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y17.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y17.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y17.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y17.IOB_Y0.SLEW.SLOW",
"LIOB33_X0Y17.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y17.IOB_Y1.PULLTYPE.PULLDOWN",
"LIOB33_X0Y17.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y19.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y19.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y19.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y19.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y19.IOB_Y0.SLEW.SLOW",
"LIOB33_X0Y19.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y19.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y19.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y19.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y19.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
"LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y43.IOB_Y0.IN_ONLY",
"LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
"LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y43.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y43.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"LIOB33_X0Y43.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y43.IOB_Y1.SLEW.SLOW",
"LIOB33_X0Y5.IOB_Y0.IN_ONLY",
"LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y5.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y5.IOB_Y0.ZINV_D",
"LIOB33_X0Y5.IOB_Y1.IN_ONLY",
"LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y5.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y5.IOB_Y1.ZINV_D",
"LIOB33_X0Y7.IOB_Y0.IN_ONLY",
"LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y7.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y7.IOB_Y0.ZINV_D",
"LIOB33_X0Y7.IOB_Y1.IN_ONLY",
"LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y7.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y7.IOB_Y1.ZINV_D",
"LIOB33_X0Y9.IOB_Y0.IN_ONLY",
"LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
"LIOB33_X0Y9.IOB_Y0.SLEW.FAST",
"LIOB33_X0Y9.IOB_Y0.ZINV_D",
"LIOB33_X0Y9.IOB_Y1.IN_ONLY",
"LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
"LIOB33_X0Y9.IOB_Y1.SLEW.FAST",
"LIOB33_X0Y9.IOB_Y1.ZINV_D",
"RIOB33_X43Y25.IOB_Y0.IN_ONLY",
"RIOB33_X43Y25.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y25.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y25.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y25.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y25.IOB_Y0.ZINV_D",
"RIOB33_X43Y25.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y25.IOB_Y1.PULLTYPE.PULLDOWN",
"RIOB33_X43Y25.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y31.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y31.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y31.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y31.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y31.IOB_Y0.SLEW.SLOW",
"RIOB33_X43Y31.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y31.IOB_Y1.PULLTYPE.PULLDOWN",
"RIOB33_X43Y31.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y37.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y37.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y37.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y37.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y37.IOB_Y0.SLEW.SLOW",
"RIOB33_X43Y37.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y37.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y37.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y37.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y37.IOB_Y1.SLEW.SLOW",
"RIOB33_X43Y39.IOB_Y0.IN_ONLY",
"RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y39.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y39.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y39.IOB_Y0.ZINV_D",
"RIOB33_X43Y39.IOB_Y1.IN_ONLY",
"RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y39.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y39.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y39.IOB_Y1.ZINV_D",
"RIOB33_X43Y43.IOB_Y0.IN_ONLY",
"RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y43.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y43.IOB_Y0.ZINV_D",
"RIOB33_X43Y43.IOB_Y1.IN_ONLY",
"RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y43.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y43.IOB_Y1.ZINV_D",
"RIOB33_X43Y45.IOB_Y0.IN_ONLY",
"RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y45.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y45.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y45.IOB_Y0.ZINV_D",
"RIOB33_X43Y45.IOB_Y1.IN_ONLY",
"RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y45.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y45.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y45.IOB_Y1.ZINV_D",
"RIOB33_X43Y47.IOB_Y0.IN_ONLY",
"RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y47.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y47.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y47.IOB_Y0.ZINV_D",
"RIOB33_X43Y47.IOB_Y1.IN_ONLY",
"RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
"RIOB33_X43Y47.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y47.IOB_Y1.SLEW.FAST",
"RIOB33_X43Y47.IOB_Y1.ZINV_D",
"RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
"RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
"RIOB33_X43Y75.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y75.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
"RIOB33_X43Y75.IOB_Y0.SLEW.SLOW",
"RIOB33_X43Y75.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y75.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y75.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y75.IOB_Y1.SLEW.SLOW",
"RIOB33_X43Y87.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y87.IOB_Y0.PULLTYPE.PULLDOWN",
"RIOB33_X43Y87.IOB_Y0.SLEW.FAST",
"RIOB33_X43Y87.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
"RIOB33_X43Y87.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
"RIOB33_X43Y87.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
"RIOB33_X43Y87.IOB_Y1.PULLTYPE.NONE",
"RIOB33_X43Y87.IOB_Y1.SLEW.SLOW"
]
}