Updating artix7 based on "Merge pull request #810 from mithro/import-wiki".
* Big update which adds timing SDF files for tiles. See [Info File](Info.md) for details.
This commit is contained in:
Tim 'mithro' Ansell
parent
d31753b768
commit
e29750043d
133
Info.md
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Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Thu Apr 11 21:39:58 UTC 2019 (2019-04-11T21:39:58+00:00).
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Last updated on Mon Apr 29 21:36:42 UTC 2019 (2019-04-29T21:36:42+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [37c46aa](https://github.com/SymbiFlow/prjxray/commit/37c46aa7f7e8993e2359cc32f0d3d2978e28d24d).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [27bba88](https://github.com/SymbiFlow/prjxray/commit/27bba88fc8ac6b08dc83a9298ef6f227c5a0d46e).
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Latest commit was;
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```
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commit 37c46aa7f7e8993e2359cc32f0d3d2978e28d24d
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Merge: ef63708 36177e9
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Author: litghost <537074+litghost@users.noreply.github.com>
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Date: Thu Apr 11 10:00:05 2019 -0700
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commit 27bba88fc8ac6b08dc83a9298ef6f227c5a0d46e
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Merge: 938f378 85060dd
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Author: Tim Ansell <me@mith.ro>
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Date: Mon Apr 29 09:30:05 2019 -0700
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Merge pull request #773 from litghost/add_more_parts
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Merge pull request #810 from mithro/import-wiki
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Add make targets to build additional outputs from each database.
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Fixing issues from wiki import
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```
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@ -59,7 +59,7 @@ Date: Thu Apr 11 10:00:05 2019 -0700
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### Settings
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/37c46aa7f7e8993e2359cc32f0d3d2978e28d24d/settings/artix7.sh)
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/27bba88fc8ac6b08dc83a9298ef6f227c5a0d46e/settings/artix7.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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@ -345,6 +345,117 @@ Results have checksums;
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* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
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* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
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* [`08912d58cee8057f7557c307700162b1d3437766adeb95a79980bf3602a7a779 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_INT_INTERFACE_L.sdf`](./artix7/timings/BRAM_INT_INTERFACE_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_INT_INTERFACE_R.sdf`](./artix7/timings/BRAM_INT_INTERFACE_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_BRAM.sdf`](./artix7/timings/BRKH_BRAM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_B_TERM_INT.sdf`](./artix7/timings/BRKH_B_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CLB.sdf`](./artix7/timings/BRKH_CLB.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CLK.sdf`](./artix7/timings/BRKH_CLK.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_CMT.sdf`](./artix7/timings/BRKH_CMT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_DSP_L.sdf`](./artix7/timings/BRKH_DSP_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_DSP_R.sdf`](./artix7/timings/BRKH_DSP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_GTX.sdf`](./artix7/timings/BRKH_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_INT.sdf`](./artix7/timings/BRKH_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/BRKH_TERM_INT.sdf`](./artix7/timings/BRKH_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/B_TERM_INT.sdf`](./artix7/timings/B_TERM_INT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CFG_CENTER_BOT.sdf`](./artix7/timings/CFG_CENTER_BOT.sdf)
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* [`da68ee39b0b3d97cccf9a57607156e26947ba0b75d769f024c3a94b990838cc2 ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
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* [`a6ee3d276725de5965953133b3298674badd2d9a892043cd67380bef3be9a840 ./artix7/timings/CFG_CENTER_TOP.sdf`](./artix7/timings/CFG_CENTER_TOP.sdf)
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* [`0b73ca38e6c462bd7567c2dea04e8b721bd14d3c0d96ec3d8718eed107e73c8c ./artix7/timings/CLBLL_L.sdf`](./artix7/timings/CLBLL_L.sdf)
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* [`0b73ca38e6c462bd7567c2dea04e8b721bd14d3c0d96ec3d8718eed107e73c8c ./artix7/timings/CLBLL_R.sdf`](./artix7/timings/CLBLL_R.sdf)
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* [`76e4fbdcdc31addedea51d1888128b638df941a091cec42dc6da9224ba5ecdd3 ./artix7/timings/CLBLM_L.sdf`](./artix7/timings/CLBLM_L.sdf)
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* [`76e4fbdcdc31addedea51d1888128b638df941a091cec42dc6da9224ba5ecdd3 ./artix7/timings/CLBLM_R.sdf`](./artix7/timings/CLBLM_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_BOT_R.sdf`](./artix7/timings/CLK_BUFG_BOT_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_REBUF.sdf`](./artix7/timings/CLK_BUFG_REBUF.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_BUFG_TOP_R.sdf`](./artix7/timings/CLK_BUFG_TOP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_FEED.sdf`](./artix7/timings/CLK_FEED.sdf)
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* [`534489925413749644e5ec08fc25b07264e88db91a75a7b76a4ca612bee8f23b ./artix7/timings/CLK_HROW_BOT_R.sdf`](./artix7/timings/CLK_HROW_BOT_R.sdf)
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* [`534489925413749644e5ec08fc25b07264e88db91a75a7b76a4ca612bee8f23b ./artix7/timings/CLK_HROW_TOP_R.sdf`](./artix7/timings/CLK_HROW_TOP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_MTBF2.sdf`](./artix7/timings/CLK_MTBF2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV.sdf`](./artix7/timings/CLK_PMV.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV2.sdf`](./artix7/timings/CLK_PMV2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMV2_SVT.sdf`](./artix7/timings/CLK_PMV2_SVT.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_PMVIOB.sdf`](./artix7/timings/CLK_PMVIOB.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CLK_TERM.sdf`](./artix7/timings/CLK_TERM.sdf)
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* [`11ee82949c2bda0d78181c7134f2809f5630cda2b28b5e4203add1cde7372fcc ./artix7/timings/CMT_FIFO_L.sdf`](./artix7/timings/CMT_FIFO_L.sdf)
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* [`11ee82949c2bda0d78181c7134f2809f5630cda2b28b5e4203add1cde7372fcc ./artix7/timings/CMT_FIFO_R.sdf`](./artix7/timings/CMT_FIFO_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CMT_PMV.sdf`](./artix7/timings/CMT_PMV.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/CMT_PMV_L.sdf`](./artix7/timings/CMT_PMV_L.sdf)
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* [`f0a3f422e55c37190cc023d7881632ce105b9519b0b32e153ba6c65c54863c6f ./artix7/timings/CMT_TOP_L_LOWER_B.sdf`](./artix7/timings/CMT_TOP_L_LOWER_B.sdf)
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* [`97c0b23cfc1e555fab674bd2c107a14790554bc0314a2cfe7d940b4ea3ebe72b ./artix7/timings/CMT_TOP_L_LOWER_T.sdf`](./artix7/timings/CMT_TOP_L_LOWER_T.sdf)
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* [`f03b8c8d322e560be02fda8951fa17daef00b3bb7acde8d6e02389aeafc31483 ./artix7/timings/CMT_TOP_L_UPPER_B.sdf`](./artix7/timings/CMT_TOP_L_UPPER_B.sdf)
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* [`19e18e8427407f3c1cb679d297cfa9028e10bf1eb6762ceef6dd0df1e77979ac ./artix7/timings/CMT_TOP_L_UPPER_T.sdf`](./artix7/timings/CMT_TOP_L_UPPER_T.sdf)
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* [`f0a3f422e55c37190cc023d7881632ce105b9519b0b32e153ba6c65c54863c6f ./artix7/timings/CMT_TOP_R_LOWER_B.sdf`](./artix7/timings/CMT_TOP_R_LOWER_B.sdf)
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* [`97c0b23cfc1e555fab674bd2c107a14790554bc0314a2cfe7d940b4ea3ebe72b ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
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* [`f03b8c8d322e560be02fda8951fa17daef00b3bb7acde8d6e02389aeafc31483 ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
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* [`19e18e8427407f3c1cb679d297cfa9028e10bf1eb6762ceef6dd0df1e77979ac ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
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* [`99916eea41e8a31ac142c2b6990fba1d78b4cd240e1db58ec91a2a5f9069b847 ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
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* [`99916eea41e8a31ac142c2b6990fba1d78b4cd240e1db58ec91a2a5f9069b847 ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
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* [`99916eea41e8a31ac142c2b6990fba1d78b4cd240e1db58ec91a2a5f9069b847 ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
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* [`99916eea41e8a31ac142c2b6990fba1d78b4cd240e1db58ec91a2a5f9069b847 ./artix7/timings/GTP_CHANNEL_3.sdf`](./artix7/timings/GTP_CHANNEL_3.sdf)
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* [`3c3d717b8c01c8faba8475822720de13896ebdb4beeb96b21a31835b11ab54d2 ./artix7/timings/GTP_COMMON.sdf`](./artix7/timings/GTP_COMMON.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/GTP_INT_INTERFACE.sdf`](./artix7/timings/GTP_INT_INTERFACE.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_BRAM.sdf`](./artix7/timings/HCLK_BRAM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_CLB.sdf`](./artix7/timings/HCLK_CLB.sdf)
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* [`1e9ba23fac7d5d7e2ad25c4f395981d9e5a00d580fd96e2d40bc37bce4859558 ./artix7/timings/HCLK_CMT.sdf`](./artix7/timings/HCLK_CMT.sdf)
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* [`1e9ba23fac7d5d7e2ad25c4f395981d9e5a00d580fd96e2d40bc37bce4859558 ./artix7/timings/HCLK_CMT_L.sdf`](./artix7/timings/HCLK_CMT_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_DSP_L.sdf`](./artix7/timings/HCLK_DSP_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_DSP_R.sdf`](./artix7/timings/HCLK_DSP_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FEEDTHRU_1.sdf`](./artix7/timings/HCLK_FEEDTHRU_1.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FEEDTHRU_2.sdf`](./artix7/timings/HCLK_FEEDTHRU_2.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_FIFO_L.sdf`](./artix7/timings/HCLK_FIFO_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_GTX.sdf`](./artix7/timings/HCLK_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_INT_INTERFACE.sdf`](./artix7/timings/HCLK_INT_INTERFACE.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_IOB.sdf`](./artix7/timings/HCLK_IOB.sdf)
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* [`338525f5ef736f1407baff9ff4eabff53a9abb0a37e8c4876a8f6d4782a8658e ./artix7/timings/HCLK_IOI3.sdf`](./artix7/timings/HCLK_IOI3.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_L.sdf`](./artix7/timings/HCLK_L.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_L_BOT_UTURN.sdf`](./artix7/timings/HCLK_L_BOT_UTURN.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_R.sdf`](./artix7/timings/HCLK_R.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_R_BOT_UTURN.sdf`](./artix7/timings/HCLK_R_BOT_UTURN.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_TERM.sdf`](./artix7/timings/HCLK_TERM.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_TERM_GTX.sdf`](./artix7/timings/HCLK_TERM_GTX.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_VBRK.sdf`](./artix7/timings/HCLK_VBRK.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/HCLK_VFRAME.sdf`](./artix7/timings/HCLK_VFRAME.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_FEEDTHRU_1.sdf`](./artix7/timings/INT_FEEDTHRU_1.sdf)
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* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_FEEDTHRU_2.sdf`](./artix7/timings/INT_FEEDTHRU_2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_INTERFACE_L.sdf`](./artix7/timings/INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_INTERFACE_R.sdf`](./artix7/timings/INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_L.sdf`](./artix7/timings/INT_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/INT_R.sdf`](./artix7/timings/INT_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/IO_INT_INTERFACE_L.sdf`](./artix7/timings/IO_INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/IO_INT_INTERFACE_R.sdf`](./artix7/timings/IO_INT_INTERFACE_R.sdf)
|
||||
* [`672c12b334f07c7243bcbd35d14742c460aee6e7d70fcdf6acecfa811da1456b ./artix7/timings/LIOB33.sdf`](./artix7/timings/LIOB33.sdf)
|
||||
* [`9befc627c1bb83308433ab488ade8d0e4e26dd59490d8d8f622a68406077b04f ./artix7/timings/LIOB33_SING.sdf`](./artix7/timings/LIOB33_SING.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/LIOI3.sdf`](./artix7/timings/LIOI3.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/LIOI3_SING.sdf`](./artix7/timings/LIOI3_SING.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/LIOI3_TBYTESRC.sdf`](./artix7/timings/LIOI3_TBYTESRC.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/LIOI3_TBYTETERM.sdf`](./artix7/timings/LIOI3_TBYTETERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/L_TERM_INT.sdf`](./artix7/timings/L_TERM_INT.sdf)
|
||||
* [`7e518763e9de6a3ae4c55b05cb24eb7541ff077a89fd6996a58939e225ff3dfc ./artix7/timings/MONITOR_BOT.sdf`](./artix7/timings/MONITOR_BOT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/MONITOR_MID.sdf`](./artix7/timings/MONITOR_MID.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/MONITOR_TOP.sdf`](./artix7/timings/MONITOR_TOP.sdf)
|
||||
* [`d6c9c750697ae9b1c7da71ee199a36d141d049a1b0cf0acc80086cc2291e2b34 ./artix7/timings/PCIE_BOT.sdf`](./artix7/timings/PCIE_BOT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_INT_INTERFACE_L.sdf`](./artix7/timings/PCIE_INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_INT_INTERFACE_R.sdf`](./artix7/timings/PCIE_INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_NULL.sdf`](./artix7/timings/PCIE_NULL.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/PCIE_TOP.sdf`](./artix7/timings/PCIE_TOP.sdf)
|
||||
* [`672c12b334f07c7243bcbd35d14742c460aee6e7d70fcdf6acecfa811da1456b ./artix7/timings/RIOB33.sdf`](./artix7/timings/RIOB33.sdf)
|
||||
* [`9befc627c1bb83308433ab488ade8d0e4e26dd59490d8d8f622a68406077b04f ./artix7/timings/RIOB33_SING.sdf`](./artix7/timings/RIOB33_SING.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/RIOI3.sdf`](./artix7/timings/RIOI3.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/RIOI3_SING.sdf`](./artix7/timings/RIOI3_SING.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/RIOI3_TBYTESRC.sdf`](./artix7/timings/RIOI3_TBYTESRC.sdf)
|
||||
* [`1ff9b2f86ccbf610746d8aa83e3c07baf945c99e0d34482c349d17806c09247f ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/R_TERM_INT.sdf`](./artix7/timings/R_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/R_TERM_INT_GTX.sdf`](./artix7/timings/R_TERM_INT_GTX.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/TERM_CMT.sdf`](./artix7/timings/TERM_CMT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/T_TERM_INT.sdf`](./artix7/timings/T_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VBRK.sdf`](./artix7/timings/VBRK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VBRK_EXT.sdf`](./artix7/timings/VBRK_EXT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./artix7/timings/VFRAME.sdf`](./artix7/timings/VFRAME.sdf)
|
||||
* [`2ba5ff1badba4350de2be5e1cb9b81b28b1ea715e5bbdc8d500d525615977bad ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
|
||||
* [`d553984e9712cff2e4bd941fd12162f1fdf18c74ad9c2126f4346e981b7f21d9 ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
|
||||
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
|
||||
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
|
||||
* [`ac928ee3c50e91facacb4173fdf70384f56e046bb14581bf75f760e406fe4f78 ./artix7/xc7a35tcpg236-1_package_pins.csv`](./artix7/xc7a35tcpg236-1_package_pins.csv)
|
||||
|
|
@ -360,7 +471,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/37c46aa7f7e8993e2359cc32f0d3d2978e28d24d/settings/kintex7.sh)
|
||||
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/27bba88fc8ac6b08dc83a9298ef6f227c5a0d46e/settings/kintex7.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="kintex7"
|
||||
export XRAY_PART="xc7k70tfbg676-2"
|
||||
|
|
@ -634,7 +745,7 @@ Results have checksums;
|
|||
|
||||
### Settings
|
||||
|
||||
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/37c46aa7f7e8993e2359cc32f0d3d2978e28d24d/settings/zynq7.sh)
|
||||
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/27bba88fc8ac6b08dc83a9298ef6f227c5a0d46e/settings/zynq7.sh)
|
||||
```shell
|
||||
export XRAY_DATABASE="zynq7"
|
||||
export XRAY_PART="xc7z010clg400-1"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CAPTURE")
|
||||
(INSTANCE CAPTURE)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (3.725::4.285))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ICAP")
|
||||
(INSTANCE ICAP)
|
||||
(TIMINGCHECK
|
||||
(HOLD CSIB (posedge CLK) (0.000::0.000))
|
||||
(SETUP CSIB (posedge CLK) (3.390::3.900))
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (5.587::6.427))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ICAP_I")
|
||||
(INSTANCE ICAP)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (2.237::2.574))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "DNA_PORT_DNA_PORTDNA_PORT")
|
||||
(INSTANCE DNA_PORT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK DOUT (1.862::2.142)(2.793::3.214))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (2.793::3.214))
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (4.656::5.356))
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (4.656::5.356))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/D5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.120::0.149))
|
||||
(IOPATH A2 O5 (0.043::0.054)(0.121::0.150))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.120::0.149))
|
||||
(IOPATH A4 O5 (0.044::0.055)(0.120::0.149))
|
||||
(IOPATH A5 O5 (0.049::0.061)(0.094::0.117))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/C5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.124::0.154))
|
||||
(IOPATH A2 O5 (0.043::0.053)(0.124::0.154))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.123::0.153))
|
||||
(IOPATH A4 O5 (0.045::0.056)(0.123::0.153))
|
||||
(IOPATH A5 O5 (0.051::0.063)(0.097::0.120))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.113::0.140)(0.301::0.374))
|
||||
(IOPATH DI0 CO1 (0.134::0.166)(0.373::0.462))
|
||||
(IOPATH DI0 CO2 (0.158::0.197)(0.432::0.536))
|
||||
(IOPATH DI0 O1 (0.124::0.154)(0.328::0.407))
|
||||
(IOPATH DI0 O2 (0.157::0.196)(0.448::0.556))
|
||||
(IOPATH DI0 O3 (0.177::0.220)(0.496::0.615))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.112::0.139)(0.306::0.379))
|
||||
(IOPATH DI0 CO1 (0.134::0.166)(0.375::0.465))
|
||||
(IOPATH DI0 CO2 (0.160::0.199)(0.435::0.540))
|
||||
(IOPATH DI0 CO3 (0.161::0.201)(0.424::0.526))
|
||||
(IOPATH DI0 O1 (0.124::0.155)(0.328::0.407))
|
||||
(IOPATH DI0 O2 (0.157::0.196)(0.448::0.556))
|
||||
(IOPATH DI0 O3 (0.178::0.222)(0.496::0.615))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.099::0.124)(0.287::0.356))
|
||||
(IOPATH DI2 CO3 (0.117::0.146)(0.321::0.398))
|
||||
(IOPATH DI2 O3 (0.127::0.158)(0.353::0.438))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.086::0.113)(0.223::0.293))
|
||||
(IOPATH CIN CO1 (0.052::0.064)(0.143::0.178))
|
||||
(IOPATH CIN CO2 (0.075::0.094)(0.201::0.250))
|
||||
(IOPATH CIN O0 (0.057::0.085)(0.159::0.235))
|
||||
(IOPATH CIN O1 (0.098::0.122)(0.280::0.348))
|
||||
(IOPATH CIN O2 (0.070::0.087)(0.206::0.256))
|
||||
(IOPATH CIN O3 (0.092::0.114)(0.265::0.329))
|
||||
(IOPATH CYINIT CO0 (0.177::0.220)(0.466::0.578))
|
||||
(IOPATH CYINIT CO1 (0.152::0.189)(0.426::0.529))
|
||||
(IOPATH CYINIT CO2 (0.180::0.224)(0.497::0.617))
|
||||
(IOPATH CYINIT O0 (0.152::0.189)(0.395::0.491))
|
||||
(IOPATH CYINIT O1 (0.183::0.228)(0.494::0.613))
|
||||
(IOPATH CYINIT O2 (0.172::0.214)(0.483::0.600))
|
||||
(IOPATH CYINIT O3 (0.194::0.241)(0.530::0.657))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.123::0.153)(0.343::0.425))
|
||||
(IOPATH DI0 CO1 (0.142::0.177)(0.393::0.487))
|
||||
(IOPATH DI0 CO2 (0.170::0.211)(0.456::0.566))
|
||||
(IOPATH DI0 O1 (0.131::0.163)(0.338::0.420))
|
||||
(IOPATH DI0 O2 (0.160::0.200)(0.462::0.573))
|
||||
(IOPATH DI0 O3 (0.182::0.227)(0.511::0.633))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
(IOPATH SR Q (0.164::0.204)(0.638::0.791))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.124::0.154)(0.359::0.445))
|
||||
(IOPATH DI1 CO2 (0.150::0.186)(0.419::0.520))
|
||||
(IOPATH DI1 CO3 (0.147::0.183)(0.409::0.507))
|
||||
(IOPATH DI1 O2 (0.146::0.182)(0.433::0.537))
|
||||
(IOPATH DI1 O3 (0.167::0.208)(0.481::0.596))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.076::0.100)(0.206::0.271))
|
||||
(IOPATH CIN CO1 (0.045::0.056)(0.127::0.157))
|
||||
(IOPATH CIN CO2 (0.065::0.081)(0.184::0.228))
|
||||
(IOPATH CIN CO3 (0.039::0.049)(0.092::0.114))
|
||||
(IOPATH CIN O0 (0.054::0.080)(0.150::0.222))
|
||||
(IOPATH CIN O1 (0.091::0.113)(0.269::0.334))
|
||||
(IOPATH CIN O2 (0.065::0.081)(0.192::0.239))
|
||||
(IOPATH CIN O3 (0.090::0.112)(0.252::0.313))
|
||||
(IOPATH CYINIT CO0 (0.165::0.206)(0.432::0.536))
|
||||
(IOPATH CYINIT CO1 (0.144::0.180)(0.398::0.494))
|
||||
(IOPATH CYINIT CO2 (0.169::0.210)(0.477::0.592))
|
||||
(IOPATH CYINIT CO3 (0.173::0.215)(0.467::0.580))
|
||||
(IOPATH CYINIT O0 (0.147::0.183)(0.388::0.482))
|
||||
(IOPATH CYINIT O1 (0.176::0.219)(0.482::0.598))
|
||||
(IOPATH CYINIT O2 (0.167::0.208)(0.471::0.584))
|
||||
(IOPATH CYINIT O3 (0.190::0.236)(0.518::0.642))
|
||||
(IOPATH S0 CO0 (0.089::0.118)(0.258::0.340))
|
||||
(IOPATH S0 CO1 (0.118::0.156)(0.329::0.433))
|
||||
(IOPATH S0 CO2 (0.144::0.190)(0.389::0.512))
|
||||
(IOPATH S0 CO3 (0.142::0.187)(0.386::0.508))
|
||||
(IOPATH S0 O0 (0.060::0.079)(0.170::0.223))
|
||||
(IOPATH S0 O1 (0.096::0.127)(0.304::0.400))
|
||||
(IOPATH S0 O2 (0.136::0.180)(0.398::0.523))
|
||||
(IOPATH S0 O3 (0.156::0.206)(0.442::0.582))
|
||||
(IOPATH S1 CO1 (0.126::0.166)(0.356::0.469))
|
||||
(IOPATH S1 CO2 (0.153::0.202)(0.417::0.548))
|
||||
(IOPATH S1 CO3 (0.146::0.192)(0.401::0.528))
|
||||
(IOPATH S1 O1 (0.056::0.074)(0.156::0.205))
|
||||
(IOPATH S1 O2 (0.143::0.189)(0.424::0.558))
|
||||
(IOPATH S1 O3 (0.163::0.215)(0.470::0.618))
|
||||
(IOPATH S2 CO2 (0.072::0.095)(0.222::0.292))
|
||||
(IOPATH S2 CO3 (0.106::0.140)(0.286::0.376))
|
||||
(IOPATH S2 O2 (0.057::0.075)(0.171::0.226))
|
||||
(IOPATH S2 O3 (0.090::0.119)(0.251::0.330))
|
||||
(IOPATH S3 CO3 (0.106::0.140)(0.289::0.380))
|
||||
(IOPATH S3 O3 (0.054::0.071)(0.172::0.227))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_OR")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
(IOPATH SR Q (0.164::0.204)(0.638::0.791))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.105::0.131)(0.308::0.383))
|
||||
(IOPATH DI2 O3 (0.129::0.160)(0.366::0.455))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.132::0.164)(0.376::0.467))
|
||||
(IOPATH DI1 CO2 (0.160::0.199)(0.441::0.547))
|
||||
(IOPATH DI1 O2 (0.150::0.186)(0.446::0.554))
|
||||
(IOPATH DI1 O3 (0.169::0.210)(0.495::0.614))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.099::0.124)(0.244::0.303))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT_QH")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.288::0.358))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CE Q (0.130::0.162)(0.409::0.507))
|
||||
(IOPATH CLK Q (0.129::0.160)(0.357::0.443))
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF_QH")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.288::0.358))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.123::0.153)(0.355::0.440))
|
||||
(IOPATH DI1 CO2 (0.148::0.184)(0.417::0.517))
|
||||
(IOPATH DI1 O2 (0.146::0.182)(0.431::0.535))
|
||||
(IOPATH DI1 O3 (0.167::0.208)(0.481::0.596))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT_QL")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.326::0.404))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_O5")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.085::0.112)(0.250::0.329))
|
||||
(IOPATH DI0 CO1 (0.103::0.136)(0.301::0.396))
|
||||
(IOPATH DI0 CO2 (0.129::0.171)(0.360::0.474))
|
||||
(IOPATH DI0 CO3 (0.129::0.171)(0.346::0.456))
|
||||
(IOPATH DI0 O1 (0.094::0.124)(0.256::0.337))
|
||||
(IOPATH DI0 O2 (0.122::0.161)(0.369::0.486))
|
||||
(IOPATH DI0 O3 (0.143::0.189)(0.414::0.545))
|
||||
(IOPATH DI1 CO1 (0.092::0.122)(0.286::0.376))
|
||||
(IOPATH DI1 CO2 (0.118::0.156)(0.349::0.459))
|
||||
(IOPATH DI1 CO3 (0.115::0.152)(0.336::0.443))
|
||||
(IOPATH DI1 O2 (0.110::0.146)(0.358::0.471))
|
||||
(IOPATH DI1 O3 (0.131::0.174)(0.404::0.532))
|
||||
(IOPATH DI2 CO2 (0.071::0.094)(0.219::0.289))
|
||||
(IOPATH DI2 CO3 (0.088::0.116)(0.246::0.324))
|
||||
(IOPATH DI2 O3 (0.098::0.129)(0.282::0.372))
|
||||
(IOPATH DI3 CO3 (0.088::0.116)(0.248::0.327))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.112::0.139)(0.274::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.099::0.124)(0.286::0.354))
|
||||
(IOPATH DI2 O3 (0.127::0.158)(0.354::0.439))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.076::0.100)(0.204::0.268))
|
||||
(IOPATH CIN CO1 (0.044::0.055)(0.125::0.155))
|
||||
(IOPATH CIN CO2 (0.064::0.080)(0.183::0.227))
|
||||
(IOPATH CIN O0 (0.055::0.081)(0.151::0.223))
|
||||
(IOPATH CIN O1 (0.090::0.112)(0.269::0.334))
|
||||
(IOPATH CIN O2 (0.065::0.081)(0.192::0.239))
|
||||
(IOPATH CIN O3 (0.090::0.112)(0.250::0.311))
|
||||
(IOPATH CYINIT CO0 (0.165::0.206)(0.429::0.532))
|
||||
(IOPATH CYINIT CO1 (0.144::0.180)(0.395::0.491))
|
||||
(IOPATH CYINIT CO2 (0.168::0.209)(0.474::0.589))
|
||||
(IOPATH CYINIT O0 (0.148::0.184)(0.385::0.477))
|
||||
(IOPATH CYINIT O1 (0.175::0.218)(0.482::0.598))
|
||||
(IOPATH CYINIT O2 (0.167::0.208)(0.468::0.581))
|
||||
(IOPATH CYINIT O3 (0.189::0.235)(0.516::0.640))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_DX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI3 CO3 (0.113::0.140)(0.310::0.385))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF_QL")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.326::0.404))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F7AMUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.053::0.067)(0.153::0.190))
|
||||
(IOPATH 1 OUT (0.055::0.069)(0.156::0.193))
|
||||
(IOPATH S0 OUT (0.085::0.106)(0.222::0.276))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/C6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F7BMUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.062::0.077)(0.175::0.217))
|
||||
(IOPATH 1 OUT (0.065::0.081)(0.180::0.223))
|
||||
(IOPATH S0 OUT (0.093::0.115)(0.239::0.296))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F8MUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.023::0.028)(0.083::0.104))
|
||||
(IOPATH 1 OUT (0.019::0.024)(0.076::0.094))
|
||||
(IOPATH S0 OUT (0.080::0.100)(0.220::0.273))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/A5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.122::0.152))
|
||||
(IOPATH A2 O5 (0.044::0.055)(0.122::0.152))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.121::0.150))
|
||||
(IOPATH A4 O5 (0.046::0.057)(0.121::0.150))
|
||||
(IOPATH A5 O5 (0.048::0.060)(0.095::0.118))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/B6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/A6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/B5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.045::0.056)(0.122::0.152))
|
||||
(IOPATH A2 O5 (0.043::0.054)(0.122::0.152))
|
||||
(IOPATH A3 O5 (0.043::0.053)(0.122::0.152))
|
||||
(IOPATH A4 O5 (0.045::0.056)(0.121::0.150))
|
||||
(IOPATH A5 O5 (0.049::0.061)(0.096::0.119))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/D6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/D5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.120::0.149))
|
||||
(IOPATH A2 O5 (0.043::0.054)(0.121::0.150))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.120::0.149))
|
||||
(IOPATH A4 O5 (0.044::0.055)(0.120::0.149))
|
||||
(IOPATH A5 O5 (0.049::0.061)(0.094::0.117))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/C5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.124::0.154))
|
||||
(IOPATH A2 O5 (0.043::0.053)(0.124::0.154))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.123::0.153))
|
||||
(IOPATH A4 O5 (0.045::0.056)(0.123::0.153))
|
||||
(IOPATH A5 O5 (0.051::0.063)(0.097::0.120))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.113::0.140)(0.301::0.374))
|
||||
(IOPATH DI0 CO1 (0.134::0.166)(0.373::0.462))
|
||||
(IOPATH DI0 CO2 (0.158::0.197)(0.432::0.536))
|
||||
(IOPATH DI0 O1 (0.124::0.154)(0.328::0.407))
|
||||
(IOPATH DI0 O2 (0.157::0.196)(0.448::0.556))
|
||||
(IOPATH DI0 O3 (0.177::0.220)(0.496::0.615))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.112::0.139)(0.306::0.379))
|
||||
(IOPATH DI0 CO1 (0.134::0.166)(0.375::0.465))
|
||||
(IOPATH DI0 CO2 (0.160::0.199)(0.435::0.540))
|
||||
(IOPATH DI0 CO3 (0.161::0.201)(0.424::0.526))
|
||||
(IOPATH DI0 O1 (0.124::0.155)(0.328::0.407))
|
||||
(IOPATH DI0 O2 (0.157::0.196)(0.448::0.556))
|
||||
(IOPATH DI0 O3 (0.178::0.222)(0.496::0.615))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.099::0.124)(0.287::0.356))
|
||||
(IOPATH DI2 CO3 (0.117::0.146)(0.321::0.398))
|
||||
(IOPATH DI2 O3 (0.127::0.158)(0.353::0.438))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.086::0.113)(0.223::0.293))
|
||||
(IOPATH CIN CO1 (0.052::0.064)(0.143::0.178))
|
||||
(IOPATH CIN CO2 (0.075::0.094)(0.201::0.250))
|
||||
(IOPATH CIN O0 (0.057::0.085)(0.159::0.235))
|
||||
(IOPATH CIN O1 (0.098::0.122)(0.280::0.348))
|
||||
(IOPATH CIN O2 (0.070::0.087)(0.206::0.256))
|
||||
(IOPATH CIN O3 (0.092::0.114)(0.265::0.329))
|
||||
(IOPATH CYINIT CO0 (0.177::0.220)(0.466::0.578))
|
||||
(IOPATH CYINIT CO1 (0.152::0.189)(0.426::0.529))
|
||||
(IOPATH CYINIT CO2 (0.180::0.224)(0.497::0.617))
|
||||
(IOPATH CYINIT O0 (0.152::0.189)(0.395::0.491))
|
||||
(IOPATH CYINIT O1 (0.183::0.228)(0.494::0.613))
|
||||
(IOPATH CYINIT O2 (0.172::0.214)(0.483::0.600))
|
||||
(IOPATH CYINIT O3 (0.194::0.241)(0.530::0.657))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_AX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.123::0.153)(0.343::0.425))
|
||||
(IOPATH DI0 CO1 (0.142::0.177)(0.393::0.487))
|
||||
(IOPATH DI0 CO2 (0.170::0.211)(0.456::0.566))
|
||||
(IOPATH DI0 O1 (0.131::0.163)(0.338::0.420))
|
||||
(IOPATH DI0 O2 (0.160::0.200)(0.462::0.573))
|
||||
(IOPATH DI0 O3 (0.182::0.227)(0.511::0.633))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
(IOPATH SR Q (0.164::0.204)(0.638::0.791))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.124::0.154)(0.359::0.445))
|
||||
(IOPATH DI1 CO2 (0.150::0.186)(0.419::0.520))
|
||||
(IOPATH DI1 CO3 (0.147::0.183)(0.409::0.507))
|
||||
(IOPATH DI1 O2 (0.146::0.182)(0.433::0.537))
|
||||
(IOPATH DI1 O3 (0.167::0.208)(0.481::0.596))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.076::0.100)(0.206::0.271))
|
||||
(IOPATH CIN CO1 (0.045::0.056)(0.127::0.157))
|
||||
(IOPATH CIN CO2 (0.065::0.081)(0.184::0.228))
|
||||
(IOPATH CIN CO3 (0.039::0.049)(0.092::0.114))
|
||||
(IOPATH CIN O0 (0.054::0.080)(0.150::0.222))
|
||||
(IOPATH CIN O1 (0.091::0.113)(0.269::0.334))
|
||||
(IOPATH CIN O2 (0.065::0.081)(0.192::0.239))
|
||||
(IOPATH CIN O3 (0.090::0.112)(0.252::0.313))
|
||||
(IOPATH CYINIT CO0 (0.165::0.206)(0.432::0.536))
|
||||
(IOPATH CYINIT CO1 (0.144::0.180)(0.398::0.494))
|
||||
(IOPATH CYINIT CO2 (0.169::0.210)(0.477::0.592))
|
||||
(IOPATH CYINIT CO3 (0.173::0.215)(0.467::0.580))
|
||||
(IOPATH CYINIT O0 (0.147::0.183)(0.388::0.482))
|
||||
(IOPATH CYINIT O1 (0.176::0.219)(0.482::0.598))
|
||||
(IOPATH CYINIT O2 (0.167::0.208)(0.471::0.584))
|
||||
(IOPATH CYINIT O3 (0.190::0.236)(0.518::0.642))
|
||||
(IOPATH S0 CO0 (0.089::0.118)(0.258::0.340))
|
||||
(IOPATH S0 CO1 (0.118::0.156)(0.329::0.433))
|
||||
(IOPATH S0 CO2 (0.144::0.190)(0.389::0.512))
|
||||
(IOPATH S0 CO3 (0.142::0.187)(0.386::0.508))
|
||||
(IOPATH S0 O0 (0.060::0.079)(0.170::0.223))
|
||||
(IOPATH S0 O1 (0.096::0.127)(0.304::0.400))
|
||||
(IOPATH S0 O2 (0.136::0.180)(0.398::0.523))
|
||||
(IOPATH S0 O3 (0.156::0.206)(0.442::0.582))
|
||||
(IOPATH S1 CO1 (0.126::0.166)(0.356::0.469))
|
||||
(IOPATH S1 CO2 (0.153::0.202)(0.417::0.548))
|
||||
(IOPATH S1 CO3 (0.146::0.192)(0.401::0.528))
|
||||
(IOPATH S1 O1 (0.056::0.074)(0.156::0.205))
|
||||
(IOPATH S1 O2 (0.143::0.189)(0.424::0.558))
|
||||
(IOPATH S1 O3 (0.163::0.215)(0.470::0.618))
|
||||
(IOPATH S2 CO2 (0.072::0.095)(0.222::0.292))
|
||||
(IOPATH S2 CO3 (0.106::0.140)(0.286::0.376))
|
||||
(IOPATH S2 O2 (0.057::0.075)(0.171::0.226))
|
||||
(IOPATH S2 O3 (0.090::0.119)(0.251::0.330))
|
||||
(IOPATH S3 CO3 (0.106::0.140)(0.289::0.380))
|
||||
(IOPATH S3 O3 (0.054::0.071)(0.172::0.227))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_OR")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
(IOPATH SR Q (0.164::0.204)(0.638::0.791))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.105::0.131)(0.308::0.383))
|
||||
(IOPATH DI2 O3 (0.129::0.160)(0.366::0.455))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX_LBOTH")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.132::0.164)(0.376::0.467))
|
||||
(IOPATH DI1 CO2 (0.160::0.199)(0.441::0.547))
|
||||
(IOPATH DI1 O2 (0.150::0.186)(0.446::0.554))
|
||||
(IOPATH DI1 O3 (0.169::0.210)(0.495::0.614))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.099::0.124)(0.244::0.303))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT_QH")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.288::0.358))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CE Q (0.130::0.162)(0.409::0.507))
|
||||
(IOPATH CLK Q (0.129::0.160)(0.357::0.443))
|
||||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF_QH")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.288::0.358))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_BX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI1 CO1 (0.123::0.153)(0.355::0.440))
|
||||
(IOPATH DI1 CO2 (0.148::0.184)(0.417::0.517))
|
||||
(IOPATH DI1 O2 (0.146::0.182)(0.431::0.535))
|
||||
(IOPATH DI1 O3 (0.167::0.208)(0.481::0.596))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "FF_INIT_QL")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.326::0.404))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_O5")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI0 CO0 (0.085::0.112)(0.250::0.329))
|
||||
(IOPATH DI0 CO1 (0.103::0.136)(0.301::0.396))
|
||||
(IOPATH DI0 CO2 (0.129::0.171)(0.360::0.474))
|
||||
(IOPATH DI0 CO3 (0.129::0.171)(0.346::0.456))
|
||||
(IOPATH DI0 O1 (0.094::0.124)(0.256::0.337))
|
||||
(IOPATH DI0 O2 (0.122::0.161)(0.369::0.486))
|
||||
(IOPATH DI0 O3 (0.143::0.189)(0.414::0.545))
|
||||
(IOPATH DI1 CO1 (0.092::0.122)(0.286::0.376))
|
||||
(IOPATH DI1 CO2 (0.118::0.156)(0.349::0.459))
|
||||
(IOPATH DI1 CO3 (0.115::0.152)(0.336::0.443))
|
||||
(IOPATH DI1 O2 (0.110::0.146)(0.358::0.471))
|
||||
(IOPATH DI1 O3 (0.131::0.174)(0.404::0.532))
|
||||
(IOPATH DI2 CO2 (0.071::0.094)(0.219::0.289))
|
||||
(IOPATH DI2 CO3 (0.088::0.116)(0.246::0.324))
|
||||
(IOPATH DI2 O3 (0.098::0.129)(0.282::0.372))
|
||||
(IOPATH DI3 CO3 (0.088::0.116)(0.248::0.327))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.112::0.139)(0.274::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_CX_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI2 CO2 (0.099::0.124)(0.286::0.354))
|
||||
(IOPATH DI2 O3 (0.127::0.158)(0.354::0.439))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_LFF")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CIN CO0 (0.076::0.100)(0.204::0.268))
|
||||
(IOPATH CIN CO1 (0.044::0.055)(0.125::0.155))
|
||||
(IOPATH CIN CO2 (0.064::0.080)(0.183::0.227))
|
||||
(IOPATH CIN O0 (0.055::0.081)(0.151::0.223))
|
||||
(IOPATH CIN O1 (0.090::0.112)(0.269::0.334))
|
||||
(IOPATH CIN O2 (0.065::0.081)(0.192::0.239))
|
||||
(IOPATH CIN O3 (0.090::0.112)(0.250::0.311))
|
||||
(IOPATH CYINIT CO0 (0.165::0.206)(0.429::0.532))
|
||||
(IOPATH CYINIT CO1 (0.144::0.180)(0.395::0.491))
|
||||
(IOPATH CYINIT CO2 (0.168::0.209)(0.474::0.589))
|
||||
(IOPATH CYINIT O0 (0.148::0.184)(0.385::0.477))
|
||||
(IOPATH CYINIT O1 (0.175::0.218)(0.482::0.598))
|
||||
(IOPATH CYINIT O2 (0.167::0.208)(0.468::0.581))
|
||||
(IOPATH CYINIT O3 (0.189::0.235)(0.516::0.640))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4_DX")
|
||||
(INSTANCE SLICEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DI3 CO3 (0.113::0.140)(0.310::0.385))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_FF_QL")
|
||||
(INSTANCE SLICEL)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY SR (posedge CLK) (0.326::0.404))
|
||||
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F7AMUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.053::0.067)(0.153::0.190))
|
||||
(IOPATH 1 OUT (0.055::0.069)(0.156::0.193))
|
||||
(IOPATH S0 OUT (0.085::0.106)(0.222::0.276))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/C6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F7BMUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.062::0.077)(0.175::0.217))
|
||||
(IOPATH 1 OUT (0.065::0.081)(0.180::0.223))
|
||||
(IOPATH S0 OUT (0.093::0.115)(0.239::0.296))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE SLICEL/F8MUX)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.023::0.028)(0.083::0.104))
|
||||
(IOPATH 1 OUT (0.019::0.024)(0.076::0.094))
|
||||
(IOPATH S0 OUT (0.080::0.100)(0.220::0.273))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/A5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.044::0.055)(0.122::0.152))
|
||||
(IOPATH A2 O5 (0.044::0.055)(0.122::0.152))
|
||||
(IOPATH A3 O5 (0.042::0.052)(0.121::0.150))
|
||||
(IOPATH A4 O5 (0.046::0.057)(0.121::0.150))
|
||||
(IOPATH A5 O5 (0.048::0.060)(0.095::0.118))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/B6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/A6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT5")
|
||||
(INSTANCE SLICEL/B5LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O5 (0.045::0.056)(0.122::0.152))
|
||||
(IOPATH A2 O5 (0.043::0.054)(0.122::0.152))
|
||||
(IOPATH A3 O5 (0.043::0.053)(0.122::0.152))
|
||||
(IOPATH A4 O5 (0.045::0.056)(0.121::0.150))
|
||||
(IOPATH A5 O5 (0.049::0.061)(0.096::0.119))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "LUT6")
|
||||
(INSTANCE SLICEL/D6LUT)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
|
||||
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFHCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.180::0.202))
|
||||
(SETUP I (posedge I) (0.246::0.275))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.127))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_SYNC_INIT_OUT_1")
|
||||
(INSTANCE BUFHCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.180::0.202))
|
||||
(SETUP I (posedge I) (0.246::0.275))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CE O (0.069::0.076)(0.249::0.263))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFHCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.180::0.202))
|
||||
(SETUP I (posedge I) (0.246::0.275))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.127))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_SYNC_INIT_OUT_1")
|
||||
(INSTANCE BUFHCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.180::0.202))
|
||||
(SETUP I (posedge I) (0.246::0.275))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CE O (0.069::0.076)(0.249::0.263))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D9")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D5")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D3")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D0")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D4")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D7")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D2")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.367::0.422))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D8")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
|
||||
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
|
||||
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDEN (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDEN (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.030::-0.026))
|
||||
(SETUP WREN (posedge WRCLK) (0.373::0.430))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D6")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_SCANIN")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D1")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D3")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.453::0.521))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D0")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.473::0.544))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D8")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.043::-0.037))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.429::0.494))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D7")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_SCANIN")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D4")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.413::0.475))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D2")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.456::0.524))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D5")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.026::-0.023))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.404::0.465))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D1")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.496::0.571))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D6")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
|
||||
(INSTANCE IN_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
|
||||
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
|
||||
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDEN (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDEN (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WREN (posedge WRCLK) (0.461::0.530))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D9")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.040::-0.035))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.454::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D9")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D5")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D3")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D0")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D4")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D7")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D2")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.367::0.422))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D8")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
|
||||
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
|
||||
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDEN (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDEN (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.030::-0.026))
|
||||
(SETUP WREN (posedge WRCLK) (0.373::0.430))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D6")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_SCANIN")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D1")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D3")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.453::0.521))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D0")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.473::0.544))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D8")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.043::-0.037))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.429::0.494))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D7")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_SCANIN")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D4")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.413::0.475))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D2")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.456::0.524))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D5")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.026::-0.023))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.404::0.465))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D1")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.496::0.571))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D6")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
|
||||
(INSTANCE IN_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
|
||||
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
|
||||
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDEN (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDEN (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WREN (posedge WRCLK) (0.461::0.530))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D9")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.040::-0.035))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.454::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
|
||||
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
(HOLD PSCLK (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSCLK (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSINCDEC (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSINCDEC (posedge PSCLK) (0.979::1.040))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DADDR")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DI")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,531 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_PHYCTLWD")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.215::0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
|
||||
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
|
||||
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
|
||||
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.158::0.182))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTINPUT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTSELECT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DADDR")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DI")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
|
||||
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
(HOLD PSCLK (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSCLK (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSINCDEC (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSINCDEC (posedge PSCLK) (0.979::1.040))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DADDR")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DI")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,531 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_PHYCTLWD")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.215::0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
|
||||
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
|
||||
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
|
||||
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.158::0.182))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTINPUT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTSELECT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ISERDESRST (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK WRENABLE (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_PHASE_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DADDR")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DI")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.121::0.129))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.121::0.129))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT2 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.121::0.129))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.121::0.129))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT2 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.121::0.129))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.121::0.129))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT2 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.119::0.126))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TX8B10BBYPASS")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.161::0.171))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXSEQUENCE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDLEVEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.113::0.120))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPMODE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.170::0.181))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.121::0.129))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXDATA")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.173::0.184))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK2")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXRATE")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARISK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXPRBSSEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.121::0.128))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.121::0.129))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.444::0.472))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_SCANIN")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPDI")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXHEADER")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT2 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
|
||||
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
|
||||
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
|
||||
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
|
||||
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
|
||||
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
|
||||
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
|
||||
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
|
||||
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
|
||||
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
|
||||
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
|
||||
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
|
||||
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
|
||||
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
|
||||
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
|
||||
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
|
||||
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
|
||||
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
|
||||
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.105::0.111))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCHBONDEN (posedge RXUSRCLK2) (0.107::0.114))
|
||||
(SETUP RXCHBONDEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.097::0.103))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.098::0.104))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXCOMMADETEN (posedge RXUSRCLK2) (0.100::0.106))
|
||||
(SETUP RXCOMMADETEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXGEARBOXSLIP (posedge RXUSRCLK2) (0.095::0.101))
|
||||
(SETUP RXGEARBOXSLIP (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.129::0.137))
|
||||
(SETUP RXMCOMMAALIGNEN (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPOLARITY (posedge RXUSRCLK2) (0.116::0.123))
|
||||
(SETUP RXPOLARITY (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXPRBSCNTRESET (posedge RXUSRCLK2) (0.132::0.140))
|
||||
(SETUP RXPRBSCNTRESET (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.133::0.141))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.723::0.832))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (1.220::1.404))
|
||||
(HOLD RXUSRCLK2 (posedge RXUSRCLK2) (0.209::0.246))
|
||||
(SETUP RXUSRCLK2 (posedge RXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.153::0.163))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.172::0.183))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXCOMSAS (posedge TXUSRCLK2) (0.136::0.144))
|
||||
(SETUP TXCOMSAS (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDETECTRX (posedge TXUSRCLK2) (0.169::0.179))
|
||||
(SETUP TXDETECTRX (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYHOLD (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.387::0.617))
|
||||
(SETUP TXDLYUPDOWN (posedge TXPHDLYTSTCLK) (0.581::0.925))
|
||||
(HOLD TXELECIDLE (posedge TXUSRCLK2) (0.072::0.076))
|
||||
(SETUP TXELECIDLE (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXINHIBIT (posedge TXUSRCLK2) (0.153::0.162))
|
||||
(SETUP TXINHIBIT (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.143::0.152))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXPRBSFORCEERR (posedge TXUSRCLK2) (0.160::0.170))
|
||||
(SETUP TXPRBSFORCEERR (posedge TXUSRCLK2) (0.680::0.722))
|
||||
(HOLD TXSTARTSEQ (posedge TXUSRCLK2) (0.148::0.157))
|
||||
(SETUP TXSTARTSEQ (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPD")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.209::0.246))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXCHARDISPVAL")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.167::0.177))
|
||||
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.680::0.722))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_DRPADDR")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_16")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
|
||||
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL_TXUSRCLK")
|
||||
(INSTANCE GTPE2_CHANNEL)
|
||||
(TIMINGCHECK
|
||||
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
|
||||
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IBUFDS_GTE2_IBUFDS_GTE2IBUFDS_GTE2")
|
||||
(INSTANCE IBUFDS_GTE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.441::0.732)(1.616::2.684))
|
||||
(IOPATH I ODIV2 (0.441::0.732)(1.616::2.684))
|
||||
(IOPATH IB O (0.441::0.732)(1.616::2.684))
|
||||
(IOPATH IB ODIV2 (0.441::0.732)(1.616::2.684))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
|
||||
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTGREFCLK1 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTGREFCLK1 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTREFCLK0 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTREFCLK0 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTREFCLK1 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH GTREFCLK1 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK0 PMASCANOUT2 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
|
||||
(IOPATH PMASCANCLK1 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.160::0.170))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.140::0.149))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON_DRPDI")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.154::0.164))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "GTPE2_COMMON_GTPE2_COMMONGTPE2_COMMON_DRPADDR")
|
||||
(INSTANCE GTPE2_COMMON)
|
||||
(TIMINGCHECK
|
||||
(HOLD DRPCLK (posedge DRPCLK) (0.172::0.183))
|
||||
(SETUP DRPCLK (posedge DRPCLK) (0.380::0.403))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_1")
|
||||
(INSTANCE BUFMRCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.197::0.224))
|
||||
(SETUP I (posedge I) (0.172::0.195))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFMRCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.197::0.224))
|
||||
(SETUP I (posedge I) (0.172::0.195))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE")
|
||||
(INSTANCE BUFMRCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.033::0.035)(0.097::0.103))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_1")
|
||||
(INSTANCE BUFMRCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.197::0.224))
|
||||
(SETUP I (posedge I) (0.172::0.195))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFMRCE)
|
||||
(TIMINGCHECK
|
||||
(HOLD I (posedge I) (0.197::0.224))
|
||||
(SETUP I (posedge I) (0.172::0.195))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE")
|
||||
(INSTANCE BUFMRCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.033::0.035)(0.097::0.103))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFIO_DELAY_BYPASS_TRUE")
|
||||
(INSTANCE BUFIO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.032::0.038)(0.294::0.400))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFIO_DELAY_BYPASS_FALSE")
|
||||
(INSTANCE BUFIO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.483::0.516)(1.431::1.532))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_2")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_BYPASS")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.092::0.254)(0.486::0.511))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_3")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_6")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_7")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_1")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_4")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_5")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFR_BUFR_DIVIDE_8")
|
||||
(INSTANCE BUFR)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLR O (0.273::0.314)(0.942::1.084))
|
||||
(IOPATH I O (0.270::0.431)(0.918::0.982))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYCTRL")
|
||||
(INSTANCE IDELAYCTRL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RST RDY (2569.982::2956.512)(3184.543::3663.504))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33S_INBUF_ENIOB33_IOBS_INBUF_EN")
|
||||
(INSTANCE IOB33S)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.340::0.391)(1.027::1.182))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
|
||||
(INSTANCE IOB33M)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.016::1.169))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
(INSTANCE IOB33)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.697::0.873))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH D1 Q (0.513::0.590)(0.989::1.138))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.352::0.405))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH D1 Q (0.488::0.561)(0.904::1.040))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.449::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VARIABLE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.108::0.116))
|
||||
(SETUP C (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
(SETUP REGRST (posedge C) (0.158::0.172))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DATAIN DATAOUT (0.278::0.392)(0.899::1.012))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_IDATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IDATAIN DATAOUT (0.243::0.305)(0.755::0.815))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP CK (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.064::0.080)(0.177::0.219))
|
||||
(IOPATH 1 OUT (0.066::0.082)(0.181::0.225))
|
||||
(IOPATH S0 OUT (0.096::0.120)(0.253::0.314))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_FF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CK (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_PIPELINED")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_LAT")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.087::0.100)(0.225::0.259))
|
||||
(IOPATH D Q1 (0.080::0.092)(0.215::0.247))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.656::0.755))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_OPPEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CKB Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.697::0.873))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH D1 Q (0.513::0.590)(0.989::1.138))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.352::0.405))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH D1 Q (0.488::0.561)(0.904::1.040))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.449::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VARIABLE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.108::0.116))
|
||||
(SETUP C (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
(SETUP REGRST (posedge C) (0.158::0.172))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DATAIN DATAOUT (0.278::0.392)(0.899::1.012))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_IDATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IDATAIN DATAOUT (0.243::0.305)(0.755::0.815))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP CK (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.064::0.080)(0.177::0.219))
|
||||
(IOPATH 1 OUT (0.066::0.082)(0.181::0.225))
|
||||
(IOPATH S0 OUT (0.096::0.120)(0.253::0.314))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_FF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CK (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_PIPELINED")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_LAT")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.087::0.100)(0.225::0.259))
|
||||
(IOPATH D Q1 (0.080::0.092)(0.215::0.247))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.656::0.755))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_OPPEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CKB Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.697::0.873))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH D1 Q (0.513::0.590)(0.989::1.138))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.352::0.405))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH D1 Q (0.488::0.561)(0.904::1.040))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.449::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VARIABLE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.108::0.116))
|
||||
(SETUP C (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
(SETUP REGRST (posedge C) (0.158::0.172))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DATAIN DATAOUT (0.278::0.392)(0.899::1.012))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_IDATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IDATAIN DATAOUT (0.243::0.305)(0.755::0.815))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP CK (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.064::0.080)(0.177::0.219))
|
||||
(IOPATH 1 OUT (0.066::0.082)(0.181::0.225))
|
||||
(IOPATH S0 OUT (0.096::0.120)(0.253::0.314))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_FF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CK (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_PIPELINED")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_LAT")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.087::0.100)(0.225::0.259))
|
||||
(IOPATH D Q1 (0.080::0.092)(0.215::0.247))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.656::0.755))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_OPPEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CKB Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.697::0.873))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH D1 Q (0.513::0.590)(0.989::1.138))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.352::0.405))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH D1 Q (0.488::0.561)(0.904::1.040))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.449::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VARIABLE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.108::0.116))
|
||||
(SETUP C (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
(SETUP REGRST (posedge C) (0.158::0.172))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DATAIN DATAOUT (0.278::0.392)(0.899::1.012))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_IDATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IDATAIN DATAOUT (0.243::0.305)(0.755::0.815))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP CK (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.064::0.080)(0.177::0.219))
|
||||
(IOPATH 1 OUT (0.066::0.082)(0.181::0.225))
|
||||
(IOPATH S0 OUT (0.096::0.120)(0.253::0.314))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_FF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CK (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_PIPELINED")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_LAT")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.087::0.100)(0.225::0.259))
|
||||
(IOPATH D Q1 (0.080::0.092)(0.215::0.247))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.656::0.755))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_OPPEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CKB Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DI")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.009::0.010))
|
||||
(SETUP DCLK (posedge DCLK) (0.610::0.648))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DADDR")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.002::0.017))
|
||||
(SETUP DCLK (posedge DCLK) (0.659::0.699))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC")
|
||||
(INSTANCE XADC)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK BUSY (0.301::0.319)(1.218::1.294))
|
||||
(IOPATH DCLK DRDY (0.256::0.272)(1.132::1.204))
|
||||
(IOPATH DCLK EOC (0.379::0.403)(1.437::1.527))
|
||||
(IOPATH DCLK EOS (0.288::0.306)(1.231::1.309))
|
||||
(IOPATH DCLK JTAGBUSY (0.334::0.354)(1.331::1.415))
|
||||
(IOPATH DCLK JTAGLOCKED (0.276::0.294)(1.190::1.264))
|
||||
(IOPATH DCLK JTAGMODIFIED (0.273::0.289)(1.177::1.251))
|
||||
(IOPATH DCLK OT (0.301::0.319)(1.269::1.349))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DEN (posedge DCLK) (-0.025::-0.013))
|
||||
(SETUP DEN (posedge DCLK) (0.800::0.848))
|
||||
(HOLD DWE (posedge DCLK) (-0.022::-0.005))
|
||||
(SETUP DWE (posedge DCLK) (0.531::0.565))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33S_INBUF_ENIOB33_IOBS_INBUF_EN")
|
||||
(INSTANCE IOB33S)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.340::0.391)(1.027::1.182))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
|
||||
(INSTANCE IOB33M)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.016::1.169))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
(INSTANCE IOB33)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.697::0.873))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.192::0.221)(0.480::0.552))
|
||||
(IOPATH D1 Q (0.513::0.590)(0.989::1.138))
|
||||
(IOPATH SR Q (0.328::0.377)(0.916::1.054))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.352::0.405))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_LAT")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.411::0.472))
|
||||
(IOPATH D1 Q (0.488::0.561)(0.904::1.040))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_FF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.177::0.204)(0.449::0.472))
|
||||
(IOPATH SR Q (0.301::0.346)(0.821::0.945))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VARIABLE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.108::0.116))
|
||||
(SETUP C (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
(SETUP REGRST (posedge C) (0.158::0.172))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.143::0.155))
|
||||
(SETUP C (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD C (posedge C) (0.131::0.141))
|
||||
(SETUP C (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DATAIN DATAOUT (0.278::0.392)(0.899::1.012))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_IDATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IDATAIN DATAOUT (0.243::0.305)(0.755::0.815))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_RECOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(SETUP CK (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "SELMUX2_1")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH 0 OUT (0.064::0.080)(0.177::0.219))
|
||||
(IOPATH 1 OUT (0.066::0.082)(0.181::0.225))
|
||||
(IOPATH S0 OUT (0.096::0.120)(0.253::0.314))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_FF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_DDR")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CKB (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CKB (posedge CKB) (0.430::0.726))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD CKB (posedge CKB) (0.022::0.026))
|
||||
(SETUP CKB (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CK (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_PIPELINED")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CK Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_LAT")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.087::0.100)(0.225::0.259))
|
||||
(IOPATH D Q1 (0.080::0.092)(0.215::0.247))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.656::0.755))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_OPPEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CK Q1 (0.060::0.069)(0.153::0.176))
|
||||
(IOPATH CKB Q2 (0.059::0.067)(0.145::0.167))
|
||||
(IOPATH SR Q1 (0.200::0.230)(0.665::0.765))
|
||||
(IOPATH SR Q2 (0.200::0.230)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue