Updating all based on "Merge pull request #1165 from antmicro/fix-lioi-ppips".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
parent
8e1506dffa
commit
d0e4646dcb
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Info.md
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Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
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# Details
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Last updated on Thu 05 Dec 2019 04:51:54 AM UTC (2019-12-05T04:51:54+00:00).
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Last updated on Fri 06 Dec 2019 10:11:16 PM UTC (2019-12-06T22:11:16+00:00).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [e328dbdc](https://github.com/SymbiFlow/prjxray/commit/e328dbdc146089b6d041c273278419ca9f315374).
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Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [446feafb](https://github.com/SymbiFlow/prjxray/commit/446feafbd162bf0de1b545fa64e8555d0d5c10e3).
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Latest commit was;
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```
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commit e328dbdc146089b6d041c273278419ca9f315374
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Merge: da33c299 24070da9
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Author: Tomasz Michalak <tmichalak@antmicro.com>
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Date: Mon Dec 2 22:00:22 2019 +0100
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commit 446feafbd162bf0de1b545fa64e8555d0d5c10e3
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Merge: 4628234e 9401d1c7
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Author: Tim Ansell <me@mith.ro>
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Date: Thu Dec 5 17:53:32 2019 -0800
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Merge pull request #1149 from antmicro/xdc_plugin_integration
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Merge pull request #1165 from antmicro/fix-lioi-ppips
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001-part-yaml: Add iobanks information to part's json
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071-ppips: fix wrong ppip in ioi tiles
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```
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@ -59,7 +59,7 @@ Date: Mon Dec 2 22:00:22 2019 +0100
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### Settings
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/e328dbdc146089b6d041c273278419ca9f315374/settings/artix7.sh)
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Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/446feafbd162bf0de1b545fa64e8555d0d5c10e3/settings/artix7.sh)
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```shell
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export XRAY_DATABASE="artix7"
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export XRAY_PART="xc7a50tfgg484-1"
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@ -203,14 +203,14 @@ Results have checksums;
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_int_r.origin_info.db`](./artix7/ppips_int_r.origin_info.db)
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* [`916e3cea00e0bf8291ae24083696833dc1ff09f06562eccba6f2c73afd267ccb ./artix7/ppips_io_int_interface_l.db`](./artix7/ppips_io_int_interface_l.db)
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* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./artix7/ppips_io_int_interface_r.db`](./artix7/ppips_io_int_interface_r.db)
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* [`b155fbb8d964a2c3359a8420c0a6fd11aafccaeee92034e78cd16d2c56d4fcf9 ./artix7/ppips_lioi3.db`](./artix7/ppips_lioi3.db)
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* [`fbe2cd3174bcec467e55558c497717480808149193c2ee80b51be78580356385 ./artix7/ppips_lioi3_sing.db`](./artix7/ppips_lioi3_sing.db)
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* [`a28a9783e37b9768245b5e48bcf5876b1c625093544b2cce9408d4d3a846cdf3 ./artix7/ppips_lioi3_tbytesrc.db`](./artix7/ppips_lioi3_tbytesrc.db)
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* [`f6bd429fc3898e869c3177de090df1c3344810738c9f9cf9babe40330b6a6f62 ./artix7/ppips_lioi3_tbyteterm.db`](./artix7/ppips_lioi3_tbyteterm.db)
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* [`df11ac1c71eefa9c06abe06bc932d36368977543fba9666ee1b36e8417cd9f78 ./artix7/ppips_rioi3.db`](./artix7/ppips_rioi3.db)
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* [`0c6263c13669085c09a61f25d68786d8f6c9b12b162fe2cd6c9a50114106f739 ./artix7/ppips_rioi3_sing.db`](./artix7/ppips_rioi3_sing.db)
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* [`76c5978b345f11a9e46733a98875a6c419b75cf863a0e42d05e9ac94f9795bfc ./artix7/ppips_rioi3_tbytesrc.db`](./artix7/ppips_rioi3_tbytesrc.db)
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* [`a9705cd0ffc8f972a6c0981d65b200a93f0b0069327133bad2aff80a6fce08ab ./artix7/ppips_rioi3_tbyteterm.db`](./artix7/ppips_rioi3_tbyteterm.db)
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* [`ac23765307613b28b2a294e5ebbea583280bcb84511237000c788c9834730323 ./artix7/ppips_lioi3.db`](./artix7/ppips_lioi3.db)
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* [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./artix7/ppips_lioi3_sing.db`](./artix7/ppips_lioi3_sing.db)
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* [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./artix7/ppips_lioi3_tbytesrc.db`](./artix7/ppips_lioi3_tbytesrc.db)
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* [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./artix7/ppips_lioi3_tbyteterm.db`](./artix7/ppips_lioi3_tbyteterm.db)
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* [`5c818ae170303c8f215cb08e33f6682eb18e4c1b142da8c86e209d80199f6512 ./artix7/ppips_rioi3.db`](./artix7/ppips_rioi3.db)
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* [`bb65252c9f425d9b6eee636057f458b5b7548ee47228127f29afe0e7e5878682 ./artix7/ppips_rioi3_sing.db`](./artix7/ppips_rioi3_sing.db)
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* [`fe8fe52b167f239f3d28ffc0c1f4dd35de5ad2572526ad79500ac2cf89a5dfb2 ./artix7/ppips_rioi3_tbytesrc.db`](./artix7/ppips_rioi3_tbytesrc.db)
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* [`f2e01a0371694c49d9f6d975767416b5e429058874a0d2ab54567584b6a9e7b7 ./artix7/ppips_rioi3_tbyteterm.db`](./artix7/ppips_rioi3_tbyteterm.db)
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* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
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* [`65b0fa7162231e9d1a9e30c64e9aad87bb3b8feaa40cf76055f96a7750d1e1da ./artix7/segbits_bram_l.block_ram.origin_info.db`](./artix7/segbits_bram_l.block_ram.origin_info.db)
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* [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
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@ -258,9 +258,9 @@ Results have checksums;
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* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
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* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
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* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
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* [`fc16202d0a1e4c9a5fcb581078f348fde9c01761227e6137989d5d843139fc67 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
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* [`feb026793ea454a0aaf9eff9dc5526251a83e599943a8ed44d740e26ea0e0c67 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
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* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
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* [`a0cf90ee8e081a6fcc85be955d3156c32327111428c614c63e13892eb0cb31ba ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
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* [`6f685c08a62b2a61cd705ab14741ed64c347c9c1277de4e33aa45e9caa55875d ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
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* [`92913f6d38cfdb14fb9c16e70a47d75e507c0ee4764bcc7941f2e0ac3e784e88 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
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* [`2772dce8b6a4f6f6691ca0c0b30535c230041ebad17d318ce9962161e607be5c ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
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* [`cf4f6a2b44d13e094f588464a902c315080d2150a522e4241c82ca201a4771e0 ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
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@ -499,7 +499,7 @@ Results have checksums;
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### Settings
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Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/e328dbdc146089b6d041c273278419ca9f315374/settings/kintex7.sh)
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Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/446feafbd162bf0de1b545fa64e8555d0d5c10e3/settings/kintex7.sh)
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```shell
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export XRAY_DATABASE="kintex7"
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export XRAY_PART="xc7k70tfbg676-2"
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@ -621,10 +621,10 @@ Results have checksums;
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_int_r.origin_info.db`](./kintex7/ppips_int_r.origin_info.db)
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* [`916e3cea00e0bf8291ae24083696833dc1ff09f06562eccba6f2c73afd267ccb ./kintex7/ppips_io_int_interface_l.db`](./kintex7/ppips_io_int_interface_l.db)
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* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./kintex7/ppips_io_int_interface_r.db`](./kintex7/ppips_io_int_interface_r.db)
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* [`b155fbb8d964a2c3359a8420c0a6fd11aafccaeee92034e78cd16d2c56d4fcf9 ./kintex7/ppips_lioi3.db`](./kintex7/ppips_lioi3.db)
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* [`fbe2cd3174bcec467e55558c497717480808149193c2ee80b51be78580356385 ./kintex7/ppips_lioi3_sing.db`](./kintex7/ppips_lioi3_sing.db)
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* [`a28a9783e37b9768245b5e48bcf5876b1c625093544b2cce9408d4d3a846cdf3 ./kintex7/ppips_lioi3_tbytesrc.db`](./kintex7/ppips_lioi3_tbytesrc.db)
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* [`f6bd429fc3898e869c3177de090df1c3344810738c9f9cf9babe40330b6a6f62 ./kintex7/ppips_lioi3_tbyteterm.db`](./kintex7/ppips_lioi3_tbyteterm.db)
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* [`ac23765307613b28b2a294e5ebbea583280bcb84511237000c788c9834730323 ./kintex7/ppips_lioi3.db`](./kintex7/ppips_lioi3.db)
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* [`f87e449ccf9c605acad950269bfe104bc3a45daf79c5b7fe21042169feb7a428 ./kintex7/ppips_lioi3_sing.db`](./kintex7/ppips_lioi3_sing.db)
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* [`1046256199fd3c54a5f3ee7e5ec7fd72863882e01cc8da326e487c763159e2f8 ./kintex7/ppips_lioi3_tbytesrc.db`](./kintex7/ppips_lioi3_tbytesrc.db)
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* [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./kintex7/ppips_lioi3_tbyteterm.db`](./kintex7/ppips_lioi3_tbyteterm.db)
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* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
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* [`65b0fa7162231e9d1a9e30c64e9aad87bb3b8feaa40cf76055f96a7750d1e1da ./kintex7/segbits_bram_l.block_ram.origin_info.db`](./kintex7/segbits_bram_l.block_ram.origin_info.db)
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* [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
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@ -671,10 +671,10 @@ Results have checksums;
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* [`39179dfde43c6dd677c705082e1e7373d1866390cae064062f6eee50e7cd6ef6 ./kintex7/segbits_hclk_l.origin_info.db`](./kintex7/segbits_hclk_l.origin_info.db)
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* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
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* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
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* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
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* [`5652347f1d8ebe99a29e2968092e6343ea250d8e61987546481abb17e5256314 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
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* [`03aa672e2db508d5b6360d8f82adbbee6c88f322d18f0d943d5f210b2218305d ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
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* [`1304da4d4096114b30b8c7fceaf1dfba573a661c2bb54d6ace65abe22d6736f6 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
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* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
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* [`b201e749296cdf898553f09f3d5250978277341febf79dfcaf6f709923803095 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
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* [`5379f28d0dd5eabc54aea4e7a7ff0ae396346914498d9371540fdeec04679c52 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
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* [`01cd7426da888ca40c5cc422a29fa9daf3d8de1901ed32ea118abd41def9d3da ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
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* [`1c214645a8a02faacd8f463ba93414ce37f082a56095eee55b39fadea2169d07 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
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* [`87adc9bb57b446e57722145e6461085763a5f0e690558e96c2581ea623b36071 ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
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|
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@ -867,7 +867,7 @@ Results have checksums;
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### Settings
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Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/e328dbdc146089b6d041c273278419ca9f315374/settings/zynq7.sh)
|
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Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/446feafbd162bf0de1b545fa64e8555d0d5c10e3/settings/zynq7.sh)
|
||||
```shell
|
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export XRAY_DATABASE="zynq7"
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export XRAY_PART="xc7z010clg400-1"
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|
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@ -938,13 +938,13 @@ Results have checksums;
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|||
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_l.origin_info.db`](./zynq7/mask_hclk_l.origin_info.db)
|
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* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
|
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* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
|
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
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* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
|
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* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
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* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
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* [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
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* [`ef9b9da062595ad50cd2196544a408ec48b7f51c2ffe6178bb2dbc1e48bc8eb7 ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
|
||||
* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
|
||||
* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
|
||||
* [`743cdc097240c723f8c04e87d15d63d2b678bae444b94160279580acfad50022 ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
|
||||
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
|
||||
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
|
||||
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
|
||||
|
|
@ -986,10 +986,10 @@ Results have checksums;
|
|||
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./zynq7/ppips_int_r.db`](./zynq7/ppips_int_r.db)
|
||||
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_int_r.origin_info.db`](./zynq7/ppips_int_r.origin_info.db)
|
||||
* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./zynq7/ppips_io_int_interface_r.db`](./zynq7/ppips_io_int_interface_r.db)
|
||||
* [`df11ac1c71eefa9c06abe06bc932d36368977543fba9666ee1b36e8417cd9f78 ./zynq7/ppips_rioi3.db`](./zynq7/ppips_rioi3.db)
|
||||
* [`0c6263c13669085c09a61f25d68786d8f6c9b12b162fe2cd6c9a50114106f739 ./zynq7/ppips_rioi3_sing.db`](./zynq7/ppips_rioi3_sing.db)
|
||||
* [`76c5978b345f11a9e46733a98875a6c419b75cf863a0e42d05e9ac94f9795bfc ./zynq7/ppips_rioi3_tbytesrc.db`](./zynq7/ppips_rioi3_tbytesrc.db)
|
||||
* [`a9705cd0ffc8f972a6c0981d65b200a93f0b0069327133bad2aff80a6fce08ab ./zynq7/ppips_rioi3_tbyteterm.db`](./zynq7/ppips_rioi3_tbyteterm.db)
|
||||
* [`5c818ae170303c8f215cb08e33f6682eb18e4c1b142da8c86e209d80199f6512 ./zynq7/ppips_rioi3.db`](./zynq7/ppips_rioi3.db)
|
||||
* [`bb65252c9f425d9b6eee636057f458b5b7548ee47228127f29afe0e7e5878682 ./zynq7/ppips_rioi3_sing.db`](./zynq7/ppips_rioi3_sing.db)
|
||||
* [`fe8fe52b167f239f3d28ffc0c1f4dd35de5ad2572526ad79500ac2cf89a5dfb2 ./zynq7/ppips_rioi3_tbytesrc.db`](./zynq7/ppips_rioi3_tbytesrc.db)
|
||||
* [`f2e01a0371694c49d9f6d975767416b5e429058874a0d2ab54567584b6a9e7b7 ./zynq7/ppips_rioi3_tbyteterm.db`](./zynq7/ppips_rioi3_tbyteterm.db)
|
||||
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db)
|
||||
* [`65b0fa7162231e9d1a9e30c64e9aad87bb3b8feaa40cf76055f96a7750d1e1da ./zynq7/segbits_bram_l.block_ram.origin_info.db`](./zynq7/segbits_bram_l.block_ram.origin_info.db)
|
||||
* [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
|
||||
|
|
@ -1035,9 +1035,9 @@ Results have checksums;
|
|||
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
|
||||
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
|
||||
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
|
||||
* [`603f7787b460ffa02ef3bd96978ea5a7bd23e0a51f5fb0fbff714b36d8975ba8 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
|
||||
* [`76c765043f01407bde4ed9a016c6f883e7c038f86bf4ad4c6ee93a417a8d9cc9 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
|
||||
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
|
||||
* [`6a5b30cccebf475562df27f63c1a26e276c1bce15142ec9d66020a7c5df4167b ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
|
||||
* [`1dbea85bbb2d14151d6b0861b1f4c474278d250c2d8eab03c5b97375fc603f0e ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
|
||||
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
|
||||
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
|
||||
* [`cf4f6a2b44d13e094f588464a902c315080d2150a522e4241c82ca201a4771e0 ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
|
||||
|
|
|
|||
|
|
@ -131,9 +131,7 @@ LIOI3.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ LIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
|
|||
LIOI3_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
|
||||
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
|
||||
LIOI3_SING.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_SING.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -124,9 +124,7 @@ LIOI3_TBYTESRC.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -122,9 +122,7 @@ LIOI3_TBYTETERM.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3_TBYTETERM.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_TBYTETERM.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3_TBYTETERM.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -131,9 +131,7 @@ RIOI3.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ RIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
|
|||
RIOI3_SING.RIOI_DCI_T_TERM0.IOI_IMUX6_0 always
|
||||
RIOI3_SING.RIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
|
||||
RIOI3_SING.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_SING.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_SING.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_SING.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_SING.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -124,9 +124,7 @@ RIOI3_TBYTESRC.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3_TBYTESRC.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3_TBYTESRC.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_TBYTESRC.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3_TBYTESRC.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_TBYTESRC.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -122,9 +122,7 @@ RIOI3_TBYTETERM.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3_TBYTETERM.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3_TBYTETERM.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_TBYTETERM.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3_TBYTETERM.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_TBYTETERM.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -172,7 +172,7 @@ INT_L.BYP_ALT7.EE2END3 origin:050-pip-seed !22_63 !23_63 !25_63 17_63 24_63
|
|||
INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
|
||||
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
|
||||
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
|
||||
|
|
@ -373,7 +373,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
|
|||
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
|
||||
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
|
||||
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
|
||||
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
|
||||
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
|
||||
INT_L.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
|
||||
INT_L.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
|
||||
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
|
||||
|
|
@ -413,7 +413,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
|
|||
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
|
||||
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
|
||||
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
|
||||
INT_L.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
|
||||
INT_L.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
|
||||
INT_L.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
|
||||
|
|
@ -2431,7 +2431,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
|
|||
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
|
||||
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
|
||||
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
|
||||
INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
|
||||
INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
|
||||
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
|
||||
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
|
||||
INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
|
||||
|
|
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
|
|||
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
|
||||
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
|
||||
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
|
||||
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
|
||||
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
|
||||
|
|
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
|
|||
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
|
||||
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
|
||||
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
|
||||
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
|
||||
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
|
||||
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
|
|||
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
|
||||
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
|
||||
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
|
||||
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
|
||||
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
|
||||
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
|
||||
|
|
@ -584,7 +584,7 @@ INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
|
|||
INT_R.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
|
||||
INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
|
||||
INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
|
||||
INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
|
||||
INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
|
||||
INT_R.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
|
||||
INT_R.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
|
||||
INT_R.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
|
||||
|
|
@ -2431,7 +2431,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
|
|||
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
|
||||
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
|
||||
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
|
||||
INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
|
||||
INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
|
||||
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
|
||||
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
|
||||
INT_R.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
|
||||
|
|
@ -3295,7 +3295,7 @@ INT_R.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
|
|||
INT_R.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
|
||||
INT_R.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
|
||||
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
|
||||
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
|
||||
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
|
||||
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
|
||||
INT_R.SW6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_60 07_61
|
||||
INT_R.SW6BEG3.LOGIC_OUTS15 origin:050-pip-seed 03_60 04_62
|
||||
|
|
@ -3563,7 +3563,7 @@ INT_R.WW4BEG0.LOGIC_OUTS4 origin:050-pip-seed 02_01 07_01
|
|||
INT_R.WW4BEG0.LOGIC_OUTS8 origin:050-pip-seed 03_00 07_01
|
||||
INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
|
||||
INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
|
||||
INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
|
||||
INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
|
||||
INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
|
||||
INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
|
||||
INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
|
||||
|
|
|
|||
|
|
@ -131,9 +131,7 @@ LIOI3.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ LIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
|
|||
LIOI3_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
|
||||
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
|
||||
LIOI3_SING.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_SING.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -124,9 +124,7 @@ LIOI3_TBYTESRC.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -122,9 +122,7 @@ LIOI3_TBYTETERM.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
LIOI3_TBYTETERM.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
LIOI3_TBYTETERM.LIOI_I0.LIOI_IBUF0 always
|
||||
LIOI3_TBYTETERM.LIOI_I1.LIOI_IBUF1 always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
|
||||
LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
|
||||
LIOI3_TBYTETERM.LIOI_ILOGIC0_D.LIOI_I0 always
|
||||
LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -1500,7 +1500,7 @@ INT_L.IMUX_L42.FAN_BOUNCE1 20_22 !22_22 23_22 24_22 25_22
|
|||
INT_L.IMUX_L42.FAN_BOUNCE7 20_22 22_22 !23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L5 21_22 22_22 !23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L9 21_22 !22_22 23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L19 21_22 !22_22 !23_22 24_22 !25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L19 20_08 21_22 !22_22 !23_22 24_22 !25_22
|
||||
INT_L.IMUX_L42.SR1BEG_S0 16_22 22_22 !23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.EE2END1 16_22 !22_22 !23_22 !24_22 25_22
|
||||
INT_L.IMUX_L42.EL1END1 18_23 !22_22 23_22 24_22 25_22
|
||||
|
|
@ -1524,7 +1524,7 @@ INT_L.IMUX_L43.FAN_BOUNCE3 20_30 !22_30 23_30 24_30 25_30
|
|||
INT_L.IMUX_L43.FAN_BOUNCE5 20_30 22_30 !23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L1 21_30 22_30 !23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L13 21_30 !22_30 23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L23 21_30 !22_30 !23_30 24_30 !25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L23 20_08 21_30 !22_30 !23_30 24_30 !25_30
|
||||
INT_L.IMUX_L43.EE2END1 19_31 !22_30 !23_30 !24_30 25_30
|
||||
INT_L.IMUX_L43.EL1END2 19_31 !22_30 23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.ER1END1 18_31 22_30 !23_30 24_30 25_30
|
||||
|
|
|
|||
|
|
@ -413,7 +413,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
|
|||
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
|
||||
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
|
||||
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
|
||||
INT_L.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
|
||||
INT_L.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
|
||||
INT_L.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
|
||||
|
|
@ -676,9 +676,9 @@ INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
|
|||
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
|
||||
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
|
||||
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
|
||||
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
|
||||
INT_L.FAN_ALT4.NE2END0 origin:050-pip-seed !22_08 !23_08 !25_08 17_08 24_08
|
||||
|
|
@ -1694,7 +1694,7 @@ INT_L.IMUX_L42.ER1END1 origin:050-pip-seed !23_22 19_23 22_22 24_22 25_22
|
|||
INT_L.IMUX_L42.FAN_BOUNCE1 origin:050-pip-seed !22_22 20_22 23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.FAN_BOUNCE7 origin:050-pip-seed !23_22 20_22 22_22 24_22 25_22
|
||||
INT_L.IMUX_L42.GFAN0 origin:049-int-imux-gfan !22_22 !23_22 !24_22 21_22 25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 21_22 24_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 20_08 21_22 24_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
|
||||
INT_L.IMUX_L42.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
|
||||
INT_L.IMUX_L42.NE2END1 origin:050-pip-seed !22_22 !23_22 !25_22 17_22 24_22
|
||||
|
|
@ -1720,7 +1720,7 @@ INT_L.IMUX_L43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
|
|||
INT_L.IMUX_L43.GFAN0 origin:049-int-imux-gfan !22_30 !23_30 !24_30 21_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
|
||||
INT_L.IMUX_L43.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 20_08 21_30 24_30
|
||||
INT_L.IMUX_L43.NE2END2 origin:050-pip-seed !22_30 !23_30 !25_30 18_31 24_30
|
||||
INT_L.IMUX_L43.NL1END2 origin:050-pip-seed !22_30 16_30 23_30 24_30 25_30
|
||||
INT_L.IMUX_L43.NN2END2 origin:050-pip-seed !22_30 !23_30 !24_30 18_31 25_30
|
||||
|
|
@ -2191,7 +2191,7 @@ INT_L.NE6BEG3.NN6END3 origin:050-pip-seed 03_53 06_52
|
|||
INT_L.NE6BEG3.NW2END3 origin:050-pip-seed 02_53 04_53
|
||||
INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
|
||||
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
|
||||
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
|
||||
INT_L.NE6BEG3.SE6END3 origin:056-pip-rem 05_55 06_52
|
||||
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
|
||||
INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
|
||||
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
|
||||
|
|
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
|
|||
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
|
||||
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
|
||||
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
|
||||
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
|
||||
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
|
||||
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
|
||||
|
|
|
|||
|
|
@ -373,7 +373,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
|
|||
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
|
||||
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
|
||||
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
|
||||
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
|
||||
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
|
||||
INT_R.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
|
||||
INT_R.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
|
||||
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
|
||||
|
|
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
|
|||
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
|
||||
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
|
||||
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
|
||||
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
|
||||
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
|
||||
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
|
||||
|
|
@ -413,7 +413,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
|
|||
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
|
||||
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
|
||||
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
|
||||
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
|
||||
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
|
||||
INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
|
||||
INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
|
||||
INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
|
||||
|
|
@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
|
|||
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
|
||||
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
|
||||
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
|
||||
INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
|
||||
INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
|
||||
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
|
||||
INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17
|
||||
INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
bit 25_00
|
||||
bit 25_07
|
||||
bit 25_16
|
||||
bit 25_20
|
||||
bit 25_21
|
||||
bit 25_23
|
||||
bit 25_24
|
||||
bit 25_31
|
||||
bit 25_32
|
||||
|
|
@ -21,6 +21,7 @@ bit 25_95
|
|||
bit 25_96
|
||||
bit 25_98
|
||||
bit 25_99
|
||||
bit 25_103
|
||||
bit 25_111
|
||||
bit 25_115
|
||||
bit 25_116
|
||||
|
|
|
|||
|
|
@ -131,9 +131,7 @@ RIOI3.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ RIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
|
|||
RIOI3_SING.RIOI_DCI_T_TERM0.IOI_IMUX6_0 always
|
||||
RIOI3_SING.RIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
|
||||
RIOI3_SING.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_SING.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_SING.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_SING.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_SING.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -124,9 +124,7 @@ RIOI3_TBYTESRC.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3_TBYTESRC.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3_TBYTESRC.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_TBYTESRC.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3_TBYTESRC.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3_TBYTESRC.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_TBYTESRC.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -122,9 +122,7 @@ RIOI3_TBYTETERM.RIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
|
|||
RIOI3_TBYTETERM.RIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
|
||||
RIOI3_TBYTETERM.RIOI_I0.RIOI_IBUF0 always
|
||||
RIOI3_TBYTETERM.RIOI_I1.RIOI_IBUF1 always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY0_DATAOUT.RIOI_IDELAY0_IDATAIN always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY0_IDATAIN.RIOI_I0 always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY1_DATAOUT.RIOI_IDELAY1_IDATAIN always
|
||||
RIOI3_TBYTETERM.RIOI_IDELAY1_IDATAIN.RIOI_I1 always
|
||||
RIOI3_TBYTETERM.RIOI_ILOGIC0_D.RIOI_I0 always
|
||||
RIOI3_TBYTETERM.RIOI_ILOGIC0_DDLY.RIOI_IDELAY0_DATAOUT always
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
|
|||
INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
|
||||
INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
|
||||
INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
|
||||
INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
|
||||
INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
|
||||
INT_L.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
|
||||
INT_L.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
|
||||
INT_L.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
|
||||
|
|
@ -413,7 +413,7 @@ INT_L.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
|
|||
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
|
||||
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
|
||||
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
|
||||
INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
|
||||
INT_L.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
|
||||
INT_L.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
|
||||
INT_L.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
|
||||
|
|
@ -2431,7 +2431,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
|
|||
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
|
||||
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
|
||||
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
|
||||
INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
|
||||
INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
|
||||
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
|
||||
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
|
||||
INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
|
||||
|
|
@ -2609,7 +2609,7 @@ INT_L.NW6BEG0.NN6END0 origin:050-pip-seed 05_02 07_03
|
|||
INT_L.NW6BEG0.NW2END0 origin:050-pip-seed 02_02 03_02
|
||||
INT_L.NW6BEG0.NW6END0 origin:050-pip-seed 02_02 07_03
|
||||
INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
|
||||
INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
|
||||
INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
|
||||
INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
|
||||
INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
|
||||
INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
|
||||
|
|
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
|
|||
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
|
||||
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
|
||||
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
|
||||
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
|
||||
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
|
||||
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
|
||||
|
|
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
|
|||
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
|
||||
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
|
||||
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
|
||||
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
|
||||
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
|
||||
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
|
||||
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
|
||||
|
|
|
|||
|
|
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
|
|||
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
|
||||
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
|
||||
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
|
||||
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
|
||||
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
|
||||
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
|
||||
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
|
||||
|
|
@ -676,7 +676,7 @@ INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
|
|||
INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
|
||||
INT_R.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
|
||||
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
|
||||
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
|
||||
|
|
@ -2431,7 +2431,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
|
|||
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
|
||||
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
|
||||
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
|
||||
INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
|
||||
INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
|
||||
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
|
||||
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
|
||||
INT_R.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
|
||||
|
|
@ -3295,7 +3295,7 @@ INT_R.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
|
|||
INT_R.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
|
||||
INT_R.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
|
||||
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
|
||||
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
|
||||
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
|
||||
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
|
||||
INT_R.SW6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_60 07_61
|
||||
INT_R.SW6BEG3.LOGIC_OUTS15 origin:050-pip-seed 03_60 04_62
|
||||
|
|
@ -3563,7 +3563,7 @@ INT_R.WW4BEG0.LOGIC_OUTS4 origin:050-pip-seed 02_01 07_01
|
|||
INT_R.WW4BEG0.LOGIC_OUTS8 origin:050-pip-seed 03_00 07_01
|
||||
INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
|
||||
INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
|
||||
INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
|
||||
INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
|
||||
INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
|
||||
INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
|
||||
INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
|
||||
|
|
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_33 07_33
|
|||
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
|
||||
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
|
||||
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
|
||||
INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
|
||||
INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
|
||||
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
|
||||
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
|
||||
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
|
||||
|
|
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_49 07_49
|
|||
INT_R.WW4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_49 04_50
|
||||
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
|
||||
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
|
||||
INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
|
||||
INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
|
||||
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
|
||||
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
|
||||
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
|
||||
|
|
|
|||
Loading…
Reference in New Issue