Updating zynq7 based on "Merge pull request #835 from antmicro/bel-timings-fixes".
See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
parent
c0137887d0
commit
cb8c9aff82
180
Info.md
180
Info.md
|
|
@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
|
|||
|
||||
# Details
|
||||
|
||||
Last updated on Thu May 30 18:43:40 UTC 2019 (2019-05-30T18:43:40+00:00).
|
||||
Last updated on Thu May 30 18:47:17 UTC 2019 (2019-05-30T18:47:17+00:00).
|
||||
|
||||
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [8cb7366](https://github.com/SymbiFlow/prjxray/commit/8cb7366fa2c361fd5c8eec0aa0cb976808a39752).
|
||||
|
||||
|
|
@ -993,95 +993,95 @@ Results have checksums;
|
|||
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
|
||||
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
|
||||
* [`93ae29cf7cd85ac8baf94a8e98cc7857d3cdd7ac0ad5720a42d6da1597b6d773 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRAM_INT_INTERFACE_L.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRAM_INT_INTERFACE_R.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_BRAM.sdf`](./zynq7/timings/BRKH_BRAM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_CLB.sdf`](./zynq7/timings/BRKH_CLB.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_CLK.sdf`](./zynq7/timings/BRKH_CLK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_CMT.sdf`](./zynq7/timings/BRKH_CMT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_DSP_L.sdf`](./zynq7/timings/BRKH_DSP_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_DSP_R.sdf`](./zynq7/timings/BRKH_DSP_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/BRKH_INT.sdf`](./zynq7/timings/BRKH_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/B_TERM_INT.sdf`](./zynq7/timings/B_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/B_TERM_INT_PSS.sdf`](./zynq7/timings/B_TERM_INT_PSS.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/B_TERM_VBRK.sdf`](./zynq7/timings/B_TERM_VBRK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CFG_CENTER_BOT.sdf`](./zynq7/timings/CFG_CENTER_BOT.sdf)
|
||||
* [`83ccaee1987ba044700bac18832ddd61404fbef77bad1465086b51663fdfaebb ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)
|
||||
* [`dab292d74a3178e993758ff011d870048c152ee15bffa56f92cb77ec84a5f356 ./zynq7/timings/CFG_CENTER_TOP.sdf`](./zynq7/timings/CFG_CENTER_TOP.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf)
|
||||
* [`99a8265d9d9b9504c7a9da30353540edd417faa80a44f8bee82ff9ecb1460ee3 ./zynq7/timings/CLBLL_L.sdf`](./zynq7/timings/CLBLL_L.sdf)
|
||||
* [`99a8265d9d9b9504c7a9da30353540edd417faa80a44f8bee82ff9ecb1460ee3 ./zynq7/timings/CLBLL_R.sdf`](./zynq7/timings/CLBLL_R.sdf)
|
||||
* [`f41ed5dac99cebce35cbb26a260384b41284c7a7f10d9bf34ebbda984cc01106 ./zynq7/timings/CLBLM_L.sdf`](./zynq7/timings/CLBLM_L.sdf)
|
||||
* [`f41ed5dac99cebce35cbb26a260384b41284c7a7f10d9bf34ebbda984cc01106 ./zynq7/timings/CLBLM_R.sdf`](./zynq7/timings/CLBLM_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_BUFG_BOT_R.sdf`](./zynq7/timings/CLK_BUFG_BOT_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_BUFG_REBUF.sdf`](./zynq7/timings/CLK_BUFG_REBUF.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_BUFG_TOP_R.sdf`](./zynq7/timings/CLK_BUFG_TOP_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_FEED.sdf`](./zynq7/timings/CLK_FEED.sdf)
|
||||
* [`7c371dfcc5b331fe8067db83aae601f7a442a1ec2e9cd340aec83ae1b19d53c2 ./zynq7/timings/CLK_HROW_BOT_R.sdf`](./zynq7/timings/CLK_HROW_BOT_R.sdf)
|
||||
* [`7c371dfcc5b331fe8067db83aae601f7a442a1ec2e9cd340aec83ae1b19d53c2 ./zynq7/timings/CLK_HROW_TOP_R.sdf`](./zynq7/timings/CLK_HROW_TOP_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_MTBF2.sdf`](./zynq7/timings/CLK_MTBF2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_PMV.sdf`](./zynq7/timings/CLK_PMV.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_PMV2.sdf`](./zynq7/timings/CLK_PMV2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_PMV2_SVT.sdf`](./zynq7/timings/CLK_PMV2_SVT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_PMVIOB.sdf`](./zynq7/timings/CLK_PMVIOB.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CLK_TERM.sdf`](./zynq7/timings/CLK_TERM.sdf)
|
||||
* [`a69c35413d0acfc143124ba92da4bd0e06b219e7d653db33a2e0606f0bdf988c ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/CMT_PMV_L.sdf`](./zynq7/timings/CMT_PMV_L.sdf)
|
||||
* [`9f3433d4e11f99aa29cc44cc2ddd44e53f582eebb41eca4bd8ec893b014b50e2 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
|
||||
* [`31e8bf0838d94b1dfa4337a3c35a5971f5f1f9187d8ace9d1e9a413a054293c7 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf)
|
||||
* [`01888b74b9bf90800da9210cf0acefa754106a21c1ea692a5825b15b1fd6b080 ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf)
|
||||
* [`58dcdaa7bed0e2d65c3587d59b5105ca78656ea5bf0822a3465c9cb6c2f5d80a ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_BRAM.sdf`](./zynq7/timings/HCLK_BRAM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_CLB.sdf`](./zynq7/timings/HCLK_CLB.sdf)
|
||||
* [`7ea90fd789cd110607d2deaf05bf2805751cfc5fe12d166e54b2ea44605d54aa ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_DSP_L.sdf`](./zynq7/timings/HCLK_DSP_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_DSP_R.sdf`](./zynq7/timings/HCLK_DSP_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_FEEDTHRU_1.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_FEEDTHRU_2.sdf`](./zynq7/timings/HCLK_FEEDTHRU_2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_FIFO_L.sdf`](./zynq7/timings/HCLK_FIFO_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_INT_INTERFACE.sdf`](./zynq7/timings/HCLK_INT_INTERFACE.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_IOB.sdf`](./zynq7/timings/HCLK_IOB.sdf)
|
||||
* [`d4c7a8e99f9f1776bb03dffbea751fb5c72b3ba5f4ddaf0edcd6050bd117279d ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_L.sdf`](./zynq7/timings/HCLK_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_R.sdf`](./zynq7/timings/HCLK_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_TERM.sdf`](./zynq7/timings/HCLK_TERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_VBRK.sdf`](./zynq7/timings/HCLK_VBRK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/HCLK_VFRAME.sdf`](./zynq7/timings/HCLK_VFRAME.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_FEEDTHRU_1.sdf`](./zynq7/timings/INT_FEEDTHRU_1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_FEEDTHRU_2.sdf`](./zynq7/timings/INT_FEEDTHRU_2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_INTERFACE_L.sdf`](./zynq7/timings/INT_INTERFACE_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_INTERFACE_PSS_L.sdf`](./zynq7/timings/INT_INTERFACE_PSS_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_INTERFACE_R.sdf`](./zynq7/timings/INT_INTERFACE_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_L.sdf`](./zynq7/timings/INT_L.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/INT_R.sdf`](./zynq7/timings/INT_R.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/IO_INT_INTERFACE_R.sdf`](./zynq7/timings/IO_INT_INTERFACE_R.sdf)
|
||||
* [`766fd9751c301c63c9a07425bb51225d824c60782e9e119f6d1fdcb2da9d51f1 ./zynq7/timings/MONITOR_BOT_PELE1.sdf`](./zynq7/timings/MONITOR_BOT_PELE1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/MONITOR_MID_PELE1.sdf`](./zynq7/timings/MONITOR_MID_PELE1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/MONITOR_TOP_PELE1.sdf`](./zynq7/timings/MONITOR_TOP_PELE1.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/PCIE_NULL.sdf`](./zynq7/timings/PCIE_NULL.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/PSS0.sdf`](./zynq7/timings/PSS0.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/PSS1.sdf`](./zynq7/timings/PSS1.sdf)
|
||||
* [`3cd28a408ec8b72e5659564f253748fecf0c742222540b8b1d30c9daf270afcf ./zynq7/timings/PSS2.sdf`](./zynq7/timings/PSS2.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/PSS3.sdf`](./zynq7/timings/PSS3.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/PSS4.sdf`](./zynq7/timings/PSS4.sdf)
|
||||
* [`07d02169a43e8006ed50d8061f1a8a07677bfccb95999804f14b42021c43b4d8 ./zynq7/timings/RIOB33.sdf`](./zynq7/timings/RIOB33.sdf)
|
||||
* [`9befc627c1bb83308433ab488ade8d0e4e26dd59490d8d8f622a68406077b04f ./zynq7/timings/RIOB33_SING.sdf`](./zynq7/timings/RIOB33_SING.sdf)
|
||||
* [`f16cfa12415250f8d01ae89a5d4905af262293217cfd25314be2607a15e32a81 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
|
||||
* [`f16cfa12415250f8d01ae89a5d4905af262293217cfd25314be2607a15e32a81 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
|
||||
* [`f16cfa12415250f8d01ae89a5d4905af262293217cfd25314be2607a15e32a81 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
|
||||
* [`f16cfa12415250f8d01ae89a5d4905af262293217cfd25314be2607a15e32a81 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/R_TERM_INT.sdf`](./zynq7/timings/R_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/TERM_CMT.sdf`](./zynq7/timings/TERM_CMT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/T_TERM_INT.sdf`](./zynq7/timings/T_TERM_INT.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/VBRK.sdf`](./zynq7/timings/VBRK.sdf)
|
||||
* [`fdbd15cd9a5b54d402980d250333c7ab8bdbff2f89eaffbc8053e1afde4dbfd5 ./zynq7/timings/VFRAME.sdf`](./zynq7/timings/VFRAME.sdf)
|
||||
* [`6187d7fa039c02e852bd43d318462c25fccd3d84a665c12299c511e11799eb46 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
|
||||
* [`9459f4403f9b458b62fe8191ec07e9ca059fe623a9f86d23ee12bf02242b9062 ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_L.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_R.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_BRAM.sdf`](./zynq7/timings/BRKH_BRAM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CLB.sdf`](./zynq7/timings/BRKH_CLB.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CLK.sdf`](./zynq7/timings/BRKH_CLK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CMT.sdf`](./zynq7/timings/BRKH_CMT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_DSP_L.sdf`](./zynq7/timings/BRKH_DSP_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_DSP_R.sdf`](./zynq7/timings/BRKH_DSP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_INT.sdf`](./zynq7/timings/BRKH_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_INT.sdf`](./zynq7/timings/B_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_INT_PSS.sdf`](./zynq7/timings/B_TERM_INT_PSS.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_VBRK.sdf`](./zynq7/timings/B_TERM_VBRK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_CENTER_BOT.sdf`](./zynq7/timings/CFG_CENTER_BOT.sdf)
|
||||
* [`8d6db739fe7463bf3806921de087423d59531ab44ff6fc1969c1421a39461bdb ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)
|
||||
* [`6dc7edd0792e8305dd8309933c264512fc6a22f45cf0386422edc219d5a3b20a ./zynq7/timings/CFG_CENTER_TOP.sdf`](./zynq7/timings/CFG_CENTER_TOP.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf)
|
||||
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./zynq7/timings/CLBLL_L.sdf`](./zynq7/timings/CLBLL_L.sdf)
|
||||
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./zynq7/timings/CLBLL_R.sdf`](./zynq7/timings/CLBLL_R.sdf)
|
||||
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./zynq7/timings/CLBLM_L.sdf`](./zynq7/timings/CLBLM_L.sdf)
|
||||
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./zynq7/timings/CLBLM_R.sdf`](./zynq7/timings/CLBLM_R.sdf)
|
||||
* [`0d9e20b4673ed1ad151e9c22f28ac2e456f4cdbf5ba31afe45576152a293fd7a ./zynq7/timings/CLK_BUFG_BOT_R.sdf`](./zynq7/timings/CLK_BUFG_BOT_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_BUFG_REBUF.sdf`](./zynq7/timings/CLK_BUFG_REBUF.sdf)
|
||||
* [`0d9e20b4673ed1ad151e9c22f28ac2e456f4cdbf5ba31afe45576152a293fd7a ./zynq7/timings/CLK_BUFG_TOP_R.sdf`](./zynq7/timings/CLK_BUFG_TOP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_FEED.sdf`](./zynq7/timings/CLK_FEED.sdf)
|
||||
* [`590c7ee72599c4d42030ba90c6e352c66d51490112b83f292345bec5c89d94c9 ./zynq7/timings/CLK_HROW_BOT_R.sdf`](./zynq7/timings/CLK_HROW_BOT_R.sdf)
|
||||
* [`590c7ee72599c4d42030ba90c6e352c66d51490112b83f292345bec5c89d94c9 ./zynq7/timings/CLK_HROW_TOP_R.sdf`](./zynq7/timings/CLK_HROW_TOP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_MTBF2.sdf`](./zynq7/timings/CLK_MTBF2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV.sdf`](./zynq7/timings/CLK_PMV.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV2.sdf`](./zynq7/timings/CLK_PMV2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV2_SVT.sdf`](./zynq7/timings/CLK_PMV2_SVT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMVIOB.sdf`](./zynq7/timings/CLK_PMVIOB.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_TERM.sdf`](./zynq7/timings/CLK_TERM.sdf)
|
||||
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CMT_PMV_L.sdf`](./zynq7/timings/CMT_PMV_L.sdf)
|
||||
* [`c2e66425da5018d6e7aa2b0aec721bcecfdba26bfa26016598cd28e3112fffc4 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
|
||||
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf)
|
||||
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf)
|
||||
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_BRAM.sdf`](./zynq7/timings/HCLK_BRAM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_CLB.sdf`](./zynq7/timings/HCLK_CLB.sdf)
|
||||
* [`e706cddf4c7392507fcaa790fcde691d58a849f520969a5ea0c2fa7870ef835c ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_DSP_L.sdf`](./zynq7/timings/HCLK_DSP_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_DSP_R.sdf`](./zynq7/timings/HCLK_DSP_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_1.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_2.sdf`](./zynq7/timings/HCLK_FEEDTHRU_2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FIFO_L.sdf`](./zynq7/timings/HCLK_FIFO_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_INT_INTERFACE.sdf`](./zynq7/timings/HCLK_INT_INTERFACE.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_IOB.sdf`](./zynq7/timings/HCLK_IOB.sdf)
|
||||
* [`b5d5ca72d453879fca2bf2470fb0a670ebfb38d6e85cdbfdb3967e2e4f59ee73 ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_L.sdf`](./zynq7/timings/HCLK_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_R.sdf`](./zynq7/timings/HCLK_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_TERM.sdf`](./zynq7/timings/HCLK_TERM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_VBRK.sdf`](./zynq7/timings/HCLK_VBRK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_VFRAME.sdf`](./zynq7/timings/HCLK_VFRAME.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_FEEDTHRU_1.sdf`](./zynq7/timings/INT_FEEDTHRU_1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_FEEDTHRU_2.sdf`](./zynq7/timings/INT_FEEDTHRU_2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_L.sdf`](./zynq7/timings/INT_INTERFACE_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_PSS_L.sdf`](./zynq7/timings/INT_INTERFACE_PSS_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_R.sdf`](./zynq7/timings/INT_INTERFACE_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_L.sdf`](./zynq7/timings/INT_L.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_R.sdf`](./zynq7/timings/INT_R.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/IO_INT_INTERFACE_R.sdf`](./zynq7/timings/IO_INT_INTERFACE_R.sdf)
|
||||
* [`2af03d31603e237767ecaef977f8b6050c71d32a7632330ac8f42909dc22befc ./zynq7/timings/MONITOR_BOT_PELE1.sdf`](./zynq7/timings/MONITOR_BOT_PELE1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/MONITOR_MID_PELE1.sdf`](./zynq7/timings/MONITOR_MID_PELE1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/MONITOR_TOP_PELE1.sdf`](./zynq7/timings/MONITOR_TOP_PELE1.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PCIE_NULL.sdf`](./zynq7/timings/PCIE_NULL.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS0.sdf`](./zynq7/timings/PSS0.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS1.sdf`](./zynq7/timings/PSS1.sdf)
|
||||
* [`4e807172f038c907022e9b8f3ff1f6e80621a3dc9ee6e132b81b9d976763b5cd ./zynq7/timings/PSS2.sdf`](./zynq7/timings/PSS2.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS3.sdf`](./zynq7/timings/PSS3.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS4.sdf`](./zynq7/timings/PSS4.sdf)
|
||||
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./zynq7/timings/RIOB33.sdf`](./zynq7/timings/RIOB33.sdf)
|
||||
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./zynq7/timings/RIOB33_SING.sdf`](./zynq7/timings/RIOB33_SING.sdf)
|
||||
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
|
||||
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
|
||||
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
|
||||
* [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/R_TERM_INT.sdf`](./zynq7/timings/R_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/TERM_CMT.sdf`](./zynq7/timings/TERM_CMT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/T_TERM_INT.sdf`](./zynq7/timings/T_TERM_INT.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VBRK.sdf`](./zynq7/timings/VBRK.sdf)
|
||||
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VFRAME.sdf`](./zynq7/timings/VFRAME.sdf)
|
||||
* [`ca3e3a61d6070397ffa76245f3435a036adefb318e29172580725f7f0b8eb2b6 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
|
||||
* [`0877c0b0d5c6dd87b2a75221fa5245f537605682b67ae4d0a064e005e701de1e ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
|
||||
* [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json)
|
||||
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml)
|
||||
* [`d9914c14b3a8d59c76dd5992c4727e4002acd5e14b32c1afe49f7be8798e4db9 ./zynq7/xc7z010clg400-1_package_pins.csv`](./zynq7/xc7z010clg400-1_package_pins.csv)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CAPTURE")
|
||||
|
|
@ -15,10 +15,10 @@
|
|||
(CELLTYPE "ICAP")
|
||||
(INSTANCE ICAP)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (3.390::3.900))
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (5.587::6.427))
|
||||
(HOLD CSIB (posedge CLK) (0.000::0.000))
|
||||
(SETUP CSIB (posedge CLK) (3.390::3.900))
|
||||
(HOLD RDWRB (posedge CLK) (0.000::0.000))
|
||||
(SETUP RDWRB (posedge CLK) (5.587::6.427))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "DNA_PORT_DNA_PORTDNA_PORT")
|
||||
|
|
@ -12,8 +12,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.000::0.000))
|
||||
(SETUP CLK (posedge CLK) (2.793::3.214))
|
||||
(HOLD DIN (posedge CLK) (0.000::0.000))
|
||||
(SETUP DIN (posedge CLK) (2.793::3.214))
|
||||
(HOLD READ (posedge CLK) (0.000::0.000))
|
||||
(SETUP READ (posedge CLK) (4.656::5.356))
|
||||
(HOLD SHIFT (posedge CLK) (0.000::0.000))
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -707,7 +719,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -734,10 +750,10 @@
|
|||
(SETUP WA1 (posedge CLK) (0.184::0.066))
|
||||
(HOLD WA2 (posedge CLK) (0.745::0.572))
|
||||
(SETUP WA2 (posedge CLK) (0.181::0.068))
|
||||
(HOLD CLK (posedge CLK) (0.579::0.460))
|
||||
(SETUP CLK (posedge CLK) (0.214::0.147))
|
||||
(HOLD CLK (posedge CLK) (0.507::0.411))
|
||||
(SETUP CLK (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA3 (posedge CLK) (0.579::0.460))
|
||||
(SETUP WA3 (posedge CLK) (0.214::0.147))
|
||||
(HOLD WA4 (posedge CLK) (0.507::0.411))
|
||||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
|
|
@ -768,10 +784,10 @@
|
|||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD WA6 (posedge CLK) (0.213::0.244))
|
||||
(SETUP WA6 (posedge CLK) (0.302::0.362))
|
||||
(HOLD CLK (posedge CLK) (0.184::0.228))
|
||||
(SETUP CLK (posedge CLK) (0.496::0.616))
|
||||
(HOLD CLK (posedge CLK) (0.199::0.247))
|
||||
(SETUP CLK (posedge CLK) (0.511::0.633))
|
||||
(HOLD WA7 (posedge CLK) (0.184::0.228))
|
||||
(SETUP WA7 (posedge CLK) (0.496::0.616))
|
||||
(HOLD WA8 (posedge CLK) (0.199::0.247))
|
||||
(SETUP WA8 (posedge CLK) (0.511::0.633))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
|
|
@ -794,7 +810,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -823,6 +843,10 @@
|
|||
(IOPATH D Q (0.075::0.094)(0.214::0.265))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(SETUP DIN (posedge CLK) (-0.078::-0.064))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -858,8 +882,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.231::0.287))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.231::0.287))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -871,8 +895,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -890,10 +914,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.366::0.453))
|
||||
(HOLD CLK (posedge CLK) (0.098::0.122))
|
||||
(SETUP CLK (posedge CLK) (0.309::0.384))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI2 (posedge CLK) (0.098::0.122))
|
||||
(SETUP DI2 (posedge CLK) (0.309::0.384))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -906,10 +930,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD CLK (posedge CLK) (0.076::0.094))
|
||||
(SETUP CLK (posedge CLK) (0.140::0.173))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI2 (posedge CLK) (0.076::0.094))
|
||||
(SETUP DI2 (posedge CLK) (0.140::0.173))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -926,8 +950,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.311))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.311))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -939,8 +963,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -958,10 +982,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.372::0.461))
|
||||
(HOLD CLK (posedge CLK) (0.107::0.133))
|
||||
(SETUP CLK (posedge CLK) (0.286::0.354))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI2 (posedge CLK) (0.107::0.133))
|
||||
(SETUP DI2 (posedge CLK) (0.286::0.354))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -974,10 +998,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD CLK (posedge CLK) (0.089::0.110))
|
||||
(SETUP CLK (posedge CLK) (0.143::0.178))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI2 (posedge CLK) (0.089::0.110))
|
||||
(SETUP DI2 (posedge CLK) (0.143::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -994,8 +1018,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.243::0.301))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.243::0.301))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1007,8 +1031,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1026,10 +1050,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.368::0.457))
|
||||
(HOLD CLK (posedge CLK) (0.091::0.113))
|
||||
(SETUP CLK (posedge CLK) (0.302::0.375))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.113))
|
||||
(SETUP DI2 (posedge CLK) (0.302::0.375))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1042,10 +1066,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD CLK (posedge CLK) (0.062::0.077))
|
||||
(SETUP CLK (posedge CLK) (0.116::0.144))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI2 (posedge CLK) (0.062::0.077))
|
||||
(SETUP DI2 (posedge CLK) (0.116::0.144))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1062,8 +1086,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.111::0.137))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.111::0.137))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1075,8 +1099,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1094,10 +1118,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.310))
|
||||
(HOLD CLK (posedge CLK) (0.106::0.132))
|
||||
(SETUP CLK (posedge CLK) (0.269::0.334))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI2 (posedge CLK) (0.106::0.132))
|
||||
(SETUP DI2 (posedge CLK) (0.269::0.334))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1110,10 +1134,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD CLK (posedge CLK) (0.091::0.112))
|
||||
(SETUP CLK (posedge CLK) (0.133::0.165))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.112))
|
||||
(SETUP DI2 (posedge CLK) (0.133::0.165))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "CARRY4")
|
||||
|
|
@ -245,7 +245,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.181::0.225))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.057::-0.046))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -274,7 +278,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.011::-0.009))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.055::-0.045))
|
||||
(SETUP INIT (posedge CLK) (0.345::0.428))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -303,6 +311,10 @@
|
|||
(IOPATH D Q (0.073::0.092)(0.213::0.264))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(SETUP DIN (posedge CLK) (-0.068::-0.056))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -707,7 +719,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.194::0.241))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -734,10 +750,10 @@
|
|||
(SETUP WA1 (posedge CLK) (0.184::0.066))
|
||||
(HOLD WA2 (posedge CLK) (0.745::0.572))
|
||||
(SETUP WA2 (posedge CLK) (0.181::0.068))
|
||||
(HOLD CLK (posedge CLK) (0.579::0.460))
|
||||
(SETUP CLK (posedge CLK) (0.214::0.147))
|
||||
(HOLD CLK (posedge CLK) (0.507::0.411))
|
||||
(SETUP CLK (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA3 (posedge CLK) (0.579::0.460))
|
||||
(SETUP WA3 (posedge CLK) (0.214::0.147))
|
||||
(HOLD WA4 (posedge CLK) (0.507::0.411))
|
||||
(SETUP WA4 (posedge CLK) (0.248::0.208))
|
||||
(HOLD WA5 (posedge CLK) (0.332::0.314))
|
||||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
|
|
@ -768,10 +784,10 @@
|
|||
(SETUP WA5 (posedge CLK) (0.236::0.245))
|
||||
(HOLD WA6 (posedge CLK) (0.213::0.244))
|
||||
(SETUP WA6 (posedge CLK) (0.302::0.362))
|
||||
(HOLD CLK (posedge CLK) (0.184::0.228))
|
||||
(SETUP CLK (posedge CLK) (0.496::0.616))
|
||||
(HOLD CLK (posedge CLK) (0.199::0.247))
|
||||
(SETUP CLK (posedge CLK) (0.511::0.633))
|
||||
(HOLD WA7 (posedge CLK) (0.184::0.228))
|
||||
(SETUP WA7 (posedge CLK) (0.496::0.616))
|
||||
(HOLD WA8 (posedge CLK) (0.199::0.247))
|
||||
(SETUP WA8 (posedge CLK) (0.511::0.633))
|
||||
(HOLD WE (posedge CLK) (0.008::0.010))
|
||||
(SETUP WE (posedge CLK) (0.527::0.654))
|
||||
)
|
||||
|
|
@ -794,7 +810,11 @@
|
|||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CLK) (-0.007::-0.005))
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(HOLD INIT (posedge CLK) (-0.050::-0.041))
|
||||
(SETUP CE (posedge CLK) (0.088::0.109))
|
||||
(SETUP DIN (posedge CLK) (-0.074::-0.060))
|
||||
(SETUP INIT (posedge CLK) (0.445::0.552))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -823,6 +843,10 @@
|
|||
(IOPATH D Q (0.075::0.094)(0.214::0.265))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DIN (posedge CLK) (0.211::0.262))
|
||||
(SETUP DIN (posedge CLK) (-0.078::-0.064))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "REG_INIT_LAT_LOGIC_AND")
|
||||
|
|
@ -858,8 +882,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.231::0.287))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.231::0.287))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -871,8 +895,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -890,10 +914,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.155::0.192))
|
||||
(SETUP CLK (posedge CLK) (0.366::0.453))
|
||||
(HOLD CLK (posedge CLK) (0.098::0.122))
|
||||
(SETUP CLK (posedge CLK) (0.309::0.384))
|
||||
(HOLD DI1 (posedge CLK) (0.155::0.192))
|
||||
(SETUP DI1 (posedge CLK) (0.366::0.453))
|
||||
(HOLD DI2 (posedge CLK) (0.098::0.122))
|
||||
(SETUP DI2 (posedge CLK) (0.309::0.384))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -906,10 +930,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.075::0.093))
|
||||
(SETUP CLK (posedge CLK) (0.137::0.170))
|
||||
(HOLD CLK (posedge CLK) (0.076::0.094))
|
||||
(SETUP CLK (posedge CLK) (0.140::0.173))
|
||||
(HOLD DI1 (posedge CLK) (0.075::0.093))
|
||||
(SETUP DI1 (posedge CLK) (0.137::0.170))
|
||||
(HOLD DI2 (posedge CLK) (0.076::0.094))
|
||||
(SETUP DI2 (posedge CLK) (0.140::0.173))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -926,8 +950,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.311))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.311))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -939,8 +963,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -958,10 +982,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.154::0.191))
|
||||
(SETUP CLK (posedge CLK) (0.372::0.461))
|
||||
(HOLD CLK (posedge CLK) (0.107::0.133))
|
||||
(SETUP CLK (posedge CLK) (0.286::0.354))
|
||||
(HOLD DI1 (posedge CLK) (0.154::0.191))
|
||||
(SETUP DI1 (posedge CLK) (0.372::0.461))
|
||||
(HOLD DI2 (posedge CLK) (0.107::0.133))
|
||||
(SETUP DI2 (posedge CLK) (0.286::0.354))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -974,10 +998,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.070::0.087))
|
||||
(SETUP CLK (posedge CLK) (0.126::0.156))
|
||||
(HOLD CLK (posedge CLK) (0.089::0.110))
|
||||
(SETUP CLK (posedge CLK) (0.143::0.178))
|
||||
(HOLD DI1 (posedge CLK) (0.070::0.087))
|
||||
(SETUP DI1 (posedge CLK) (0.126::0.156))
|
||||
(HOLD DI2 (posedge CLK) (0.089::0.110))
|
||||
(SETUP DI2 (posedge CLK) (0.143::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -994,8 +1018,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.243::0.301))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.243::0.301))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1007,8 +1031,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1026,10 +1050,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.152::0.189))
|
||||
(SETUP CLK (posedge CLK) (0.368::0.457))
|
||||
(HOLD CLK (posedge CLK) (0.091::0.113))
|
||||
(SETUP CLK (posedge CLK) (0.302::0.375))
|
||||
(HOLD DI1 (posedge CLK) (0.152::0.189))
|
||||
(SETUP DI1 (posedge CLK) (0.368::0.457))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.113))
|
||||
(SETUP DI2 (posedge CLK) (0.302::0.375))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1042,10 +1066,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.058::0.072))
|
||||
(SETUP CLK (posedge CLK) (0.117::0.145))
|
||||
(HOLD CLK (posedge CLK) (0.062::0.077))
|
||||
(SETUP CLK (posedge CLK) (0.116::0.144))
|
||||
(HOLD DI1 (posedge CLK) (0.058::0.072))
|
||||
(SETUP DI1 (posedge CLK) (0.117::0.145))
|
||||
(HOLD DI2 (posedge CLK) (0.062::0.077))
|
||||
(SETUP DI2 (posedge CLK) (0.116::0.144))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1062,8 +1086,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.111::0.137))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.111::0.137))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1075,8 +1099,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1094,10 +1118,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.153::0.190))
|
||||
(SETUP CLK (posedge CLK) (0.250::0.310))
|
||||
(HOLD CLK (posedge CLK) (0.106::0.132))
|
||||
(SETUP CLK (posedge CLK) (0.269::0.334))
|
||||
(HOLD DI1 (posedge CLK) (0.153::0.190))
|
||||
(SETUP DI1 (posedge CLK) (0.250::0.310))
|
||||
(HOLD DI2 (posedge CLK) (0.106::0.132))
|
||||
(SETUP DI2 (posedge CLK) (0.269::0.334))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -1110,10 +1134,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CLK (posedge CLK) (0.217::0.269))
|
||||
(SETUP CLK (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD CLK (posedge CLK) (0.091::0.112))
|
||||
(SETUP CLK (posedge CLK) (0.133::0.165))
|
||||
(HOLD DI1 (posedge CLK) (0.217::0.269))
|
||||
(SETUP DI1 (posedge CLK) (-0.040::-0.033))
|
||||
(HOLD DI2 (posedge CLK) (0.091::0.112))
|
||||
(SETUP DI2 (posedge CLK) (0.133::0.165))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFGCTRL")
|
||||
(INSTANCE BUFGCTRL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.026::0.029)(0.091::0.101))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,15 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFGCTRL")
|
||||
(INSTANCE BUFGCTRL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.026::0.029)(0.091::0.101))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.132))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
|
|
|
|||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE")
|
||||
(INSTANCE BUFHCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.020::0.043)(0.081::0.132))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
|
||||
(INSTANCE BUFHCE)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,230 +1,66 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
|
||||
(INSTANCE IN_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
|
||||
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
|
||||
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP D0 (posedge WRCLK) (0.473::0.544))
|
||||
(HOLD D1 (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP D1 (posedge WRCLK) (0.496::0.571))
|
||||
(HOLD D2 (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP D2 (posedge WRCLK) (0.456::0.524))
|
||||
(HOLD D3 (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP D3 (posedge WRCLK) (0.453::0.521))
|
||||
(HOLD RDEN (posedge RDCLK) (0.015::0.018))
|
||||
(SETUP RDEN (posedge RDCLK) (0.509::0.586))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WREN (posedge WRCLK) (0.461::0.530))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D0")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.080::-0.070))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.473::0.544))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D1")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.069::-0.060))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.496::0.571))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D2")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.073::-0.063))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.456::0.524))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D3")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.050::-0.043))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.453::0.521))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D4")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.413::0.475))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D5")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.026::-0.023))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.404::0.465))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D6")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D7")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.032::-0.028))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.414::0.476))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D8")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.043::-0.037))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.429::0.494))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_D9")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.040::-0.035))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.454::0.522))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO_SCANIN")
|
||||
(INSTANCE IN_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
|
||||
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
|
||||
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
|
||||
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D0 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D1 (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP D1 (posedge WRCLK) (0.381::0.438))
|
||||
(HOLD D2 (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP D2 (posedge WRCLK) (0.367::0.422))
|
||||
(HOLD D3 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D3 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D4 (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP D4 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D5 (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP D5 (posedge WRCLK) (0.354::0.408))
|
||||
(HOLD D6 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D6 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD D7 (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP D7 (posedge WRCLK) (0.344::0.395))
|
||||
(HOLD RDEN (posedge RDCLK) (-0.013::-0.012))
|
||||
(SETUP RDEN (posedge RDCLK) (0.566::0.651))
|
||||
(HOLD SCANENB (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANENB (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANENB (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD SCANIN (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP SCANIN (posedge WRCLK) (0.976::1.123))
|
||||
(HOLD WREN (posedge WRCLK) (-0.030::-0.026))
|
||||
(SETUP WREN (posedge WRCLK) (0.373::0.430))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D0")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D1")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.022::-0.019))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.381::0.438))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D2")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.019::-0.016))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.367::0.422))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D3")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D4")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.012::-0.011))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D5")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.011::-0.010))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.354::0.408))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D6")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D7")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D8")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_D9")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD WRCLK (posedge WRCLK) (-0.013::-0.012))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.344::0.395))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO_SCANIN")
|
||||
(INSTANCE OUT_FIFO)
|
||||
(TIMINGCHECK
|
||||
(HOLD RDCLK (posedge RDCLK) (0.537::0.618))
|
||||
(SETUP RDCLK (posedge RDCLK) (0.976::1.123))
|
||||
(HOLD WRCLK (posedge WRCLK) (0.537::0.618))
|
||||
(SETUP WRCLK (posedge WRCLK) (0.976::1.123))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,271 +1,257 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
|
||||
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
(HOLD PSCLK (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSCLK (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSCLK (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSCLK (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSEN (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSEN (posedge PSCLK) (0.979::1.040))
|
||||
(HOLD PSINCDEC (posedge PSCLK) (0.000::0.000))
|
||||
(SETUP PSINCDEC (posedge PSCLK) (0.979::1.040))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_BUF_IN")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_EXTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_INTERNAL")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DADDR")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_DI")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
|
||||
(INSTANCE MMCME2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,9 +65,6 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
|
|
@ -75,52 +72,44 @@
|
|||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF")
|
||||
|
|
@ -65,9 +65,6 @@
|
|||
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
|
||||
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
|
||||
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
|
|
@ -75,52 +72,44 @@
|
|||
(SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101))
|
||||
(HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.028::0.030))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180))
|
||||
(HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.057::0.061))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD RANKSEL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RANKSEL (posedge SYSCLK) (0.228::0.242))
|
||||
(HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.212::0.225))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.030::0.032))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559))
|
||||
(HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241))
|
||||
(HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232))
|
||||
(HOLD STG1READ (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1READ (posedge SYSCLK) (0.154::0.164))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.067::0.071))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.217::0.230))
|
||||
(HOLD STG1REGL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP STG1REGL (posedge SYSCLK) (0.218::0.231))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -196,19 +185,14 @@
|
|||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_RANKSEL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.228::0.242))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_STG1REGL")
|
||||
(INSTANCE PHASER_IN_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.218::0.231))
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
|
||||
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
|
||||
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -340,36 +324,33 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
|
||||
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
|
||||
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121))
|
||||
(HOLD COARSEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COARSEINC (posedge SYSCLK) (0.133::0.141))
|
||||
(HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105))
|
||||
(HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178))
|
||||
(HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077))
|
||||
(HOLD EDGEADV (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP EDGEADV (posedge SYSCLK) (0.027::0.029))
|
||||
(HOLD ENCALIB (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP ENCALIB (posedge SYSCLK) (0.176::0.187))
|
||||
(HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053))
|
||||
(SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179))
|
||||
(HOLD FINEINC (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP FINEINC (posedge SYSCLK) (0.050::0.053))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANCLK (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANCLK (posedge SCANCLK) (0.966::1.026))
|
||||
(HOLD SCANENB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANENB (posedge SCANCLK) (0.488::0.518))
|
||||
(HOLD SCANIN (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANIN (posedge SCANCLK) (0.194::0.206))
|
||||
(HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000))
|
||||
(SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -492,22 +473,6 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COUNTERLOADVAL")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.168::0.178))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_ENCALIB")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
(TIMINGCHECK
|
||||
(HOLD SYSCLK (posedge SYSCLK) (0.000::0.000))
|
||||
(SETUP SYSCLK (posedge SYSCLK) (0.176::0.187))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF")
|
||||
(INSTANCE PHASER_OUT_PHY)
|
||||
|
|
@ -531,45 +496,19 @@
|
|||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
|
||||
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
|
||||
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
|
||||
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.158::0.182))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_PHYCTLWD")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD PHYCLK (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCLK (posedge PHYCLK) (0.215::0.248))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTINPUT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL_TESTSELECT")
|
||||
(INSTANCE PHY_CONTROL)
|
||||
(TIMINGCHECK
|
||||
(HOLD MEMREFCLK (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP MEMREFCLK (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
|
||||
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))
|
||||
(HOLD PHYCTLWD (posedge PHYCLK) (0.172::0.198))
|
||||
(SETUP PHYCTLWD (posedge PHYCLK) (0.215::0.248))
|
||||
(HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056))
|
||||
(SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376))
|
||||
(HOLD SYNCIN (posedge MEMREFCLK) (0.151::0.174))
|
||||
(SETUP SYNCIN (posedge MEMREFCLK) (0.158::0.182))
|
||||
(HOLD TESTINPUT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTINPUT (posedge MEMREFCLK) (0.244::0.281))
|
||||
(HOLD TESTSELECT (posedge MEMREFCLK) (0.049::0.056))
|
||||
(SETUP TESTSELECT (posedge MEMREFCLK) (0.244::0.281))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,144 +1,131 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
|
||||
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DADDR (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DADDR (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DEN (posedge DCLK) (0.000::0.000))
|
||||
(SETUP DEN (posedge DCLK) (2.156::2.290))
|
||||
(HOLD DI (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DI (posedge DCLK) (1.527::1.622))
|
||||
(HOLD DWE (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DWE (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DADDR")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_DI")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (0.141::0.150))
|
||||
(SETUP DCLK (posedge DCLK) (1.527::1.622))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
|
||||
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
|
||||
(INSTANCE PLLE2_ADV)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
|
||||
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,17 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE")
|
||||
(INSTANCE BUFMRCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH I O (0.033::0.035)(0.097::0.103))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
|
||||
(INSTANCE BUFMRCE)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "BUFIO_DELAY_BYPASS_FALSE")
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,44 +1,20 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "XADC")
|
||||
(INSTANCE XADC)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH DCLK BUSY (0.301::0.319)(1.218::1.294))
|
||||
(IOPATH DCLK DRDY (0.256::0.272)(1.132::1.204))
|
||||
(IOPATH DCLK EOC (0.379::0.403)(1.437::1.527))
|
||||
(IOPATH DCLK EOS (0.288::0.306)(1.231::1.309))
|
||||
(IOPATH DCLK JTAGBUSY (0.334::0.354)(1.331::1.415))
|
||||
(IOPATH DCLK JTAGLOCKED (0.276::0.294)(1.190::1.264))
|
||||
(IOPATH DCLK JTAGMODIFIED (0.273::0.289)(1.177::1.251))
|
||||
(IOPATH DCLK OT (0.301::0.319)(1.269::1.349))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.025::-0.013))
|
||||
(SETUP DCLK (posedge DCLK) (0.800::0.848))
|
||||
(HOLD DADDR (posedge DCLK) (-0.002::0.017))
|
||||
(SETUP DADDR (posedge DCLK) (0.659::0.699))
|
||||
(HOLD DEN (posedge DCLK) (-0.025::-0.013))
|
||||
(SETUP DEN (posedge DCLK) (0.800::0.848))
|
||||
(HOLD DI (posedge DCLK) (-0.009::0.010))
|
||||
(SETUP DI (posedge DCLK) (0.610::0.648))
|
||||
(HOLD DWE (posedge DCLK) (-0.022::-0.005))
|
||||
(SETUP DWE (posedge DCLK) (0.531::0.565))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DADDR")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.002::0.017))
|
||||
(SETUP DCLK (posedge DCLK) (0.659::0.699))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "XADC_DI")
|
||||
(INSTANCE XADC)
|
||||
(TIMINGCHECK
|
||||
(HOLD DCLK (posedge DCLK) (-0.009::0.010))
|
||||
(SETUP DCLK (posedge DCLK) (0.610::0.648))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,23 +1,23 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
(CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
|
||||
(INSTANCE IOB33M)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.016::1.169))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
(CELLTYPE "IOB33S_INBUF_ENIOB33_IOBS_INBUF_EN")
|
||||
(INSTANCE IOB33S)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
|
||||
(IOPATH IBUFDISABLE OUT (0.340::0.391)(1.027::1.182))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
|
||||
|
|
|
|||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -43,8 +27,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
|
|
@ -53,8 +37,8 @@
|
|||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LDPIPEEN (posedge C) (0.108::0.116))
|
||||
(SETUP LDPIPEEN (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
|
|
@ -67,20 +51,36 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
(HOLD SR (posedge CK) (-0.077::-0.066))
|
||||
(SETUP SR (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -89,8 +89,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
|
|
@ -105,15 +105,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_HOLD")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL CK (posedge CK) (-0.409::-0.357))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -127,8 +120,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.140::0.161))
|
||||
(SETUP CK (posedge CK) (0.035::0.041))
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +148,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD SR (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -171,7 +171,7 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY CK (posedge CK) (0.518::0.596))
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -189,10 +189,12 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -201,16 +203,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -290,10 +278,12 @@
|
|||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
(HOLD SR (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -302,16 +292,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -43,8 +27,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
|
|
@ -53,8 +37,8 @@
|
|||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LDPIPEEN (posedge C) (0.108::0.116))
|
||||
(SETUP LDPIPEEN (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
|
|
@ -67,20 +51,36 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
(HOLD SR (posedge CK) (-0.077::-0.066))
|
||||
(SETUP SR (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -89,8 +89,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
|
|
@ -105,15 +105,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_HOLD")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL CK (posedge CK) (-0.409::-0.357))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -127,8 +120,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.140::0.161))
|
||||
(SETUP CK (posedge CK) (0.035::0.041))
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +148,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD SR (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -171,7 +171,7 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY CK (posedge CK) (0.518::0.596))
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -189,10 +189,12 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -201,16 +203,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -290,10 +278,12 @@
|
|||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
(HOLD SR (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -302,16 +292,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -43,8 +27,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
|
|
@ -53,8 +37,8 @@
|
|||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LDPIPEEN (posedge C) (0.108::0.116))
|
||||
(SETUP LDPIPEEN (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
|
|
@ -67,20 +51,36 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
(HOLD SR (posedge CK) (-0.077::-0.066))
|
||||
(SETUP SR (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -89,8 +89,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
|
|
@ -105,15 +105,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_HOLD")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL CK (posedge CK) (-0.409::-0.357))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -127,8 +120,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.140::0.161))
|
||||
(SETUP CK (posedge CK) (0.035::0.041))
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +148,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD SR (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -171,7 +171,7 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY CK (posedge CK) (0.518::0.596))
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -189,10 +189,12 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -201,16 +203,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -290,10 +278,12 @@
|
|||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
(HOLD SR (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -302,16 +292,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,24 +1,8 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.128::0.138))
|
||||
(SETUP C (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_CNTVALUEIN_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.258::0.280))
|
||||
(SETUP C (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2_DELAY_SRC_DATAIN")
|
||||
(INSTANCE IDELAYE2)
|
||||
|
|
@ -43,8 +27,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
|
|
@ -53,8 +37,8 @@
|
|||
(CELLTYPE "IDELAYE2_IDELAY_TYPE_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LDPIPEEN (posedge C) (0.108::0.116))
|
||||
(SETUP LDPIPEEN (posedge C) (0.031::0.033))
|
||||
(HOLD REGRST (posedge C) (0.122::0.132))
|
||||
|
|
@ -67,20 +51,36 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge C) (0.143::0.155))
|
||||
(SETUP CE (posedge C) (0.187::0.203))
|
||||
(HOLD C (posedge C) (0.203::0.219))
|
||||
(SETUP C (posedge C) (0.140::0.152))
|
||||
(HOLD INC (posedge C) (0.203::0.219))
|
||||
(SETUP INC (posedge C) (0.140::0.152))
|
||||
(HOLD LD (posedge C) (0.131::0.141))
|
||||
(SETUP LD (posedge C) (0.089::0.097))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.128::0.138))
|
||||
(SETUP IDELAY_TYPE (posedge C) (0.094::0.102))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "IDELAYE2CNTVALUEIN_VAR_LOAD_PIPE")
|
||||
(INSTANCE IDELAYE2)
|
||||
(TIMINGCHECK
|
||||
(HOLD IDELAY_TYPE (posedge C) (0.258::0.280))
|
||||
(SETUP IDELAY_TYPE (posedge C) (-0.081::-0.075))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CK) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CK) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (-0.077::-0.066))
|
||||
(SETUP CK (posedge CK) (0.764::0.922))
|
||||
(HOLD SR (posedge CK) (-0.077::-0.066))
|
||||
(SETUP SR (posedge CK) (0.764::0.922))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -89,8 +89,8 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD CE (posedge CKB) (-0.076::-0.066))
|
||||
(SETUP CE (posedge CKB) (0.430::0.726))
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
(HOLD D (posedge CKB) (0.022::0.026))
|
||||
(SETUP D (posedge CKB) (0.091::0.105))
|
||||
)
|
||||
|
|
@ -105,15 +105,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.022::0.026))
|
||||
(SETUP CK (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_HOLD")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL CK (posedge CK) (-0.409::-0.357))
|
||||
(HOLD D (posedge CK) (0.022::0.026))
|
||||
(SETUP D (posedge CK) (0.091::0.105))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -127,8 +120,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (0.140::0.161))
|
||||
(SETUP CK (posedge CK) (0.035::0.041))
|
||||
(HOLD D (posedge CK) (0.140::0.161))
|
||||
(SETUP D (posedge CK) (0.035::0.041))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -155,6 +148,13 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_REMOV")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD SR (posedge CK) (-0.409::-0.357))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "ILOGICE3_IFF_SAMEEDGE")
|
||||
(INSTANCE ILOGICE3)
|
||||
|
|
@ -171,7 +171,7 @@
|
|||
(CELLTYPE "ILOGICE3_IFF_SETUP")
|
||||
(INSTANCE ILOGICE3)
|
||||
(TIMINGCHECK
|
||||
(RECOVERY CK (posedge CK) (0.518::0.596))
|
||||
(RECOVERY SR (posedge CK) (0.518::0.596))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -189,10 +189,12 @@
|
|||
(CELLTYPE "OLOGICE3_OUTFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY CK (posedge CK) (0.261::0.300))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.651::0.798))
|
||||
(HOLD OCE (posedge CK) (-0.059::-0.051))
|
||||
(SETUP OCE (posedge CK) (0.380::0.504))
|
||||
(HOLD SR (posedge CK) (-0.142::-0.124))
|
||||
(RECOVERY SR (posedge CK) (0.261::0.300))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.651::0.798))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -201,16 +203,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D1 (posedge CK) (0.689::0.834))
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.164::-0.143))
|
||||
(SETUP CK (posedge CK) (0.689::0.834))
|
||||
(HOLD D2 (posedge CK) (-0.164::-0.143))
|
||||
(SETUP D2 (posedge CK) (0.689::0.834))
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD OCE (posedge CK) (-0.124::-0.108))
|
||||
(SETUP OCE (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -242,30 +254,6 @@
|
|||
(SETUP D1 (posedge CK) (0.351::0.404))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.059::-0.051))
|
||||
(SETUP CK (posedge CK) (0.380::0.504))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.124::-0.108))
|
||||
(SETUP CK (posedge CK) (0.380::0.482))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_OUTFF_OPPEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
|
|
@ -290,10 +278,12 @@
|
|||
(CELLTYPE "OLOGICE3_TFF")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY CK (posedge CK) (0.249::0.286))
|
||||
(REMOVAL CK (posedge CK) (0.000::0.000))
|
||||
(SETUP CK (posedge CK) (0.471::0.591))
|
||||
(HOLD SR (posedge CK) (-0.318::-0.277))
|
||||
(RECOVERY SR (posedge CK) (0.249::0.286))
|
||||
(REMOVAL SR (posedge CK) (0.000::0.000))
|
||||
(SETUP SR (posedge CK) (0.471::0.591))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -302,16 +292,26 @@
|
|||
(TIMINGCHECK
|
||||
(HOLD D1 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D1 (posedge CK) (0.707::0.885))
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.302::-0.264))
|
||||
(SETUP CK (posedge CK) (0.622::0.788))
|
||||
(HOLD D2 (posedge CK) (-0.302::-0.264))
|
||||
(SETUP D2 (posedge CK) (0.622::0.788))
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD TCE (posedge CK) (-0.068::-0.060))
|
||||
(SETUP TCE (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
|
|
@ -363,28 +363,4 @@
|
|||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_NEG")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "OLOGICE3_TFF_TCE_DDR_SAMEEDGE")
|
||||
(INSTANCE OLOGICE3)
|
||||
(TIMINGCHECK
|
||||
(HOLD CK (posedge CK) (-0.068::-0.060))
|
||||
(SETUP CK (posedge CK) (0.389::0.505))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
|
||||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(TIMESCALE 1ps)
|
||||
(TIMESCALE 1ns)
|
||||
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue