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prjxray-db
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Updating info based on "Merge pull request #624 from mithro/kmaster". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-02-08 07:17:20 +00:00
parent d3ae4c65ef
commit b9c0324464
177 changed files with 1108013 additions and 1 deletions
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Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Fri Feb 8 04:18:20 UTC 2019 (2019-02-08T04:18:20+00:00).
Last updated on Fri Feb 8 07:33:25 UTC 2019 (2019-02-08T07:33:25+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [2830c4a](https://github.com/SymbiFlow/prjxray/commit/2830c4ab88edd4984acea9ac1d53f3f9be89dc8e).
@ -592,4 +592,180 @@ source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh
Results have checksums;
* [`389d7501980b8d12b5fe58af98158372ac3eaa1f557434f6ad96b7610c1ad378 ./zynq7/element_counts.csv`](./zynq7/element_counts.csv)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
* [`2504bd2baf68b3d20d6fe3a982494731258ebadddf0f27963b2e7f7cb5024d74 ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
* [`2504bd2baf68b3d20d6fe3a982494731258ebadddf0f27963b2e7f7cb5024d74 ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db)
* [`e58acdfa3cc740d2346dcb5d3a4c13434d459ebdc2ceb655dcb65fd631da4e4d ./zynq7/ppips_bram_r.db`](./zynq7/ppips_bram_r.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./zynq7/ppips_clbll_l.db`](./zynq7/ppips_clbll_l.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./zynq7/ppips_clbll_r.db`](./zynq7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./zynq7/ppips_clblm_l.db`](./zynq7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./zynq7/ppips_clblm_r.db`](./zynq7/ppips_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_l.db`](./zynq7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_r.db`](./zynq7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_l.db`](./zynq7/ppips_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_r.db`](./zynq7/ppips_hclk_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./zynq7/ppips_int_l.db`](./zynq7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./zynq7/ppips_int_r.db`](./zynq7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db)
* [`d365ac435d962883e23d83dc1b665cec2568de8cf7fab483f3af419e42a9866d ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db)
* [`365a1df8c7ad8e8259767b9a4296db9b1475ee2d1bddce9c11bf4b7a07ffee86 ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./zynq7/segbits_hclk_l.db`](./zynq7/segbits_hclk_l.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`bf41c15c9ab5f5453b1d9168101436a14ceac96a69055f12a1d8137f9c764cc9 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
* [`aa69b29ddfd61c2e1c8a3f7136486baa7165eb7d5cf46868b5ac1ee5f776f381 ./zynq7/site_type_BUFHCE.json`](./zynq7/site_type_BUFHCE.json)
* [`01b21db6c1e64995e74cb8ad29e244692e26dc19f3038a70dec569094d699018 ./zynq7/site_type_BUFIO.json`](./zynq7/site_type_BUFIO.json)
* [`d16f5baaba75a01d36a60efa8c07c3fddca230e11b496871b04e8f3823e25916 ./zynq7/site_type_BUFMRCE.json`](./zynq7/site_type_BUFMRCE.json)
* [`a5a19be7b32a9e26182a2646cf8608e98e6ec4aaf285baea3ab039078788e109 ./zynq7/site_type_BUFR.json`](./zynq7/site_type_BUFR.json)
* [`a06dc3686fd07cb3b0776319d7fc91431ae6bb297f3783e827989aa0e9e97fe7 ./zynq7/site_type_CAPTURE.json`](./zynq7/site_type_CAPTURE.json)
* [`d6d095ed918127a2970d71c73cf668124fc000fcf37ad5eec803dbd9efbe9a17 ./zynq7/site_type_DCIRESET.json`](./zynq7/site_type_DCIRESET.json)
* [`012311ea9db7d8d1a88c6a8ad13bec27d8d77295f854aa74846f14b28cefcc75 ./zynq7/site_type_DNA_PORT.json`](./zynq7/site_type_DNA_PORT.json)
* [`7bc10b6943898ec18297f8e2d94c294ad4e9b4899f1ca5e84eba3f8c55eea436 ./zynq7/site_type_DSP48E1.json`](./zynq7/site_type_DSP48E1.json)
* [`04cfc4a15f1a10add40b9d1d10f987293f89e5e1aef984c3cd9ecca781b02909 ./zynq7/site_type_EFUSE_USR.json`](./zynq7/site_type_EFUSE_USR.json)
* [`81110626cbec259d60eb732ea135546bfc69b8f26d5f45d34a54e4e5fba30f9d ./zynq7/site_type_FIFO18E1.json`](./zynq7/site_type_FIFO18E1.json)
* [`bcd387295f597629764677c85865ef34930e82d84999843163f6415ee83470d9 ./zynq7/site_type_FRAME_ECC.json`](./zynq7/site_type_FRAME_ECC.json)
* [`798da94b860f4cf48ef481cc0d647f46e7a2d3d7525c9300a671af5fa60b945a ./zynq7/site_type_ICAP.json`](./zynq7/site_type_ICAP.json)
* [`186345922143f4f47e397a9ad0d21f0f22f62210c77035c836f6fce7cfb82809 ./zynq7/site_type_IDELAYCTRL.json`](./zynq7/site_type_IDELAYCTRL.json)
* [`f6d9451dfc382946eb679d9c8de40fc5386a03ce710b471c5ff01561c5f9e84a ./zynq7/site_type_IDELAYE2.json`](./zynq7/site_type_IDELAYE2.json)
* [`3ea826fe33445c45d450e9600640830dde8a53d9ef0a32e8777d40842c25dc1e ./zynq7/site_type_ILOGICE3.json`](./zynq7/site_type_ILOGICE3.json)
* [`cffd17f7cce991b97d3af468b7462d8d3d72fa58423b715545a488ea5d9358e5 ./zynq7/site_type_IN_FIFO.json`](./zynq7/site_type_IN_FIFO.json)
* [`f615da462018bb36b8f28fb5dc5b3871581a7f33b6ed7704bd6787f586c2ab5c ./zynq7/site_type_IOB33.json`](./zynq7/site_type_IOB33.json)
* [`94d649164e7dd8724b49e2fe16a3d1ec8dd37994f6ee53fe52aff2fd61604737 ./zynq7/site_type_IOB33M.json`](./zynq7/site_type_IOB33M.json)
* [`f26fbc06575fa2d5abde06ec617af86bf386473dd97e6eff17c3929c87e889fb ./zynq7/site_type_IOB33S.json`](./zynq7/site_type_IOB33S.json)
* [`76bfa959e57791ca27a135530290504fd686a1d771b4f174494fa11dae5320ba ./zynq7/site_type_IOPAD.json`](./zynq7/site_type_IOPAD.json)
* [`57f36c456bb9936328761cba5d98ac11aef35480951e4bbd01ebff87f281da35 ./zynq7/site_type_IPAD.json`](./zynq7/site_type_IPAD.json)
* [`57376aa966edcaf803d50d2a88fa393149915e35175f353375d09c0d41e10172 ./zynq7/site_type_MMCME2_ADV.json`](./zynq7/site_type_MMCME2_ADV.json)
* [`dc96b19ee6e827360c59e845bbf9ea559ea881226a0344fd932fa691d53a099d ./zynq7/site_type_OLOGICE3.json`](./zynq7/site_type_OLOGICE3.json)
* [`c42ae28d4ea844f7bdd8eee4cafd9e5c5a1fff1b37206311cb0c9496f033b111 ./zynq7/site_type_OUT_FIFO.json`](./zynq7/site_type_OUT_FIFO.json)
* [`aeb8e6803ff63bb256644a65840ed39dcb64fccb3e01b44ae3479ae67f3341ac ./zynq7/site_type_PHASER_IN_PHY.json`](./zynq7/site_type_PHASER_IN_PHY.json)
* [`9d56de422cf14b2886d45d8b88a38ae159bd66630f98aea1acb1b1bd1321d52d ./zynq7/site_type_PHASER_OUT_PHY.json`](./zynq7/site_type_PHASER_OUT_PHY.json)
* [`eafe5543b8d36752a006772e9c1046331157c3f6fcaead642a1d93b6ec3c5caa ./zynq7/site_type_PHASER_REF.json`](./zynq7/site_type_PHASER_REF.json)
* [`684700d5ca81c587e4cb36b4e4832d09c295f2832c1fb6eadc8142b5d93451d3 ./zynq7/site_type_PHY_CONTROL.json`](./zynq7/site_type_PHY_CONTROL.json)
* [`d7d4341d7e1029cf59f70de76a59c627510c97a421964d1bb7d8e83bd918aa4f ./zynq7/site_type_PLLE2_ADV.json`](./zynq7/site_type_PLLE2_ADV.json)
* [`c01006fabc55d6b03265a3cc14576c9e28ccc37109331daef8cfdef3e726a029 ./zynq7/site_type_PMV2.json`](./zynq7/site_type_PMV2.json)
* [`59c2e67b36f6fb734a32526b3949d08751b29e113a53b57cac458d2100d3b9d3 ./zynq7/site_type_PS7.json`](./zynq7/site_type_PS7.json)
* [`261782a60bf2c6419f6b9bc41e830003cdd000c0b96b6c1b0a2713ba49f62348 ./zynq7/site_type_RAMB18E1.json`](./zynq7/site_type_RAMB18E1.json)
* [`df462af9d9cad14c6c500bbd01b30d0620320851692e5330ebb16b01250a81da ./zynq7/site_type_RAMBFIFO36E1.json`](./zynq7/site_type_RAMBFIFO36E1.json)
* [`5237c206807877602106a66506a2a73bc345fca67189ca7873bbfc6d8b52be53 ./zynq7/site_type_SLICEL.json`](./zynq7/site_type_SLICEL.json)
* [`a0af169e3f78dbb650a631ae61c2a7bbe175e48942729f4a5aed2351f1844439 ./zynq7/site_type_SLICEM.json`](./zynq7/site_type_SLICEM.json)
* [`bfd80f11db70c478290494ee936a172aac3ebd2351c9d82a0ebd10189a389c6f ./zynq7/site_type_STARTUP.json`](./zynq7/site_type_STARTUP.json)
* [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./zynq7/site_type_TIEOFF.json`](./zynq7/site_type_TIEOFF.json)
* [`4a52214be0712e1f5e3746c304d3299fd2bfa9e578956df1d6fcd6128614da12 ./zynq7/site_type_USR_ACCESS.json`](./zynq7/site_type_USR_ACCESS.json)
* [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./zynq7/site_type_XADC.json`](./zynq7/site_type_XADC.json)
* [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./zynq7/tile_type_BRAM_INT_INTERFACE_L.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./zynq7/tile_type_BRAM_INT_INTERFACE_R.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`c0f50db1186b7694801c078137764c273f217e019bd96754edbc9ab19b0ade49 ./zynq7/tile_type_BRAM_L.json`](./zynq7/tile_type_BRAM_L.json)
* [`8d18be624cb3094d3775d67ecb1eddc571ada7089deb0278e737c362870b35e4 ./zynq7/tile_type_BRAM_R.json`](./zynq7/tile_type_BRAM_R.json)
* [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./zynq7/tile_type_BRKH_BRAM.json`](./zynq7/tile_type_BRKH_BRAM.json)
* [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./zynq7/tile_type_BRKH_CLB.json`](./zynq7/tile_type_BRKH_CLB.json)
* [`d036cb35cb1bb3237b76f2e755fd3e5902e4588b03e565e4c01ecaa6429457fa ./zynq7/tile_type_BRKH_CLK.json`](./zynq7/tile_type_BRKH_CLK.json)
* [`ec60392fdf039d697e2de0b6c856d118a52ac7fb5bc50da206802f98a8967ea6 ./zynq7/tile_type_BRKH_CMT.json`](./zynq7/tile_type_BRKH_CMT.json)
* [`721f0a9fab25908b7ae0da9b94903a8ca1cb63d42dc5119d7b143309d27156fd ./zynq7/tile_type_BRKH_DSP_L.json`](./zynq7/tile_type_BRKH_DSP_L.json)
* [`db175274054c15c1cf7093a5117628fb30f27ddd50a29eabcc894e39236f95d8 ./zynq7/tile_type_BRKH_DSP_R.json`](./zynq7/tile_type_BRKH_DSP_R.json)
* [`68c36646e682266cb3aecade1627160b22112d72b5859f4aae3cd32df488422a ./zynq7/tile_type_BRKH_INT.json`](./zynq7/tile_type_BRKH_INT.json)
* [`b3700d8432a5ea4375fab4419bba143bc79dfd137a7110117ea085d79a2dd766 ./zynq7/tile_type_B_TERM_INT.json`](./zynq7/tile_type_B_TERM_INT.json)
* [`db3f1d44e0db5cf61bc97ee1c2002584e4588c473d412ca6739132fedabfa08b ./zynq7/tile_type_B_TERM_INT_PSS.json`](./zynq7/tile_type_B_TERM_INT_PSS.json)
* [`89e6d861ce30aaeb1df937f32aac00d4121de3089ea2bfa74945f93f1c4303b4 ./zynq7/tile_type_B_TERM_VBRK.json`](./zynq7/tile_type_B_TERM_VBRK.json)
* [`606581f9ab6d5c8ded71371ea6806e741b0739e5e32e69c503e4ebddc9544ec9 ./zynq7/tile_type_CFG_CENTER_BOT.json`](./zynq7/tile_type_CFG_CENTER_BOT.json)
* [`820a133d2cdab23ca7c64570daa391e3329826759fa82b2d12914878676274ce ./zynq7/tile_type_CFG_CENTER_MID.json`](./zynq7/tile_type_CFG_CENTER_MID.json)
* [`cc6b420c4804236a1b2928e5c86cfa6f6143b93843e40081d14c2bfd5d5e76a8 ./zynq7/tile_type_CFG_CENTER_TOP.json`](./zynq7/tile_type_CFG_CENTER_TOP.json)
* [`9fc927b122dbb55a74c48f846abf42ffc92537365d5524866b47d2217f70067f ./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json)
* [`8eaac15316c7feb9da13a331e52d3c5f140fd92b4bcde5ceb5495fc35bef2c4d ./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json)
* [`9f229626a932dd9ea0db5f82d923089f8d14f7495e2db348a9bcd4413528591b ./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json)
* [`0cf36c0ab629c583c01ae9efa04093e0644da71b7b0dfbc175dfcf9ed56650d5 ./zynq7/tile_type_CLBLL_L.json`](./zynq7/tile_type_CLBLL_L.json)
* [`3607f851807c3b420d21b4fe0c0b26b91db19d1384ba39d45f4c771f7251544e ./zynq7/tile_type_CLBLL_R.json`](./zynq7/tile_type_CLBLL_R.json)
* [`8f91f81d6f549d0f728dbab89baca64bae44491b1b0df30ae6ca4193b6eed951 ./zynq7/tile_type_CLBLM_L.json`](./zynq7/tile_type_CLBLM_L.json)
* [`50812dbe755a110f8e33285728a9b565d46d1e71e76e63085fc6d1dea4f4dee7 ./zynq7/tile_type_CLBLM_R.json`](./zynq7/tile_type_CLBLM_R.json)
* [`3ab28fa68486317ac22e260c8d0ac81bcccc0b214cff21b66cda2cf0974d62bb ./zynq7/tile_type_CLK_BUFG_BOT_R.json`](./zynq7/tile_type_CLK_BUFG_BOT_R.json)
* [`7e7b949435c6724c886ab674148e7a241d7761b63d8b700fbeb2b3f4105329bb ./zynq7/tile_type_CLK_BUFG_REBUF.json`](./zynq7/tile_type_CLK_BUFG_REBUF.json)
* [`b1fdae383da0691975b3836a0a66fa566165de094e4bd416d664dc32f2d010c8 ./zynq7/tile_type_CLK_BUFG_TOP_R.json`](./zynq7/tile_type_CLK_BUFG_TOP_R.json)
* [`9900c1d7c03b75bb765c57b00b20fbefd09efeccb325afba72901b941d5db0de ./zynq7/tile_type_CLK_FEED.json`](./zynq7/tile_type_CLK_FEED.json)
* [`fa0923a2169819ecc93697c7255aef24e9dbee2a3c5d8c1df3f86956e0bc8b08 ./zynq7/tile_type_CLK_HROW_BOT_R.json`](./zynq7/tile_type_CLK_HROW_BOT_R.json)
* [`71f60f081cb9718ca95f3c004034dde427a1323ae4f71f94c68f3ecb961f1d2f ./zynq7/tile_type_CLK_HROW_TOP_R.json`](./zynq7/tile_type_CLK_HROW_TOP_R.json)
* [`3d200f97f5d0608d4577dcaf9ae59c34be18f4d1406aa71815d56327fc2a3564 ./zynq7/tile_type_CLK_MTBF2.json`](./zynq7/tile_type_CLK_MTBF2.json)
* [`0163ab8305f14d439e303fc072bf980549efd65c42494e468bc2b2e0bd3ff0a6 ./zynq7/tile_type_CLK_PMV.json`](./zynq7/tile_type_CLK_PMV.json)
* [`1e08a2d1f2c7e0ec12b0eec202c3759fbfc82fab01b9d0b5d1658299d8ac5506 ./zynq7/tile_type_CLK_PMV2.json`](./zynq7/tile_type_CLK_PMV2.json)
* [`bf52b93861ca5856dab593dde196a21ab8a9522b4eb58f13fe206beaba8c78f2 ./zynq7/tile_type_CLK_PMV2_SVT.json`](./zynq7/tile_type_CLK_PMV2_SVT.json)
* [`e7123b7dbeba2ebbf4a6ae04fb87bd114548befc9bb812d7bf4bee3401aa44fa ./zynq7/tile_type_CLK_PMVIOB.json`](./zynq7/tile_type_CLK_PMVIOB.json)
* [`42236b4ea5a40883822299aef2c5eb6ef2adb30c715145a9c36c5dd9e84e102e ./zynq7/tile_type_CLK_TERM.json`](./zynq7/tile_type_CLK_TERM.json)
* [`f985c5c1c1186eb314e1bd727b4195b88f69739fcb991efbafee963310b880f9 ./zynq7/tile_type_CMT_FIFO_L.json`](./zynq7/tile_type_CMT_FIFO_L.json)
* [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./zynq7/tile_type_CMT_PMV_L.json`](./zynq7/tile_type_CMT_PMV_L.json)
* [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./zynq7/tile_type_CMT_TOP_L_LOWER_B.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_B.json)
* [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./zynq7/tile_type_CMT_TOP_L_LOWER_T.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_T.json)
* [`74796039811f8938f5ba648cdf6776631345c63a4460e72c6562f457dd176af9 ./zynq7/tile_type_CMT_TOP_L_UPPER_B.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_B.json)
* [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./zynq7/tile_type_CMT_TOP_L_UPPER_T.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_T.json)
* [`893e626468a393ecd83bf68f313b4148de82f37d41ac18274be0e3056b23eebd ./zynq7/tile_type_DSP_L.json`](./zynq7/tile_type_DSP_L.json)
* [`9cb67583b70ebc2ae291d3129f67dff2f034745fe7c70478b61b0c8214018346 ./zynq7/tile_type_DSP_R.json`](./zynq7/tile_type_DSP_R.json)
* [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./zynq7/tile_type_HCLK_BRAM.json`](./zynq7/tile_type_HCLK_BRAM.json)
* [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./zynq7/tile_type_HCLK_CLB.json`](./zynq7/tile_type_HCLK_CLB.json)
* [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./zynq7/tile_type_HCLK_CMT_L.json`](./zynq7/tile_type_HCLK_CMT_L.json)
* [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./zynq7/tile_type_HCLK_DSP_L.json`](./zynq7/tile_type_HCLK_DSP_L.json)
* [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./zynq7/tile_type_HCLK_DSP_R.json`](./zynq7/tile_type_HCLK_DSP_R.json)
* [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./zynq7/tile_type_HCLK_FEEDTHRU_1.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1.json)
* [`2c887222cc585d9f90588029f5076f4a6dc8b7449928f5ba1d919845076c0b9d ./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json)
* [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./zynq7/tile_type_HCLK_FEEDTHRU_2.json`](./zynq7/tile_type_HCLK_FEEDTHRU_2.json)
* [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./zynq7/tile_type_HCLK_FIFO_L.json`](./zynq7/tile_type_HCLK_FIFO_L.json)
* [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./zynq7/tile_type_HCLK_INT_INTERFACE.json`](./zynq7/tile_type_HCLK_INT_INTERFACE.json)
* [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./zynq7/tile_type_HCLK_IOB.json`](./zynq7/tile_type_HCLK_IOB.json)
* [`012dd251f28565bd1e4c32568338f9de1b7096b0cd8ed7cd61c7a4e482eafd2e ./zynq7/tile_type_HCLK_IOI3.json`](./zynq7/tile_type_HCLK_IOI3.json)
* [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./zynq7/tile_type_HCLK_L.json`](./zynq7/tile_type_HCLK_L.json)
* [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./zynq7/tile_type_HCLK_R.json`](./zynq7/tile_type_HCLK_R.json)
* [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./zynq7/tile_type_HCLK_TERM.json`](./zynq7/tile_type_HCLK_TERM.json)
* [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./zynq7/tile_type_HCLK_VBRK.json`](./zynq7/tile_type_HCLK_VBRK.json)
* [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./zynq7/tile_type_HCLK_VFRAME.json`](./zynq7/tile_type_HCLK_VFRAME.json)
* [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./zynq7/tile_type_INT_FEEDTHRU_1.json`](./zynq7/tile_type_INT_FEEDTHRU_1.json)
* [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./zynq7/tile_type_INT_FEEDTHRU_2.json`](./zynq7/tile_type_INT_FEEDTHRU_2.json)
* [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./zynq7/tile_type_INT_INTERFACE_L.json`](./zynq7/tile_type_INT_INTERFACE_L.json)
* [`39d9152faf8afe07a8605aaf0e775b2668dca2eed3a46e4c1b6d444f594308db ./zynq7/tile_type_INT_INTERFACE_PSS_L.json`](./zynq7/tile_type_INT_INTERFACE_PSS_L.json)
* [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./zynq7/tile_type_INT_INTERFACE_R.json`](./zynq7/tile_type_INT_INTERFACE_R.json)
* [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./zynq7/tile_type_INT_L.json`](./zynq7/tile_type_INT_L.json)
* [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./zynq7/tile_type_INT_R.json`](./zynq7/tile_type_INT_R.json)
* [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./zynq7/tile_type_IO_INT_INTERFACE_R.json`](./zynq7/tile_type_IO_INT_INTERFACE_R.json)
* [`ec029a5a1ca3912c5582864edab9b46e0e955e901a8f08264bf9ec3fba0aca0d ./zynq7/tile_type_MONITOR_BOT_PELE1.json`](./zynq7/tile_type_MONITOR_BOT_PELE1.json)
* [`6ead1217a6413d2ce272c1447b230031b508d1cc897ec80260d4afb03f66dcdf ./zynq7/tile_type_MONITOR_MID_PELE1.json`](./zynq7/tile_type_MONITOR_MID_PELE1.json)
* [`1c88d8e7f113af2e568b2ddaa0f0a7da71bd5fcb97a19aca2caef1d963e60e3a ./zynq7/tile_type_MONITOR_TOP_PELE1.json`](./zynq7/tile_type_MONITOR_TOP_PELE1.json)
* [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./zynq7/tile_type_NULL.json`](./zynq7/tile_type_NULL.json)
* [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./zynq7/tile_type_PCIE_NULL.json`](./zynq7/tile_type_PCIE_NULL.json)
* [`a122f8026a2a5edab39eabc9117a63bc29fb1d2aeaf7b1afd2b40d1b493afa4d ./zynq7/tile_type_PSS0.json`](./zynq7/tile_type_PSS0.json)
* [`178db0b66318b31f8852f82297ab39d02287feca33c4fd8284f1c0e19791082a ./zynq7/tile_type_PSS1.json`](./zynq7/tile_type_PSS1.json)
* [`2dc21c523cfe81330135816b6006f75b82538da3741feca3a1fc720e6c6d9855 ./zynq7/tile_type_PSS2.json`](./zynq7/tile_type_PSS2.json)
* [`a40337531311fa9e1bc0371b0deee86008a7cba18f3924a62b0e684f9f1b4537 ./zynq7/tile_type_PSS3.json`](./zynq7/tile_type_PSS3.json)
* [`bda246d0e8ea8ca946ba6877502428ed0fd52240fb6fc5339d9b263653c0cf93 ./zynq7/tile_type_PSS4.json`](./zynq7/tile_type_PSS4.json)
* [`a01a9bfa1d6ac7762d56b57487ab1f4efa8f53e77c6fa452adfa3aff120811fb ./zynq7/tile_type_RIOB33.json`](./zynq7/tile_type_RIOB33.json)
* [`66ea3a8940b40915699e7e2fa37b3d65403e7f5d51afe0daf14537e662da9385 ./zynq7/tile_type_RIOB33_SING.json`](./zynq7/tile_type_RIOB33_SING.json)
* [`96029c4d8a29149b3aa063bbcd3a64bbbf28f987e8e491d2630f7e78d47354b2 ./zynq7/tile_type_RIOI3.json`](./zynq7/tile_type_RIOI3.json)
* [`6c8c8745a8bcd8ebcf6396dfda55fd7b958b2de19ac1a926e412716b7d8dd2b2 ./zynq7/tile_type_RIOI3_SING.json`](./zynq7/tile_type_RIOI3_SING.json)
* [`89b4d83a435609119ca878a4cdbfc3fc31c8c30d66459bf3d84b4c8c012c1139 ./zynq7/tile_type_RIOI3_TBYTESRC.json`](./zynq7/tile_type_RIOI3_TBYTESRC.json)
* [`e188cfd52a8cd3edb869bd29a02e95e8cfc06688727982f9c364c54b5d20c409 ./zynq7/tile_type_RIOI3_TBYTETERM.json`](./zynq7/tile_type_RIOI3_TBYTETERM.json)
* [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./zynq7/tile_type_R_TERM_INT.json`](./zynq7/tile_type_R_TERM_INT.json)
* [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./zynq7/tile_type_TERM_CMT.json`](./zynq7/tile_type_TERM_CMT.json)
* [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./zynq7/tile_type_T_TERM_INT.json`](./zynq7/tile_type_T_TERM_INT.json)
* [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
* [`ec8a809ea4fb28ce8779491097bb32bf1c7a740b70039b4210c03ce75de2070e ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json)
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml)

9
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@ -0,0 +1,9 @@
type,count
tiles,13440
sites,8590
site_pins,305582
site_pips,644768
pips,12462138
package_pins,400
nodes,1122477
wires,3607758
1 type count
2 tiles 13440
3 sites 8590
4 site_pins 305582
5 site_pips 644768
6 pips 12462138
7 package_pins 400
8 nodes 1122477
9 wires 3607758

36864
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104
zynq7/mask_hclk_l.db Normal file
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@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

104
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@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

24
zynq7/ppips_bram_int_interface_l.db Normal file
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@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
zynq7/ppips_bram_int_interface_r.db Normal file
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@ -0,0 +1,24 @@
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

794
zynq7/ppips_bram_l.db Normal file
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@ -0,0 +1,794 @@
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_L.BRAM_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_L.BRAM_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_L.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_L.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_L.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_L.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_L.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_L.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_L.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_L.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_L.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_L.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_L.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_L.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_L.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_L.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_L.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_L.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_L.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_L.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_L.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_L.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_L.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_L.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_L.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_L.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_L.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_L.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_L.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_L.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_L.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_L.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_L.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_L.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_L.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_L.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_L.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_L.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_L.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_L.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_L.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_L.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_L.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_L.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_L.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_L.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_L.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_L.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_L.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_L.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_L.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_L.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_L.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_L.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_L.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_L.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_L.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_L.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_L.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_L.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_L.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_L.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_L.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_L.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_L.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_L.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_L.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_L.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_L.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_L.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_L.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_L.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_L.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_L.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_L.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_L.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_L.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_L.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_L.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_L.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_L.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_L.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_L.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_L.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_L.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_L.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_L.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_L.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_L.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_L.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_L.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_L.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_L.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_L.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_L.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_L.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_L.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_L.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_L.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_L.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_L.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_L.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_L.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_L.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_L.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_L.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_L.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_L.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_L.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_L.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_L.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_L.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_L.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_L.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_L.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_L.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_L.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_L.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_L.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_L.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_L.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_L.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_L.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_L.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_L.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_L.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_L.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_L.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_L.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_L.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_L.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_L.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_L.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_L.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_L.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_L.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_L.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_L.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_L.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_L.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_L.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_L.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_L.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_L.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_L.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_L.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_L.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_L.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_L.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_L.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_L.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_L.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_L.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_L.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_L.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_L.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_L.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_L.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_L.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_L.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_L.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_L.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_L.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_L.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_L.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_L.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_L.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_L.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_L.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_L.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_L.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_L.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_L.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_L.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_L.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_L.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_L.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_L.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_L.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_L.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_L.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_L.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_L.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_L.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_L.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_L.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_L.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_L.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_ADDRARDADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_L.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_ADDRBWRADDRL15 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_L.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_L.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_L.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_L.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_L.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_L.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_L.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_L.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_L.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_L.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_L.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_L.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_L.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_L.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_L.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_L.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_L.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_L.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_L.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_L.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_L.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_L.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_L.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_L.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_L.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_L.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_L.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_L.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_L.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_L.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_L.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_L.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_L.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_L.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_L.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_L.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_L.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_L.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_L.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_L.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_L.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_L.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_L.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_L.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_L.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_L.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_L.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_L.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_L.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

794
zynq7/ppips_bram_r.db Normal file
View File

@ -0,0 +1,794 @@
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_CASCOUT_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15.BRAM_IMUX31_3 always
BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15.BRAM_IMUX39_3 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_0.BRAM_FIFO36_DOADOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_1.BRAM_FIFO36_DOPADOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_2.BRAM_FIFO36_DOADOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_FIFO36_DOADOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_3.BRAM_RAMB18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_FIFO36_DOADOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B0_4.BRAM_RAMB18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_0.BRAM_FIFO36_DOBDOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_1.BRAM_FIFO36_DOBDOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO18_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_2.BRAM_FIFO36_ALMOSTFULL always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_FIFO36_DOBDOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_3.BRAM_RAMB18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_FIFO36_DOBDOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B1_4.BRAM_RAMB18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_0.BRAM_FIFO36_DOADOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_1.BRAM_FIFO36_DOADOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO18_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_2.BRAM_FIFO36_ALMOSTEMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_FIFO36_DOADOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_3.BRAM_RAMB18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_FIFO36_DOADOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B2_4.BRAM_RAMB18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_0.BRAM_FIFO36_DOBDOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_1.BRAM_FIFO36_DOBDOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_FIFO36_DOBDOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_2.BRAM_RAMB18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_FIFO36_DOPBDOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_3.BRAM_RAMB18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_FIFO36_DOBDOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B3_4.BRAM_RAMB18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO18_DOBDO0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_0.BRAM_FIFO36_DOBDOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO18_DOPBDOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_1.BRAM_FIFO36_DOPBDOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO18_DOBDO7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_2.BRAM_FIFO36_DOBDOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_FIFO36_DOBDOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_3.BRAM_RAMB18_DOBDO1 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_FIFO36_DOBDOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B4_4.BRAM_RAMB18_DOBDO4 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO18_DOADO9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_0.BRAM_FIFO36_DOADOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO18_DOADO12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_1.BRAM_FIFO36_DOADOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO18_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_2.BRAM_FIFO36_FULL always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_FIFO36_DOADOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_3.BRAM_RAMB18_DOADO10 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_FIFO36_DOADOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B5_4.BRAM_RAMB18_DOADO13 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO18_DOBDO2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_0.BRAM_FIFO36_DOBDOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO18_DOBDO5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_1.BRAM_FIFO36_DOBDOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO18_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_2.BRAM_FIFO36_EMPTY always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_FIFO36_DOBDOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_3.BRAM_RAMB18_DOBDO3 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_FIFO36_DOBDOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B6_4.BRAM_RAMB18_DOBDO6 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO18_DOADO11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_0.BRAM_FIFO36_DOADOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO18_DOADO14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_1.BRAM_FIFO36_DOADOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_FIFO36_DOADOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_2.BRAM_RAMB18_DOADO8 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_FIFO36_DOPADOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_3.BRAM_RAMB18_DOPADOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_FIFO36_DOADOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B7_4.BRAM_RAMB18_DOADO15 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_0.BRAM_FIFO36_DOADOL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_1.BRAM_FIFO36_DOPADOPL0 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_2.BRAM_FIFO36_DOADOL7 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_FIFO36_DOADOU1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_3.BRAM_RAMB18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_FIFO36_DOADOU4 always
BRAM_R.BRAM_LOGIC_OUTS_B8_4.BRAM_RAMB18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO18_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_0.BRAM_FIFO36_RDCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO18_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_1.BRAM_FIFO36_RDCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B9_2.BRAM_FIFO36_SBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO18_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B9_3.BRAM_FIFO36_WRCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_0.BRAM_FIFO36_DOADOL2 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_1.BRAM_FIFO36_DOADOL5 always
BRAM_R.BRAM_LOGIC_OUTS_B10_2.BRAM_FIFO36_ECCPARITY4 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_FIFO36_DOADOU3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_3.BRAM_RAMB18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_FIFO36_DOADOU6 always
BRAM_R.BRAM_LOGIC_OUTS_B10_4.BRAM_RAMB18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B11_0.BRAM_FIFO36_TSTOUT4 always
BRAM_R.BRAM_LOGIC_OUTS_B11_1.BRAM_FIFO36_TSTOUT3 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO18_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_2.BRAM_FIFO36_RDCOUNT9 always
BRAM_R.BRAM_LOGIC_OUTS_B11_3.BRAM_FIFO36_ECCPARITY7 always
BRAM_R.BRAM_LOGIC_OUTS_B11_4.BRAM_FIFO36_TSTOUT2 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO18_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_0.BRAM_FIFO36_RDCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO18_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_1.BRAM_FIFO36_RDCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO18_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_2.BRAM_FIFO36_WRCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B12_3.BRAM_FIFO36_ECCPARITY1 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO18_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B12_4.BRAM_FIFO36_WRCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO18_DOADO1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_0.BRAM_FIFO36_DOADOL1 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO18_DOADO4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_1.BRAM_FIFO36_DOADOL4 always
BRAM_R.BRAM_LOGIC_OUTS_B13_2.BRAM_FIFO36_ECCPARITY2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_FIFO36_DOADOU2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_3.BRAM_RAMB18_DOADO2 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_FIFO36_DOADOU5 always
BRAM_R.BRAM_LOGIC_OUTS_B13_4.BRAM_RAMB18_DOADO5 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO18_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_0.BRAM_FIFO36_WRCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO18_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_1.BRAM_FIFO36_WRCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO18_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_2.BRAM_FIFO36_RDERR always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO18_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_3.BRAM_FIFO36_RDCOUNT7 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO18_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B14_4.BRAM_FIFO36_RDCOUNT11 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO18_DOADO3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_0.BRAM_FIFO36_DOADOL3 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO18_DOADO6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_1.BRAM_FIFO36_DOADOL6 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_FIFO36_DOADOU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_2.BRAM_RAMB18_DOADO0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_FIFO36_DOPADOPU0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_3.BRAM_RAMB18_DOPADOP0 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_FIFO36_DOADOU7 always
BRAM_R.BRAM_LOGIC_OUTS_B15_4.BRAM_RAMB18_DOADO7 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO18_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_0.BRAM_FIFO36_WRCOUNT0 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO18_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_1.BRAM_FIFO36_WRCOUNT3 always
BRAM_R.BRAM_LOGIC_OUTS_B16_2.BRAM_FIFO36_DBITERR always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO18_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_3.BRAM_FIFO36_RDCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO18_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B16_4.BRAM_FIFO36_RDCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_0.BRAM_FIFO36_DOBDOL11 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_1.BRAM_FIFO36_DOBDOL14 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_FIFO36_DOBDOU8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_2.BRAM_RAMB18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_FIFO36_DOPBDOPU1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_3.BRAM_RAMB18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_FIFO36_DOBDOU15 always
BRAM_R.BRAM_LOGIC_OUTS_B17_4.BRAM_RAMB18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B18_0.BRAM_FIFO36_TSTOUT1 always
BRAM_R.BRAM_LOGIC_OUTS_B18_1.BRAM_FIFO36_TSTOUT0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO18_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_2.BRAM_FIFO36_WRCOUNT6 always
BRAM_R.BRAM_LOGIC_OUTS_B18_3.BRAM_FIFO36_ECCPARITY0 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO18_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B18_4.BRAM_FIFO36_WRCOUNT10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_0.BRAM_FIFO36_DOBDOL9 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_1.BRAM_FIFO36_DOBDOL12 always
BRAM_R.BRAM_LOGIC_OUTS_B19_2.BRAM_FIFO36_ECCPARITY3 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_FIFO36_DOBDOU10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_3.BRAM_RAMB18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_FIFO36_DOBDOU13 always
BRAM_R.BRAM_LOGIC_OUTS_B19_4.BRAM_RAMB18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO18_DOBDO10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_0.BRAM_FIFO36_DOBDOL10 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO18_DOBDO13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_1.BRAM_FIFO36_DOBDOL13 always
BRAM_R.BRAM_LOGIC_OUTS_B20_2.BRAM_FIFO36_ECCPARITY5 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_FIFO36_DOBDOU11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_3.BRAM_RAMB18_DOBDO11 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_FIFO36_DOBDOU14 always
BRAM_R.BRAM_LOGIC_OUTS_B20_4.BRAM_RAMB18_DOBDO14 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO18_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_0.BRAM_FIFO36_WRCOUNT2 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO18_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_1.BRAM_FIFO36_WRCOUNT5 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO18_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_2.BRAM_FIFO36_RDCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B21_3.BRAM_FIFO36_ECCPARITY6 always
BRAM_R.BRAM_LOGIC_OUTS_B21_4.BRAM_FIFO36_RDCOUNT12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO18_DOBDO8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_0.BRAM_FIFO36_DOBDOL8 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO18_DOPBDOP1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_1.BRAM_FIFO36_DOPBDOPL1 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO18_DOBDO15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_2.BRAM_FIFO36_DOBDOL15 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_FIFO36_DOBDOU9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_3.BRAM_RAMB18_DOBDO9 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_FIFO36_DOBDOU12 always
BRAM_R.BRAM_LOGIC_OUTS_B22_4.BRAM_RAMB18_DOBDO12 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO18_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_0.BRAM_FIFO36_RDCOUNT1 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO18_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_1.BRAM_FIFO36_RDCOUNT4 always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO18_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_2.BRAM_FIFO36_WRERR always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO18_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_3.BRAM_FIFO36_WRCOUNT8 always
BRAM_R.BRAM_LOGIC_OUTS_B23_4.BRAM_FIFO36_WRCOUNT12 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0.BRAM_IMUX17_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1.BRAM_IMUX18_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2.BRAM_IMUX19_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3.BRAM_IMUX18_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4.BRAM_IMUX21_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5.BRAM_IMUX20_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6.BRAM_IMUX16_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7.BRAM_IMUX17_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8.BRAM_IMUX20_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9.BRAM_IMUX19_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10.BRAM_IMUX20_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11.BRAM_IMUX22_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12.BRAM_IMUX21_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13.BRAM_IMUX23_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14.BRAM_IMUX22_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0.BRAM_IMUX9_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1.BRAM_IMUX10_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2.BRAM_IMUX11_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3.BRAM_IMUX10_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4.BRAM_IMUX13_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5.BRAM_IMUX12_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6.BRAM_IMUX8_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7.BRAM_IMUX9_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8.BRAM_IMUX12_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9.BRAM_IMUX11_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10.BRAM_IMUX12_2 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11.BRAM_IMUX14_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12.BRAM_IMUX13_3 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13.BRAM_IMUX15_1 always
BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14.BRAM_IMUX14_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0.BRAM_IMUX33_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1.BRAM_IMUX34_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2.BRAM_IMUX35_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3.BRAM_IMUX34_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4.BRAM_IMUX37_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5.BRAM_IMUX36_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6.BRAM_IMUX32_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7.BRAM_IMUX33_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8.BRAM_IMUX36_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9.BRAM_IMUX35_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10.BRAM_IMUX36_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11.BRAM_IMUX38_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12.BRAM_IMUX37_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13.BRAM_IMUX39_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14.BRAM_IMUX38_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0.BRAM_IMUX25_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1.BRAM_IMUX26_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2.BRAM_IMUX27_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3.BRAM_IMUX26_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4.BRAM_IMUX29_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5.BRAM_IMUX28_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6.BRAM_IMUX24_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7.BRAM_IMUX25_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8.BRAM_IMUX28_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9.BRAM_IMUX27_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10.BRAM_IMUX28_2 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11.BRAM_IMUX30_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12.BRAM_IMUX29_3 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13.BRAM_IMUX31_1 always
BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14.BRAM_IMUX30_3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_UTURN_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_UTURN_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_UTURN_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO18_CLKARDCLK.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO18_CLKBWRCLK.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO18_ENARDEN.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO18_ENBWREN.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO18_REGCEAREGCE.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO18_REGCEB.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO18_REGCLKARDRCLK.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO18_REGCLKB.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO18_RSTRAMARSTRAM.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO18_RSTRAMB.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO18_RSTREGARSTREG.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO18_RSTREGB.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR0.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR1.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR2.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR3.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR4.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR5.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR6.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR7.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR8.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR9.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR10.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR11.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR12.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRARDADDR13.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR0.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR1.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR2.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR3.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR4.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR5.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR6.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR7.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR8.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR9.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR10.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR11.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR12.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO18_ADDRBWRADDR13.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO18_DIADI0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO18_DIADI1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO18_DIADI2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO18_DIADI3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO18_DIADI4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO18_DIADI5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO18_DIADI6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO18_DIADI7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO18_DIADI8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO18_DIADI9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO18_DIADI10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO18_DIADI11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO18_DIADI12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO18_DIADI13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO18_DIADI14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO18_DIADI15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO18_DIBDI0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO18_DIBDI1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO18_DIBDI2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO18_DIBDI3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO18_DIBDI4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO18_DIBDI5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO18_DIBDI6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO18_DIBDI7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO18_DIBDI8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO18_DIBDI9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO18_DIBDI10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO18_DIBDI11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO18_DIBDI12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO18_DIBDI13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO18_DIBDI14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO18_DIBDI15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO18_DIPADIP0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO18_DIPADIP1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO18_DIPBDIP0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO18_DIPBDIP1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO18_WEA0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO18_WEA1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO18_WEA2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO18_WEA3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO18_WEBWE0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO18_WEBWE1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO18_WEBWE2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO18_WEBWE3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO18_WEBWE4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO18_WEBWE5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO18_WEBWE6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO18_WEBWE7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_CASCADEOUTA_1.BRAM_FIFO36_CASCADEOUTA always
BRAM_R.BRAM_FIFO36_CASCADEOUTB_1.BRAM_FIFO36_CASCADEOUTB always
BRAM_R.BRAM_FIFO36_CLKARDCLKL.BRAM_CLK0_3 always
BRAM_R.BRAM_FIFO36_CLKARDCLKU.BRAM_CLK1_3 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKL.BRAM_CLK0_1 always
BRAM_R.BRAM_FIFO36_CLKBWRCLKU.BRAM_CLK1_1 always
BRAM_R.BRAM_FIFO36_ENARDENL.BRAM_IMUX18_2 always
BRAM_R.BRAM_FIFO36_ENARDENU.BRAM_IMUX10_2 always
BRAM_R.BRAM_FIFO36_ENBWRENL.BRAM_IMUX34_2 always
BRAM_R.BRAM_FIFO36_ENBWRENU.BRAM_IMUX26_2 always
BRAM_R.BRAM_FIFO36_INJECTDBITERR.BRAM_IMUX31_2 always
BRAM_R.BRAM_FIFO36_INJECTSBITERR.BRAM_IMUX39_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEL.BRAM_IMUX19_2 always
BRAM_R.BRAM_FIFO36_REGCEAREGCEU.BRAM_IMUX11_2 always
BRAM_R.BRAM_FIFO36_REGCEBL.BRAM_IMUX35_2 always
BRAM_R.BRAM_FIFO36_REGCEBU.BRAM_IMUX27_2 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKL.BRAM_CLK0_4 always
BRAM_R.BRAM_FIFO36_REGCLKARDRCLKU.BRAM_CLK1_4 always
BRAM_R.BRAM_FIFO36_REGCLKBL.BRAM_CLK0_0 always
BRAM_R.BRAM_FIFO36_REGCLKBU.BRAM_CLK1_0 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMLRST.BRAM_CTRL0_3 always
BRAM_R.BRAM_FIFO36_RSTRAMARSTRAMU.BRAM_CTRL1_3 always
BRAM_R.BRAM_FIFO36_RSTRAMBL.BRAM_CTRL0_1 always
BRAM_R.BRAM_FIFO36_RSTRAMBU.BRAM_CTRL1_1 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGL.BRAM_CTRL0_4 always
BRAM_R.BRAM_FIFO36_RSTREGARSTREGU.BRAM_CTRL1_4 always
BRAM_R.BRAM_FIFO36_RSTREGBL.BRAM_CTRL0_0 always
BRAM_R.BRAM_FIFO36_RSTREGBU.BRAM_CTRL1_0 always
BRAM_R.BRAM_FIFO36_TSTBRAMRST.BRAM_IMUX0_0 always
BRAM_R.BRAM_FIFO36_TSTFLAGIN.BRAM_IMUX5_0 always
BRAM_R.BRAM_FIFO36_TSTOFF.BRAM_IMUX4_0 always
BRAM_R.BRAM_FIFO36_TSTRDCNTOFF.BRAM_IMUX2_0 always
BRAM_R.BRAM_FIFO36_TSTWRCNTOFF.BRAM_IMUX3_0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL0.BRAM_ADDRARDADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL1.BRAM_ADDRARDADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL2.BRAM_ADDRARDADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL3.BRAM_ADDRARDADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL4.BRAM_ADDRARDADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL5.BRAM_ADDRARDADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL6.BRAM_ADDRARDADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL7.BRAM_ADDRARDADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL8.BRAM_ADDRARDADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL9.BRAM_ADDRARDADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL10.BRAM_ADDRARDADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL11.BRAM_ADDRARDADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL12.BRAM_ADDRARDADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL13.BRAM_ADDRARDADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL14.BRAM_ADDRARDADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRL15.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU1.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU2.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU3.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU4.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU5.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU6.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU7.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU8.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU9.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU10.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU11.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU12.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU13.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRARDADDRU14.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL0.BRAM_ADDRBWRADDRL0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL1.BRAM_ADDRBWRADDRL1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL2.BRAM_ADDRBWRADDRL2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL3.BRAM_ADDRBWRADDRL3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL4.BRAM_ADDRBWRADDRL4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL5.BRAM_ADDRBWRADDRL5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL6.BRAM_ADDRBWRADDRL6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL7.BRAM_ADDRBWRADDRL7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL8.BRAM_ADDRBWRADDRL8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL9.BRAM_ADDRBWRADDRL9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL10.BRAM_ADDRBWRADDRL10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL11.BRAM_ADDRBWRADDRL11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL12.BRAM_ADDRBWRADDRL12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL13.BRAM_ADDRBWRADDRL13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL14.BRAM_ADDRBWRADDRL14 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRL15.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU1.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU2.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU3.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU4.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU5.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU6.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU7.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU8.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU9.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU10.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU11.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU12.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU13.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_FIFO36_ADDRBWRADDRU14.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_FIFO36_DIADIL0.BRAM_IMUX16_1 always
BRAM_R.BRAM_FIFO36_DIADIL1.BRAM_IMUX26_0 always
BRAM_R.BRAM_FIFO36_DIADIL2.BRAM_IMUX28_0 always
BRAM_R.BRAM_FIFO36_DIADIL3.BRAM_IMUX30_0 always
BRAM_R.BRAM_FIFO36_DIADIL4.BRAM_IMUX41_1 always
BRAM_R.BRAM_FIFO36_DIADIL5.BRAM_IMUX43_1 always
BRAM_R.BRAM_FIFO36_DIADIL6.BRAM_IMUX45_1 always
BRAM_R.BRAM_FIFO36_DIADIL7.BRAM_IMUX40_2 always
BRAM_R.BRAM_FIFO36_DIADIL8.BRAM_IMUX25_0 always
BRAM_R.BRAM_FIFO36_DIADIL9.BRAM_IMUX27_0 always
BRAM_R.BRAM_FIFO36_DIADIL10.BRAM_IMUX29_0 always
BRAM_R.BRAM_FIFO36_DIADIL11.BRAM_IMUX31_0 always
BRAM_R.BRAM_FIFO36_DIADIL12.BRAM_IMUX42_1 always
BRAM_R.BRAM_FIFO36_DIADIL13.BRAM_IMUX44_1 always
BRAM_R.BRAM_FIFO36_DIADIL14.BRAM_IMUX46_1 always
BRAM_R.BRAM_FIFO36_DIADIL15.BRAM_IMUX41_2 always
BRAM_R.BRAM_FIFO36_DIADIU0.BRAM_IMUX8_1 always
BRAM_R.BRAM_FIFO36_DIADIU1.BRAM_IMUX40_3 always
BRAM_R.BRAM_FIFO36_DIADIU2.BRAM_IMUX42_3 always
BRAM_R.BRAM_FIFO36_DIADIU3.BRAM_IMUX44_3 always
BRAM_R.BRAM_FIFO36_DIADIU4.BRAM_IMUX8_4 always
BRAM_R.BRAM_FIFO36_DIADIU5.BRAM_IMUX10_4 always
BRAM_R.BRAM_FIFO36_DIADIU6.BRAM_IMUX12_4 always
BRAM_R.BRAM_FIFO36_DIADIU7.BRAM_IMUX14_4 always
BRAM_R.BRAM_FIFO36_DIADIU8.BRAM_IMUX15_2 always
BRAM_R.BRAM_FIFO36_DIADIU9.BRAM_IMUX41_3 always
BRAM_R.BRAM_FIFO36_DIADIU10.BRAM_IMUX43_3 always
BRAM_R.BRAM_FIFO36_DIADIU11.BRAM_IMUX45_3 always
BRAM_R.BRAM_FIFO36_DIADIU12.BRAM_IMUX9_4 always
BRAM_R.BRAM_FIFO36_DIADIU13.BRAM_IMUX11_4 always
BRAM_R.BRAM_FIFO36_DIADIU14.BRAM_IMUX13_4 always
BRAM_R.BRAM_FIFO36_DIADIU15.BRAM_IMUX15_4 always
BRAM_R.BRAM_FIFO36_DIBDIL0.BRAM_IMUX32_1 always
BRAM_R.BRAM_FIFO36_DIBDIL1.BRAM_IMUX34_0 always
BRAM_R.BRAM_FIFO36_DIBDIL2.BRAM_IMUX36_0 always
BRAM_R.BRAM_FIFO36_DIBDIL3.BRAM_IMUX38_0 always
BRAM_R.BRAM_FIFO36_DIBDIL4.BRAM_IMUX2_1 always
BRAM_R.BRAM_FIFO36_DIBDIL5.BRAM_IMUX4_1 always
BRAM_R.BRAM_FIFO36_DIBDIL6.BRAM_IMUX6_1 always
BRAM_R.BRAM_FIFO36_DIBDIL7.BRAM_IMUX1_2 always
BRAM_R.BRAM_FIFO36_DIBDIL8.BRAM_IMUX33_0 always
BRAM_R.BRAM_FIFO36_DIBDIL9.BRAM_IMUX35_0 always
BRAM_R.BRAM_FIFO36_DIBDIL10.BRAM_IMUX37_0 always
BRAM_R.BRAM_FIFO36_DIBDIL11.BRAM_IMUX39_0 always
BRAM_R.BRAM_FIFO36_DIBDIL12.BRAM_IMUX3_1 always
BRAM_R.BRAM_FIFO36_DIBDIL13.BRAM_IMUX5_1 always
BRAM_R.BRAM_FIFO36_DIBDIL14.BRAM_IMUX7_1 always
BRAM_R.BRAM_FIFO36_DIBDIL15.BRAM_IMUX2_2 always
BRAM_R.BRAM_FIFO36_DIBDIU0.BRAM_IMUX24_1 always
BRAM_R.BRAM_FIFO36_DIBDIU1.BRAM_IMUX1_3 always
BRAM_R.BRAM_FIFO36_DIBDIU2.BRAM_IMUX3_3 always
BRAM_R.BRAM_FIFO36_DIBDIU3.BRAM_IMUX5_3 always
BRAM_R.BRAM_FIFO36_DIBDIU4.BRAM_IMUX16_4 always
BRAM_R.BRAM_FIFO36_DIBDIU5.BRAM_IMUX18_4 always
BRAM_R.BRAM_FIFO36_DIBDIU6.BRAM_IMUX20_4 always
BRAM_R.BRAM_FIFO36_DIBDIU7.BRAM_IMUX22_4 always
BRAM_R.BRAM_FIFO36_DIBDIU8.BRAM_IMUX23_2 always
BRAM_R.BRAM_FIFO36_DIBDIU9.BRAM_IMUX2_3 always
BRAM_R.BRAM_FIFO36_DIBDIU10.BRAM_IMUX4_3 always
BRAM_R.BRAM_FIFO36_DIBDIU11.BRAM_IMUX6_3 always
BRAM_R.BRAM_FIFO36_DIBDIU12.BRAM_IMUX17_4 always
BRAM_R.BRAM_FIFO36_DIBDIU13.BRAM_IMUX19_4 always
BRAM_R.BRAM_FIFO36_DIBDIU14.BRAM_IMUX21_4 always
BRAM_R.BRAM_FIFO36_DIBDIU15.BRAM_IMUX23_4 always
BRAM_R.BRAM_FIFO36_DIPADIPL0.BRAM_IMUX3_2 always
BRAM_R.BRAM_FIFO36_DIPADIPL1.BRAM_IMUX40_1 always
BRAM_R.BRAM_FIFO36_DIPADIPU0.BRAM_IMUX42_2 always
BRAM_R.BRAM_FIFO36_DIPADIPU1.BRAM_IMUX15_3 always
BRAM_R.BRAM_FIFO36_DIPBDIPL0.BRAM_IMUX4_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPL1.BRAM_IMUX1_1 always
BRAM_R.BRAM_FIFO36_DIPBDIPU0.BRAM_IMUX43_2 always
BRAM_R.BRAM_FIFO36_DIPBDIPU1.BRAM_IMUX23_3 always
BRAM_R.BRAM_FIFO36_TSTCNT0.BRAM_IMUX10_0 always
BRAM_R.BRAM_FIFO36_TSTCNT1.BRAM_IMUX11_0 always
BRAM_R.BRAM_FIFO36_TSTCNT2.BRAM_IMUX12_0 always
BRAM_R.BRAM_FIFO36_TSTCNT3.BRAM_IMUX13_0 always
BRAM_R.BRAM_FIFO36_TSTCNT4.BRAM_IMUX14_0 always
BRAM_R.BRAM_FIFO36_TSTCNT5.BRAM_IMUX15_0 always
BRAM_R.BRAM_FIFO36_TSTCNT6.BRAM_IMUX24_4 always
BRAM_R.BRAM_FIFO36_TSTCNT7.BRAM_IMUX25_4 always
BRAM_R.BRAM_FIFO36_TSTCNT8.BRAM_IMUX26_4 always
BRAM_R.BRAM_FIFO36_TSTCNT9.BRAM_IMUX27_4 always
BRAM_R.BRAM_FIFO36_TSTCNT10.BRAM_IMUX28_4 always
BRAM_R.BRAM_FIFO36_TSTCNT11.BRAM_IMUX29_4 always
BRAM_R.BRAM_FIFO36_TSTCNT12.BRAM_IMUX30_4 always
BRAM_R.BRAM_FIFO36_TSTIN0.BRAM_IMUX5_4 always
BRAM_R.BRAM_FIFO36_TSTIN1.BRAM_IMUX16_0 always
BRAM_R.BRAM_FIFO36_TSTIN2.BRAM_IMUX4_4 always
BRAM_R.BRAM_FIFO36_TSTIN3.BRAM_IMUX8_0 always
BRAM_R.BRAM_FIFO36_TSTIN4.BRAM_IMUX41_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS0.BRAM_IMUX18_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS1.BRAM_IMUX19_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS2.BRAM_IMUX20_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS3.BRAM_IMUX21_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS4.BRAM_IMUX22_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS5.BRAM_IMUX23_0 always
BRAM_R.BRAM_FIFO36_TSTRDOS6.BRAM_IMUX32_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS7.BRAM_IMUX33_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS8.BRAM_IMUX34_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS9.BRAM_IMUX35_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS10.BRAM_IMUX36_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS11.BRAM_IMUX37_4 always
BRAM_R.BRAM_FIFO36_TSTRDOS12.BRAM_IMUX38_4 always
BRAM_R.BRAM_FIFO36_TSTWROS0.BRAM_IMUX42_0 always
BRAM_R.BRAM_FIFO36_TSTWROS1.BRAM_IMUX43_0 always
BRAM_R.BRAM_FIFO36_TSTWROS2.BRAM_IMUX44_0 always
BRAM_R.BRAM_FIFO36_TSTWROS3.BRAM_IMUX45_0 always
BRAM_R.BRAM_FIFO36_TSTWROS4.BRAM_IMUX46_0 always
BRAM_R.BRAM_FIFO36_TSTWROS5.BRAM_IMUX47_0 always
BRAM_R.BRAM_FIFO36_TSTWROS6.BRAM_IMUX40_4 always
BRAM_R.BRAM_FIFO36_TSTWROS7.BRAM_IMUX41_4 always
BRAM_R.BRAM_FIFO36_TSTWROS8.BRAM_IMUX42_4 always
BRAM_R.BRAM_FIFO36_TSTWROS9.BRAM_IMUX43_4 always
BRAM_R.BRAM_FIFO36_TSTWROS10.BRAM_IMUX44_4 always
BRAM_R.BRAM_FIFO36_TSTWROS11.BRAM_IMUX45_4 always
BRAM_R.BRAM_FIFO36_TSTWROS12.BRAM_IMUX46_4 always
BRAM_R.BRAM_FIFO36_WEAL0.BRAM_IMUX16_2 always
BRAM_R.BRAM_FIFO36_WEAL1.BRAM_IMUX32_2 always
BRAM_R.BRAM_FIFO36_WEAL2.BRAM_IMUX17_2 always
BRAM_R.BRAM_FIFO36_WEAL3.BRAM_IMUX33_2 always
BRAM_R.BRAM_FIFO36_WEAU0.BRAM_IMUX8_2 always
BRAM_R.BRAM_FIFO36_WEAU1.BRAM_IMUX24_2 always
BRAM_R.BRAM_FIFO36_WEAU2.BRAM_IMUX9_2 always
BRAM_R.BRAM_FIFO36_WEAU3.BRAM_IMUX25_2 always
BRAM_R.BRAM_FIFO36_WEBWEL0.BRAM_IMUX5_2 always
BRAM_R.BRAM_FIFO36_WEBWEL1.BRAM_IMUX21_2 always
BRAM_R.BRAM_FIFO36_WEBWEL2.BRAM_IMUX37_2 always
BRAM_R.BRAM_FIFO36_WEBWEL3.BRAM_BYP3_2 always
BRAM_R.BRAM_FIFO36_WEBWEL4.BRAM_IMUX6_2 always
BRAM_R.BRAM_FIFO36_WEBWEL5.BRAM_IMUX22_2 always
BRAM_R.BRAM_FIFO36_WEBWEL6.BRAM_IMUX38_2 always
BRAM_R.BRAM_FIFO36_WEBWEL7.BRAM_BYP6_2 always
BRAM_R.BRAM_FIFO36_WEBWEU0.BRAM_FAN5_2 always
BRAM_R.BRAM_FIFO36_WEBWEU1.BRAM_IMUX13_2 always
BRAM_R.BRAM_FIFO36_WEBWEU2.BRAM_IMUX29_2 always
BRAM_R.BRAM_FIFO36_WEBWEU3.BRAM_IMUX45_2 always
BRAM_R.BRAM_FIFO36_WEBWEU4.BRAM_FAN1_2 always
BRAM_R.BRAM_FIFO36_WEBWEU5.BRAM_IMUX14_2 always
BRAM_R.BRAM_FIFO36_WEBWEU6.BRAM_IMUX30_2 always
BRAM_R.BRAM_FIFO36_WEBWEU7.BRAM_IMUX46_2 always
BRAM_R.BRAM_RAMB18_CLKARDCLK.BRAM_CLK1_3 always
BRAM_R.BRAM_RAMB18_CLKBWRCLK.BRAM_CLK1_1 always
BRAM_R.BRAM_RAMB18_ENARDEN.BRAM_IMUX10_2 always
BRAM_R.BRAM_RAMB18_ENBWREN.BRAM_IMUX26_2 always
BRAM_R.BRAM_RAMB18_REGCEAREGCE.BRAM_IMUX11_2 always
BRAM_R.BRAM_RAMB18_REGCEB.BRAM_IMUX27_2 always
BRAM_R.BRAM_RAMB18_REGCLKARDRCLK.BRAM_CLK1_4 always
BRAM_R.BRAM_RAMB18_REGCLKB.BRAM_CLK1_0 always
BRAM_R.BRAM_RAMB18_RSTRAMARSTRAM.BRAM_CTRL1_3 always
BRAM_R.BRAM_RAMB18_RSTRAMB.BRAM_CTRL1_1 always
BRAM_R.BRAM_RAMB18_RSTREGARSTREG.BRAM_CTRL1_4 always
BRAM_R.BRAM_RAMB18_RSTREGB.BRAM_CTRL1_0 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR0.BRAM_ADDRARDADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR1.BRAM_ADDRARDADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR2.BRAM_ADDRARDADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR3.BRAM_ADDRARDADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR4.BRAM_ADDRARDADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR5.BRAM_ADDRARDADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR6.BRAM_ADDRARDADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR7.BRAM_ADDRARDADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR8.BRAM_ADDRARDADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR9.BRAM_ADDRARDADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR10.BRAM_ADDRARDADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR11.BRAM_ADDRARDADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR12.BRAM_ADDRARDADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRARDADDR13.BRAM_ADDRARDADDRU14 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH0.BRAM_ADDRARDADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRATIEHIGH1.BRAM_IMUX_R_ADDRARDADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH0.BRAM_ADDRBWRADDRU0 always
BRAM_R.BRAM_RAMB18_ADDRBTIEHIGH1.BRAM_IMUX_R_ADDRBWRADDRL15 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR0.BRAM_ADDRBWRADDRU1 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR1.BRAM_ADDRBWRADDRU2 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR2.BRAM_ADDRBWRADDRU3 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR3.BRAM_ADDRBWRADDRU4 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR4.BRAM_ADDRBWRADDRU5 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR5.BRAM_ADDRBWRADDRU6 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR6.BRAM_ADDRBWRADDRU7 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR7.BRAM_ADDRBWRADDRU8 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR8.BRAM_ADDRBWRADDRU9 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR9.BRAM_ADDRBWRADDRU10 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR10.BRAM_ADDRBWRADDRU11 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR11.BRAM_ADDRBWRADDRU12 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR12.BRAM_ADDRBWRADDRU13 always
BRAM_R.BRAM_RAMB18_ADDRBWRADDR13.BRAM_ADDRBWRADDRU14 always
BRAM_R.BRAM_RAMB18_DIADI0.BRAM_IMUX8_1 always
BRAM_R.BRAM_RAMB18_DIADI1.BRAM_IMUX40_3 always
BRAM_R.BRAM_RAMB18_DIADI2.BRAM_IMUX42_3 always
BRAM_R.BRAM_RAMB18_DIADI3.BRAM_IMUX44_3 always
BRAM_R.BRAM_RAMB18_DIADI4.BRAM_IMUX8_4 always
BRAM_R.BRAM_RAMB18_DIADI5.BRAM_IMUX10_4 always
BRAM_R.BRAM_RAMB18_DIADI6.BRAM_IMUX12_4 always
BRAM_R.BRAM_RAMB18_DIADI7.BRAM_IMUX14_4 always
BRAM_R.BRAM_RAMB18_DIADI8.BRAM_IMUX15_2 always
BRAM_R.BRAM_RAMB18_DIADI9.BRAM_IMUX41_3 always
BRAM_R.BRAM_RAMB18_DIADI10.BRAM_IMUX43_3 always
BRAM_R.BRAM_RAMB18_DIADI11.BRAM_IMUX45_3 always
BRAM_R.BRAM_RAMB18_DIADI12.BRAM_IMUX9_4 always
BRAM_R.BRAM_RAMB18_DIADI13.BRAM_IMUX11_4 always
BRAM_R.BRAM_RAMB18_DIADI14.BRAM_IMUX13_4 always
BRAM_R.BRAM_RAMB18_DIADI15.BRAM_IMUX15_4 always
BRAM_R.BRAM_RAMB18_DIBDI0.BRAM_IMUX24_1 always
BRAM_R.BRAM_RAMB18_DIBDI1.BRAM_IMUX1_3 always
BRAM_R.BRAM_RAMB18_DIBDI2.BRAM_IMUX3_3 always
BRAM_R.BRAM_RAMB18_DIBDI3.BRAM_IMUX5_3 always
BRAM_R.BRAM_RAMB18_DIBDI4.BRAM_IMUX16_4 always
BRAM_R.BRAM_RAMB18_DIBDI5.BRAM_IMUX18_4 always
BRAM_R.BRAM_RAMB18_DIBDI6.BRAM_IMUX20_4 always
BRAM_R.BRAM_RAMB18_DIBDI7.BRAM_IMUX22_4 always
BRAM_R.BRAM_RAMB18_DIBDI8.BRAM_IMUX23_2 always
BRAM_R.BRAM_RAMB18_DIBDI9.BRAM_IMUX2_3 always
BRAM_R.BRAM_RAMB18_DIBDI10.BRAM_IMUX4_3 always
BRAM_R.BRAM_RAMB18_DIBDI11.BRAM_IMUX6_3 always
BRAM_R.BRAM_RAMB18_DIBDI12.BRAM_IMUX17_4 always
BRAM_R.BRAM_RAMB18_DIBDI13.BRAM_IMUX19_4 always
BRAM_R.BRAM_RAMB18_DIBDI14.BRAM_IMUX21_4 always
BRAM_R.BRAM_RAMB18_DIBDI15.BRAM_IMUX23_4 always
BRAM_R.BRAM_RAMB18_DIPADIP0.BRAM_IMUX42_2 always
BRAM_R.BRAM_RAMB18_DIPADIP1.BRAM_IMUX15_3 always
BRAM_R.BRAM_RAMB18_DIPBDIP0.BRAM_IMUX43_2 always
BRAM_R.BRAM_RAMB18_DIPBDIP1.BRAM_IMUX23_3 always
BRAM_R.BRAM_RAMB18_WEA0.BRAM_IMUX8_2 always
BRAM_R.BRAM_RAMB18_WEA1.BRAM_IMUX24_2 always
BRAM_R.BRAM_RAMB18_WEA2.BRAM_IMUX9_2 always
BRAM_R.BRAM_RAMB18_WEA3.BRAM_IMUX25_2 always
BRAM_R.BRAM_RAMB18_WEBWE0.BRAM_FAN5_2 always
BRAM_R.BRAM_RAMB18_WEBWE1.BRAM_IMUX13_2 always
BRAM_R.BRAM_RAMB18_WEBWE2.BRAM_IMUX29_2 always
BRAM_R.BRAM_RAMB18_WEBWE3.BRAM_IMUX45_2 always
BRAM_R.BRAM_RAMB18_WEBWE4.BRAM_FAN1_2 always
BRAM_R.BRAM_RAMB18_WEBWE5.BRAM_IMUX14_2 always
BRAM_R.BRAM_RAMB18_WEBWE6.BRAM_IMUX30_2 always
BRAM_R.BRAM_RAMB18_WEBWE7.BRAM_IMUX46_2 always

146
zynq7/ppips_clbll_l.db Normal file
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@ -0,0 +1,146 @@
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

146
zynq7/ppips_clbll_r.db Normal file
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@ -0,0 +1,146 @@
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always

151
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@ -0,0 +1,151 @@
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always

151
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CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always

0
zynq7/ppips_dsp_l.db Normal file
View File

0
zynq7/ppips_dsp_r.db Normal file
View File

0
zynq7/ppips_hclk_l.db Normal file
View File

0
zynq7/ppips_hclk_r.db Normal file
View File

108
zynq7/ppips_int_l.db Normal file
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@ -0,0 +1,108 @@
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
INT_L.BYP_BOUNCE3.BYP_ALT3 always
INT_L.BYP_BOUNCE4.BYP_ALT4 always
INT_L.BYP_BOUNCE5.BYP_ALT5 always
INT_L.BYP_BOUNCE6.BYP_ALT6 always
INT_L.BYP_BOUNCE7.BYP_ALT7 always
INT_L.BYP_L0.BYP_ALT0 always
INT_L.BYP_L1.BYP_ALT1 always
INT_L.BYP_L2.BYP_ALT2 always
INT_L.BYP_L3.BYP_ALT3 always
INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
INT_L.FAN_BOUNCE3.FAN_ALT3 always
INT_L.FAN_BOUNCE4.FAN_ALT4 always
INT_L.FAN_BOUNCE5.FAN_ALT5 always
INT_L.FAN_BOUNCE6.FAN_ALT6 always
INT_L.FAN_BOUNCE7.FAN_ALT7 always
INT_L.FAN_L0.FAN_ALT0 always
INT_L.FAN_L1.FAN_ALT1 always
INT_L.FAN_L2.FAN_ALT2 always
INT_L.FAN_L3.FAN_ALT3 always
INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default

108
zynq7/ppips_int_r.db Normal file
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@ -0,0 +1,108 @@
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
INT_R.BYP_BOUNCE3.BYP_ALT3 always
INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
INT_R.FAN_BOUNCE3.FAN_ALT3 always
INT_R.FAN_BOUNCE4.FAN_ALT4 always
INT_R.FAN_BOUNCE5.FAN_ALT5 always
INT_R.FAN_BOUNCE6.FAN_ALT6 always
INT_R.FAN_BOUNCE7.FAN_ALT7 always
INT_R.GCLK_B0_EAST.GCLK_B0 always
INT_R.GCLK_B0_WEST.GCLK_B0 always
INT_R.GCLK_B1_EAST.GCLK_B1 always
INT_R.GCLK_B1_WEST.GCLK_B1 always
INT_R.GCLK_B2_EAST.GCLK_B2 always
INT_R.GCLK_B2_WEST.GCLK_B2 always
INT_R.GCLK_B3_EAST.GCLK_B3 always
INT_R.GCLK_B3_WEST.GCLK_B3 always
INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default

36864
zynq7/segbits_bram_l.block_ram.db Normal file
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File diff suppressed because it is too large Load Diff

446
zynq7/segbits_bram_l.db Normal file
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@ -0,0 +1,446 @@
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 26_64 !26_65 26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 26_64 26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2 !26_64 !26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 26_192 !26_193 26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 26_192 26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3 !26_192 !26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 26_96 !26_97 26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 26_96 26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4 !26_96 !26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 26_224 !26_225 26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 26_224 26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5 !26_224 !26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 26_160 !26_161 26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 26_160 26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6 !26_160 !26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 26_176 !26_177 26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 26_176 26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7 !26_176 !26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 26_80 !26_81 26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 26_80 26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 26_69 !26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 !26_69 26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 !26_69 !26_70 !26_71
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 26_197 !26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 !26_197 26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 !26_197 !26_198 !26_199
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 26_101 !26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 !26_101 26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 !26_101 !26_102 !26_103
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 26_229 !26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 !26_229 26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 !26_229 !26_230 !26_231
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 26_165 !26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 !26_165 26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6 !26_165 !26_166 !26_167
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 26_181 !26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 !26_181 26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 !26_181 !26_182 !26_183
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 26_85 !26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 !26_85 26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_72 !26_73 26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 26_72 26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_IMUX_ADDRBWRADDRL2 !26_72 !26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_200 !26_201 26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 26_200 26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_IMUX_ADDRBWRADDRL3 !26_200 !26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_104 !26_105 26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 26_104 26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_IMUX_ADDRBWRADDRL4 !26_104 !26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_232 !26_233 26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 26_232 26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_IMUX_ADDRBWRADDRL5 !26_232 !26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_168 !26_169 26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 26_168 26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_IMUX_ADDRBWRADDRL6 !26_168 !26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_184 !26_185 26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 26_184 26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 !26_184 !26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_88 !26_89 26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 26_88 26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_77 !26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 !26_77 26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 !26_77 !26_78 !26_79
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_205 !26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 !26_205 26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 !26_205 !26_206 !26_207
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_109 !26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 !26_109 26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 !26_109 !26_110 !26_111
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_237 !26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 !26_237 26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 !26_237 !26_238 !26_239
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_173 !26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 !26_173 26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 !26_173 !26_174 !26_175
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_189 !26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 !26_189 26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 !26_189 !26_190 !26_191
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_93 !26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 !26_93 26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.EN_SYN 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_L.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_L.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_L.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_L.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 24_240 27_150
BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_L.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_L.RAMB18_Y0.ZINV_REGCLKARDRCLK 27_104
BRAM_L.RAMB18_Y0.ZINV_REGCLKB 27_108
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_L.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_L.RAMB18_Y1.ZINV_REGCLKARDRCLK 27_216
BRAM_L.RAMB18_Y1.ZINV_REGCLKB 27_212
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187

36864
zynq7/segbits_bram_r.block_ram.db Normal file
View File

File diff suppressed because it is too large Load Diff

446
zynq7/segbits_bram_r.db Normal file
View File

@ -0,0 +1,446 @@
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 26_32 !26_33 26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 26_32 26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 !26_32 !26_33 !26_35
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 26_48 !26_49 26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 26_48 26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 !26_48 !26_49 !26_51
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 26_64 !26_65 26_67
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 26_64 26_65 !26_67
BRAM_R.BRAM_ADDRARDADDRL2.BRAM_R_IMUX_ADDRARDADDRL2 !26_64 !26_65 !26_67
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 26_192 !26_193 26_195
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 26_192 26_193 !26_195
BRAM_R.BRAM_ADDRARDADDRL3.BRAM_R_IMUX_ADDRARDADDRL3 !26_192 !26_193 !26_195
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 26_96 !26_97 26_99
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 26_96 26_97 !26_99
BRAM_R.BRAM_ADDRARDADDRL4.BRAM_R_IMUX_ADDRARDADDRL4 !26_96 !26_97 !26_99
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 26_224 !26_225 26_227
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 26_224 26_225 !26_227
BRAM_R.BRAM_ADDRARDADDRL5.BRAM_R_IMUX_ADDRARDADDRL5 !26_224 !26_225 !26_227
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 26_160 !26_161 26_163
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 26_160 26_161 !26_163
BRAM_R.BRAM_ADDRARDADDRL6.BRAM_R_IMUX_ADDRARDADDRL6 !26_160 !26_161 !26_163
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 26_176 !26_177 26_179
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 26_176 26_177 !26_179
BRAM_R.BRAM_ADDRARDADDRL7.BRAM_R_IMUX_ADDRARDADDRL7 !26_176 !26_177 !26_179
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 26_80 !26_81 26_83
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 26_80 26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 !26_80 !26_81 !26_83
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 26_208 !26_209 26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 26_208 26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 !26_208 !26_209 !26_211
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 26_144 !26_145 26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 26_144 26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 !26_144 !26_145 !26_147
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 26_112 !26_113 26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 26_112 26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL11.BRAM_R_IMUX_ADDRARDADDRL11 !26_112 !26_113 !26_115
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 26_240 !26_241 26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 26_240 26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL12.BRAM_R_IMUX_ADDRARDADDRL12 !26_240 !26_241 !26_243
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 26_128 !26_129 26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 26_128 26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL13.BRAM_R_IMUX_ADDRARDADDRL13 !26_128 !26_129 !26_131
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 26_256 !26_257 26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 26_256 26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 !26_256 !26_257 !26_259
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 26_37 !26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 !26_37 26_38 26_39
BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 !26_37 !26_38 !26_39
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 26_53 !26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 !26_53 26_54 26_55
BRAM_R.BRAM_ADDRARDADDRU1.BRAM_R_IMUX_ADDRARDADDRU1 !26_53 !26_54 !26_55
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 26_69 !26_70 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 !26_69 26_70 26_71
BRAM_R.BRAM_ADDRARDADDRU2.BRAM_R_IMUX_ADDRARDADDRU2 !26_69 !26_70 !26_71
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 26_197 !26_198 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 !26_197 26_198 26_199
BRAM_R.BRAM_ADDRARDADDRU3.BRAM_R_IMUX_ADDRARDADDRU3 !26_197 !26_198 !26_199
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 26_101 !26_102 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 !26_101 26_102 26_103
BRAM_R.BRAM_ADDRARDADDRU4.BRAM_R_IMUX_ADDRARDADDRU4 !26_101 !26_102 !26_103
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 26_229 !26_230 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 !26_229 26_230 26_231
BRAM_R.BRAM_ADDRARDADDRU5.BRAM_R_IMUX_ADDRARDADDRU5 !26_229 !26_230 !26_231
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 26_165 !26_166 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 !26_165 26_166 26_167
BRAM_R.BRAM_ADDRARDADDRU6.BRAM_R_IMUX_ADDRARDADDRU6 !26_165 !26_166 !26_167
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 26_181 !26_182 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 !26_181 26_182 26_183
BRAM_R.BRAM_ADDRARDADDRU7.BRAM_R_IMUX_ADDRARDADDRU7 !26_181 !26_182 !26_183
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 26_85 !26_86 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 !26_85 26_86 26_87
BRAM_R.BRAM_ADDRARDADDRU8.BRAM_R_IMUX_ADDRARDADDRU8 !26_85 !26_86 !26_87
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 26_213 !26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 !26_213 26_214 26_215
BRAM_R.BRAM_ADDRARDADDRU9.BRAM_R_IMUX_ADDRARDADDRU9 !26_213 !26_214 !26_215
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 26_149 !26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 !26_149 26_150 26_151
BRAM_R.BRAM_ADDRARDADDRU10.BRAM_R_IMUX_ADDRARDADDRU10 !26_149 !26_150 !26_151
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 26_117 !26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 !26_117 26_118 26_119
BRAM_R.BRAM_ADDRARDADDRU11.BRAM_R_IMUX_ADDRARDADDRU11 !26_117 !26_118 !26_119
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 26_245 !26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 !26_245 26_246 26_247
BRAM_R.BRAM_ADDRARDADDRU12.BRAM_R_IMUX_ADDRARDADDRU12 !26_245 !26_246 !26_247
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 26_133 !26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 !26_133 26_134 26_135
BRAM_R.BRAM_ADDRARDADDRU13.BRAM_R_IMUX_ADDRARDADDRU13 !26_133 !26_134 !26_135
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 26_261 !26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 !26_261 26_262 26_263
BRAM_R.BRAM_ADDRARDADDRU14.BRAM_R_IMUX_ADDRARDADDRU14 !26_261 !26_262 !26_263
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_40 !26_41 26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 26_40 26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL0.BRAM_R_IMUX_ADDRBWRADDRL0 !26_40 !26_41 !26_43
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_56 !26_57 26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 26_56 26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL1.BRAM_R_IMUX_ADDRBWRADDRL1 !26_56 !26_57 !26_59
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_72 !26_73 26_75
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 26_72 26_73 !26_75
BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_R_IMUX_ADDRBWRADDRL2 !26_72 !26_73 !26_75
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_200 !26_201 26_203
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 26_200 26_201 !26_203
BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_R_IMUX_ADDRBWRADDRL3 !26_200 !26_201 !26_203
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_104 !26_105 26_107
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 26_104 26_105 !26_107
BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_R_IMUX_ADDRBWRADDRL4 !26_104 !26_105 !26_107
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_232 !26_233 26_235
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 26_232 26_233 !26_235
BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_R_IMUX_ADDRBWRADDRL5 !26_232 !26_233 !26_235
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_168 !26_169 26_171
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 26_168 26_169 !26_171
BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_R_IMUX_ADDRBWRADDRL6 !26_168 !26_169 !26_171
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_184 !26_185 26_187
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 26_184 26_185 !26_187
BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_R_IMUX_ADDRBWRADDRL7 !26_184 !26_185 !26_187
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_88 !26_89 26_91
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 26_88 26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 !26_88 !26_89 !26_91
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_216 !26_217 26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 26_216 26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 !26_216 !26_217 !26_219
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_152 !26_153 26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 26_152 26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL10.BRAM_R_IMUX_ADDRBWRADDRL10 !26_152 !26_153 !26_155
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_120 !26_121 26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 26_120 26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL11.BRAM_R_IMUX_ADDRBWRADDRL11 !26_120 !26_121 !26_123
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_248 !26_249 26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 26_248 26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL12.BRAM_R_IMUX_ADDRBWRADDRL12 !26_248 !26_249 !26_251
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_136 !26_137 26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 26_136 26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 !26_136 !26_137 !26_139
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_264 !26_265 26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 26_264 26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 !26_264 !26_265 !26_267
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 26_45 !26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 !26_45 26_46 26_47
BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 !26_45 !26_46 !26_47
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 26_61 !26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 !26_61 26_62 26_63
BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 !26_61 !26_62 !26_63
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 26_77 !26_78 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 !26_77 26_78 26_79
BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_R_IMUX_ADDRBWRADDRU2 !26_77 !26_78 !26_79
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 26_205 !26_206 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 !26_205 26_206 26_207
BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_R_IMUX_ADDRBWRADDRU3 !26_205 !26_206 !26_207
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 26_109 !26_110 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 !26_109 26_110 26_111
BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_R_IMUX_ADDRBWRADDRU4 !26_109 !26_110 !26_111
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 26_237 !26_238 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 !26_237 26_238 26_239
BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_R_IMUX_ADDRBWRADDRU5 !26_237 !26_238 !26_239
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 26_173 !26_174 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 !26_173 26_174 26_175
BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_R_IMUX_ADDRBWRADDRU6 !26_173 !26_174 !26_175
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 26_189 !26_190 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 !26_189 26_190 26_191
BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_R_IMUX_ADDRBWRADDRU7 !26_189 !26_190 !26_191
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 26_93 !26_94 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 !26_93 26_94 26_95
BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 !26_93 !26_94 !26_95
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 26_221 !26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 !26_221 26_222 26_223
BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 !26_221 !26_222 !26_223
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 26_157 !26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 !26_157 26_158 26_159
BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 !26_157 !26_158 !26_159
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 26_125 !26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 !26_125 26_126 26_127
BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 !26_125 !26_126 !26_127
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 26_253 !26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 !26_253 26_254 26_255
BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 !26_253 !26_254 !26_255
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 26_141 !26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 !26_141 26_142 26_143
BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.EN_SYN 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
BRAM_R.ZALMOST_EMPTY_OFFSET[1] 27_291
BRAM_R.ZALMOST_EMPTY_OFFSET[2] 27_292
BRAM_R.ZALMOST_EMPTY_OFFSET[3] 27_293
BRAM_R.ZALMOST_EMPTY_OFFSET[4] 27_296
BRAM_R.ZALMOST_EMPTY_OFFSET[5] 27_299
BRAM_R.ZALMOST_EMPTY_OFFSET[6] 27_300
BRAM_R.ZALMOST_EMPTY_OFFSET[7] 27_301
BRAM_R.ZALMOST_EMPTY_OFFSET[8] 27_304
BRAM_R.ZALMOST_EMPTY_OFFSET[9] 27_307
BRAM_R.ZALMOST_EMPTY_OFFSET[10] 27_308
BRAM_R.ZALMOST_EMPTY_OFFSET[11] 27_309
BRAM_R.ZALMOST_EMPTY_OFFSET[12] 27_312
BRAM_R.ZALMOST_FULL_OFFSET[0] 27_32
BRAM_R.ZALMOST_FULL_OFFSET[1] 27_29
BRAM_R.ZALMOST_FULL_OFFSET[2] 27_28
BRAM_R.ZALMOST_FULL_OFFSET[3] 27_27
BRAM_R.ZALMOST_FULL_OFFSET[4] 27_24
BRAM_R.ZALMOST_FULL_OFFSET[5] 27_21
BRAM_R.ZALMOST_FULL_OFFSET[6] 27_20
BRAM_R.ZALMOST_FULL_OFFSET[7] 27_19
BRAM_R.ZALMOST_FULL_OFFSET[8] 27_16
BRAM_R.ZALMOST_FULL_OFFSET[9] 27_13
BRAM_R.ZALMOST_FULL_OFFSET[10] 27_12
BRAM_R.ZALMOST_FULL_OFFSET[11] 27_11
BRAM_R.ZALMOST_FULL_OFFSET[12] 27_08
BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 24_240 27_150
BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 27_35 !27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 !27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 27_35 27_36 !27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 !27_35 !27_36 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 !27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 27_43 !27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 !27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 27_43 27_44 !27_45
BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 !27_43 !27_44 27_45
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 !27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 27_51 !27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 !27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 27_51 27_52 !27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 !27_51 !27_52 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 !27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_R.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_R.RAMB18_Y0.ZINV_REGCLKARDRCLK 27_104
BRAM_R.RAMB18_Y0.ZINV_REGCLKB 27_108
BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 !27_283 !27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 !27_283 27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 !27_283 27_284 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 27_283 !27_284 !27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 !27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 !27_275 !27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 !27_275 27_276 !27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 !27_275 27_276 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 27_275 !27_276 !27_277
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 !27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 !27_267 !27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 !27_267 27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 !27_267 27_268 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 27_267 !27_268 !27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 !27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_R.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_R.RAMB18_Y1.ZINV_REGCLKARDRCLK 27_216
BRAM_R.RAMB18_Y1.ZINV_REGCLKB 27_212
BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187

678
zynq7/segbits_clbll_l.db Normal file
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@ -0,0 +1,678 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
CLBLL_L.SLICEL_X0.ALUT.INIT[03] 33_14
CLBLL_L.SLICEL_X0.ALUT.INIT[04] 32_13
CLBLL_L.SLICEL_X0.ALUT.INIT[05] 33_13
CLBLL_L.SLICEL_X0.ALUT.INIT[06] 32_12
CLBLL_L.SLICEL_X0.ALUT.INIT[07] 33_12
CLBLL_L.SLICEL_X0.ALUT.INIT[08] 35_15
CLBLL_L.SLICEL_X0.ALUT.INIT[09] 34_15
CLBLL_L.SLICEL_X0.ALUT.INIT[10] 35_14
CLBLL_L.SLICEL_X0.ALUT.INIT[11] 34_14
CLBLL_L.SLICEL_X0.ALUT.INIT[12] 35_13
CLBLL_L.SLICEL_X0.ALUT.INIT[13] 34_13
CLBLL_L.SLICEL_X0.ALUT.INIT[14] 35_12
CLBLL_L.SLICEL_X0.ALUT.INIT[15] 34_12
CLBLL_L.SLICEL_X0.ALUT.INIT[16] 32_11
CLBLL_L.SLICEL_X0.ALUT.INIT[17] 33_11
CLBLL_L.SLICEL_X0.ALUT.INIT[18] 32_10
CLBLL_L.SLICEL_X0.ALUT.INIT[19] 33_10
CLBLL_L.SLICEL_X0.ALUT.INIT[20] 32_09
CLBLL_L.SLICEL_X0.ALUT.INIT[21] 33_09
CLBLL_L.SLICEL_X0.ALUT.INIT[22] 32_08
CLBLL_L.SLICEL_X0.ALUT.INIT[23] 33_08
CLBLL_L.SLICEL_X0.ALUT.INIT[24] 35_11
CLBLL_L.SLICEL_X0.ALUT.INIT[25] 34_11
CLBLL_L.SLICEL_X0.ALUT.INIT[26] 35_10
CLBLL_L.SLICEL_X0.ALUT.INIT[27] 34_10
CLBLL_L.SLICEL_X0.ALUT.INIT[28] 35_09
CLBLL_L.SLICEL_X0.ALUT.INIT[29] 34_09
CLBLL_L.SLICEL_X0.ALUT.INIT[30] 35_08
CLBLL_L.SLICEL_X0.ALUT.INIT[31] 34_08
CLBLL_L.SLICEL_X0.ALUT.INIT[32] 32_07
CLBLL_L.SLICEL_X0.ALUT.INIT[33] 33_07
CLBLL_L.SLICEL_X0.ALUT.INIT[34] 32_06
CLBLL_L.SLICEL_X0.ALUT.INIT[35] 33_06
CLBLL_L.SLICEL_X0.ALUT.INIT[36] 32_05
CLBLL_L.SLICEL_X0.ALUT.INIT[37] 33_05
CLBLL_L.SLICEL_X0.ALUT.INIT[38] 32_04
CLBLL_L.SLICEL_X0.ALUT.INIT[39] 33_04
CLBLL_L.SLICEL_X0.ALUT.INIT[40] 35_07
CLBLL_L.SLICEL_X0.ALUT.INIT[41] 34_07
CLBLL_L.SLICEL_X0.ALUT.INIT[42] 35_06
CLBLL_L.SLICEL_X0.ALUT.INIT[43] 34_06
CLBLL_L.SLICEL_X0.ALUT.INIT[44] 35_05
CLBLL_L.SLICEL_X0.ALUT.INIT[45] 34_05
CLBLL_L.SLICEL_X0.ALUT.INIT[46] 35_04
CLBLL_L.SLICEL_X0.ALUT.INIT[47] 34_04
CLBLL_L.SLICEL_X0.ALUT.INIT[48] 32_03
CLBLL_L.SLICEL_X0.ALUT.INIT[49] 33_03
CLBLL_L.SLICEL_X0.ALUT.INIT[50] 32_02
CLBLL_L.SLICEL_X0.ALUT.INIT[51] 33_02
CLBLL_L.SLICEL_X0.ALUT.INIT[52] 32_01
CLBLL_L.SLICEL_X0.ALUT.INIT[53] 33_01
CLBLL_L.SLICEL_X0.ALUT.INIT[54] 32_00
CLBLL_L.SLICEL_X0.ALUT.INIT[55] 33_00
CLBLL_L.SLICEL_X0.ALUT.INIT[56] 35_03
CLBLL_L.SLICEL_X0.ALUT.INIT[57] 34_03
CLBLL_L.SLICEL_X0.ALUT.INIT[58] 35_02
CLBLL_L.SLICEL_X0.ALUT.INIT[59] 34_02
CLBLL_L.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
CLBLL_L.SLICEL_X0.BLUT.INIT[03] 33_30
CLBLL_L.SLICEL_X0.BLUT.INIT[04] 32_29
CLBLL_L.SLICEL_X0.BLUT.INIT[05] 33_29
CLBLL_L.SLICEL_X0.BLUT.INIT[06] 32_28
CLBLL_L.SLICEL_X0.BLUT.INIT[07] 33_28
CLBLL_L.SLICEL_X0.BLUT.INIT[08] 35_31
CLBLL_L.SLICEL_X0.BLUT.INIT[09] 34_31
CLBLL_L.SLICEL_X0.BLUT.INIT[10] 35_30
CLBLL_L.SLICEL_X0.BLUT.INIT[11] 34_30
CLBLL_L.SLICEL_X0.BLUT.INIT[12] 35_29
CLBLL_L.SLICEL_X0.BLUT.INIT[13] 34_29
CLBLL_L.SLICEL_X0.BLUT.INIT[14] 35_28
CLBLL_L.SLICEL_X0.BLUT.INIT[15] 34_28
CLBLL_L.SLICEL_X0.BLUT.INIT[16] 32_27
CLBLL_L.SLICEL_X0.BLUT.INIT[17] 33_27
CLBLL_L.SLICEL_X0.BLUT.INIT[18] 32_26
CLBLL_L.SLICEL_X0.BLUT.INIT[19] 33_26
CLBLL_L.SLICEL_X0.BLUT.INIT[20] 32_25
CLBLL_L.SLICEL_X0.BLUT.INIT[21] 33_25
CLBLL_L.SLICEL_X0.BLUT.INIT[22] 32_24
CLBLL_L.SLICEL_X0.BLUT.INIT[23] 33_24
CLBLL_L.SLICEL_X0.BLUT.INIT[24] 35_27
CLBLL_L.SLICEL_X0.BLUT.INIT[25] 34_27
CLBLL_L.SLICEL_X0.BLUT.INIT[26] 35_26
CLBLL_L.SLICEL_X0.BLUT.INIT[27] 34_26
CLBLL_L.SLICEL_X0.BLUT.INIT[28] 35_25
CLBLL_L.SLICEL_X0.BLUT.INIT[29] 34_25
CLBLL_L.SLICEL_X0.BLUT.INIT[30] 35_24
CLBLL_L.SLICEL_X0.BLUT.INIT[31] 34_24
CLBLL_L.SLICEL_X0.BLUT.INIT[32] 32_23
CLBLL_L.SLICEL_X0.BLUT.INIT[33] 33_23
CLBLL_L.SLICEL_X0.BLUT.INIT[34] 32_22
CLBLL_L.SLICEL_X0.BLUT.INIT[35] 33_22
CLBLL_L.SLICEL_X0.BLUT.INIT[36] 32_21
CLBLL_L.SLICEL_X0.BLUT.INIT[37] 33_21
CLBLL_L.SLICEL_X0.BLUT.INIT[38] 32_20
CLBLL_L.SLICEL_X0.BLUT.INIT[39] 33_20
CLBLL_L.SLICEL_X0.BLUT.INIT[40] 35_23
CLBLL_L.SLICEL_X0.BLUT.INIT[41] 34_23
CLBLL_L.SLICEL_X0.BLUT.INIT[42] 35_22
CLBLL_L.SLICEL_X0.BLUT.INIT[43] 34_22
CLBLL_L.SLICEL_X0.BLUT.INIT[44] 35_21
CLBLL_L.SLICEL_X0.BLUT.INIT[45] 34_21
CLBLL_L.SLICEL_X0.BLUT.INIT[46] 35_20
CLBLL_L.SLICEL_X0.BLUT.INIT[47] 34_20
CLBLL_L.SLICEL_X0.BLUT.INIT[48] 32_19
CLBLL_L.SLICEL_X0.BLUT.INIT[49] 33_19
CLBLL_L.SLICEL_X0.BLUT.INIT[50] 32_18
CLBLL_L.SLICEL_X0.BLUT.INIT[51] 33_18
CLBLL_L.SLICEL_X0.BLUT.INIT[52] 32_17
CLBLL_L.SLICEL_X0.BLUT.INIT[53] 33_17
CLBLL_L.SLICEL_X0.BLUT.INIT[54] 32_16
CLBLL_L.SLICEL_X0.BLUT.INIT[55] 33_16
CLBLL_L.SLICEL_X0.BLUT.INIT[56] 35_19
CLBLL_L.SLICEL_X0.BLUT.INIT[57] 34_19
CLBLL_L.SLICEL_X0.BLUT.INIT[58] 35_18
CLBLL_L.SLICEL_X0.BLUT.INIT[59] 34_18
CLBLL_L.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
CLBLL_L.SLICEL_X0.CLUT.INIT[02] 32_46
CLBLL_L.SLICEL_X0.CLUT.INIT[03] 33_46
CLBLL_L.SLICEL_X0.CLUT.INIT[04] 32_45
CLBLL_L.SLICEL_X0.CLUT.INIT[05] 33_45
CLBLL_L.SLICEL_X0.CLUT.INIT[06] 32_44
CLBLL_L.SLICEL_X0.CLUT.INIT[07] 33_44
CLBLL_L.SLICEL_X0.CLUT.INIT[08] 35_47
CLBLL_L.SLICEL_X0.CLUT.INIT[09] 34_47
CLBLL_L.SLICEL_X0.CLUT.INIT[10] 35_46
CLBLL_L.SLICEL_X0.CLUT.INIT[11] 34_46
CLBLL_L.SLICEL_X0.CLUT.INIT[12] 35_45
CLBLL_L.SLICEL_X0.CLUT.INIT[13] 34_45
CLBLL_L.SLICEL_X0.CLUT.INIT[14] 35_44
CLBLL_L.SLICEL_X0.CLUT.INIT[15] 34_44
CLBLL_L.SLICEL_X0.CLUT.INIT[16] 32_43
CLBLL_L.SLICEL_X0.CLUT.INIT[17] 33_43
CLBLL_L.SLICEL_X0.CLUT.INIT[18] 32_42
CLBLL_L.SLICEL_X0.CLUT.INIT[19] 33_42
CLBLL_L.SLICEL_X0.CLUT.INIT[20] 32_41
CLBLL_L.SLICEL_X0.CLUT.INIT[21] 33_41
CLBLL_L.SLICEL_X0.CLUT.INIT[22] 32_40
CLBLL_L.SLICEL_X0.CLUT.INIT[23] 33_40
CLBLL_L.SLICEL_X0.CLUT.INIT[24] 35_43
CLBLL_L.SLICEL_X0.CLUT.INIT[25] 34_43
CLBLL_L.SLICEL_X0.CLUT.INIT[26] 35_42
CLBLL_L.SLICEL_X0.CLUT.INIT[27] 34_42
CLBLL_L.SLICEL_X0.CLUT.INIT[28] 35_41
CLBLL_L.SLICEL_X0.CLUT.INIT[29] 34_41
CLBLL_L.SLICEL_X0.CLUT.INIT[30] 35_40
CLBLL_L.SLICEL_X0.CLUT.INIT[31] 34_40
CLBLL_L.SLICEL_X0.CLUT.INIT[32] 32_39
CLBLL_L.SLICEL_X0.CLUT.INIT[33] 33_39
CLBLL_L.SLICEL_X0.CLUT.INIT[34] 32_38
CLBLL_L.SLICEL_X0.CLUT.INIT[35] 33_38
CLBLL_L.SLICEL_X0.CLUT.INIT[36] 32_37
CLBLL_L.SLICEL_X0.CLUT.INIT[37] 33_37
CLBLL_L.SLICEL_X0.CLUT.INIT[38] 32_36
CLBLL_L.SLICEL_X0.CLUT.INIT[39] 33_36
CLBLL_L.SLICEL_X0.CLUT.INIT[40] 35_39
CLBLL_L.SLICEL_X0.CLUT.INIT[41] 34_39
CLBLL_L.SLICEL_X0.CLUT.INIT[42] 35_38
CLBLL_L.SLICEL_X0.CLUT.INIT[43] 34_38
CLBLL_L.SLICEL_X0.CLUT.INIT[44] 35_37
CLBLL_L.SLICEL_X0.CLUT.INIT[45] 34_37
CLBLL_L.SLICEL_X0.CLUT.INIT[46] 35_36
CLBLL_L.SLICEL_X0.CLUT.INIT[47] 34_36
CLBLL_L.SLICEL_X0.CLUT.INIT[48] 32_35
CLBLL_L.SLICEL_X0.CLUT.INIT[49] 33_35
CLBLL_L.SLICEL_X0.CLUT.INIT[50] 32_34
CLBLL_L.SLICEL_X0.CLUT.INIT[51] 33_34
CLBLL_L.SLICEL_X0.CLUT.INIT[52] 32_33
CLBLL_L.SLICEL_X0.CLUT.INIT[53] 33_33
CLBLL_L.SLICEL_X0.CLUT.INIT[54] 32_32
CLBLL_L.SLICEL_X0.CLUT.INIT[55] 33_32
CLBLL_L.SLICEL_X0.CLUT.INIT[56] 35_35
CLBLL_L.SLICEL_X0.CLUT.INIT[57] 34_35
CLBLL_L.SLICEL_X0.CLUT.INIT[58] 35_34
CLBLL_L.SLICEL_X0.CLUT.INIT[59] 34_34
CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_L.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
CLBLL_L.SLICEL_X0.DLUT.INIT[03] 33_62
CLBLL_L.SLICEL_X0.DLUT.INIT[04] 32_61
CLBLL_L.SLICEL_X0.DLUT.INIT[05] 33_61
CLBLL_L.SLICEL_X0.DLUT.INIT[06] 32_60
CLBLL_L.SLICEL_X0.DLUT.INIT[07] 33_60
CLBLL_L.SLICEL_X0.DLUT.INIT[08] 35_63
CLBLL_L.SLICEL_X0.DLUT.INIT[09] 34_63
CLBLL_L.SLICEL_X0.DLUT.INIT[10] 35_62
CLBLL_L.SLICEL_X0.DLUT.INIT[11] 34_62
CLBLL_L.SLICEL_X0.DLUT.INIT[12] 35_61
CLBLL_L.SLICEL_X0.DLUT.INIT[13] 34_61
CLBLL_L.SLICEL_X0.DLUT.INIT[14] 35_60
CLBLL_L.SLICEL_X0.DLUT.INIT[15] 34_60
CLBLL_L.SLICEL_X0.DLUT.INIT[16] 32_59
CLBLL_L.SLICEL_X0.DLUT.INIT[17] 33_59
CLBLL_L.SLICEL_X0.DLUT.INIT[18] 32_58
CLBLL_L.SLICEL_X0.DLUT.INIT[19] 33_58
CLBLL_L.SLICEL_X0.DLUT.INIT[20] 32_57
CLBLL_L.SLICEL_X0.DLUT.INIT[21] 33_57
CLBLL_L.SLICEL_X0.DLUT.INIT[22] 32_56
CLBLL_L.SLICEL_X0.DLUT.INIT[23] 33_56
CLBLL_L.SLICEL_X0.DLUT.INIT[24] 35_59
CLBLL_L.SLICEL_X0.DLUT.INIT[25] 34_59
CLBLL_L.SLICEL_X0.DLUT.INIT[26] 35_58
CLBLL_L.SLICEL_X0.DLUT.INIT[27] 34_58
CLBLL_L.SLICEL_X0.DLUT.INIT[28] 35_57
CLBLL_L.SLICEL_X0.DLUT.INIT[29] 34_57
CLBLL_L.SLICEL_X0.DLUT.INIT[30] 35_56
CLBLL_L.SLICEL_X0.DLUT.INIT[31] 34_56
CLBLL_L.SLICEL_X0.DLUT.INIT[32] 32_55
CLBLL_L.SLICEL_X0.DLUT.INIT[33] 33_55
CLBLL_L.SLICEL_X0.DLUT.INIT[34] 32_54
CLBLL_L.SLICEL_X0.DLUT.INIT[35] 33_54
CLBLL_L.SLICEL_X0.DLUT.INIT[36] 32_53
CLBLL_L.SLICEL_X0.DLUT.INIT[37] 33_53
CLBLL_L.SLICEL_X0.DLUT.INIT[38] 32_52
CLBLL_L.SLICEL_X0.DLUT.INIT[39] 33_52
CLBLL_L.SLICEL_X0.DLUT.INIT[40] 35_55
CLBLL_L.SLICEL_X0.DLUT.INIT[41] 34_55
CLBLL_L.SLICEL_X0.DLUT.INIT[42] 35_54
CLBLL_L.SLICEL_X0.DLUT.INIT[43] 34_54
CLBLL_L.SLICEL_X0.DLUT.INIT[44] 35_53
CLBLL_L.SLICEL_X0.DLUT.INIT[45] 34_53
CLBLL_L.SLICEL_X0.DLUT.INIT[46] 35_52
CLBLL_L.SLICEL_X0.DLUT.INIT[47] 34_52
CLBLL_L.SLICEL_X0.DLUT.INIT[48] 32_51
CLBLL_L.SLICEL_X0.DLUT.INIT[49] 33_51
CLBLL_L.SLICEL_X0.DLUT.INIT[50] 32_50
CLBLL_L.SLICEL_X0.DLUT.INIT[51] 33_50
CLBLL_L.SLICEL_X0.DLUT.INIT[52] 32_49
CLBLL_L.SLICEL_X0.DLUT.INIT[53] 33_49
CLBLL_L.SLICEL_X0.DLUT.INIT[54] 32_48
CLBLL_L.SLICEL_X0.DLUT.INIT[55] 33_48
CLBLL_L.SLICEL_X0.DLUT.INIT[56] 35_51
CLBLL_L.SLICEL_X0.DLUT.INIT[57] 34_51
CLBLL_L.SLICEL_X0.DLUT.INIT[58] 35_50
CLBLL_L.SLICEL_X0.DLUT.INIT[59] 34_50
CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
CLBLL_L.SLICEL_X1.ALUT.INIT[03] 27_14
CLBLL_L.SLICEL_X1.ALUT.INIT[04] 26_13
CLBLL_L.SLICEL_X1.ALUT.INIT[05] 27_13
CLBLL_L.SLICEL_X1.ALUT.INIT[06] 26_12
CLBLL_L.SLICEL_X1.ALUT.INIT[07] 27_12
CLBLL_L.SLICEL_X1.ALUT.INIT[08] 29_15
CLBLL_L.SLICEL_X1.ALUT.INIT[09] 28_15
CLBLL_L.SLICEL_X1.ALUT.INIT[10] 29_14
CLBLL_L.SLICEL_X1.ALUT.INIT[11] 28_14
CLBLL_L.SLICEL_X1.ALUT.INIT[12] 29_13
CLBLL_L.SLICEL_X1.ALUT.INIT[13] 28_13
CLBLL_L.SLICEL_X1.ALUT.INIT[14] 29_12
CLBLL_L.SLICEL_X1.ALUT.INIT[15] 28_12
CLBLL_L.SLICEL_X1.ALUT.INIT[16] 26_11
CLBLL_L.SLICEL_X1.ALUT.INIT[17] 27_11
CLBLL_L.SLICEL_X1.ALUT.INIT[18] 26_10
CLBLL_L.SLICEL_X1.ALUT.INIT[19] 27_10
CLBLL_L.SLICEL_X1.ALUT.INIT[20] 26_09
CLBLL_L.SLICEL_X1.ALUT.INIT[21] 27_09
CLBLL_L.SLICEL_X1.ALUT.INIT[22] 26_08
CLBLL_L.SLICEL_X1.ALUT.INIT[23] 27_08
CLBLL_L.SLICEL_X1.ALUT.INIT[24] 29_11
CLBLL_L.SLICEL_X1.ALUT.INIT[25] 28_11
CLBLL_L.SLICEL_X1.ALUT.INIT[26] 29_10
CLBLL_L.SLICEL_X1.ALUT.INIT[27] 28_10
CLBLL_L.SLICEL_X1.ALUT.INIT[28] 29_09
CLBLL_L.SLICEL_X1.ALUT.INIT[29] 28_09
CLBLL_L.SLICEL_X1.ALUT.INIT[30] 29_08
CLBLL_L.SLICEL_X1.ALUT.INIT[31] 28_08
CLBLL_L.SLICEL_X1.ALUT.INIT[32] 26_07
CLBLL_L.SLICEL_X1.ALUT.INIT[33] 27_07
CLBLL_L.SLICEL_X1.ALUT.INIT[34] 26_06
CLBLL_L.SLICEL_X1.ALUT.INIT[35] 27_06
CLBLL_L.SLICEL_X1.ALUT.INIT[36] 26_05
CLBLL_L.SLICEL_X1.ALUT.INIT[37] 27_05
CLBLL_L.SLICEL_X1.ALUT.INIT[38] 26_04
CLBLL_L.SLICEL_X1.ALUT.INIT[39] 27_04
CLBLL_L.SLICEL_X1.ALUT.INIT[40] 29_07
CLBLL_L.SLICEL_X1.ALUT.INIT[41] 28_07
CLBLL_L.SLICEL_X1.ALUT.INIT[42] 29_06
CLBLL_L.SLICEL_X1.ALUT.INIT[43] 28_06
CLBLL_L.SLICEL_X1.ALUT.INIT[44] 29_05
CLBLL_L.SLICEL_X1.ALUT.INIT[45] 28_05
CLBLL_L.SLICEL_X1.ALUT.INIT[46] 29_04
CLBLL_L.SLICEL_X1.ALUT.INIT[47] 28_04
CLBLL_L.SLICEL_X1.ALUT.INIT[48] 26_03
CLBLL_L.SLICEL_X1.ALUT.INIT[49] 27_03
CLBLL_L.SLICEL_X1.ALUT.INIT[50] 26_02
CLBLL_L.SLICEL_X1.ALUT.INIT[51] 27_02
CLBLL_L.SLICEL_X1.ALUT.INIT[52] 26_01
CLBLL_L.SLICEL_X1.ALUT.INIT[53] 27_01
CLBLL_L.SLICEL_X1.ALUT.INIT[54] 26_00
CLBLL_L.SLICEL_X1.ALUT.INIT[55] 27_00
CLBLL_L.SLICEL_X1.ALUT.INIT[56] 29_03
CLBLL_L.SLICEL_X1.ALUT.INIT[57] 28_03
CLBLL_L.SLICEL_X1.ALUT.INIT[58] 29_02
CLBLL_L.SLICEL_X1.ALUT.INIT[59] 28_02
CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
CLBLL_L.SLICEL_X1.BLUT.INIT[03] 27_30
CLBLL_L.SLICEL_X1.BLUT.INIT[04] 26_29
CLBLL_L.SLICEL_X1.BLUT.INIT[05] 27_29
CLBLL_L.SLICEL_X1.BLUT.INIT[06] 26_28
CLBLL_L.SLICEL_X1.BLUT.INIT[07] 27_28
CLBLL_L.SLICEL_X1.BLUT.INIT[08] 29_31
CLBLL_L.SLICEL_X1.BLUT.INIT[09] 28_31
CLBLL_L.SLICEL_X1.BLUT.INIT[10] 29_30
CLBLL_L.SLICEL_X1.BLUT.INIT[11] 28_30
CLBLL_L.SLICEL_X1.BLUT.INIT[12] 29_29
CLBLL_L.SLICEL_X1.BLUT.INIT[13] 28_29
CLBLL_L.SLICEL_X1.BLUT.INIT[14] 29_28
CLBLL_L.SLICEL_X1.BLUT.INIT[15] 28_28
CLBLL_L.SLICEL_X1.BLUT.INIT[16] 26_27
CLBLL_L.SLICEL_X1.BLUT.INIT[17] 27_27
CLBLL_L.SLICEL_X1.BLUT.INIT[18] 26_26
CLBLL_L.SLICEL_X1.BLUT.INIT[19] 27_26
CLBLL_L.SLICEL_X1.BLUT.INIT[20] 26_25
CLBLL_L.SLICEL_X1.BLUT.INIT[21] 27_25
CLBLL_L.SLICEL_X1.BLUT.INIT[22] 26_24
CLBLL_L.SLICEL_X1.BLUT.INIT[23] 27_24
CLBLL_L.SLICEL_X1.BLUT.INIT[24] 29_27
CLBLL_L.SLICEL_X1.BLUT.INIT[25] 28_27
CLBLL_L.SLICEL_X1.BLUT.INIT[26] 29_26
CLBLL_L.SLICEL_X1.BLUT.INIT[27] 28_26
CLBLL_L.SLICEL_X1.BLUT.INIT[28] 29_25
CLBLL_L.SLICEL_X1.BLUT.INIT[29] 28_25
CLBLL_L.SLICEL_X1.BLUT.INIT[30] 29_24
CLBLL_L.SLICEL_X1.BLUT.INIT[31] 28_24
CLBLL_L.SLICEL_X1.BLUT.INIT[32] 26_23
CLBLL_L.SLICEL_X1.BLUT.INIT[33] 27_23
CLBLL_L.SLICEL_X1.BLUT.INIT[34] 26_22
CLBLL_L.SLICEL_X1.BLUT.INIT[35] 27_22
CLBLL_L.SLICEL_X1.BLUT.INIT[36] 26_21
CLBLL_L.SLICEL_X1.BLUT.INIT[37] 27_21
CLBLL_L.SLICEL_X1.BLUT.INIT[38] 26_20
CLBLL_L.SLICEL_X1.BLUT.INIT[39] 27_20
CLBLL_L.SLICEL_X1.BLUT.INIT[40] 29_23
CLBLL_L.SLICEL_X1.BLUT.INIT[41] 28_23
CLBLL_L.SLICEL_X1.BLUT.INIT[42] 29_22
CLBLL_L.SLICEL_X1.BLUT.INIT[43] 28_22
CLBLL_L.SLICEL_X1.BLUT.INIT[44] 29_21
CLBLL_L.SLICEL_X1.BLUT.INIT[45] 28_21
CLBLL_L.SLICEL_X1.BLUT.INIT[46] 29_20
CLBLL_L.SLICEL_X1.BLUT.INIT[47] 28_20
CLBLL_L.SLICEL_X1.BLUT.INIT[48] 26_19
CLBLL_L.SLICEL_X1.BLUT.INIT[49] 27_19
CLBLL_L.SLICEL_X1.BLUT.INIT[50] 26_18
CLBLL_L.SLICEL_X1.BLUT.INIT[51] 27_18
CLBLL_L.SLICEL_X1.BLUT.INIT[52] 26_17
CLBLL_L.SLICEL_X1.BLUT.INIT[53] 27_17
CLBLL_L.SLICEL_X1.BLUT.INIT[54] 26_16
CLBLL_L.SLICEL_X1.BLUT.INIT[55] 27_16
CLBLL_L.SLICEL_X1.BLUT.INIT[56] 29_19
CLBLL_L.SLICEL_X1.BLUT.INIT[57] 28_19
CLBLL_L.SLICEL_X1.BLUT.INIT[58] 29_18
CLBLL_L.SLICEL_X1.BLUT.INIT[59] 28_18
CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
CLBLL_L.SLICEL_X1.CLUT.INIT[02] 26_46
CLBLL_L.SLICEL_X1.CLUT.INIT[03] 27_46
CLBLL_L.SLICEL_X1.CLUT.INIT[04] 26_45
CLBLL_L.SLICEL_X1.CLUT.INIT[05] 27_45
CLBLL_L.SLICEL_X1.CLUT.INIT[06] 26_44
CLBLL_L.SLICEL_X1.CLUT.INIT[07] 27_44
CLBLL_L.SLICEL_X1.CLUT.INIT[08] 29_47
CLBLL_L.SLICEL_X1.CLUT.INIT[09] 28_47
CLBLL_L.SLICEL_X1.CLUT.INIT[10] 29_46
CLBLL_L.SLICEL_X1.CLUT.INIT[11] 28_46
CLBLL_L.SLICEL_X1.CLUT.INIT[12] 29_45
CLBLL_L.SLICEL_X1.CLUT.INIT[13] 28_45
CLBLL_L.SLICEL_X1.CLUT.INIT[14] 29_44
CLBLL_L.SLICEL_X1.CLUT.INIT[15] 28_44
CLBLL_L.SLICEL_X1.CLUT.INIT[16] 26_43
CLBLL_L.SLICEL_X1.CLUT.INIT[17] 27_43
CLBLL_L.SLICEL_X1.CLUT.INIT[18] 26_42
CLBLL_L.SLICEL_X1.CLUT.INIT[19] 27_42
CLBLL_L.SLICEL_X1.CLUT.INIT[20] 26_41
CLBLL_L.SLICEL_X1.CLUT.INIT[21] 27_41
CLBLL_L.SLICEL_X1.CLUT.INIT[22] 26_40
CLBLL_L.SLICEL_X1.CLUT.INIT[23] 27_40
CLBLL_L.SLICEL_X1.CLUT.INIT[24] 29_43
CLBLL_L.SLICEL_X1.CLUT.INIT[25] 28_43
CLBLL_L.SLICEL_X1.CLUT.INIT[26] 29_42
CLBLL_L.SLICEL_X1.CLUT.INIT[27] 28_42
CLBLL_L.SLICEL_X1.CLUT.INIT[28] 29_41
CLBLL_L.SLICEL_X1.CLUT.INIT[29] 28_41
CLBLL_L.SLICEL_X1.CLUT.INIT[30] 29_40
CLBLL_L.SLICEL_X1.CLUT.INIT[31] 28_40
CLBLL_L.SLICEL_X1.CLUT.INIT[32] 26_39
CLBLL_L.SLICEL_X1.CLUT.INIT[33] 27_39
CLBLL_L.SLICEL_X1.CLUT.INIT[34] 26_38
CLBLL_L.SLICEL_X1.CLUT.INIT[35] 27_38
CLBLL_L.SLICEL_X1.CLUT.INIT[36] 26_37
CLBLL_L.SLICEL_X1.CLUT.INIT[37] 27_37
CLBLL_L.SLICEL_X1.CLUT.INIT[38] 26_36
CLBLL_L.SLICEL_X1.CLUT.INIT[39] 27_36
CLBLL_L.SLICEL_X1.CLUT.INIT[40] 29_39
CLBLL_L.SLICEL_X1.CLUT.INIT[41] 28_39
CLBLL_L.SLICEL_X1.CLUT.INIT[42] 29_38
CLBLL_L.SLICEL_X1.CLUT.INIT[43] 28_38
CLBLL_L.SLICEL_X1.CLUT.INIT[44] 29_37
CLBLL_L.SLICEL_X1.CLUT.INIT[45] 28_37
CLBLL_L.SLICEL_X1.CLUT.INIT[46] 29_36
CLBLL_L.SLICEL_X1.CLUT.INIT[47] 28_36
CLBLL_L.SLICEL_X1.CLUT.INIT[48] 26_35
CLBLL_L.SLICEL_X1.CLUT.INIT[49] 27_35
CLBLL_L.SLICEL_X1.CLUT.INIT[50] 26_34
CLBLL_L.SLICEL_X1.CLUT.INIT[51] 27_34
CLBLL_L.SLICEL_X1.CLUT.INIT[52] 26_33
CLBLL_L.SLICEL_X1.CLUT.INIT[53] 27_33
CLBLL_L.SLICEL_X1.CLUT.INIT[54] 26_32
CLBLL_L.SLICEL_X1.CLUT.INIT[55] 27_32
CLBLL_L.SLICEL_X1.CLUT.INIT[56] 29_35
CLBLL_L.SLICEL_X1.CLUT.INIT[57] 28_35
CLBLL_L.SLICEL_X1.CLUT.INIT[58] 29_34
CLBLL_L.SLICEL_X1.CLUT.INIT[59] 28_34
CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
CLBLL_L.SLICEL_X1.DLUT.INIT[03] 27_62
CLBLL_L.SLICEL_X1.DLUT.INIT[04] 26_61
CLBLL_L.SLICEL_X1.DLUT.INIT[05] 27_61
CLBLL_L.SLICEL_X1.DLUT.INIT[06] 26_60
CLBLL_L.SLICEL_X1.DLUT.INIT[07] 27_60
CLBLL_L.SLICEL_X1.DLUT.INIT[08] 29_63
CLBLL_L.SLICEL_X1.DLUT.INIT[09] 28_63
CLBLL_L.SLICEL_X1.DLUT.INIT[10] 29_62
CLBLL_L.SLICEL_X1.DLUT.INIT[11] 28_62
CLBLL_L.SLICEL_X1.DLUT.INIT[12] 29_61
CLBLL_L.SLICEL_X1.DLUT.INIT[13] 28_61
CLBLL_L.SLICEL_X1.DLUT.INIT[14] 29_60
CLBLL_L.SLICEL_X1.DLUT.INIT[15] 28_60
CLBLL_L.SLICEL_X1.DLUT.INIT[16] 26_59
CLBLL_L.SLICEL_X1.DLUT.INIT[17] 27_59
CLBLL_L.SLICEL_X1.DLUT.INIT[18] 26_58
CLBLL_L.SLICEL_X1.DLUT.INIT[19] 27_58
CLBLL_L.SLICEL_X1.DLUT.INIT[20] 26_57
CLBLL_L.SLICEL_X1.DLUT.INIT[21] 27_57
CLBLL_L.SLICEL_X1.DLUT.INIT[22] 26_56
CLBLL_L.SLICEL_X1.DLUT.INIT[23] 27_56
CLBLL_L.SLICEL_X1.DLUT.INIT[24] 29_59
CLBLL_L.SLICEL_X1.DLUT.INIT[25] 28_59
CLBLL_L.SLICEL_X1.DLUT.INIT[26] 29_58
CLBLL_L.SLICEL_X1.DLUT.INIT[27] 28_58
CLBLL_L.SLICEL_X1.DLUT.INIT[28] 29_57
CLBLL_L.SLICEL_X1.DLUT.INIT[29] 28_57
CLBLL_L.SLICEL_X1.DLUT.INIT[30] 29_56
CLBLL_L.SLICEL_X1.DLUT.INIT[31] 28_56
CLBLL_L.SLICEL_X1.DLUT.INIT[32] 26_55
CLBLL_L.SLICEL_X1.DLUT.INIT[33] 27_55
CLBLL_L.SLICEL_X1.DLUT.INIT[34] 26_54
CLBLL_L.SLICEL_X1.DLUT.INIT[35] 27_54
CLBLL_L.SLICEL_X1.DLUT.INIT[36] 26_53
CLBLL_L.SLICEL_X1.DLUT.INIT[37] 27_53
CLBLL_L.SLICEL_X1.DLUT.INIT[38] 26_52
CLBLL_L.SLICEL_X1.DLUT.INIT[39] 27_52
CLBLL_L.SLICEL_X1.DLUT.INIT[40] 29_55
CLBLL_L.SLICEL_X1.DLUT.INIT[41] 28_55
CLBLL_L.SLICEL_X1.DLUT.INIT[42] 29_54
CLBLL_L.SLICEL_X1.DLUT.INIT[43] 28_54
CLBLL_L.SLICEL_X1.DLUT.INIT[44] 29_53
CLBLL_L.SLICEL_X1.DLUT.INIT[45] 28_53
CLBLL_L.SLICEL_X1.DLUT.INIT[46] 29_52
CLBLL_L.SLICEL_X1.DLUT.INIT[47] 28_52
CLBLL_L.SLICEL_X1.DLUT.INIT[48] 26_51
CLBLL_L.SLICEL_X1.DLUT.INIT[49] 27_51
CLBLL_L.SLICEL_X1.DLUT.INIT[50] 26_50
CLBLL_L.SLICEL_X1.DLUT.INIT[51] 27_50
CLBLL_L.SLICEL_X1.DLUT.INIT[52] 26_49
CLBLL_L.SLICEL_X1.DLUT.INIT[53] 27_49
CLBLL_L.SLICEL_X1.DLUT.INIT[54] 26_48
CLBLL_L.SLICEL_X1.DLUT.INIT[55] 27_48
CLBLL_L.SLICEL_X1.DLUT.INIT[56] 29_51
CLBLL_L.SLICEL_X1.DLUT.INIT[57] 28_51
CLBLL_L.SLICEL_X1.DLUT.INIT[58] 29_50
CLBLL_L.SLICEL_X1.DLUT.INIT[59] 28_50
CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49

678
zynq7/segbits_clbll_r.db Normal file
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@ -0,0 +1,678 @@
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_R.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
CLBLL_R.SLICEL_X0.ALUT.INIT[03] 33_14
CLBLL_R.SLICEL_X0.ALUT.INIT[04] 32_13
CLBLL_R.SLICEL_X0.ALUT.INIT[05] 33_13
CLBLL_R.SLICEL_X0.ALUT.INIT[06] 32_12
CLBLL_R.SLICEL_X0.ALUT.INIT[07] 33_12
CLBLL_R.SLICEL_X0.ALUT.INIT[08] 35_15
CLBLL_R.SLICEL_X0.ALUT.INIT[09] 34_15
CLBLL_R.SLICEL_X0.ALUT.INIT[10] 35_14
CLBLL_R.SLICEL_X0.ALUT.INIT[11] 34_14
CLBLL_R.SLICEL_X0.ALUT.INIT[12] 35_13
CLBLL_R.SLICEL_X0.ALUT.INIT[13] 34_13
CLBLL_R.SLICEL_X0.ALUT.INIT[14] 35_12
CLBLL_R.SLICEL_X0.ALUT.INIT[15] 34_12
CLBLL_R.SLICEL_X0.ALUT.INIT[16] 32_11
CLBLL_R.SLICEL_X0.ALUT.INIT[17] 33_11
CLBLL_R.SLICEL_X0.ALUT.INIT[18] 32_10
CLBLL_R.SLICEL_X0.ALUT.INIT[19] 33_10
CLBLL_R.SLICEL_X0.ALUT.INIT[20] 32_09
CLBLL_R.SLICEL_X0.ALUT.INIT[21] 33_09
CLBLL_R.SLICEL_X0.ALUT.INIT[22] 32_08
CLBLL_R.SLICEL_X0.ALUT.INIT[23] 33_08
CLBLL_R.SLICEL_X0.ALUT.INIT[24] 35_11
CLBLL_R.SLICEL_X0.ALUT.INIT[25] 34_11
CLBLL_R.SLICEL_X0.ALUT.INIT[26] 35_10
CLBLL_R.SLICEL_X0.ALUT.INIT[27] 34_10
CLBLL_R.SLICEL_X0.ALUT.INIT[28] 35_09
CLBLL_R.SLICEL_X0.ALUT.INIT[29] 34_09
CLBLL_R.SLICEL_X0.ALUT.INIT[30] 35_08
CLBLL_R.SLICEL_X0.ALUT.INIT[31] 34_08
CLBLL_R.SLICEL_X0.ALUT.INIT[32] 32_07
CLBLL_R.SLICEL_X0.ALUT.INIT[33] 33_07
CLBLL_R.SLICEL_X0.ALUT.INIT[34] 32_06
CLBLL_R.SLICEL_X0.ALUT.INIT[35] 33_06
CLBLL_R.SLICEL_X0.ALUT.INIT[36] 32_05
CLBLL_R.SLICEL_X0.ALUT.INIT[37] 33_05
CLBLL_R.SLICEL_X0.ALUT.INIT[38] 32_04
CLBLL_R.SLICEL_X0.ALUT.INIT[39] 33_04
CLBLL_R.SLICEL_X0.ALUT.INIT[40] 35_07
CLBLL_R.SLICEL_X0.ALUT.INIT[41] 34_07
CLBLL_R.SLICEL_X0.ALUT.INIT[42] 35_06
CLBLL_R.SLICEL_X0.ALUT.INIT[43] 34_06
CLBLL_R.SLICEL_X0.ALUT.INIT[44] 35_05
CLBLL_R.SLICEL_X0.ALUT.INIT[45] 34_05
CLBLL_R.SLICEL_X0.ALUT.INIT[46] 35_04
CLBLL_R.SLICEL_X0.ALUT.INIT[47] 34_04
CLBLL_R.SLICEL_X0.ALUT.INIT[48] 32_03
CLBLL_R.SLICEL_X0.ALUT.INIT[49] 33_03
CLBLL_R.SLICEL_X0.ALUT.INIT[50] 32_02
CLBLL_R.SLICEL_X0.ALUT.INIT[51] 33_02
CLBLL_R.SLICEL_X0.ALUT.INIT[52] 32_01
CLBLL_R.SLICEL_X0.ALUT.INIT[53] 33_01
CLBLL_R.SLICEL_X0.ALUT.INIT[54] 32_00
CLBLL_R.SLICEL_X0.ALUT.INIT[55] 33_00
CLBLL_R.SLICEL_X0.ALUT.INIT[56] 35_03
CLBLL_R.SLICEL_X0.ALUT.INIT[57] 34_03
CLBLL_R.SLICEL_X0.ALUT.INIT[58] 35_02
CLBLL_R.SLICEL_X0.ALUT.INIT[59] 34_02
CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
CLBLL_R.SLICEL_X0.BLUT.INIT[03] 33_30
CLBLL_R.SLICEL_X0.BLUT.INIT[04] 32_29
CLBLL_R.SLICEL_X0.BLUT.INIT[05] 33_29
CLBLL_R.SLICEL_X0.BLUT.INIT[06] 32_28
CLBLL_R.SLICEL_X0.BLUT.INIT[07] 33_28
CLBLL_R.SLICEL_X0.BLUT.INIT[08] 35_31
CLBLL_R.SLICEL_X0.BLUT.INIT[09] 34_31
CLBLL_R.SLICEL_X0.BLUT.INIT[10] 35_30
CLBLL_R.SLICEL_X0.BLUT.INIT[11] 34_30
CLBLL_R.SLICEL_X0.BLUT.INIT[12] 35_29
CLBLL_R.SLICEL_X0.BLUT.INIT[13] 34_29
CLBLL_R.SLICEL_X0.BLUT.INIT[14] 35_28
CLBLL_R.SLICEL_X0.BLUT.INIT[15] 34_28
CLBLL_R.SLICEL_X0.BLUT.INIT[16] 32_27
CLBLL_R.SLICEL_X0.BLUT.INIT[17] 33_27
CLBLL_R.SLICEL_X0.BLUT.INIT[18] 32_26
CLBLL_R.SLICEL_X0.BLUT.INIT[19] 33_26
CLBLL_R.SLICEL_X0.BLUT.INIT[20] 32_25
CLBLL_R.SLICEL_X0.BLUT.INIT[21] 33_25
CLBLL_R.SLICEL_X0.BLUT.INIT[22] 32_24
CLBLL_R.SLICEL_X0.BLUT.INIT[23] 33_24
CLBLL_R.SLICEL_X0.BLUT.INIT[24] 35_27
CLBLL_R.SLICEL_X0.BLUT.INIT[25] 34_27
CLBLL_R.SLICEL_X0.BLUT.INIT[26] 35_26
CLBLL_R.SLICEL_X0.BLUT.INIT[27] 34_26
CLBLL_R.SLICEL_X0.BLUT.INIT[28] 35_25
CLBLL_R.SLICEL_X0.BLUT.INIT[29] 34_25
CLBLL_R.SLICEL_X0.BLUT.INIT[30] 35_24
CLBLL_R.SLICEL_X0.BLUT.INIT[31] 34_24
CLBLL_R.SLICEL_X0.BLUT.INIT[32] 32_23
CLBLL_R.SLICEL_X0.BLUT.INIT[33] 33_23
CLBLL_R.SLICEL_X0.BLUT.INIT[34] 32_22
CLBLL_R.SLICEL_X0.BLUT.INIT[35] 33_22
CLBLL_R.SLICEL_X0.BLUT.INIT[36] 32_21
CLBLL_R.SLICEL_X0.BLUT.INIT[37] 33_21
CLBLL_R.SLICEL_X0.BLUT.INIT[38] 32_20
CLBLL_R.SLICEL_X0.BLUT.INIT[39] 33_20
CLBLL_R.SLICEL_X0.BLUT.INIT[40] 35_23
CLBLL_R.SLICEL_X0.BLUT.INIT[41] 34_23
CLBLL_R.SLICEL_X0.BLUT.INIT[42] 35_22
CLBLL_R.SLICEL_X0.BLUT.INIT[43] 34_22
CLBLL_R.SLICEL_X0.BLUT.INIT[44] 35_21
CLBLL_R.SLICEL_X0.BLUT.INIT[45] 34_21
CLBLL_R.SLICEL_X0.BLUT.INIT[46] 35_20
CLBLL_R.SLICEL_X0.BLUT.INIT[47] 34_20
CLBLL_R.SLICEL_X0.BLUT.INIT[48] 32_19
CLBLL_R.SLICEL_X0.BLUT.INIT[49] 33_19
CLBLL_R.SLICEL_X0.BLUT.INIT[50] 32_18
CLBLL_R.SLICEL_X0.BLUT.INIT[51] 33_18
CLBLL_R.SLICEL_X0.BLUT.INIT[52] 32_17
CLBLL_R.SLICEL_X0.BLUT.INIT[53] 33_17
CLBLL_R.SLICEL_X0.BLUT.INIT[54] 32_16
CLBLL_R.SLICEL_X0.BLUT.INIT[55] 33_16
CLBLL_R.SLICEL_X0.BLUT.INIT[56] 35_19
CLBLL_R.SLICEL_X0.BLUT.INIT[57] 34_19
CLBLL_R.SLICEL_X0.BLUT.INIT[58] 35_18
CLBLL_R.SLICEL_X0.BLUT.INIT[59] 34_18
CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_R.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CLKINV 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
CLBLL_R.SLICEL_X0.CLUT.INIT[02] 32_46
CLBLL_R.SLICEL_X0.CLUT.INIT[03] 33_46
CLBLL_R.SLICEL_X0.CLUT.INIT[04] 32_45
CLBLL_R.SLICEL_X0.CLUT.INIT[05] 33_45
CLBLL_R.SLICEL_X0.CLUT.INIT[06] 32_44
CLBLL_R.SLICEL_X0.CLUT.INIT[07] 33_44
CLBLL_R.SLICEL_X0.CLUT.INIT[08] 35_47
CLBLL_R.SLICEL_X0.CLUT.INIT[09] 34_47
CLBLL_R.SLICEL_X0.CLUT.INIT[10] 35_46
CLBLL_R.SLICEL_X0.CLUT.INIT[11] 34_46
CLBLL_R.SLICEL_X0.CLUT.INIT[12] 35_45
CLBLL_R.SLICEL_X0.CLUT.INIT[13] 34_45
CLBLL_R.SLICEL_X0.CLUT.INIT[14] 35_44
CLBLL_R.SLICEL_X0.CLUT.INIT[15] 34_44
CLBLL_R.SLICEL_X0.CLUT.INIT[16] 32_43
CLBLL_R.SLICEL_X0.CLUT.INIT[17] 33_43
CLBLL_R.SLICEL_X0.CLUT.INIT[18] 32_42
CLBLL_R.SLICEL_X0.CLUT.INIT[19] 33_42
CLBLL_R.SLICEL_X0.CLUT.INIT[20] 32_41
CLBLL_R.SLICEL_X0.CLUT.INIT[21] 33_41
CLBLL_R.SLICEL_X0.CLUT.INIT[22] 32_40
CLBLL_R.SLICEL_X0.CLUT.INIT[23] 33_40
CLBLL_R.SLICEL_X0.CLUT.INIT[24] 35_43
CLBLL_R.SLICEL_X0.CLUT.INIT[25] 34_43
CLBLL_R.SLICEL_X0.CLUT.INIT[26] 35_42
CLBLL_R.SLICEL_X0.CLUT.INIT[27] 34_42
CLBLL_R.SLICEL_X0.CLUT.INIT[28] 35_41
CLBLL_R.SLICEL_X0.CLUT.INIT[29] 34_41
CLBLL_R.SLICEL_X0.CLUT.INIT[30] 35_40
CLBLL_R.SLICEL_X0.CLUT.INIT[31] 34_40
CLBLL_R.SLICEL_X0.CLUT.INIT[32] 32_39
CLBLL_R.SLICEL_X0.CLUT.INIT[33] 33_39
CLBLL_R.SLICEL_X0.CLUT.INIT[34] 32_38
CLBLL_R.SLICEL_X0.CLUT.INIT[35] 33_38
CLBLL_R.SLICEL_X0.CLUT.INIT[36] 32_37
CLBLL_R.SLICEL_X0.CLUT.INIT[37] 33_37
CLBLL_R.SLICEL_X0.CLUT.INIT[38] 32_36
CLBLL_R.SLICEL_X0.CLUT.INIT[39] 33_36
CLBLL_R.SLICEL_X0.CLUT.INIT[40] 35_39
CLBLL_R.SLICEL_X0.CLUT.INIT[41] 34_39
CLBLL_R.SLICEL_X0.CLUT.INIT[42] 35_38
CLBLL_R.SLICEL_X0.CLUT.INIT[43] 34_38
CLBLL_R.SLICEL_X0.CLUT.INIT[44] 35_37
CLBLL_R.SLICEL_X0.CLUT.INIT[45] 34_37
CLBLL_R.SLICEL_X0.CLUT.INIT[46] 35_36
CLBLL_R.SLICEL_X0.CLUT.INIT[47] 34_36
CLBLL_R.SLICEL_X0.CLUT.INIT[48] 32_35
CLBLL_R.SLICEL_X0.CLUT.INIT[49] 33_35
CLBLL_R.SLICEL_X0.CLUT.INIT[50] 32_34
CLBLL_R.SLICEL_X0.CLUT.INIT[51] 33_34
CLBLL_R.SLICEL_X0.CLUT.INIT[52] 32_33
CLBLL_R.SLICEL_X0.CLUT.INIT[53] 33_33
CLBLL_R.SLICEL_X0.CLUT.INIT[54] 32_32
CLBLL_R.SLICEL_X0.CLUT.INIT[55] 33_32
CLBLL_R.SLICEL_X0.CLUT.INIT[56] 35_35
CLBLL_R.SLICEL_X0.CLUT.INIT[57] 34_35
CLBLL_R.SLICEL_X0.CLUT.INIT[58] 35_34
CLBLL_R.SLICEL_X0.CLUT.INIT[59] 34_34
CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLL_R.SLICEL_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
CLBLL_R.SLICEL_X0.DLUT.INIT[03] 33_62
CLBLL_R.SLICEL_X0.DLUT.INIT[04] 32_61
CLBLL_R.SLICEL_X0.DLUT.INIT[05] 33_61
CLBLL_R.SLICEL_X0.DLUT.INIT[06] 32_60
CLBLL_R.SLICEL_X0.DLUT.INIT[07] 33_60
CLBLL_R.SLICEL_X0.DLUT.INIT[08] 35_63
CLBLL_R.SLICEL_X0.DLUT.INIT[09] 34_63
CLBLL_R.SLICEL_X0.DLUT.INIT[10] 35_62
CLBLL_R.SLICEL_X0.DLUT.INIT[11] 34_62
CLBLL_R.SLICEL_X0.DLUT.INIT[12] 35_61
CLBLL_R.SLICEL_X0.DLUT.INIT[13] 34_61
CLBLL_R.SLICEL_X0.DLUT.INIT[14] 35_60
CLBLL_R.SLICEL_X0.DLUT.INIT[15] 34_60
CLBLL_R.SLICEL_X0.DLUT.INIT[16] 32_59
CLBLL_R.SLICEL_X0.DLUT.INIT[17] 33_59
CLBLL_R.SLICEL_X0.DLUT.INIT[18] 32_58
CLBLL_R.SLICEL_X0.DLUT.INIT[19] 33_58
CLBLL_R.SLICEL_X0.DLUT.INIT[20] 32_57
CLBLL_R.SLICEL_X0.DLUT.INIT[21] 33_57
CLBLL_R.SLICEL_X0.DLUT.INIT[22] 32_56
CLBLL_R.SLICEL_X0.DLUT.INIT[23] 33_56
CLBLL_R.SLICEL_X0.DLUT.INIT[24] 35_59
CLBLL_R.SLICEL_X0.DLUT.INIT[25] 34_59
CLBLL_R.SLICEL_X0.DLUT.INIT[26] 35_58
CLBLL_R.SLICEL_X0.DLUT.INIT[27] 34_58
CLBLL_R.SLICEL_X0.DLUT.INIT[28] 35_57
CLBLL_R.SLICEL_X0.DLUT.INIT[29] 34_57
CLBLL_R.SLICEL_X0.DLUT.INIT[30] 35_56
CLBLL_R.SLICEL_X0.DLUT.INIT[31] 34_56
CLBLL_R.SLICEL_X0.DLUT.INIT[32] 32_55
CLBLL_R.SLICEL_X0.DLUT.INIT[33] 33_55
CLBLL_R.SLICEL_X0.DLUT.INIT[34] 32_54
CLBLL_R.SLICEL_X0.DLUT.INIT[35] 33_54
CLBLL_R.SLICEL_X0.DLUT.INIT[36] 32_53
CLBLL_R.SLICEL_X0.DLUT.INIT[37] 33_53
CLBLL_R.SLICEL_X0.DLUT.INIT[38] 32_52
CLBLL_R.SLICEL_X0.DLUT.INIT[39] 33_52
CLBLL_R.SLICEL_X0.DLUT.INIT[40] 35_55
CLBLL_R.SLICEL_X0.DLUT.INIT[41] 34_55
CLBLL_R.SLICEL_X0.DLUT.INIT[42] 35_54
CLBLL_R.SLICEL_X0.DLUT.INIT[43] 34_54
CLBLL_R.SLICEL_X0.DLUT.INIT[44] 35_53
CLBLL_R.SLICEL_X0.DLUT.INIT[45] 34_53
CLBLL_R.SLICEL_X0.DLUT.INIT[46] 35_52
CLBLL_R.SLICEL_X0.DLUT.INIT[47] 34_52
CLBLL_R.SLICEL_X0.DLUT.INIT[48] 32_51
CLBLL_R.SLICEL_X0.DLUT.INIT[49] 33_51
CLBLL_R.SLICEL_X0.DLUT.INIT[50] 32_50
CLBLL_R.SLICEL_X0.DLUT.INIT[51] 33_50
CLBLL_R.SLICEL_X0.DLUT.INIT[52] 32_49
CLBLL_R.SLICEL_X0.DLUT.INIT[53] 33_49
CLBLL_R.SLICEL_X0.DLUT.INIT[54] 32_48
CLBLL_R.SLICEL_X0.DLUT.INIT[55] 33_48
CLBLL_R.SLICEL_X0.DLUT.INIT[56] 35_51
CLBLL_R.SLICEL_X0.DLUT.INIT[57] 34_51
CLBLL_R.SLICEL_X0.DLUT.INIT[58] 35_50
CLBLL_R.SLICEL_X0.DLUT.INIT[59] 34_50
CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
CLBLL_R.SLICEL_X1.ALUT.INIT[03] 27_14
CLBLL_R.SLICEL_X1.ALUT.INIT[04] 26_13
CLBLL_R.SLICEL_X1.ALUT.INIT[05] 27_13
CLBLL_R.SLICEL_X1.ALUT.INIT[06] 26_12
CLBLL_R.SLICEL_X1.ALUT.INIT[07] 27_12
CLBLL_R.SLICEL_X1.ALUT.INIT[08] 29_15
CLBLL_R.SLICEL_X1.ALUT.INIT[09] 28_15
CLBLL_R.SLICEL_X1.ALUT.INIT[10] 29_14
CLBLL_R.SLICEL_X1.ALUT.INIT[11] 28_14
CLBLL_R.SLICEL_X1.ALUT.INIT[12] 29_13
CLBLL_R.SLICEL_X1.ALUT.INIT[13] 28_13
CLBLL_R.SLICEL_X1.ALUT.INIT[14] 29_12
CLBLL_R.SLICEL_X1.ALUT.INIT[15] 28_12
CLBLL_R.SLICEL_X1.ALUT.INIT[16] 26_11
CLBLL_R.SLICEL_X1.ALUT.INIT[17] 27_11
CLBLL_R.SLICEL_X1.ALUT.INIT[18] 26_10
CLBLL_R.SLICEL_X1.ALUT.INIT[19] 27_10
CLBLL_R.SLICEL_X1.ALUT.INIT[20] 26_09
CLBLL_R.SLICEL_X1.ALUT.INIT[21] 27_09
CLBLL_R.SLICEL_X1.ALUT.INIT[22] 26_08
CLBLL_R.SLICEL_X1.ALUT.INIT[23] 27_08
CLBLL_R.SLICEL_X1.ALUT.INIT[24] 29_11
CLBLL_R.SLICEL_X1.ALUT.INIT[25] 28_11
CLBLL_R.SLICEL_X1.ALUT.INIT[26] 29_10
CLBLL_R.SLICEL_X1.ALUT.INIT[27] 28_10
CLBLL_R.SLICEL_X1.ALUT.INIT[28] 29_09
CLBLL_R.SLICEL_X1.ALUT.INIT[29] 28_09
CLBLL_R.SLICEL_X1.ALUT.INIT[30] 29_08
CLBLL_R.SLICEL_X1.ALUT.INIT[31] 28_08
CLBLL_R.SLICEL_X1.ALUT.INIT[32] 26_07
CLBLL_R.SLICEL_X1.ALUT.INIT[33] 27_07
CLBLL_R.SLICEL_X1.ALUT.INIT[34] 26_06
CLBLL_R.SLICEL_X1.ALUT.INIT[35] 27_06
CLBLL_R.SLICEL_X1.ALUT.INIT[36] 26_05
CLBLL_R.SLICEL_X1.ALUT.INIT[37] 27_05
CLBLL_R.SLICEL_X1.ALUT.INIT[38] 26_04
CLBLL_R.SLICEL_X1.ALUT.INIT[39] 27_04
CLBLL_R.SLICEL_X1.ALUT.INIT[40] 29_07
CLBLL_R.SLICEL_X1.ALUT.INIT[41] 28_07
CLBLL_R.SLICEL_X1.ALUT.INIT[42] 29_06
CLBLL_R.SLICEL_X1.ALUT.INIT[43] 28_06
CLBLL_R.SLICEL_X1.ALUT.INIT[44] 29_05
CLBLL_R.SLICEL_X1.ALUT.INIT[45] 28_05
CLBLL_R.SLICEL_X1.ALUT.INIT[46] 29_04
CLBLL_R.SLICEL_X1.ALUT.INIT[47] 28_04
CLBLL_R.SLICEL_X1.ALUT.INIT[48] 26_03
CLBLL_R.SLICEL_X1.ALUT.INIT[49] 27_03
CLBLL_R.SLICEL_X1.ALUT.INIT[50] 26_02
CLBLL_R.SLICEL_X1.ALUT.INIT[51] 27_02
CLBLL_R.SLICEL_X1.ALUT.INIT[52] 26_01
CLBLL_R.SLICEL_X1.ALUT.INIT[53] 27_01
CLBLL_R.SLICEL_X1.ALUT.INIT[54] 26_00
CLBLL_R.SLICEL_X1.ALUT.INIT[55] 27_00
CLBLL_R.SLICEL_X1.ALUT.INIT[56] 29_03
CLBLL_R.SLICEL_X1.ALUT.INIT[57] 28_03
CLBLL_R.SLICEL_X1.ALUT.INIT[58] 29_02
CLBLL_R.SLICEL_X1.ALUT.INIT[59] 28_02
CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
CLBLL_R.SLICEL_X1.BLUT.INIT[03] 27_30
CLBLL_R.SLICEL_X1.BLUT.INIT[04] 26_29
CLBLL_R.SLICEL_X1.BLUT.INIT[05] 27_29
CLBLL_R.SLICEL_X1.BLUT.INIT[06] 26_28
CLBLL_R.SLICEL_X1.BLUT.INIT[07] 27_28
CLBLL_R.SLICEL_X1.BLUT.INIT[08] 29_31
CLBLL_R.SLICEL_X1.BLUT.INIT[09] 28_31
CLBLL_R.SLICEL_X1.BLUT.INIT[10] 29_30
CLBLL_R.SLICEL_X1.BLUT.INIT[11] 28_30
CLBLL_R.SLICEL_X1.BLUT.INIT[12] 29_29
CLBLL_R.SLICEL_X1.BLUT.INIT[13] 28_29
CLBLL_R.SLICEL_X1.BLUT.INIT[14] 29_28
CLBLL_R.SLICEL_X1.BLUT.INIT[15] 28_28
CLBLL_R.SLICEL_X1.BLUT.INIT[16] 26_27
CLBLL_R.SLICEL_X1.BLUT.INIT[17] 27_27
CLBLL_R.SLICEL_X1.BLUT.INIT[18] 26_26
CLBLL_R.SLICEL_X1.BLUT.INIT[19] 27_26
CLBLL_R.SLICEL_X1.BLUT.INIT[20] 26_25
CLBLL_R.SLICEL_X1.BLUT.INIT[21] 27_25
CLBLL_R.SLICEL_X1.BLUT.INIT[22] 26_24
CLBLL_R.SLICEL_X1.BLUT.INIT[23] 27_24
CLBLL_R.SLICEL_X1.BLUT.INIT[24] 29_27
CLBLL_R.SLICEL_X1.BLUT.INIT[25] 28_27
CLBLL_R.SLICEL_X1.BLUT.INIT[26] 29_26
CLBLL_R.SLICEL_X1.BLUT.INIT[27] 28_26
CLBLL_R.SLICEL_X1.BLUT.INIT[28] 29_25
CLBLL_R.SLICEL_X1.BLUT.INIT[29] 28_25
CLBLL_R.SLICEL_X1.BLUT.INIT[30] 29_24
CLBLL_R.SLICEL_X1.BLUT.INIT[31] 28_24
CLBLL_R.SLICEL_X1.BLUT.INIT[32] 26_23
CLBLL_R.SLICEL_X1.BLUT.INIT[33] 27_23
CLBLL_R.SLICEL_X1.BLUT.INIT[34] 26_22
CLBLL_R.SLICEL_X1.BLUT.INIT[35] 27_22
CLBLL_R.SLICEL_X1.BLUT.INIT[36] 26_21
CLBLL_R.SLICEL_X1.BLUT.INIT[37] 27_21
CLBLL_R.SLICEL_X1.BLUT.INIT[38] 26_20
CLBLL_R.SLICEL_X1.BLUT.INIT[39] 27_20
CLBLL_R.SLICEL_X1.BLUT.INIT[40] 29_23
CLBLL_R.SLICEL_X1.BLUT.INIT[41] 28_23
CLBLL_R.SLICEL_X1.BLUT.INIT[42] 29_22
CLBLL_R.SLICEL_X1.BLUT.INIT[43] 28_22
CLBLL_R.SLICEL_X1.BLUT.INIT[44] 29_21
CLBLL_R.SLICEL_X1.BLUT.INIT[45] 28_21
CLBLL_R.SLICEL_X1.BLUT.INIT[46] 29_20
CLBLL_R.SLICEL_X1.BLUT.INIT[47] 28_20
CLBLL_R.SLICEL_X1.BLUT.INIT[48] 26_19
CLBLL_R.SLICEL_X1.BLUT.INIT[49] 27_19
CLBLL_R.SLICEL_X1.BLUT.INIT[50] 26_18
CLBLL_R.SLICEL_X1.BLUT.INIT[51] 27_18
CLBLL_R.SLICEL_X1.BLUT.INIT[52] 26_17
CLBLL_R.SLICEL_X1.BLUT.INIT[53] 27_17
CLBLL_R.SLICEL_X1.BLUT.INIT[54] 26_16
CLBLL_R.SLICEL_X1.BLUT.INIT[55] 27_16
CLBLL_R.SLICEL_X1.BLUT.INIT[56] 29_19
CLBLL_R.SLICEL_X1.BLUT.INIT[57] 28_19
CLBLL_R.SLICEL_X1.BLUT.INIT[58] 29_18
CLBLL_R.SLICEL_X1.BLUT.INIT[59] 28_18
CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_R.SLICEL_X1.CLKINV 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
CLBLL_R.SLICEL_X1.CLUT.INIT[02] 26_46
CLBLL_R.SLICEL_X1.CLUT.INIT[03] 27_46
CLBLL_R.SLICEL_X1.CLUT.INIT[04] 26_45
CLBLL_R.SLICEL_X1.CLUT.INIT[05] 27_45
CLBLL_R.SLICEL_X1.CLUT.INIT[06] 26_44
CLBLL_R.SLICEL_X1.CLUT.INIT[07] 27_44
CLBLL_R.SLICEL_X1.CLUT.INIT[08] 29_47
CLBLL_R.SLICEL_X1.CLUT.INIT[09] 28_47
CLBLL_R.SLICEL_X1.CLUT.INIT[10] 29_46
CLBLL_R.SLICEL_X1.CLUT.INIT[11] 28_46
CLBLL_R.SLICEL_X1.CLUT.INIT[12] 29_45
CLBLL_R.SLICEL_X1.CLUT.INIT[13] 28_45
CLBLL_R.SLICEL_X1.CLUT.INIT[14] 29_44
CLBLL_R.SLICEL_X1.CLUT.INIT[15] 28_44
CLBLL_R.SLICEL_X1.CLUT.INIT[16] 26_43
CLBLL_R.SLICEL_X1.CLUT.INIT[17] 27_43
CLBLL_R.SLICEL_X1.CLUT.INIT[18] 26_42
CLBLL_R.SLICEL_X1.CLUT.INIT[19] 27_42
CLBLL_R.SLICEL_X1.CLUT.INIT[20] 26_41
CLBLL_R.SLICEL_X1.CLUT.INIT[21] 27_41
CLBLL_R.SLICEL_X1.CLUT.INIT[22] 26_40
CLBLL_R.SLICEL_X1.CLUT.INIT[23] 27_40
CLBLL_R.SLICEL_X1.CLUT.INIT[24] 29_43
CLBLL_R.SLICEL_X1.CLUT.INIT[25] 28_43
CLBLL_R.SLICEL_X1.CLUT.INIT[26] 29_42
CLBLL_R.SLICEL_X1.CLUT.INIT[27] 28_42
CLBLL_R.SLICEL_X1.CLUT.INIT[28] 29_41
CLBLL_R.SLICEL_X1.CLUT.INIT[29] 28_41
CLBLL_R.SLICEL_X1.CLUT.INIT[30] 29_40
CLBLL_R.SLICEL_X1.CLUT.INIT[31] 28_40
CLBLL_R.SLICEL_X1.CLUT.INIT[32] 26_39
CLBLL_R.SLICEL_X1.CLUT.INIT[33] 27_39
CLBLL_R.SLICEL_X1.CLUT.INIT[34] 26_38
CLBLL_R.SLICEL_X1.CLUT.INIT[35] 27_38
CLBLL_R.SLICEL_X1.CLUT.INIT[36] 26_37
CLBLL_R.SLICEL_X1.CLUT.INIT[37] 27_37
CLBLL_R.SLICEL_X1.CLUT.INIT[38] 26_36
CLBLL_R.SLICEL_X1.CLUT.INIT[39] 27_36
CLBLL_R.SLICEL_X1.CLUT.INIT[40] 29_39
CLBLL_R.SLICEL_X1.CLUT.INIT[41] 28_39
CLBLL_R.SLICEL_X1.CLUT.INIT[42] 29_38
CLBLL_R.SLICEL_X1.CLUT.INIT[43] 28_38
CLBLL_R.SLICEL_X1.CLUT.INIT[44] 29_37
CLBLL_R.SLICEL_X1.CLUT.INIT[45] 28_37
CLBLL_R.SLICEL_X1.CLUT.INIT[46] 29_36
CLBLL_R.SLICEL_X1.CLUT.INIT[47] 28_36
CLBLL_R.SLICEL_X1.CLUT.INIT[48] 26_35
CLBLL_R.SLICEL_X1.CLUT.INIT[49] 27_35
CLBLL_R.SLICEL_X1.CLUT.INIT[50] 26_34
CLBLL_R.SLICEL_X1.CLUT.INIT[51] 27_34
CLBLL_R.SLICEL_X1.CLUT.INIT[52] 26_33
CLBLL_R.SLICEL_X1.CLUT.INIT[53] 27_33
CLBLL_R.SLICEL_X1.CLUT.INIT[54] 26_32
CLBLL_R.SLICEL_X1.CLUT.INIT[55] 27_32
CLBLL_R.SLICEL_X1.CLUT.INIT[56] 29_35
CLBLL_R.SLICEL_X1.CLUT.INIT[57] 28_35
CLBLL_R.SLICEL_X1.CLUT.INIT[58] 29_34
CLBLL_R.SLICEL_X1.CLUT.INIT[59] 28_34
CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
CLBLL_R.SLICEL_X1.DLUT.INIT[03] 27_62
CLBLL_R.SLICEL_X1.DLUT.INIT[04] 26_61
CLBLL_R.SLICEL_X1.DLUT.INIT[05] 27_61
CLBLL_R.SLICEL_X1.DLUT.INIT[06] 26_60
CLBLL_R.SLICEL_X1.DLUT.INIT[07] 27_60
CLBLL_R.SLICEL_X1.DLUT.INIT[08] 29_63
CLBLL_R.SLICEL_X1.DLUT.INIT[09] 28_63
CLBLL_R.SLICEL_X1.DLUT.INIT[10] 29_62
CLBLL_R.SLICEL_X1.DLUT.INIT[11] 28_62
CLBLL_R.SLICEL_X1.DLUT.INIT[12] 29_61
CLBLL_R.SLICEL_X1.DLUT.INIT[13] 28_61
CLBLL_R.SLICEL_X1.DLUT.INIT[14] 29_60
CLBLL_R.SLICEL_X1.DLUT.INIT[15] 28_60
CLBLL_R.SLICEL_X1.DLUT.INIT[16] 26_59
CLBLL_R.SLICEL_X1.DLUT.INIT[17] 27_59
CLBLL_R.SLICEL_X1.DLUT.INIT[18] 26_58
CLBLL_R.SLICEL_X1.DLUT.INIT[19] 27_58
CLBLL_R.SLICEL_X1.DLUT.INIT[20] 26_57
CLBLL_R.SLICEL_X1.DLUT.INIT[21] 27_57
CLBLL_R.SLICEL_X1.DLUT.INIT[22] 26_56
CLBLL_R.SLICEL_X1.DLUT.INIT[23] 27_56
CLBLL_R.SLICEL_X1.DLUT.INIT[24] 29_59
CLBLL_R.SLICEL_X1.DLUT.INIT[25] 28_59
CLBLL_R.SLICEL_X1.DLUT.INIT[26] 29_58
CLBLL_R.SLICEL_X1.DLUT.INIT[27] 28_58
CLBLL_R.SLICEL_X1.DLUT.INIT[28] 29_57
CLBLL_R.SLICEL_X1.DLUT.INIT[29] 28_57
CLBLL_R.SLICEL_X1.DLUT.INIT[30] 29_56
CLBLL_R.SLICEL_X1.DLUT.INIT[31] 28_56
CLBLL_R.SLICEL_X1.DLUT.INIT[32] 26_55
CLBLL_R.SLICEL_X1.DLUT.INIT[33] 27_55
CLBLL_R.SLICEL_X1.DLUT.INIT[34] 26_54
CLBLL_R.SLICEL_X1.DLUT.INIT[35] 27_54
CLBLL_R.SLICEL_X1.DLUT.INIT[36] 26_53
CLBLL_R.SLICEL_X1.DLUT.INIT[37] 27_53
CLBLL_R.SLICEL_X1.DLUT.INIT[38] 26_52
CLBLL_R.SLICEL_X1.DLUT.INIT[39] 27_52
CLBLL_R.SLICEL_X1.DLUT.INIT[40] 29_55
CLBLL_R.SLICEL_X1.DLUT.INIT[41] 28_55
CLBLL_R.SLICEL_X1.DLUT.INIT[42] 29_54
CLBLL_R.SLICEL_X1.DLUT.INIT[43] 28_54
CLBLL_R.SLICEL_X1.DLUT.INIT[44] 29_53
CLBLL_R.SLICEL_X1.DLUT.INIT[45] 28_53
CLBLL_R.SLICEL_X1.DLUT.INIT[46] 29_52
CLBLL_R.SLICEL_X1.DLUT.INIT[47] 28_52
CLBLL_R.SLICEL_X1.DLUT.INIT[48] 26_51
CLBLL_R.SLICEL_X1.DLUT.INIT[49] 27_51
CLBLL_R.SLICEL_X1.DLUT.INIT[50] 26_50
CLBLL_R.SLICEL_X1.DLUT.INIT[51] 27_50
CLBLL_R.SLICEL_X1.DLUT.INIT[52] 26_49
CLBLL_R.SLICEL_X1.DLUT.INIT[53] 27_49
CLBLL_R.SLICEL_X1.DLUT.INIT[54] 26_48
CLBLL_R.SLICEL_X1.DLUT.INIT[55] 27_48
CLBLL_R.SLICEL_X1.DLUT.INIT[56] 29_51
CLBLL_R.SLICEL_X1.DLUT.INIT[57] 28_51
CLBLL_R.SLICEL_X1.DLUT.INIT[58] 29_50
CLBLL_R.SLICEL_X1.DLUT.INIT[59] 28_50
CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49

696
zynq7/segbits_clblm_l.db Normal file
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@ -0,0 +1,696 @@
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
CLBLM_L.SLICEL_X1.ALUT.INIT[03] 27_14
CLBLM_L.SLICEL_X1.ALUT.INIT[04] 26_13
CLBLM_L.SLICEL_X1.ALUT.INIT[05] 27_13
CLBLM_L.SLICEL_X1.ALUT.INIT[06] 26_12
CLBLM_L.SLICEL_X1.ALUT.INIT[07] 27_12
CLBLM_L.SLICEL_X1.ALUT.INIT[08] 29_15
CLBLM_L.SLICEL_X1.ALUT.INIT[09] 28_15
CLBLM_L.SLICEL_X1.ALUT.INIT[10] 29_14
CLBLM_L.SLICEL_X1.ALUT.INIT[11] 28_14
CLBLM_L.SLICEL_X1.ALUT.INIT[12] 29_13
CLBLM_L.SLICEL_X1.ALUT.INIT[13] 28_13
CLBLM_L.SLICEL_X1.ALUT.INIT[14] 29_12
CLBLM_L.SLICEL_X1.ALUT.INIT[15] 28_12
CLBLM_L.SLICEL_X1.ALUT.INIT[16] 26_11
CLBLM_L.SLICEL_X1.ALUT.INIT[17] 27_11
CLBLM_L.SLICEL_X1.ALUT.INIT[18] 26_10
CLBLM_L.SLICEL_X1.ALUT.INIT[19] 27_10
CLBLM_L.SLICEL_X1.ALUT.INIT[20] 26_09
CLBLM_L.SLICEL_X1.ALUT.INIT[21] 27_09
CLBLM_L.SLICEL_X1.ALUT.INIT[22] 26_08
CLBLM_L.SLICEL_X1.ALUT.INIT[23] 27_08
CLBLM_L.SLICEL_X1.ALUT.INIT[24] 29_11
CLBLM_L.SLICEL_X1.ALUT.INIT[25] 28_11
CLBLM_L.SLICEL_X1.ALUT.INIT[26] 29_10
CLBLM_L.SLICEL_X1.ALUT.INIT[27] 28_10
CLBLM_L.SLICEL_X1.ALUT.INIT[28] 29_09
CLBLM_L.SLICEL_X1.ALUT.INIT[29] 28_09
CLBLM_L.SLICEL_X1.ALUT.INIT[30] 29_08
CLBLM_L.SLICEL_X1.ALUT.INIT[31] 28_08
CLBLM_L.SLICEL_X1.ALUT.INIT[32] 26_07
CLBLM_L.SLICEL_X1.ALUT.INIT[33] 27_07
CLBLM_L.SLICEL_X1.ALUT.INIT[34] 26_06
CLBLM_L.SLICEL_X1.ALUT.INIT[35] 27_06
CLBLM_L.SLICEL_X1.ALUT.INIT[36] 26_05
CLBLM_L.SLICEL_X1.ALUT.INIT[37] 27_05
CLBLM_L.SLICEL_X1.ALUT.INIT[38] 26_04
CLBLM_L.SLICEL_X1.ALUT.INIT[39] 27_04
CLBLM_L.SLICEL_X1.ALUT.INIT[40] 29_07
CLBLM_L.SLICEL_X1.ALUT.INIT[41] 28_07
CLBLM_L.SLICEL_X1.ALUT.INIT[42] 29_06
CLBLM_L.SLICEL_X1.ALUT.INIT[43] 28_06
CLBLM_L.SLICEL_X1.ALUT.INIT[44] 29_05
CLBLM_L.SLICEL_X1.ALUT.INIT[45] 28_05
CLBLM_L.SLICEL_X1.ALUT.INIT[46] 29_04
CLBLM_L.SLICEL_X1.ALUT.INIT[47] 28_04
CLBLM_L.SLICEL_X1.ALUT.INIT[48] 26_03
CLBLM_L.SLICEL_X1.ALUT.INIT[49] 27_03
CLBLM_L.SLICEL_X1.ALUT.INIT[50] 26_02
CLBLM_L.SLICEL_X1.ALUT.INIT[51] 27_02
CLBLM_L.SLICEL_X1.ALUT.INIT[52] 26_01
CLBLM_L.SLICEL_X1.ALUT.INIT[53] 27_01
CLBLM_L.SLICEL_X1.ALUT.INIT[54] 26_00
CLBLM_L.SLICEL_X1.ALUT.INIT[55] 27_00
CLBLM_L.SLICEL_X1.ALUT.INIT[56] 29_03
CLBLM_L.SLICEL_X1.ALUT.INIT[57] 28_03
CLBLM_L.SLICEL_X1.ALUT.INIT[58] 29_02
CLBLM_L.SLICEL_X1.ALUT.INIT[59] 28_02
CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
CLBLM_L.SLICEL_X1.BLUT.INIT[03] 27_30
CLBLM_L.SLICEL_X1.BLUT.INIT[04] 26_29
CLBLM_L.SLICEL_X1.BLUT.INIT[05] 27_29
CLBLM_L.SLICEL_X1.BLUT.INIT[06] 26_28
CLBLM_L.SLICEL_X1.BLUT.INIT[07] 27_28
CLBLM_L.SLICEL_X1.BLUT.INIT[08] 29_31
CLBLM_L.SLICEL_X1.BLUT.INIT[09] 28_31
CLBLM_L.SLICEL_X1.BLUT.INIT[10] 29_30
CLBLM_L.SLICEL_X1.BLUT.INIT[11] 28_30
CLBLM_L.SLICEL_X1.BLUT.INIT[12] 29_29
CLBLM_L.SLICEL_X1.BLUT.INIT[13] 28_29
CLBLM_L.SLICEL_X1.BLUT.INIT[14] 29_28
CLBLM_L.SLICEL_X1.BLUT.INIT[15] 28_28
CLBLM_L.SLICEL_X1.BLUT.INIT[16] 26_27
CLBLM_L.SLICEL_X1.BLUT.INIT[17] 27_27
CLBLM_L.SLICEL_X1.BLUT.INIT[18] 26_26
CLBLM_L.SLICEL_X1.BLUT.INIT[19] 27_26
CLBLM_L.SLICEL_X1.BLUT.INIT[20] 26_25
CLBLM_L.SLICEL_X1.BLUT.INIT[21] 27_25
CLBLM_L.SLICEL_X1.BLUT.INIT[22] 26_24
CLBLM_L.SLICEL_X1.BLUT.INIT[23] 27_24
CLBLM_L.SLICEL_X1.BLUT.INIT[24] 29_27
CLBLM_L.SLICEL_X1.BLUT.INIT[25] 28_27
CLBLM_L.SLICEL_X1.BLUT.INIT[26] 29_26
CLBLM_L.SLICEL_X1.BLUT.INIT[27] 28_26
CLBLM_L.SLICEL_X1.BLUT.INIT[28] 29_25
CLBLM_L.SLICEL_X1.BLUT.INIT[29] 28_25
CLBLM_L.SLICEL_X1.BLUT.INIT[30] 29_24
CLBLM_L.SLICEL_X1.BLUT.INIT[31] 28_24
CLBLM_L.SLICEL_X1.BLUT.INIT[32] 26_23
CLBLM_L.SLICEL_X1.BLUT.INIT[33] 27_23
CLBLM_L.SLICEL_X1.BLUT.INIT[34] 26_22
CLBLM_L.SLICEL_X1.BLUT.INIT[35] 27_22
CLBLM_L.SLICEL_X1.BLUT.INIT[36] 26_21
CLBLM_L.SLICEL_X1.BLUT.INIT[37] 27_21
CLBLM_L.SLICEL_X1.BLUT.INIT[38] 26_20
CLBLM_L.SLICEL_X1.BLUT.INIT[39] 27_20
CLBLM_L.SLICEL_X1.BLUT.INIT[40] 29_23
CLBLM_L.SLICEL_X1.BLUT.INIT[41] 28_23
CLBLM_L.SLICEL_X1.BLUT.INIT[42] 29_22
CLBLM_L.SLICEL_X1.BLUT.INIT[43] 28_22
CLBLM_L.SLICEL_X1.BLUT.INIT[44] 29_21
CLBLM_L.SLICEL_X1.BLUT.INIT[45] 28_21
CLBLM_L.SLICEL_X1.BLUT.INIT[46] 29_20
CLBLM_L.SLICEL_X1.BLUT.INIT[47] 28_20
CLBLM_L.SLICEL_X1.BLUT.INIT[48] 26_19
CLBLM_L.SLICEL_X1.BLUT.INIT[49] 27_19
CLBLM_L.SLICEL_X1.BLUT.INIT[50] 26_18
CLBLM_L.SLICEL_X1.BLUT.INIT[51] 27_18
CLBLM_L.SLICEL_X1.BLUT.INIT[52] 26_17
CLBLM_L.SLICEL_X1.BLUT.INIT[53] 27_17
CLBLM_L.SLICEL_X1.BLUT.INIT[54] 26_16
CLBLM_L.SLICEL_X1.BLUT.INIT[55] 27_16
CLBLM_L.SLICEL_X1.BLUT.INIT[56] 29_19
CLBLM_L.SLICEL_X1.BLUT.INIT[57] 28_19
CLBLM_L.SLICEL_X1.BLUT.INIT[58] 29_18
CLBLM_L.SLICEL_X1.BLUT.INIT[59] 28_18
CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_L.SLICEL_X1.CLKINV 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
CLBLM_L.SLICEL_X1.CLUT.INIT[02] 26_46
CLBLM_L.SLICEL_X1.CLUT.INIT[03] 27_46
CLBLM_L.SLICEL_X1.CLUT.INIT[04] 26_45
CLBLM_L.SLICEL_X1.CLUT.INIT[05] 27_45
CLBLM_L.SLICEL_X1.CLUT.INIT[06] 26_44
CLBLM_L.SLICEL_X1.CLUT.INIT[07] 27_44
CLBLM_L.SLICEL_X1.CLUT.INIT[08] 29_47
CLBLM_L.SLICEL_X1.CLUT.INIT[09] 28_47
CLBLM_L.SLICEL_X1.CLUT.INIT[10] 29_46
CLBLM_L.SLICEL_X1.CLUT.INIT[11] 28_46
CLBLM_L.SLICEL_X1.CLUT.INIT[12] 29_45
CLBLM_L.SLICEL_X1.CLUT.INIT[13] 28_45
CLBLM_L.SLICEL_X1.CLUT.INIT[14] 29_44
CLBLM_L.SLICEL_X1.CLUT.INIT[15] 28_44
CLBLM_L.SLICEL_X1.CLUT.INIT[16] 26_43
CLBLM_L.SLICEL_X1.CLUT.INIT[17] 27_43
CLBLM_L.SLICEL_X1.CLUT.INIT[18] 26_42
CLBLM_L.SLICEL_X1.CLUT.INIT[19] 27_42
CLBLM_L.SLICEL_X1.CLUT.INIT[20] 26_41
CLBLM_L.SLICEL_X1.CLUT.INIT[21] 27_41
CLBLM_L.SLICEL_X1.CLUT.INIT[22] 26_40
CLBLM_L.SLICEL_X1.CLUT.INIT[23] 27_40
CLBLM_L.SLICEL_X1.CLUT.INIT[24] 29_43
CLBLM_L.SLICEL_X1.CLUT.INIT[25] 28_43
CLBLM_L.SLICEL_X1.CLUT.INIT[26] 29_42
CLBLM_L.SLICEL_X1.CLUT.INIT[27] 28_42
CLBLM_L.SLICEL_X1.CLUT.INIT[28] 29_41
CLBLM_L.SLICEL_X1.CLUT.INIT[29] 28_41
CLBLM_L.SLICEL_X1.CLUT.INIT[30] 29_40
CLBLM_L.SLICEL_X1.CLUT.INIT[31] 28_40
CLBLM_L.SLICEL_X1.CLUT.INIT[32] 26_39
CLBLM_L.SLICEL_X1.CLUT.INIT[33] 27_39
CLBLM_L.SLICEL_X1.CLUT.INIT[34] 26_38
CLBLM_L.SLICEL_X1.CLUT.INIT[35] 27_38
CLBLM_L.SLICEL_X1.CLUT.INIT[36] 26_37
CLBLM_L.SLICEL_X1.CLUT.INIT[37] 27_37
CLBLM_L.SLICEL_X1.CLUT.INIT[38] 26_36
CLBLM_L.SLICEL_X1.CLUT.INIT[39] 27_36
CLBLM_L.SLICEL_X1.CLUT.INIT[40] 29_39
CLBLM_L.SLICEL_X1.CLUT.INIT[41] 28_39
CLBLM_L.SLICEL_X1.CLUT.INIT[42] 29_38
CLBLM_L.SLICEL_X1.CLUT.INIT[43] 28_38
CLBLM_L.SLICEL_X1.CLUT.INIT[44] 29_37
CLBLM_L.SLICEL_X1.CLUT.INIT[45] 28_37
CLBLM_L.SLICEL_X1.CLUT.INIT[46] 29_36
CLBLM_L.SLICEL_X1.CLUT.INIT[47] 28_36
CLBLM_L.SLICEL_X1.CLUT.INIT[48] 26_35
CLBLM_L.SLICEL_X1.CLUT.INIT[49] 27_35
CLBLM_L.SLICEL_X1.CLUT.INIT[50] 26_34
CLBLM_L.SLICEL_X1.CLUT.INIT[51] 27_34
CLBLM_L.SLICEL_X1.CLUT.INIT[52] 26_33
CLBLM_L.SLICEL_X1.CLUT.INIT[53] 27_33
CLBLM_L.SLICEL_X1.CLUT.INIT[54] 26_32
CLBLM_L.SLICEL_X1.CLUT.INIT[55] 27_32
CLBLM_L.SLICEL_X1.CLUT.INIT[56] 29_35
CLBLM_L.SLICEL_X1.CLUT.INIT[57] 28_35
CLBLM_L.SLICEL_X1.CLUT.INIT[58] 29_34
CLBLM_L.SLICEL_X1.CLUT.INIT[59] 28_34
CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
CLBLM_L.SLICEL_X1.DLUT.INIT[03] 27_62
CLBLM_L.SLICEL_X1.DLUT.INIT[04] 26_61
CLBLM_L.SLICEL_X1.DLUT.INIT[05] 27_61
CLBLM_L.SLICEL_X1.DLUT.INIT[06] 26_60
CLBLM_L.SLICEL_X1.DLUT.INIT[07] 27_60
CLBLM_L.SLICEL_X1.DLUT.INIT[08] 29_63
CLBLM_L.SLICEL_X1.DLUT.INIT[09] 28_63
CLBLM_L.SLICEL_X1.DLUT.INIT[10] 29_62
CLBLM_L.SLICEL_X1.DLUT.INIT[11] 28_62
CLBLM_L.SLICEL_X1.DLUT.INIT[12] 29_61
CLBLM_L.SLICEL_X1.DLUT.INIT[13] 28_61
CLBLM_L.SLICEL_X1.DLUT.INIT[14] 29_60
CLBLM_L.SLICEL_X1.DLUT.INIT[15] 28_60
CLBLM_L.SLICEL_X1.DLUT.INIT[16] 26_59
CLBLM_L.SLICEL_X1.DLUT.INIT[17] 27_59
CLBLM_L.SLICEL_X1.DLUT.INIT[18] 26_58
CLBLM_L.SLICEL_X1.DLUT.INIT[19] 27_58
CLBLM_L.SLICEL_X1.DLUT.INIT[20] 26_57
CLBLM_L.SLICEL_X1.DLUT.INIT[21] 27_57
CLBLM_L.SLICEL_X1.DLUT.INIT[22] 26_56
CLBLM_L.SLICEL_X1.DLUT.INIT[23] 27_56
CLBLM_L.SLICEL_X1.DLUT.INIT[24] 29_59
CLBLM_L.SLICEL_X1.DLUT.INIT[25] 28_59
CLBLM_L.SLICEL_X1.DLUT.INIT[26] 29_58
CLBLM_L.SLICEL_X1.DLUT.INIT[27] 28_58
CLBLM_L.SLICEL_X1.DLUT.INIT[28] 29_57
CLBLM_L.SLICEL_X1.DLUT.INIT[29] 28_57
CLBLM_L.SLICEL_X1.DLUT.INIT[30] 29_56
CLBLM_L.SLICEL_X1.DLUT.INIT[31] 28_56
CLBLM_L.SLICEL_X1.DLUT.INIT[32] 26_55
CLBLM_L.SLICEL_X1.DLUT.INIT[33] 27_55
CLBLM_L.SLICEL_X1.DLUT.INIT[34] 26_54
CLBLM_L.SLICEL_X1.DLUT.INIT[35] 27_54
CLBLM_L.SLICEL_X1.DLUT.INIT[36] 26_53
CLBLM_L.SLICEL_X1.DLUT.INIT[37] 27_53
CLBLM_L.SLICEL_X1.DLUT.INIT[38] 26_52
CLBLM_L.SLICEL_X1.DLUT.INIT[39] 27_52
CLBLM_L.SLICEL_X1.DLUT.INIT[40] 29_55
CLBLM_L.SLICEL_X1.DLUT.INIT[41] 28_55
CLBLM_L.SLICEL_X1.DLUT.INIT[42] 29_54
CLBLM_L.SLICEL_X1.DLUT.INIT[43] 28_54
CLBLM_L.SLICEL_X1.DLUT.INIT[44] 29_53
CLBLM_L.SLICEL_X1.DLUT.INIT[45] 28_53
CLBLM_L.SLICEL_X1.DLUT.INIT[46] 29_52
CLBLM_L.SLICEL_X1.DLUT.INIT[47] 28_52
CLBLM_L.SLICEL_X1.DLUT.INIT[48] 26_51
CLBLM_L.SLICEL_X1.DLUT.INIT[49] 27_51
CLBLM_L.SLICEL_X1.DLUT.INIT[50] 26_50
CLBLM_L.SLICEL_X1.DLUT.INIT[51] 27_50
CLBLM_L.SLICEL_X1.DLUT.INIT[52] 26_49
CLBLM_L.SLICEL_X1.DLUT.INIT[53] 27_49
CLBLM_L.SLICEL_X1.DLUT.INIT[54] 26_48
CLBLM_L.SLICEL_X1.DLUT.INIT[55] 27_48
CLBLM_L.SLICEL_X1.DLUT.INIT[56] 29_51
CLBLM_L.SLICEL_X1.DLUT.INIT[57] 28_51
CLBLM_L.SLICEL_X1.DLUT.INIT[58] 29_50
CLBLM_L.SLICEL_X1.DLUT.INIT[59] 28_50
CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
CLBLM_L.SLICEM_X0.ALUT.INIT[03] 35_14
CLBLM_L.SLICEM_X0.ALUT.INIT[04] 34_13
CLBLM_L.SLICEM_X0.ALUT.INIT[05] 35_13
CLBLM_L.SLICEM_X0.ALUT.INIT[06] 34_12
CLBLM_L.SLICEM_X0.ALUT.INIT[07] 35_12
CLBLM_L.SLICEM_X0.ALUT.INIT[08] 32_15
CLBLM_L.SLICEM_X0.ALUT.INIT[09] 33_15
CLBLM_L.SLICEM_X0.ALUT.INIT[10] 32_14
CLBLM_L.SLICEM_X0.ALUT.INIT[11] 33_14
CLBLM_L.SLICEM_X0.ALUT.INIT[12] 32_13
CLBLM_L.SLICEM_X0.ALUT.INIT[13] 33_13
CLBLM_L.SLICEM_X0.ALUT.INIT[14] 32_12
CLBLM_L.SLICEM_X0.ALUT.INIT[15] 33_12
CLBLM_L.SLICEM_X0.ALUT.INIT[16] 34_11
CLBLM_L.SLICEM_X0.ALUT.INIT[17] 35_11
CLBLM_L.SLICEM_X0.ALUT.INIT[18] 34_10
CLBLM_L.SLICEM_X0.ALUT.INIT[19] 35_10
CLBLM_L.SLICEM_X0.ALUT.INIT[20] 34_09
CLBLM_L.SLICEM_X0.ALUT.INIT[21] 35_09
CLBLM_L.SLICEM_X0.ALUT.INIT[22] 34_08
CLBLM_L.SLICEM_X0.ALUT.INIT[23] 35_08
CLBLM_L.SLICEM_X0.ALUT.INIT[24] 32_11
CLBLM_L.SLICEM_X0.ALUT.INIT[25] 33_11
CLBLM_L.SLICEM_X0.ALUT.INIT[26] 32_10
CLBLM_L.SLICEM_X0.ALUT.INIT[27] 33_10
CLBLM_L.SLICEM_X0.ALUT.INIT[28] 32_09
CLBLM_L.SLICEM_X0.ALUT.INIT[29] 33_09
CLBLM_L.SLICEM_X0.ALUT.INIT[30] 32_08
CLBLM_L.SLICEM_X0.ALUT.INIT[31] 33_08
CLBLM_L.SLICEM_X0.ALUT.INIT[32] 34_07
CLBLM_L.SLICEM_X0.ALUT.INIT[33] 35_07
CLBLM_L.SLICEM_X0.ALUT.INIT[34] 34_06
CLBLM_L.SLICEM_X0.ALUT.INIT[35] 35_06
CLBLM_L.SLICEM_X0.ALUT.INIT[36] 34_05
CLBLM_L.SLICEM_X0.ALUT.INIT[37] 35_05
CLBLM_L.SLICEM_X0.ALUT.INIT[38] 34_04
CLBLM_L.SLICEM_X0.ALUT.INIT[39] 35_04
CLBLM_L.SLICEM_X0.ALUT.INIT[40] 32_07
CLBLM_L.SLICEM_X0.ALUT.INIT[41] 33_07
CLBLM_L.SLICEM_X0.ALUT.INIT[42] 32_06
CLBLM_L.SLICEM_X0.ALUT.INIT[43] 33_06
CLBLM_L.SLICEM_X0.ALUT.INIT[44] 32_05
CLBLM_L.SLICEM_X0.ALUT.INIT[45] 33_05
CLBLM_L.SLICEM_X0.ALUT.INIT[46] 32_04
CLBLM_L.SLICEM_X0.ALUT.INIT[47] 33_04
CLBLM_L.SLICEM_X0.ALUT.INIT[48] 34_03
CLBLM_L.SLICEM_X0.ALUT.INIT[49] 35_03
CLBLM_L.SLICEM_X0.ALUT.INIT[50] 34_02
CLBLM_L.SLICEM_X0.ALUT.INIT[51] 35_02
CLBLM_L.SLICEM_X0.ALUT.INIT[52] 34_01
CLBLM_L.SLICEM_X0.ALUT.INIT[53] 35_01
CLBLM_L.SLICEM_X0.ALUT.INIT[54] 34_00
CLBLM_L.SLICEM_X0.ALUT.INIT[55] 35_00
CLBLM_L.SLICEM_X0.ALUT.INIT[56] 32_03
CLBLM_L.SLICEM_X0.ALUT.INIT[57] 33_03
CLBLM_L.SLICEM_X0.ALUT.INIT[58] 32_02
CLBLM_L.SLICEM_X0.ALUT.INIT[59] 33_02
CLBLM_L.SLICEM_X0.ALUT.INIT[60] 32_01
CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
CLBLM_L.SLICEM_X0.BLUT.INIT[03] 35_30
CLBLM_L.SLICEM_X0.BLUT.INIT[04] 34_29
CLBLM_L.SLICEM_X0.BLUT.INIT[05] 35_29
CLBLM_L.SLICEM_X0.BLUT.INIT[06] 34_28
CLBLM_L.SLICEM_X0.BLUT.INIT[07] 35_28
CLBLM_L.SLICEM_X0.BLUT.INIT[08] 32_31
CLBLM_L.SLICEM_X0.BLUT.INIT[09] 33_31
CLBLM_L.SLICEM_X0.BLUT.INIT[10] 32_30
CLBLM_L.SLICEM_X0.BLUT.INIT[11] 33_30
CLBLM_L.SLICEM_X0.BLUT.INIT[12] 32_29
CLBLM_L.SLICEM_X0.BLUT.INIT[13] 33_29
CLBLM_L.SLICEM_X0.BLUT.INIT[14] 32_28
CLBLM_L.SLICEM_X0.BLUT.INIT[15] 33_28
CLBLM_L.SLICEM_X0.BLUT.INIT[16] 34_27
CLBLM_L.SLICEM_X0.BLUT.INIT[17] 35_27
CLBLM_L.SLICEM_X0.BLUT.INIT[18] 34_26
CLBLM_L.SLICEM_X0.BLUT.INIT[19] 35_26
CLBLM_L.SLICEM_X0.BLUT.INIT[20] 34_25
CLBLM_L.SLICEM_X0.BLUT.INIT[21] 35_25
CLBLM_L.SLICEM_X0.BLUT.INIT[22] 34_24
CLBLM_L.SLICEM_X0.BLUT.INIT[23] 35_24
CLBLM_L.SLICEM_X0.BLUT.INIT[24] 32_27
CLBLM_L.SLICEM_X0.BLUT.INIT[25] 33_27
CLBLM_L.SLICEM_X0.BLUT.INIT[26] 32_26
CLBLM_L.SLICEM_X0.BLUT.INIT[27] 33_26
CLBLM_L.SLICEM_X0.BLUT.INIT[28] 32_25
CLBLM_L.SLICEM_X0.BLUT.INIT[29] 33_25
CLBLM_L.SLICEM_X0.BLUT.INIT[30] 32_24
CLBLM_L.SLICEM_X0.BLUT.INIT[31] 33_24
CLBLM_L.SLICEM_X0.BLUT.INIT[32] 34_23
CLBLM_L.SLICEM_X0.BLUT.INIT[33] 35_23
CLBLM_L.SLICEM_X0.BLUT.INIT[34] 34_22
CLBLM_L.SLICEM_X0.BLUT.INIT[35] 35_22
CLBLM_L.SLICEM_X0.BLUT.INIT[36] 34_21
CLBLM_L.SLICEM_X0.BLUT.INIT[37] 35_21
CLBLM_L.SLICEM_X0.BLUT.INIT[38] 34_20
CLBLM_L.SLICEM_X0.BLUT.INIT[39] 35_20
CLBLM_L.SLICEM_X0.BLUT.INIT[40] 32_23
CLBLM_L.SLICEM_X0.BLUT.INIT[41] 33_23
CLBLM_L.SLICEM_X0.BLUT.INIT[42] 32_22
CLBLM_L.SLICEM_X0.BLUT.INIT[43] 33_22
CLBLM_L.SLICEM_X0.BLUT.INIT[44] 32_21
CLBLM_L.SLICEM_X0.BLUT.INIT[45] 33_21
CLBLM_L.SLICEM_X0.BLUT.INIT[46] 32_20
CLBLM_L.SLICEM_X0.BLUT.INIT[47] 33_20
CLBLM_L.SLICEM_X0.BLUT.INIT[48] 34_19
CLBLM_L.SLICEM_X0.BLUT.INIT[49] 35_19
CLBLM_L.SLICEM_X0.BLUT.INIT[50] 34_18
CLBLM_L.SLICEM_X0.BLUT.INIT[51] 35_18
CLBLM_L.SLICEM_X0.BLUT.INIT[52] 34_17
CLBLM_L.SLICEM_X0.BLUT.INIT[53] 35_17
CLBLM_L.SLICEM_X0.BLUT.INIT[54] 34_16
CLBLM_L.SLICEM_X0.BLUT.INIT[55] 35_16
CLBLM_L.SLICEM_X0.BLUT.INIT[56] 32_19
CLBLM_L.SLICEM_X0.BLUT.INIT[57] 33_19
CLBLM_L.SLICEM_X0.BLUT.INIT[58] 32_18
CLBLM_L.SLICEM_X0.BLUT.INIT[59] 33_18
CLBLM_L.SLICEM_X0.BLUT.INIT[60] 32_17
CLBLM_L.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_L.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_L.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_L.SLICEM_X0.BLUT.RAM 31_17
CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
CLBLM_L.SLICEM_X0.CLUT.INIT[03] 35_46
CLBLM_L.SLICEM_X0.CLUT.INIT[04] 34_45
CLBLM_L.SLICEM_X0.CLUT.INIT[05] 35_45
CLBLM_L.SLICEM_X0.CLUT.INIT[06] 34_44
CLBLM_L.SLICEM_X0.CLUT.INIT[07] 35_44
CLBLM_L.SLICEM_X0.CLUT.INIT[08] 32_47
CLBLM_L.SLICEM_X0.CLUT.INIT[09] 33_47
CLBLM_L.SLICEM_X0.CLUT.INIT[10] 32_46
CLBLM_L.SLICEM_X0.CLUT.INIT[11] 33_46
CLBLM_L.SLICEM_X0.CLUT.INIT[12] 32_45
CLBLM_L.SLICEM_X0.CLUT.INIT[13] 33_45
CLBLM_L.SLICEM_X0.CLUT.INIT[14] 32_44
CLBLM_L.SLICEM_X0.CLUT.INIT[15] 33_44
CLBLM_L.SLICEM_X0.CLUT.INIT[16] 34_43
CLBLM_L.SLICEM_X0.CLUT.INIT[17] 35_43
CLBLM_L.SLICEM_X0.CLUT.INIT[18] 34_42
CLBLM_L.SLICEM_X0.CLUT.INIT[19] 35_42
CLBLM_L.SLICEM_X0.CLUT.INIT[20] 34_41
CLBLM_L.SLICEM_X0.CLUT.INIT[21] 35_41
CLBLM_L.SLICEM_X0.CLUT.INIT[22] 34_40
CLBLM_L.SLICEM_X0.CLUT.INIT[23] 35_40
CLBLM_L.SLICEM_X0.CLUT.INIT[24] 32_43
CLBLM_L.SLICEM_X0.CLUT.INIT[25] 33_43
CLBLM_L.SLICEM_X0.CLUT.INIT[26] 32_42
CLBLM_L.SLICEM_X0.CLUT.INIT[27] 33_42
CLBLM_L.SLICEM_X0.CLUT.INIT[28] 32_41
CLBLM_L.SLICEM_X0.CLUT.INIT[29] 33_41
CLBLM_L.SLICEM_X0.CLUT.INIT[30] 32_40
CLBLM_L.SLICEM_X0.CLUT.INIT[31] 33_40
CLBLM_L.SLICEM_X0.CLUT.INIT[32] 34_39
CLBLM_L.SLICEM_X0.CLUT.INIT[33] 35_39
CLBLM_L.SLICEM_X0.CLUT.INIT[34] 34_38
CLBLM_L.SLICEM_X0.CLUT.INIT[35] 35_38
CLBLM_L.SLICEM_X0.CLUT.INIT[36] 34_37
CLBLM_L.SLICEM_X0.CLUT.INIT[37] 35_37
CLBLM_L.SLICEM_X0.CLUT.INIT[38] 34_36
CLBLM_L.SLICEM_X0.CLUT.INIT[39] 35_36
CLBLM_L.SLICEM_X0.CLUT.INIT[40] 32_39
CLBLM_L.SLICEM_X0.CLUT.INIT[41] 33_39
CLBLM_L.SLICEM_X0.CLUT.INIT[42] 32_38
CLBLM_L.SLICEM_X0.CLUT.INIT[43] 33_38
CLBLM_L.SLICEM_X0.CLUT.INIT[44] 32_37
CLBLM_L.SLICEM_X0.CLUT.INIT[45] 33_37
CLBLM_L.SLICEM_X0.CLUT.INIT[46] 32_36
CLBLM_L.SLICEM_X0.CLUT.INIT[47] 33_36
CLBLM_L.SLICEM_X0.CLUT.INIT[48] 34_35
CLBLM_L.SLICEM_X0.CLUT.INIT[49] 35_35
CLBLM_L.SLICEM_X0.CLUT.INIT[50] 34_34
CLBLM_L.SLICEM_X0.CLUT.INIT[51] 35_34
CLBLM_L.SLICEM_X0.CLUT.INIT[52] 34_33
CLBLM_L.SLICEM_X0.CLUT.INIT[53] 35_33
CLBLM_L.SLICEM_X0.CLUT.INIT[54] 34_32
CLBLM_L.SLICEM_X0.CLUT.INIT[55] 35_32
CLBLM_L.SLICEM_X0.CLUT.INIT[56] 32_35
CLBLM_L.SLICEM_X0.CLUT.INIT[57] 33_35
CLBLM_L.SLICEM_X0.CLUT.INIT[58] 32_34
CLBLM_L.SLICEM_X0.CLUT.INIT[59] 33_34
CLBLM_L.SLICEM_X0.CLUT.INIT[60] 32_33
CLBLM_L.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_L.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_L.SLICEM_X0.CLUT.RAM 31_46
CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_L.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
CLBLM_L.SLICEM_X0.DLUT.INIT[03] 35_62
CLBLM_L.SLICEM_X0.DLUT.INIT[04] 34_61
CLBLM_L.SLICEM_X0.DLUT.INIT[05] 35_61
CLBLM_L.SLICEM_X0.DLUT.INIT[06] 34_60
CLBLM_L.SLICEM_X0.DLUT.INIT[07] 35_60
CLBLM_L.SLICEM_X0.DLUT.INIT[08] 32_63
CLBLM_L.SLICEM_X0.DLUT.INIT[09] 33_63
CLBLM_L.SLICEM_X0.DLUT.INIT[10] 32_62
CLBLM_L.SLICEM_X0.DLUT.INIT[11] 33_62
CLBLM_L.SLICEM_X0.DLUT.INIT[12] 32_61
CLBLM_L.SLICEM_X0.DLUT.INIT[13] 33_61
CLBLM_L.SLICEM_X0.DLUT.INIT[14] 32_60
CLBLM_L.SLICEM_X0.DLUT.INIT[15] 33_60
CLBLM_L.SLICEM_X0.DLUT.INIT[16] 34_59
CLBLM_L.SLICEM_X0.DLUT.INIT[17] 35_59
CLBLM_L.SLICEM_X0.DLUT.INIT[18] 34_58
CLBLM_L.SLICEM_X0.DLUT.INIT[19] 35_58
CLBLM_L.SLICEM_X0.DLUT.INIT[20] 34_57
CLBLM_L.SLICEM_X0.DLUT.INIT[21] 35_57
CLBLM_L.SLICEM_X0.DLUT.INIT[22] 34_56
CLBLM_L.SLICEM_X0.DLUT.INIT[23] 35_56
CLBLM_L.SLICEM_X0.DLUT.INIT[24] 32_59
CLBLM_L.SLICEM_X0.DLUT.INIT[25] 33_59
CLBLM_L.SLICEM_X0.DLUT.INIT[26] 32_58
CLBLM_L.SLICEM_X0.DLUT.INIT[27] 33_58
CLBLM_L.SLICEM_X0.DLUT.INIT[28] 32_57
CLBLM_L.SLICEM_X0.DLUT.INIT[29] 33_57
CLBLM_L.SLICEM_X0.DLUT.INIT[30] 32_56
CLBLM_L.SLICEM_X0.DLUT.INIT[31] 33_56
CLBLM_L.SLICEM_X0.DLUT.INIT[32] 34_55
CLBLM_L.SLICEM_X0.DLUT.INIT[33] 35_55
CLBLM_L.SLICEM_X0.DLUT.INIT[34] 34_54
CLBLM_L.SLICEM_X0.DLUT.INIT[35] 35_54
CLBLM_L.SLICEM_X0.DLUT.INIT[36] 34_53
CLBLM_L.SLICEM_X0.DLUT.INIT[37] 35_53
CLBLM_L.SLICEM_X0.DLUT.INIT[38] 34_52
CLBLM_L.SLICEM_X0.DLUT.INIT[39] 35_52
CLBLM_L.SLICEM_X0.DLUT.INIT[40] 32_55
CLBLM_L.SLICEM_X0.DLUT.INIT[41] 33_55
CLBLM_L.SLICEM_X0.DLUT.INIT[42] 32_54
CLBLM_L.SLICEM_X0.DLUT.INIT[43] 33_54
CLBLM_L.SLICEM_X0.DLUT.INIT[44] 32_53
CLBLM_L.SLICEM_X0.DLUT.INIT[45] 33_53
CLBLM_L.SLICEM_X0.DLUT.INIT[46] 32_52
CLBLM_L.SLICEM_X0.DLUT.INIT[47] 33_52
CLBLM_L.SLICEM_X0.DLUT.INIT[48] 34_51
CLBLM_L.SLICEM_X0.DLUT.INIT[49] 35_51
CLBLM_L.SLICEM_X0.DLUT.INIT[50] 34_50
CLBLM_L.SLICEM_X0.DLUT.INIT[51] 35_50
CLBLM_L.SLICEM_X0.DLUT.INIT[52] 34_49
CLBLM_L.SLICEM_X0.DLUT.INIT[53] 35_49
CLBLM_L.SLICEM_X0.DLUT.INIT[54] 34_48
CLBLM_L.SLICEM_X0.DLUT.INIT[55] 35_48
CLBLM_L.SLICEM_X0.DLUT.INIT[56] 32_51
CLBLM_L.SLICEM_X0.DLUT.INIT[57] 33_51
CLBLM_L.SLICEM_X0.DLUT.INIT[58] 32_50
CLBLM_L.SLICEM_X0.DLUT.INIT[59] 33_50
CLBLM_L.SLICEM_X0.DLUT.INIT[60] 32_49
CLBLM_L.SLICEM_X0.DLUT.INIT[61] 33_49
CLBLM_L.SLICEM_X0.DLUT.INIT[62] 32_48
CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_L.SLICEM_X0.DLUT.RAM 31_47
CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49

696
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CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
CLBLM_R.SLICEL_X1.ALUT.INIT[03] 27_14
CLBLM_R.SLICEL_X1.ALUT.INIT[04] 26_13
CLBLM_R.SLICEL_X1.ALUT.INIT[05] 27_13
CLBLM_R.SLICEL_X1.ALUT.INIT[06] 26_12
CLBLM_R.SLICEL_X1.ALUT.INIT[07] 27_12
CLBLM_R.SLICEL_X1.ALUT.INIT[08] 29_15
CLBLM_R.SLICEL_X1.ALUT.INIT[09] 28_15
CLBLM_R.SLICEL_X1.ALUT.INIT[10] 29_14
CLBLM_R.SLICEL_X1.ALUT.INIT[11] 28_14
CLBLM_R.SLICEL_X1.ALUT.INIT[12] 29_13
CLBLM_R.SLICEL_X1.ALUT.INIT[13] 28_13
CLBLM_R.SLICEL_X1.ALUT.INIT[14] 29_12
CLBLM_R.SLICEL_X1.ALUT.INIT[15] 28_12
CLBLM_R.SLICEL_X1.ALUT.INIT[16] 26_11
CLBLM_R.SLICEL_X1.ALUT.INIT[17] 27_11
CLBLM_R.SLICEL_X1.ALUT.INIT[18] 26_10
CLBLM_R.SLICEL_X1.ALUT.INIT[19] 27_10
CLBLM_R.SLICEL_X1.ALUT.INIT[20] 26_09
CLBLM_R.SLICEL_X1.ALUT.INIT[21] 27_09
CLBLM_R.SLICEL_X1.ALUT.INIT[22] 26_08
CLBLM_R.SLICEL_X1.ALUT.INIT[23] 27_08
CLBLM_R.SLICEL_X1.ALUT.INIT[24] 29_11
CLBLM_R.SLICEL_X1.ALUT.INIT[25] 28_11
CLBLM_R.SLICEL_X1.ALUT.INIT[26] 29_10
CLBLM_R.SLICEL_X1.ALUT.INIT[27] 28_10
CLBLM_R.SLICEL_X1.ALUT.INIT[28] 29_09
CLBLM_R.SLICEL_X1.ALUT.INIT[29] 28_09
CLBLM_R.SLICEL_X1.ALUT.INIT[30] 29_08
CLBLM_R.SLICEL_X1.ALUT.INIT[31] 28_08
CLBLM_R.SLICEL_X1.ALUT.INIT[32] 26_07
CLBLM_R.SLICEL_X1.ALUT.INIT[33] 27_07
CLBLM_R.SLICEL_X1.ALUT.INIT[34] 26_06
CLBLM_R.SLICEL_X1.ALUT.INIT[35] 27_06
CLBLM_R.SLICEL_X1.ALUT.INIT[36] 26_05
CLBLM_R.SLICEL_X1.ALUT.INIT[37] 27_05
CLBLM_R.SLICEL_X1.ALUT.INIT[38] 26_04
CLBLM_R.SLICEL_X1.ALUT.INIT[39] 27_04
CLBLM_R.SLICEL_X1.ALUT.INIT[40] 29_07
CLBLM_R.SLICEL_X1.ALUT.INIT[41] 28_07
CLBLM_R.SLICEL_X1.ALUT.INIT[42] 29_06
CLBLM_R.SLICEL_X1.ALUT.INIT[43] 28_06
CLBLM_R.SLICEL_X1.ALUT.INIT[44] 29_05
CLBLM_R.SLICEL_X1.ALUT.INIT[45] 28_05
CLBLM_R.SLICEL_X1.ALUT.INIT[46] 29_04
CLBLM_R.SLICEL_X1.ALUT.INIT[47] 28_04
CLBLM_R.SLICEL_X1.ALUT.INIT[48] 26_03
CLBLM_R.SLICEL_X1.ALUT.INIT[49] 27_03
CLBLM_R.SLICEL_X1.ALUT.INIT[50] 26_02
CLBLM_R.SLICEL_X1.ALUT.INIT[51] 27_02
CLBLM_R.SLICEL_X1.ALUT.INIT[52] 26_01
CLBLM_R.SLICEL_X1.ALUT.INIT[53] 27_01
CLBLM_R.SLICEL_X1.ALUT.INIT[54] 26_00
CLBLM_R.SLICEL_X1.ALUT.INIT[55] 27_00
CLBLM_R.SLICEL_X1.ALUT.INIT[56] 29_03
CLBLM_R.SLICEL_X1.ALUT.INIT[57] 28_03
CLBLM_R.SLICEL_X1.ALUT.INIT[58] 29_02
CLBLM_R.SLICEL_X1.ALUT.INIT[59] 28_02
CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q 30_05 !31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 31_07 !31_09 !31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 30_05 !31_07 !31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O6 !30_05 !31_07 31_09 !31_10
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
CLBLM_R.SLICEL_X1.BLUT.INIT[03] 27_30
CLBLM_R.SLICEL_X1.BLUT.INIT[04] 26_29
CLBLM_R.SLICEL_X1.BLUT.INIT[05] 27_29
CLBLM_R.SLICEL_X1.BLUT.INIT[06] 26_28
CLBLM_R.SLICEL_X1.BLUT.INIT[07] 27_28
CLBLM_R.SLICEL_X1.BLUT.INIT[08] 29_31
CLBLM_R.SLICEL_X1.BLUT.INIT[09] 28_31
CLBLM_R.SLICEL_X1.BLUT.INIT[10] 29_30
CLBLM_R.SLICEL_X1.BLUT.INIT[11] 28_30
CLBLM_R.SLICEL_X1.BLUT.INIT[12] 29_29
CLBLM_R.SLICEL_X1.BLUT.INIT[13] 28_29
CLBLM_R.SLICEL_X1.BLUT.INIT[14] 29_28
CLBLM_R.SLICEL_X1.BLUT.INIT[15] 28_28
CLBLM_R.SLICEL_X1.BLUT.INIT[16] 26_27
CLBLM_R.SLICEL_X1.BLUT.INIT[17] 27_27
CLBLM_R.SLICEL_X1.BLUT.INIT[18] 26_26
CLBLM_R.SLICEL_X1.BLUT.INIT[19] 27_26
CLBLM_R.SLICEL_X1.BLUT.INIT[20] 26_25
CLBLM_R.SLICEL_X1.BLUT.INIT[21] 27_25
CLBLM_R.SLICEL_X1.BLUT.INIT[22] 26_24
CLBLM_R.SLICEL_X1.BLUT.INIT[23] 27_24
CLBLM_R.SLICEL_X1.BLUT.INIT[24] 29_27
CLBLM_R.SLICEL_X1.BLUT.INIT[25] 28_27
CLBLM_R.SLICEL_X1.BLUT.INIT[26] 29_26
CLBLM_R.SLICEL_X1.BLUT.INIT[27] 28_26
CLBLM_R.SLICEL_X1.BLUT.INIT[28] 29_25
CLBLM_R.SLICEL_X1.BLUT.INIT[29] 28_25
CLBLM_R.SLICEL_X1.BLUT.INIT[30] 29_24
CLBLM_R.SLICEL_X1.BLUT.INIT[31] 28_24
CLBLM_R.SLICEL_X1.BLUT.INIT[32] 26_23
CLBLM_R.SLICEL_X1.BLUT.INIT[33] 27_23
CLBLM_R.SLICEL_X1.BLUT.INIT[34] 26_22
CLBLM_R.SLICEL_X1.BLUT.INIT[35] 27_22
CLBLM_R.SLICEL_X1.BLUT.INIT[36] 26_21
CLBLM_R.SLICEL_X1.BLUT.INIT[37] 27_21
CLBLM_R.SLICEL_X1.BLUT.INIT[38] 26_20
CLBLM_R.SLICEL_X1.BLUT.INIT[39] 27_20
CLBLM_R.SLICEL_X1.BLUT.INIT[40] 29_23
CLBLM_R.SLICEL_X1.BLUT.INIT[41] 28_23
CLBLM_R.SLICEL_X1.BLUT.INIT[42] 29_22
CLBLM_R.SLICEL_X1.BLUT.INIT[43] 28_22
CLBLM_R.SLICEL_X1.BLUT.INIT[44] 29_21
CLBLM_R.SLICEL_X1.BLUT.INIT[45] 28_21
CLBLM_R.SLICEL_X1.BLUT.INIT[46] 29_20
CLBLM_R.SLICEL_X1.BLUT.INIT[47] 28_20
CLBLM_R.SLICEL_X1.BLUT.INIT[48] 26_19
CLBLM_R.SLICEL_X1.BLUT.INIT[49] 27_19
CLBLM_R.SLICEL_X1.BLUT.INIT[50] 26_18
CLBLM_R.SLICEL_X1.BLUT.INIT[51] 27_18
CLBLM_R.SLICEL_X1.BLUT.INIT[52] 26_17
CLBLM_R.SLICEL_X1.BLUT.INIT[53] 27_17
CLBLM_R.SLICEL_X1.BLUT.INIT[54] 26_16
CLBLM_R.SLICEL_X1.BLUT.INIT[55] 27_16
CLBLM_R.SLICEL_X1.BLUT.INIT[56] 29_19
CLBLM_R.SLICEL_X1.BLUT.INIT[57] 28_19
CLBLM_R.SLICEL_X1.BLUT.INIT[58] 29_18
CLBLM_R.SLICEL_X1.BLUT.INIT[59] 28_18
CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.CY 30_28 !30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR 30_28 !30_29 !31_20 !31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 30_29 !31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O6 !30_28 !30_29 31_20 !31_21
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLM_R.SLICEL_X1.CLKINV 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
CLBLM_R.SLICEL_X1.CLUT.INIT[02] 26_46
CLBLM_R.SLICEL_X1.CLUT.INIT[03] 27_46
CLBLM_R.SLICEL_X1.CLUT.INIT[04] 26_45
CLBLM_R.SLICEL_X1.CLUT.INIT[05] 27_45
CLBLM_R.SLICEL_X1.CLUT.INIT[06] 26_44
CLBLM_R.SLICEL_X1.CLUT.INIT[07] 27_44
CLBLM_R.SLICEL_X1.CLUT.INIT[08] 29_47
CLBLM_R.SLICEL_X1.CLUT.INIT[09] 28_47
CLBLM_R.SLICEL_X1.CLUT.INIT[10] 29_46
CLBLM_R.SLICEL_X1.CLUT.INIT[11] 28_46
CLBLM_R.SLICEL_X1.CLUT.INIT[12] 29_45
CLBLM_R.SLICEL_X1.CLUT.INIT[13] 28_45
CLBLM_R.SLICEL_X1.CLUT.INIT[14] 29_44
CLBLM_R.SLICEL_X1.CLUT.INIT[15] 28_44
CLBLM_R.SLICEL_X1.CLUT.INIT[16] 26_43
CLBLM_R.SLICEL_X1.CLUT.INIT[17] 27_43
CLBLM_R.SLICEL_X1.CLUT.INIT[18] 26_42
CLBLM_R.SLICEL_X1.CLUT.INIT[19] 27_42
CLBLM_R.SLICEL_X1.CLUT.INIT[20] 26_41
CLBLM_R.SLICEL_X1.CLUT.INIT[21] 27_41
CLBLM_R.SLICEL_X1.CLUT.INIT[22] 26_40
CLBLM_R.SLICEL_X1.CLUT.INIT[23] 27_40
CLBLM_R.SLICEL_X1.CLUT.INIT[24] 29_43
CLBLM_R.SLICEL_X1.CLUT.INIT[25] 28_43
CLBLM_R.SLICEL_X1.CLUT.INIT[26] 29_42
CLBLM_R.SLICEL_X1.CLUT.INIT[27] 28_42
CLBLM_R.SLICEL_X1.CLUT.INIT[28] 29_41
CLBLM_R.SLICEL_X1.CLUT.INIT[29] 28_41
CLBLM_R.SLICEL_X1.CLUT.INIT[30] 29_40
CLBLM_R.SLICEL_X1.CLUT.INIT[31] 28_40
CLBLM_R.SLICEL_X1.CLUT.INIT[32] 26_39
CLBLM_R.SLICEL_X1.CLUT.INIT[33] 27_39
CLBLM_R.SLICEL_X1.CLUT.INIT[34] 26_38
CLBLM_R.SLICEL_X1.CLUT.INIT[35] 27_38
CLBLM_R.SLICEL_X1.CLUT.INIT[36] 26_37
CLBLM_R.SLICEL_X1.CLUT.INIT[37] 27_37
CLBLM_R.SLICEL_X1.CLUT.INIT[38] 26_36
CLBLM_R.SLICEL_X1.CLUT.INIT[39] 27_36
CLBLM_R.SLICEL_X1.CLUT.INIT[40] 29_39
CLBLM_R.SLICEL_X1.CLUT.INIT[41] 28_39
CLBLM_R.SLICEL_X1.CLUT.INIT[42] 29_38
CLBLM_R.SLICEL_X1.CLUT.INIT[43] 28_38
CLBLM_R.SLICEL_X1.CLUT.INIT[44] 29_37
CLBLM_R.SLICEL_X1.CLUT.INIT[45] 28_37
CLBLM_R.SLICEL_X1.CLUT.INIT[46] 29_36
CLBLM_R.SLICEL_X1.CLUT.INIT[47] 28_36
CLBLM_R.SLICEL_X1.CLUT.INIT[48] 26_35
CLBLM_R.SLICEL_X1.CLUT.INIT[49] 27_35
CLBLM_R.SLICEL_X1.CLUT.INIT[50] 26_34
CLBLM_R.SLICEL_X1.CLUT.INIT[51] 27_34
CLBLM_R.SLICEL_X1.CLUT.INIT[52] 26_33
CLBLM_R.SLICEL_X1.CLUT.INIT[53] 27_33
CLBLM_R.SLICEL_X1.CLUT.INIT[54] 26_32
CLBLM_R.SLICEL_X1.CLUT.INIT[55] 27_32
CLBLM_R.SLICEL_X1.CLUT.INIT[56] 29_35
CLBLM_R.SLICEL_X1.CLUT.INIT[57] 28_35
CLBLM_R.SLICEL_X1.CLUT.INIT[58] 29_34
CLBLM_R.SLICEL_X1.CLUT.INIT[59] 28_34
CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q 30_41 !30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 30_42 !31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.F7 30_41 !30_42 31_40 !31_43
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.O6 !30_41 !30_42 !31_40 31_43
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
CLBLM_R.SLICEL_X1.DLUT.INIT[03] 27_62
CLBLM_R.SLICEL_X1.DLUT.INIT[04] 26_61
CLBLM_R.SLICEL_X1.DLUT.INIT[05] 27_61
CLBLM_R.SLICEL_X1.DLUT.INIT[06] 26_60
CLBLM_R.SLICEL_X1.DLUT.INIT[07] 27_60
CLBLM_R.SLICEL_X1.DLUT.INIT[08] 29_63
CLBLM_R.SLICEL_X1.DLUT.INIT[09] 28_63
CLBLM_R.SLICEL_X1.DLUT.INIT[10] 29_62
CLBLM_R.SLICEL_X1.DLUT.INIT[11] 28_62
CLBLM_R.SLICEL_X1.DLUT.INIT[12] 29_61
CLBLM_R.SLICEL_X1.DLUT.INIT[13] 28_61
CLBLM_R.SLICEL_X1.DLUT.INIT[14] 29_60
CLBLM_R.SLICEL_X1.DLUT.INIT[15] 28_60
CLBLM_R.SLICEL_X1.DLUT.INIT[16] 26_59
CLBLM_R.SLICEL_X1.DLUT.INIT[17] 27_59
CLBLM_R.SLICEL_X1.DLUT.INIT[18] 26_58
CLBLM_R.SLICEL_X1.DLUT.INIT[19] 27_58
CLBLM_R.SLICEL_X1.DLUT.INIT[20] 26_57
CLBLM_R.SLICEL_X1.DLUT.INIT[21] 27_57
CLBLM_R.SLICEL_X1.DLUT.INIT[22] 26_56
CLBLM_R.SLICEL_X1.DLUT.INIT[23] 27_56
CLBLM_R.SLICEL_X1.DLUT.INIT[24] 29_59
CLBLM_R.SLICEL_X1.DLUT.INIT[25] 28_59
CLBLM_R.SLICEL_X1.DLUT.INIT[26] 29_58
CLBLM_R.SLICEL_X1.DLUT.INIT[27] 28_58
CLBLM_R.SLICEL_X1.DLUT.INIT[28] 29_57
CLBLM_R.SLICEL_X1.DLUT.INIT[29] 28_57
CLBLM_R.SLICEL_X1.DLUT.INIT[30] 29_56
CLBLM_R.SLICEL_X1.DLUT.INIT[31] 28_56
CLBLM_R.SLICEL_X1.DLUT.INIT[32] 26_55
CLBLM_R.SLICEL_X1.DLUT.INIT[33] 27_55
CLBLM_R.SLICEL_X1.DLUT.INIT[34] 26_54
CLBLM_R.SLICEL_X1.DLUT.INIT[35] 27_54
CLBLM_R.SLICEL_X1.DLUT.INIT[36] 26_53
CLBLM_R.SLICEL_X1.DLUT.INIT[37] 27_53
CLBLM_R.SLICEL_X1.DLUT.INIT[38] 26_52
CLBLM_R.SLICEL_X1.DLUT.INIT[39] 27_52
CLBLM_R.SLICEL_X1.DLUT.INIT[40] 29_55
CLBLM_R.SLICEL_X1.DLUT.INIT[41] 28_55
CLBLM_R.SLICEL_X1.DLUT.INIT[42] 29_54
CLBLM_R.SLICEL_X1.DLUT.INIT[43] 28_54
CLBLM_R.SLICEL_X1.DLUT.INIT[44] 29_53
CLBLM_R.SLICEL_X1.DLUT.INIT[45] 28_53
CLBLM_R.SLICEL_X1.DLUT.INIT[46] 29_52
CLBLM_R.SLICEL_X1.DLUT.INIT[47] 28_52
CLBLM_R.SLICEL_X1.DLUT.INIT[48] 26_51
CLBLM_R.SLICEL_X1.DLUT.INIT[49] 27_51
CLBLM_R.SLICEL_X1.DLUT.INIT[50] 26_50
CLBLM_R.SLICEL_X1.DLUT.INIT[51] 27_50
CLBLM_R.SLICEL_X1.DLUT.INIT[52] 26_49
CLBLM_R.SLICEL_X1.DLUT.INIT[53] 27_49
CLBLM_R.SLICEL_X1.DLUT.INIT[54] 26_48
CLBLM_R.SLICEL_X1.DLUT.INIT[55] 27_48
CLBLM_R.SLICEL_X1.DLUT.INIT[56] 29_51
CLBLM_R.SLICEL_X1.DLUT.INIT[57] 28_51
CLBLM_R.SLICEL_X1.DLUT.INIT[58] 29_50
CLBLM_R.SLICEL_X1.DLUT.INIT[59] 28_50
CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY 30_53 !31_53 !31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR 30_53 !31_53 !31_56 !31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
CLBLM_R.SLICEM_X0.ALUT.INIT[03] 35_14
CLBLM_R.SLICEM_X0.ALUT.INIT[04] 34_13
CLBLM_R.SLICEM_X0.ALUT.INIT[05] 35_13
CLBLM_R.SLICEM_X0.ALUT.INIT[06] 34_12
CLBLM_R.SLICEM_X0.ALUT.INIT[07] 35_12
CLBLM_R.SLICEM_X0.ALUT.INIT[08] 32_15
CLBLM_R.SLICEM_X0.ALUT.INIT[09] 33_15
CLBLM_R.SLICEM_X0.ALUT.INIT[10] 32_14
CLBLM_R.SLICEM_X0.ALUT.INIT[11] 33_14
CLBLM_R.SLICEM_X0.ALUT.INIT[12] 32_13
CLBLM_R.SLICEM_X0.ALUT.INIT[13] 33_13
CLBLM_R.SLICEM_X0.ALUT.INIT[14] 32_12
CLBLM_R.SLICEM_X0.ALUT.INIT[15] 33_12
CLBLM_R.SLICEM_X0.ALUT.INIT[16] 34_11
CLBLM_R.SLICEM_X0.ALUT.INIT[17] 35_11
CLBLM_R.SLICEM_X0.ALUT.INIT[18] 34_10
CLBLM_R.SLICEM_X0.ALUT.INIT[19] 35_10
CLBLM_R.SLICEM_X0.ALUT.INIT[20] 34_09
CLBLM_R.SLICEM_X0.ALUT.INIT[21] 35_09
CLBLM_R.SLICEM_X0.ALUT.INIT[22] 34_08
CLBLM_R.SLICEM_X0.ALUT.INIT[23] 35_08
CLBLM_R.SLICEM_X0.ALUT.INIT[24] 32_11
CLBLM_R.SLICEM_X0.ALUT.INIT[25] 33_11
CLBLM_R.SLICEM_X0.ALUT.INIT[26] 32_10
CLBLM_R.SLICEM_X0.ALUT.INIT[27] 33_10
CLBLM_R.SLICEM_X0.ALUT.INIT[28] 32_09
CLBLM_R.SLICEM_X0.ALUT.INIT[29] 33_09
CLBLM_R.SLICEM_X0.ALUT.INIT[30] 32_08
CLBLM_R.SLICEM_X0.ALUT.INIT[31] 33_08
CLBLM_R.SLICEM_X0.ALUT.INIT[32] 34_07
CLBLM_R.SLICEM_X0.ALUT.INIT[33] 35_07
CLBLM_R.SLICEM_X0.ALUT.INIT[34] 34_06
CLBLM_R.SLICEM_X0.ALUT.INIT[35] 35_06
CLBLM_R.SLICEM_X0.ALUT.INIT[36] 34_05
CLBLM_R.SLICEM_X0.ALUT.INIT[37] 35_05
CLBLM_R.SLICEM_X0.ALUT.INIT[38] 34_04
CLBLM_R.SLICEM_X0.ALUT.INIT[39] 35_04
CLBLM_R.SLICEM_X0.ALUT.INIT[40] 32_07
CLBLM_R.SLICEM_X0.ALUT.INIT[41] 33_07
CLBLM_R.SLICEM_X0.ALUT.INIT[42] 32_06
CLBLM_R.SLICEM_X0.ALUT.INIT[43] 33_06
CLBLM_R.SLICEM_X0.ALUT.INIT[44] 32_05
CLBLM_R.SLICEM_X0.ALUT.INIT[45] 33_05
CLBLM_R.SLICEM_X0.ALUT.INIT[46] 32_04
CLBLM_R.SLICEM_X0.ALUT.INIT[47] 33_04
CLBLM_R.SLICEM_X0.ALUT.INIT[48] 34_03
CLBLM_R.SLICEM_X0.ALUT.INIT[49] 35_03
CLBLM_R.SLICEM_X0.ALUT.INIT[50] 34_02
CLBLM_R.SLICEM_X0.ALUT.INIT[51] 35_02
CLBLM_R.SLICEM_X0.ALUT.INIT[52] 34_01
CLBLM_R.SLICEM_X0.ALUT.INIT[53] 35_01
CLBLM_R.SLICEM_X0.ALUT.INIT[54] 34_00
CLBLM_R.SLICEM_X0.ALUT.INIT[55] 35_00
CLBLM_R.SLICEM_X0.ALUT.INIT[56] 32_03
CLBLM_R.SLICEM_X0.ALUT.INIT[57] 33_03
CLBLM_R.SLICEM_X0.ALUT.INIT[58] 32_02
CLBLM_R.SLICEM_X0.ALUT.INIT[59] 33_02
CLBLM_R.SLICEM_X0.ALUT.INIT[60] 32_01
CLBLM_R.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_R.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_R.SLICEM_X0.ALUT.RAM 31_16
CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.CY 30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.F7 30_06 30_07 !30_08 !30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O5 30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.O6 !30_06 !30_07 !30_08 30_11
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
CLBLM_R.SLICEM_X0.BLUT.INIT[03] 35_30
CLBLM_R.SLICEM_X0.BLUT.INIT[04] 34_29
CLBLM_R.SLICEM_X0.BLUT.INIT[05] 35_29
CLBLM_R.SLICEM_X0.BLUT.INIT[06] 34_28
CLBLM_R.SLICEM_X0.BLUT.INIT[07] 35_28
CLBLM_R.SLICEM_X0.BLUT.INIT[08] 32_31
CLBLM_R.SLICEM_X0.BLUT.INIT[09] 33_31
CLBLM_R.SLICEM_X0.BLUT.INIT[10] 32_30
CLBLM_R.SLICEM_X0.BLUT.INIT[11] 33_30
CLBLM_R.SLICEM_X0.BLUT.INIT[12] 32_29
CLBLM_R.SLICEM_X0.BLUT.INIT[13] 33_29
CLBLM_R.SLICEM_X0.BLUT.INIT[14] 32_28
CLBLM_R.SLICEM_X0.BLUT.INIT[15] 33_28
CLBLM_R.SLICEM_X0.BLUT.INIT[16] 34_27
CLBLM_R.SLICEM_X0.BLUT.INIT[17] 35_27
CLBLM_R.SLICEM_X0.BLUT.INIT[18] 34_26
CLBLM_R.SLICEM_X0.BLUT.INIT[19] 35_26
CLBLM_R.SLICEM_X0.BLUT.INIT[20] 34_25
CLBLM_R.SLICEM_X0.BLUT.INIT[21] 35_25
CLBLM_R.SLICEM_X0.BLUT.INIT[22] 34_24
CLBLM_R.SLICEM_X0.BLUT.INIT[23] 35_24
CLBLM_R.SLICEM_X0.BLUT.INIT[24] 32_27
CLBLM_R.SLICEM_X0.BLUT.INIT[25] 33_27
CLBLM_R.SLICEM_X0.BLUT.INIT[26] 32_26
CLBLM_R.SLICEM_X0.BLUT.INIT[27] 33_26
CLBLM_R.SLICEM_X0.BLUT.INIT[28] 32_25
CLBLM_R.SLICEM_X0.BLUT.INIT[29] 33_25
CLBLM_R.SLICEM_X0.BLUT.INIT[30] 32_24
CLBLM_R.SLICEM_X0.BLUT.INIT[31] 33_24
CLBLM_R.SLICEM_X0.BLUT.INIT[32] 34_23
CLBLM_R.SLICEM_X0.BLUT.INIT[33] 35_23
CLBLM_R.SLICEM_X0.BLUT.INIT[34] 34_22
CLBLM_R.SLICEM_X0.BLUT.INIT[35] 35_22
CLBLM_R.SLICEM_X0.BLUT.INIT[36] 34_21
CLBLM_R.SLICEM_X0.BLUT.INIT[37] 35_21
CLBLM_R.SLICEM_X0.BLUT.INIT[38] 34_20
CLBLM_R.SLICEM_X0.BLUT.INIT[39] 35_20
CLBLM_R.SLICEM_X0.BLUT.INIT[40] 32_23
CLBLM_R.SLICEM_X0.BLUT.INIT[41] 33_23
CLBLM_R.SLICEM_X0.BLUT.INIT[42] 32_22
CLBLM_R.SLICEM_X0.BLUT.INIT[43] 33_22
CLBLM_R.SLICEM_X0.BLUT.INIT[44] 32_21
CLBLM_R.SLICEM_X0.BLUT.INIT[45] 33_21
CLBLM_R.SLICEM_X0.BLUT.INIT[46] 32_20
CLBLM_R.SLICEM_X0.BLUT.INIT[47] 33_20
CLBLM_R.SLICEM_X0.BLUT.INIT[48] 34_19
CLBLM_R.SLICEM_X0.BLUT.INIT[49] 35_19
CLBLM_R.SLICEM_X0.BLUT.INIT[50] 34_18
CLBLM_R.SLICEM_X0.BLUT.INIT[51] 35_18
CLBLM_R.SLICEM_X0.BLUT.INIT[52] 34_17
CLBLM_R.SLICEM_X0.BLUT.INIT[53] 35_17
CLBLM_R.SLICEM_X0.BLUT.INIT[54] 34_16
CLBLM_R.SLICEM_X0.BLUT.INIT[55] 35_16
CLBLM_R.SLICEM_X0.BLUT.INIT[56] 32_19
CLBLM_R.SLICEM_X0.BLUT.INIT[57] 33_19
CLBLM_R.SLICEM_X0.BLUT.INIT[58] 32_18
CLBLM_R.SLICEM_X0.BLUT.INIT[59] 33_18
CLBLM_R.SLICEM_X0.BLUT.INIT[60] 32_17
CLBLM_R.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_R.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_R.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_R.SLICEM_X0.BLUT.RAM 31_17
CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 30_20 !30_21 30_22 !30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O6 30_20 !30_21 !30_22 !30_23
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
CLBLM_R.SLICEM_X0.CLUT.INIT[03] 35_46
CLBLM_R.SLICEM_X0.CLUT.INIT[04] 34_45
CLBLM_R.SLICEM_X0.CLUT.INIT[05] 35_45
CLBLM_R.SLICEM_X0.CLUT.INIT[06] 34_44
CLBLM_R.SLICEM_X0.CLUT.INIT[07] 35_44
CLBLM_R.SLICEM_X0.CLUT.INIT[08] 32_47
CLBLM_R.SLICEM_X0.CLUT.INIT[09] 33_47
CLBLM_R.SLICEM_X0.CLUT.INIT[10] 32_46
CLBLM_R.SLICEM_X0.CLUT.INIT[11] 33_46
CLBLM_R.SLICEM_X0.CLUT.INIT[12] 32_45
CLBLM_R.SLICEM_X0.CLUT.INIT[13] 33_45
CLBLM_R.SLICEM_X0.CLUT.INIT[14] 32_44
CLBLM_R.SLICEM_X0.CLUT.INIT[15] 33_44
CLBLM_R.SLICEM_X0.CLUT.INIT[16] 34_43
CLBLM_R.SLICEM_X0.CLUT.INIT[17] 35_43
CLBLM_R.SLICEM_X0.CLUT.INIT[18] 34_42
CLBLM_R.SLICEM_X0.CLUT.INIT[19] 35_42
CLBLM_R.SLICEM_X0.CLUT.INIT[20] 34_41
CLBLM_R.SLICEM_X0.CLUT.INIT[21] 35_41
CLBLM_R.SLICEM_X0.CLUT.INIT[22] 34_40
CLBLM_R.SLICEM_X0.CLUT.INIT[23] 35_40
CLBLM_R.SLICEM_X0.CLUT.INIT[24] 32_43
CLBLM_R.SLICEM_X0.CLUT.INIT[25] 33_43
CLBLM_R.SLICEM_X0.CLUT.INIT[26] 32_42
CLBLM_R.SLICEM_X0.CLUT.INIT[27] 33_42
CLBLM_R.SLICEM_X0.CLUT.INIT[28] 32_41
CLBLM_R.SLICEM_X0.CLUT.INIT[29] 33_41
CLBLM_R.SLICEM_X0.CLUT.INIT[30] 32_40
CLBLM_R.SLICEM_X0.CLUT.INIT[31] 33_40
CLBLM_R.SLICEM_X0.CLUT.INIT[32] 34_39
CLBLM_R.SLICEM_X0.CLUT.INIT[33] 35_39
CLBLM_R.SLICEM_X0.CLUT.INIT[34] 34_38
CLBLM_R.SLICEM_X0.CLUT.INIT[35] 35_38
CLBLM_R.SLICEM_X0.CLUT.INIT[36] 34_37
CLBLM_R.SLICEM_X0.CLUT.INIT[37] 35_37
CLBLM_R.SLICEM_X0.CLUT.INIT[38] 34_36
CLBLM_R.SLICEM_X0.CLUT.INIT[39] 35_36
CLBLM_R.SLICEM_X0.CLUT.INIT[40] 32_39
CLBLM_R.SLICEM_X0.CLUT.INIT[41] 33_39
CLBLM_R.SLICEM_X0.CLUT.INIT[42] 32_38
CLBLM_R.SLICEM_X0.CLUT.INIT[43] 33_38
CLBLM_R.SLICEM_X0.CLUT.INIT[44] 32_37
CLBLM_R.SLICEM_X0.CLUT.INIT[45] 33_37
CLBLM_R.SLICEM_X0.CLUT.INIT[46] 32_36
CLBLM_R.SLICEM_X0.CLUT.INIT[47] 33_36
CLBLM_R.SLICEM_X0.CLUT.INIT[48] 34_35
CLBLM_R.SLICEM_X0.CLUT.INIT[49] 35_35
CLBLM_R.SLICEM_X0.CLUT.INIT[50] 34_34
CLBLM_R.SLICEM_X0.CLUT.INIT[51] 35_34
CLBLM_R.SLICEM_X0.CLUT.INIT[52] 34_33
CLBLM_R.SLICEM_X0.CLUT.INIT[53] 35_33
CLBLM_R.SLICEM_X0.CLUT.INIT[54] 34_32
CLBLM_R.SLICEM_X0.CLUT.INIT[55] 35_32
CLBLM_R.SLICEM_X0.CLUT.INIT[56] 32_35
CLBLM_R.SLICEM_X0.CLUT.INIT[57] 33_35
CLBLM_R.SLICEM_X0.CLUT.INIT[58] 32_34
CLBLM_R.SLICEM_X0.CLUT.INIT[59] 33_34
CLBLM_R.SLICEM_X0.CLUT.INIT[60] 32_33
CLBLM_R.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_R.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_R.SLICEM_X0.CLUT.RAM 31_46
CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.CY 30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.F7 30_40 30_43 !30_44 !30_45
CLBLM_R.SLICEM_X0.COUTMUX.O5 30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.COUTMUX.O6 !30_40 !30_43 !30_44 30_45
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
CLBLM_R.SLICEM_X0.DLUT.INIT[03] 35_62
CLBLM_R.SLICEM_X0.DLUT.INIT[04] 34_61
CLBLM_R.SLICEM_X0.DLUT.INIT[05] 35_61
CLBLM_R.SLICEM_X0.DLUT.INIT[06] 34_60
CLBLM_R.SLICEM_X0.DLUT.INIT[07] 35_60
CLBLM_R.SLICEM_X0.DLUT.INIT[08] 32_63
CLBLM_R.SLICEM_X0.DLUT.INIT[09] 33_63
CLBLM_R.SLICEM_X0.DLUT.INIT[10] 32_62
CLBLM_R.SLICEM_X0.DLUT.INIT[11] 33_62
CLBLM_R.SLICEM_X0.DLUT.INIT[12] 32_61
CLBLM_R.SLICEM_X0.DLUT.INIT[13] 33_61
CLBLM_R.SLICEM_X0.DLUT.INIT[14] 32_60
CLBLM_R.SLICEM_X0.DLUT.INIT[15] 33_60
CLBLM_R.SLICEM_X0.DLUT.INIT[16] 34_59
CLBLM_R.SLICEM_X0.DLUT.INIT[17] 35_59
CLBLM_R.SLICEM_X0.DLUT.INIT[18] 34_58
CLBLM_R.SLICEM_X0.DLUT.INIT[19] 35_58
CLBLM_R.SLICEM_X0.DLUT.INIT[20] 34_57
CLBLM_R.SLICEM_X0.DLUT.INIT[21] 35_57
CLBLM_R.SLICEM_X0.DLUT.INIT[22] 34_56
CLBLM_R.SLICEM_X0.DLUT.INIT[23] 35_56
CLBLM_R.SLICEM_X0.DLUT.INIT[24] 32_59
CLBLM_R.SLICEM_X0.DLUT.INIT[25] 33_59
CLBLM_R.SLICEM_X0.DLUT.INIT[26] 32_58
CLBLM_R.SLICEM_X0.DLUT.INIT[27] 33_58
CLBLM_R.SLICEM_X0.DLUT.INIT[28] 32_57
CLBLM_R.SLICEM_X0.DLUT.INIT[29] 33_57
CLBLM_R.SLICEM_X0.DLUT.INIT[30] 32_56
CLBLM_R.SLICEM_X0.DLUT.INIT[31] 33_56
CLBLM_R.SLICEM_X0.DLUT.INIT[32] 34_55
CLBLM_R.SLICEM_X0.DLUT.INIT[33] 35_55
CLBLM_R.SLICEM_X0.DLUT.INIT[34] 34_54
CLBLM_R.SLICEM_X0.DLUT.INIT[35] 35_54
CLBLM_R.SLICEM_X0.DLUT.INIT[36] 34_53
CLBLM_R.SLICEM_X0.DLUT.INIT[37] 35_53
CLBLM_R.SLICEM_X0.DLUT.INIT[38] 34_52
CLBLM_R.SLICEM_X0.DLUT.INIT[39] 35_52
CLBLM_R.SLICEM_X0.DLUT.INIT[40] 32_55
CLBLM_R.SLICEM_X0.DLUT.INIT[41] 33_55
CLBLM_R.SLICEM_X0.DLUT.INIT[42] 32_54
CLBLM_R.SLICEM_X0.DLUT.INIT[43] 33_54
CLBLM_R.SLICEM_X0.DLUT.INIT[44] 32_53
CLBLM_R.SLICEM_X0.DLUT.INIT[45] 33_53
CLBLM_R.SLICEM_X0.DLUT.INIT[46] 32_52
CLBLM_R.SLICEM_X0.DLUT.INIT[47] 33_52
CLBLM_R.SLICEM_X0.DLUT.INIT[48] 34_51
CLBLM_R.SLICEM_X0.DLUT.INIT[49] 35_51
CLBLM_R.SLICEM_X0.DLUT.INIT[50] 34_50
CLBLM_R.SLICEM_X0.DLUT.INIT[51] 35_50
CLBLM_R.SLICEM_X0.DLUT.INIT[52] 34_49
CLBLM_R.SLICEM_X0.DLUT.INIT[53] 35_49
CLBLM_R.SLICEM_X0.DLUT.INIT[54] 34_48
CLBLM_R.SLICEM_X0.DLUT.INIT[55] 35_48
CLBLM_R.SLICEM_X0.DLUT.INIT[56] 32_51
CLBLM_R.SLICEM_X0.DLUT.INIT[57] 33_51
CLBLM_R.SLICEM_X0.DLUT.INIT[58] 32_50
CLBLM_R.SLICEM_X0.DLUT.INIT[59] 33_50
CLBLM_R.SLICEM_X0.DLUT.INIT[60] 32_49
CLBLM_R.SLICEM_X0.DLUT.INIT[61] 33_49
CLBLM_R.SLICEM_X0.DLUT.INIT[62] 32_48
CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_R.SLICEM_X0.DLUT.RAM 31_47
CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49

0
zynq7/segbits_dsp_l.db Normal file
View File

0
zynq7/segbits_dsp_r.db Normal file
View File

196
zynq7/segbits_hclk_l.db Normal file
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@ -0,0 +1,196 @@
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 01_19
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 01_14 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 01_14 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 01_14 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L3 01_14 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 00_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 00_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 00_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 00_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 01_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 00_16 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 00_16 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 00_16 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 00_16 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 02_14 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 03_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 02_15 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L3 03_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 02_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 05_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 02_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 05_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 02_14 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 04_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 02_15 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 04_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 02_14 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 02_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 02_15 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 02_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 00_18 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 00_18 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 00_18 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L3 00_18 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 01_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 01_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 01_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 01_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 00_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 00_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 00_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 00_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 01_16 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 01_16 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 01_16 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 01_16 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 02_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 02_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 02_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L3 02_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 03_19 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 04_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 03_18 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 04_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 03_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 04_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 03_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 04_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 03_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 03_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 03_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 03_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 00_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 00_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 00_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L3 00_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 01_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 01_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 01_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 01_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 00_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 00_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 00_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 00_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 01_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 01_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 01_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 01_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 02_20 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 03_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 02_21 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L3 03_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 02_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 05_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 02_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 05_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 04_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 02_21 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 04_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 02_20 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 02_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 02_21 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 02_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 01_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 01_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 01_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L3 01_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 00_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 00_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 00_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 00_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 01_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 01_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 01_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 01_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 00_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 00_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 00_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 00_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 02_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 02_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 02_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L3 02_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 03_31 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 04_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 03_30 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 04_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 03_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 04_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 03_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 04_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 03_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 03_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 03_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 03_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 00_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 00_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 00_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L3 00_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 01_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 01_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 01_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 01_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 00_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 00_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 00_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 00_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 01_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 01_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 01_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 01_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 02_26 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 03_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 02_27 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L3 03_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 02_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 05_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 02_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 05_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 02_26 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 04_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 02_27 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 04_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 02_26 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 02_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 02_27 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 02_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 01_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 01_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 01_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L3 01_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 00_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 00_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 00_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 00_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 01_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 01_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 01_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 01_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 00_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 00_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 00_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 00_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 02_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 02_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 02_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L3 02_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 03_25 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 04_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 03_24 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 04_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 03_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 04_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 03_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 04_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 03_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 03_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 03_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 03_23 04_24

200
zynq7/segbits_hclk_r.db Normal file
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@ -0,0 +1,200 @@
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK0 00_14
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK1 01_19
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK2 00_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK3 01_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 00_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 01_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 00_31
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 01_31
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 00_16 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R1 00_16 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R2 00_16 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R3 00_16 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R4 01_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R5 01_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R6 01_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R7 01_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 01_14 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 01_14 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 01_14 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 01_14 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 00_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 00_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 00_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 00_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 02_14 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 02_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 02_15 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R3 02_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 02_14 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 04_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 02_15 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 04_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 02_14 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 03_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 02_15 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 03_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 02_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 05_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 02_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 05_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 01_16 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 01_16 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 01_16 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R3 01_16 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 00_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 00_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 00_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 00_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 00_18 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 00_18 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 00_18 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 00_18 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 01_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 01_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 01_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 01_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 03_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 03_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 03_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R3 03_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 03_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 04_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 03_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 04_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 02_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 02_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 02_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 02_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 03_19 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 04_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 03_18 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 04_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 01_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 01_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 01_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R3 01_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 00_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 00_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 00_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 00_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 00_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 00_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 00_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 00_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 01_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 01_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 01_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 01_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 02_20 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 02_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 02_21 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R3 02_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 02_20 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 04_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 02_21 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 04_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 02_20 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 03_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 02_21 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 03_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 02_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 05_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 02_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 05_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 00_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 00_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 00_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R3 00_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 01_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 01_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 01_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 01_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 01_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 01_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 01_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 01_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 00_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 00_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 00_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 00_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 03_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 03_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 03_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R3 03_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 03_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 04_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 03_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 04_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 02_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 02_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 02_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 02_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 03_31 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 04_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 03_30 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 04_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 01_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 01_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 01_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R3 01_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 00_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 00_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 00_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 00_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 00_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 00_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 00_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 00_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 01_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 01_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 01_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 01_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 02_26 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 02_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 02_27 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R3 02_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 02_26 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 04_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 02_27 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 04_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 02_26 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 03_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 02_27 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 03_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 02_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 05_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 02_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 05_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 00_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 00_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 00_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R3 00_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 01_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 01_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 01_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 01_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 01_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 01_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 01_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 01_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 00_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 00_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 00_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 00_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 03_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 03_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 03_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R3 03_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 03_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 04_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 03_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 04_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 02_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 02_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 02_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 02_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 03_25 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 04_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 03_24 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 04_23 04_24

3636
zynq7/segbits_int_l.db Normal file
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3636
zynq7/segbits_int_r.db Normal file
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File diff suppressed because it is too large Load Diff

39
zynq7/site_type_BSCAN.json Normal file
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@ -0,0 +1,39 @@
{
"site_pins": {
"CAPTURE": {
"direction": "OUT"
},
"DRCK": {
"direction": "OUT"
},
"RESET": {
"direction": "OUT"
},
"RUNTEST": {
"direction": "OUT"
},
"SEL": {
"direction": "OUT"
},
"SHIFT": {
"direction": "OUT"
},
"TCK": {
"direction": "OUT"
},
"TDI": {
"direction": "OUT"
},
"TDO": {
"direction": "IN"
},
"TMS": {
"direction": "OUT"
},
"UPDATE": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "BSCAN"
}

82
zynq7/site_type_BUFGCTRL.json Normal file
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@ -0,0 +1,82 @@
{
"site_pins": {
"CE0": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"I0": {
"direction": "IN"
},
"I1": {
"direction": "IN"
},
"IGNORE0": {
"direction": "IN"
},
"IGNORE1": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"S0": {
"direction": "IN"
},
"S1": {
"direction": "IN"
}
},
"site_pips": {
"CE0INV:CE0": {
"from_pin": "CE0",
"to_pin": "OUT"
},
"CE0INV:CE0_B": {
"from_pin": "CE0_B",
"to_pin": "OUT"
},
"CE1INV:CE1": {
"from_pin": "CE1",
"to_pin": "OUT"
},
"CE1INV:CE1_B": {
"from_pin": "CE1_B",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0": {
"from_pin": "IGNORE0",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0_B": {
"from_pin": "IGNORE0_B",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1": {
"from_pin": "IGNORE1",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1_B": {
"from_pin": "IGNORE1_B",
"to_pin": "OUT"
},
"S0INV:S0": {
"from_pin": "S0",
"to_pin": "OUT"
},
"S0INV:S0_B": {
"from_pin": "S0_B",
"to_pin": "OUT"
},
"S1INV:S1": {
"from_pin": "S1",
"to_pin": "OUT"
},
"S1INV:S1_B": {
"from_pin": "S1_B",
"to_pin": "OUT"
}
},
"type": "BUFGCTRL"
}

24
zynq7/site_type_BUFHCE.json Normal file
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@ -0,0 +1,24 @@
{
"site_pins": {
"CE": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
},
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"type": "BUFHCE"
}

12
zynq7/site_type_BUFIO.json Normal file
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@ -0,0 +1,12 @@
{
"site_pins": {
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "BUFIO"
}

24
zynq7/site_type_BUFMRCE.json Normal file
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@ -0,0 +1,24 @@
{
"site_pins": {
"CE": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
},
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"type": "BUFMRCE"
}

18
zynq7/site_type_BUFR.json Normal file
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@ -0,0 +1,18 @@
{
"site_pins": {
"CE": {
"direction": "IN"
},
"CLR": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "BUFR"
}

12
zynq7/site_type_CAPTURE.json Normal file
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@ -0,0 +1,12 @@
{
"site_pins": {
"CAP": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
}
},
"site_pips": {},
"type": "CAPTURE"
}

12
zynq7/site_type_DCIRESET.json Normal file
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@ -0,0 +1,12 @@
{
"site_pins": {
"LOCKED": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
}
},
"site_pips": {},
"type": "DCIRESET"
}

21
zynq7/site_type_DNA_PORT.json Normal file
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{
"site_pins": {
"CLK": {
"direction": "IN"
},
"DIN": {
"direction": "IN"
},
"DOUT": {
"direction": "OUT"
},
"READ": {
"direction": "IN"
},
"SHIFT": {
"direction": "IN"
}
},
"site_pips": {},
"type": "DNA_PORT"
}

1402
zynq7/site_type_DSP48E1.json Normal file
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102
zynq7/site_type_EFUSE_USR.json Normal file
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{
"site_pins": {
"EFUSEUSR0": {
"direction": "OUT"
},
"EFUSEUSR1": {
"direction": "OUT"
},
"EFUSEUSR10": {
"direction": "OUT"
},
"EFUSEUSR11": {
"direction": "OUT"
},
"EFUSEUSR12": {
"direction": "OUT"
},
"EFUSEUSR13": {
"direction": "OUT"
},
"EFUSEUSR14": {
"direction": "OUT"
},
"EFUSEUSR15": {
"direction": "OUT"
},
"EFUSEUSR16": {
"direction": "OUT"
},
"EFUSEUSR17": {
"direction": "OUT"
},
"EFUSEUSR18": {
"direction": "OUT"
},
"EFUSEUSR19": {
"direction": "OUT"
},
"EFUSEUSR2": {
"direction": "OUT"
},
"EFUSEUSR20": {
"direction": "OUT"
},
"EFUSEUSR21": {
"direction": "OUT"
},
"EFUSEUSR22": {
"direction": "OUT"
},
"EFUSEUSR23": {
"direction": "OUT"
},
"EFUSEUSR24": {
"direction": "OUT"
},
"EFUSEUSR25": {
"direction": "OUT"
},
"EFUSEUSR26": {
"direction": "OUT"
},
"EFUSEUSR27": {
"direction": "OUT"
},
"EFUSEUSR28": {
"direction": "OUT"
},
"EFUSEUSR29": {
"direction": "OUT"
},
"EFUSEUSR3": {
"direction": "OUT"
},
"EFUSEUSR30": {
"direction": "OUT"
},
"EFUSEUSR31": {
"direction": "OUT"
},
"EFUSEUSR4": {
"direction": "OUT"
},
"EFUSEUSR5": {
"direction": "OUT"
},
"EFUSEUSR6": {
"direction": "OUT"
},
"EFUSEUSR7": {
"direction": "OUT"
},
"EFUSEUSR8": {
"direction": "OUT"
},
"EFUSEUSR9": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "EFUSE_USR"
}

537
zynq7/site_type_FIFO18E1.json Normal file
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{
"site_pins": {
"ADDRARDADDR0": {
"direction": "IN"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"DIADI0": {
"direction": "IN"
},
"DIADI1": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"DIADI11": {
"direction": "IN"
},
"DIADI12": {
"direction": "IN"
},
"DIADI13": {
"direction": "IN"
},
"DIADI14": {
"direction": "IN"
},
"DIADI15": {
"direction": "IN"
},
"DIADI2": {
"direction": "IN"
},
"DIADI3": {
"direction": "IN"
},
"DIADI4": {
"direction": "IN"
},
"DIADI5": {
"direction": "IN"
},
"DIADI6": {
"direction": "IN"
},
"DIADI7": {
"direction": "IN"
},
"DIADI8": {
"direction": "IN"
},
"DIADI9": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
},
"DIBDI11": {
"direction": "IN"
},
"DIBDI12": {
"direction": "IN"
},
"DIBDI13": {
"direction": "IN"
},
"DIBDI14": {
"direction": "IN"
},
"DIBDI15": {
"direction": "IN"
},
"DIBDI2": {
"direction": "IN"
},
"DIBDI3": {
"direction": "IN"
},
"DIBDI4": {
"direction": "IN"
},
"DIBDI5": {
"direction": "IN"
},
"DIBDI6": {
"direction": "IN"
},
"DIBDI7": {
"direction": "IN"
},
"DIBDI8": {
"direction": "IN"
},
"DIBDI9": {
"direction": "IN"
},
"DIPADIP0": {
"direction": "IN"
},
"DIPADIP1": {
"direction": "IN"
},
"DIPBDIP0": {
"direction": "IN"
},
"DIPBDIP1": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DO16": {
"direction": "OUT"
},
"DO17": {
"direction": "OUT"
},
"DO18": {
"direction": "OUT"
},
"DO19": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO20": {
"direction": "OUT"
},
"DO21": {
"direction": "OUT"
},
"DO22": {
"direction": "OUT"
},
"DO23": {
"direction": "OUT"
},
"DO24": {
"direction": "OUT"
},
"DO25": {
"direction": "OUT"
},
"DO26": {
"direction": "OUT"
},
"DO27": {
"direction": "OUT"
},
"DO28": {
"direction": "OUT"
},
"DO29": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"DO30": {
"direction": "OUT"
},
"DO31": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DOP0": {
"direction": "OUT"
},
"DOP1": {
"direction": "OUT"
},
"DOP2": {
"direction": "OUT"
},
"DOP3": {
"direction": "OUT"
},
"EMPTY": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"RDCOUNT0": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"RDCOUNT11": {
"direction": "OUT"
},
"RDCOUNT2": {
"direction": "OUT"
},
"RDCOUNT3": {
"direction": "OUT"
},
"RDCOUNT4": {
"direction": "OUT"
},
"RDCOUNT5": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"RDCOUNT7": {
"direction": "OUT"
},
"RDCOUNT8": {
"direction": "OUT"
},
"RDCOUNT9": {
"direction": "OUT"
},
"RDEN": {
"direction": "IN"
},
"RDERR": {
"direction": "OUT"
},
"RDRCLK": {
"direction": "IN"
},
"REGCE": {
"direction": "IN"
},
"REGCEB": {
"direction": "IN"
},
"REGCLKB": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"RSTRAMB": {
"direction": "IN"
},
"RSTREG": {
"direction": "IN"
},
"RSTREGB": {
"direction": "IN"
},
"WEA0": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"WEA2": {
"direction": "IN"
},
"WEA3": {
"direction": "IN"
},
"WEBWE0": {
"direction": "IN"
},
"WEBWE1": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"WEBWE3": {
"direction": "IN"
},
"WEBWE4": {
"direction": "IN"
},
"WEBWE5": {
"direction": "IN"
},
"WEBWE6": {
"direction": "IN"
},
"WEBWE7": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"WRCOUNT0": {
"direction": "OUT"
},
"WRCOUNT1": {
"direction": "OUT"
},
"WRCOUNT10": {
"direction": "OUT"
},
"WRCOUNT11": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"WRCOUNT3": {
"direction": "OUT"
},
"WRCOUNT4": {
"direction": "OUT"
},
"WRCOUNT5": {
"direction": "OUT"
},
"WRCOUNT6": {
"direction": "OUT"
},
"WRCOUNT7": {
"direction": "OUT"
},
"WRCOUNT8": {
"direction": "OUT"
},
"WRCOUNT9": {
"direction": "OUT"
},
"WREN": {
"direction": "IN"
},
"WRERR": {
"direction": "OUT"
}
},
"site_pips": {
"RDCLKINV:RDCLK": {
"from_pin": "RDCLK",
"to_pin": "OUT"
},
"RDCLKINV:RDCLK_B": {
"from_pin": "RDCLK_B",
"to_pin": "OUT"
},
"RDENINV:RDEN": {
"from_pin": "RDEN",
"to_pin": "OUT"
},
"RDENINV:RDEN_B": {
"from_pin": "RDEN_B",
"to_pin": "OUT"
},
"RDRCLKINV:RDRCLK": {
"from_pin": "RDRCLK",
"to_pin": "OUT"
},
"RDRCLKINV:RDRCLK_B": {
"from_pin": "RDRCLK_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"RSTREGINV:RSTREG": {
"from_pin": "RSTREG",
"to_pin": "OUT"
},
"RSTREGINV:RSTREG_B": {
"from_pin": "RSTREG_B",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK": {
"from_pin": "WRCLK",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK_B": {
"from_pin": "WRCLK_B",
"to_pin": "OUT"
},
"WRENINV:WREN": {
"from_pin": "WREN",
"to_pin": "OUT"
},
"WRENINV:WREN_B": {
"from_pin": "WREN_B",
"to_pin": "OUT"
}
},
"type": "FIFO18E1"
}

171
zynq7/site_type_FRAME_ECC.json Normal file
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{
"site_pins": {
"CRCERROR": {
"direction": "OUT"
},
"ECCERROR": {
"direction": "OUT"
},
"ECCERRORSINGLE": {
"direction": "OUT"
},
"FAR0": {
"direction": "OUT"
},
"FAR1": {
"direction": "OUT"
},
"FAR10": {
"direction": "OUT"
},
"FAR11": {
"direction": "OUT"
},
"FAR12": {
"direction": "OUT"
},
"FAR13": {
"direction": "OUT"
},
"FAR14": {
"direction": "OUT"
},
"FAR15": {
"direction": "OUT"
},
"FAR16": {
"direction": "OUT"
},
"FAR17": {
"direction": "OUT"
},
"FAR18": {
"direction": "OUT"
},
"FAR19": {
"direction": "OUT"
},
"FAR2": {
"direction": "OUT"
},
"FAR20": {
"direction": "OUT"
},
"FAR21": {
"direction": "OUT"
},
"FAR22": {
"direction": "OUT"
},
"FAR23": {
"direction": "OUT"
},
"FAR24": {
"direction": "OUT"
},
"FAR25": {
"direction": "OUT"
},
"FAR3": {
"direction": "OUT"
},
"FAR4": {
"direction": "OUT"
},
"FAR5": {
"direction": "OUT"
},
"FAR6": {
"direction": "OUT"
},
"FAR7": {
"direction": "OUT"
},
"FAR8": {
"direction": "OUT"
},
"FAR9": {
"direction": "OUT"
},
"SYNBIT0": {
"direction": "OUT"
},
"SYNBIT1": {
"direction": "OUT"
},
"SYNBIT2": {
"direction": "OUT"
},
"SYNBIT3": {
"direction": "OUT"
},
"SYNBIT4": {
"direction": "OUT"
},
"SYNDROME0": {
"direction": "OUT"
},
"SYNDROME1": {
"direction": "OUT"
},
"SYNDROME10": {
"direction": "OUT"
},
"SYNDROME11": {
"direction": "OUT"
},
"SYNDROME12": {
"direction": "OUT"
},
"SYNDROME2": {
"direction": "OUT"
},
"SYNDROME3": {
"direction": "OUT"
},
"SYNDROME4": {
"direction": "OUT"
},
"SYNDROME5": {
"direction": "OUT"
},
"SYNDROME6": {
"direction": "OUT"
},
"SYNDROME7": {
"direction": "OUT"
},
"SYNDROME8": {
"direction": "OUT"
},
"SYNDROME9": {
"direction": "OUT"
},
"SYNDROMEVALID": {
"direction": "OUT"
},
"SYNWORD0": {
"direction": "OUT"
},
"SYNWORD1": {
"direction": "OUT"
},
"SYNWORD2": {
"direction": "OUT"
},
"SYNWORD3": {
"direction": "OUT"
},
"SYNWORD4": {
"direction": "OUT"
},
"SYNWORD5": {
"direction": "OUT"
},
"SYNWORD6": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "FRAME_ECC"
}

207
zynq7/site_type_ICAP.json Normal file
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{
"site_pins": {
"CLK": {
"direction": "IN"
},
"CSIB": {
"direction": "IN"
},
"I0": {
"direction": "IN"
},
"I1": {
"direction": "IN"
},
"I10": {
"direction": "IN"
},
"I11": {
"direction": "IN"
},
"I12": {
"direction": "IN"
},
"I13": {
"direction": "IN"
},
"I14": {
"direction": "IN"
},
"I15": {
"direction": "IN"
},
"I16": {
"direction": "IN"
},
"I17": {
"direction": "IN"
},
"I18": {
"direction": "IN"
},
"I19": {
"direction": "IN"
},
"I2": {
"direction": "IN"
},
"I20": {
"direction": "IN"
},
"I21": {
"direction": "IN"
},
"I22": {
"direction": "IN"
},
"I23": {
"direction": "IN"
},
"I24": {
"direction": "IN"
},
"I25": {
"direction": "IN"
},
"I26": {
"direction": "IN"
},
"I27": {
"direction": "IN"
},
"I28": {
"direction": "IN"
},
"I29": {
"direction": "IN"
},
"I3": {
"direction": "IN"
},
"I30": {
"direction": "IN"
},
"I31": {
"direction": "IN"
},
"I4": {
"direction": "IN"
},
"I5": {
"direction": "IN"
},
"I6": {
"direction": "IN"
},
"I7": {
"direction": "IN"
},
"I8": {
"direction": "IN"
},
"I9": {
"direction": "IN"
},
"O0": {
"direction": "OUT"
},
"O1": {
"direction": "OUT"
},
"O10": {
"direction": "OUT"
},
"O11": {
"direction": "OUT"
},
"O12": {
"direction": "OUT"
},
"O13": {
"direction": "OUT"
},
"O14": {
"direction": "OUT"
},
"O15": {
"direction": "OUT"
},
"O16": {
"direction": "OUT"
},
"O17": {
"direction": "OUT"
},
"O18": {
"direction": "OUT"
},
"O19": {
"direction": "OUT"
},
"O2": {
"direction": "OUT"
},
"O20": {
"direction": "OUT"
},
"O21": {
"direction": "OUT"
},
"O22": {
"direction": "OUT"
},
"O23": {
"direction": "OUT"
},
"O24": {
"direction": "OUT"
},
"O25": {
"direction": "OUT"
},
"O26": {
"direction": "OUT"
},
"O27": {
"direction": "OUT"
},
"O28": {
"direction": "OUT"
},
"O29": {
"direction": "OUT"
},
"O3": {
"direction": "OUT"
},
"O30": {
"direction": "OUT"
},
"O31": {
"direction": "OUT"
},
"O4": {
"direction": "OUT"
},
"O5": {
"direction": "OUT"
},
"O6": {
"direction": "OUT"
},
"O7": {
"direction": "OUT"
},
"O8": {
"direction": "OUT"
},
"O9": {
"direction": "OUT"
},
"RDWRB": {
"direction": "IN"
}
},
"site_pips": {},
"type": "ICAP"
}

27
zynq7/site_type_IDELAYCTRL.json Normal file
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@ -0,0 +1,27 @@
{
"site_pins": {
"DNPULSEOUT": {
"direction": "OUT"
},
"OUTN1": {
"direction": "OUT"
},
"OUTN65": {
"direction": "OUT"
},
"RDY": {
"direction": "OUT"
},
"REFCLK": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"UPPULSEOUT": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "IDELAYCTRL"
}

100
zynq7/site_type_IDELAYE2.json Normal file
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@ -0,0 +1,100 @@
{
"site_pins": {
"C": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"CINVCTRL": {
"direction": "IN"
},
"CNTVALUEIN0": {
"direction": "IN"
},
"CNTVALUEIN1": {
"direction": "IN"
},
"CNTVALUEIN2": {
"direction": "IN"
},
"CNTVALUEIN3": {
"direction": "IN"
},
"CNTVALUEIN4": {
"direction": "IN"
},
"CNTVALUEOUT0": {
"direction": "OUT"
},
"CNTVALUEOUT1": {
"direction": "OUT"
},
"CNTVALUEOUT2": {
"direction": "OUT"
},
"CNTVALUEOUT3": {
"direction": "OUT"
},
"CNTVALUEOUT4": {
"direction": "OUT"
},
"DATAIN": {
"direction": "IN"
},
"DATAOUT": {
"direction": "OUT"
},
"IDATAIN": {
"direction": "IN"
},
"IFDLY0": {
"direction": "IN"
},
"IFDLY1": {
"direction": "IN"
},
"IFDLY2": {
"direction": "IN"
},
"INC": {
"direction": "IN"
},
"LD": {
"direction": "IN"
},
"LDPIPEEN": {
"direction": "IN"
},
"REGRST": {
"direction": "IN"
}
},
"site_pips": {
"CINV:C": {
"from_pin": "C",
"to_pin": "OUT"
},
"CINV:C_B": {
"from_pin": "C_B",
"to_pin": "OUT"
},
"DATAININV:DATAIN": {
"from_pin": "DATAIN",
"to_pin": "OUT"
},
"DATAININV:DATAIN_B": {
"from_pin": "DATAIN_B",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN": {
"from_pin": "IDATAIN",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN_B": {
"from_pin": "IDATAIN_B",
"to_pin": "OUT"
}
},
"type": "IDELAYE2"
}

208
zynq7/site_type_ILOGICE3.json Normal file
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@ -0,0 +1,208 @@
{
"site_pins": {
"BITSLIP": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"CE2": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"CLKDIV": {
"direction": "IN"
},
"CLKDIVP": {
"direction": "IN"
},
"D": {
"direction": "IN"
},
"DDLY": {
"direction": "IN"
},
"DYNCLKDIVPSEL": {
"direction": "IN"
},
"DYNCLKDIVSEL": {
"direction": "IN"
},
"DYNCLKSEL": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"OCLK": {
"direction": "IN"
},
"OCLKB": {
"direction": "IN"
},
"OFB": {
"direction": "IN"
},
"Q1": {
"direction": "OUT"
},
"Q2": {
"direction": "OUT"
},
"Q3": {
"direction": "OUT"
},
"Q4": {
"direction": "OUT"
},
"Q5": {
"direction": "OUT"
},
"Q6": {
"direction": "OUT"
},
"Q7": {
"direction": "OUT"
},
"Q8": {
"direction": "OUT"
},
"REV": {
"direction": "IN"
},
"SHIFTIN1": {
"direction": "IN"
},
"SHIFTIN2": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"TFB": {
"direction": "IN"
}
},
"site_pips": {
"CE1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKBINV:CLKB": {
"from_pin": "CLKB",
"to_pin": "OUT"
},
"CLKBINV:CLKB_B": {
"from_pin": "CLKB_B",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"D2OBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"D2OBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"DINV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"DINV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"IDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
},
"IFFDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IFFDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
},
"IFFMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"REVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"SRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
}
},
"type": "ILOGICE3"
}

453
zynq7/site_type_IN_FIFO.json Normal file
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@ -0,0 +1,453 @@
{
"site_pins": {
"ALMOSTEMPTY": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"D00": {
"direction": "IN"
},
"D01": {
"direction": "IN"
},
"D02": {
"direction": "IN"
},
"D03": {
"direction": "IN"
},
"D10": {
"direction": "IN"
},
"D11": {
"direction": "IN"
},
"D12": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"D20": {
"direction": "IN"
},
"D21": {
"direction": "IN"
},
"D22": {
"direction": "IN"
},
"D23": {
"direction": "IN"
},
"D30": {
"direction": "IN"
},
"D31": {
"direction": "IN"
},
"D32": {
"direction": "IN"
},
"D33": {
"direction": "IN"
},
"D40": {
"direction": "IN"
},
"D41": {
"direction": "IN"
},
"D42": {
"direction": "IN"
},
"D43": {
"direction": "IN"
},
"D50": {
"direction": "IN"
},
"D51": {
"direction": "IN"
},
"D52": {
"direction": "IN"
},
"D53": {
"direction": "IN"
},
"D54": {
"direction": "IN"
},
"D55": {
"direction": "IN"
},
"D56": {
"direction": "IN"
},
"D57": {
"direction": "IN"
},
"D60": {
"direction": "IN"
},
"D61": {
"direction": "IN"
},
"D62": {
"direction": "IN"
},
"D63": {
"direction": "IN"
},
"D64": {
"direction": "IN"
},
"D65": {
"direction": "IN"
},
"D66": {
"direction": "IN"
},
"D67": {
"direction": "IN"
},
"D70": {
"direction": "IN"
},
"D71": {
"direction": "IN"
},
"D72": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D80": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"D82": {
"direction": "IN"
},
"D83": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"D91": {
"direction": "IN"
},
"D92": {
"direction": "IN"
},
"D93": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"Q00": {
"direction": "OUT"
},
"Q01": {
"direction": "OUT"
},
"Q02": {
"direction": "OUT"
},
"Q03": {
"direction": "OUT"
},
"Q04": {
"direction": "OUT"
},
"Q05": {
"direction": "OUT"
},
"Q06": {
"direction": "OUT"
},
"Q07": {
"direction": "OUT"
},
"Q10": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
},
"Q12": {
"direction": "OUT"
},
"Q13": {
"direction": "OUT"
},
"Q14": {
"direction": "OUT"
},
"Q15": {
"direction": "OUT"
},
"Q16": {
"direction": "OUT"
},
"Q17": {
"direction": "OUT"
},
"Q20": {
"direction": "OUT"
},
"Q21": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"Q23": {
"direction": "OUT"
},
"Q24": {
"direction": "OUT"
},
"Q25": {
"direction": "OUT"
},
"Q26": {
"direction": "OUT"
},
"Q27": {
"direction": "OUT"
},
"Q30": {
"direction": "OUT"
},
"Q31": {
"direction": "OUT"
},
"Q32": {
"direction": "OUT"
},
"Q33": {
"direction": "OUT"
},
"Q34": {
"direction": "OUT"
},
"Q35": {
"direction": "OUT"
},
"Q36": {
"direction": "OUT"
},
"Q37": {
"direction": "OUT"
},
"Q40": {
"direction": "OUT"
},
"Q41": {
"direction": "OUT"
},
"Q42": {
"direction": "OUT"
},
"Q43": {
"direction": "OUT"
},
"Q44": {
"direction": "OUT"
},
"Q45": {
"direction": "OUT"
},
"Q46": {
"direction": "OUT"
},
"Q47": {
"direction": "OUT"
},
"Q50": {
"direction": "OUT"
},
"Q51": {
"direction": "OUT"
},
"Q52": {
"direction": "OUT"
},
"Q53": {
"direction": "OUT"
},
"Q54": {
"direction": "OUT"
},
"Q55": {
"direction": "OUT"
},
"Q56": {
"direction": "OUT"
},
"Q57": {
"direction": "OUT"
},
"Q60": {
"direction": "OUT"
},
"Q61": {
"direction": "OUT"
},
"Q62": {
"direction": "OUT"
},
"Q63": {
"direction": "OUT"
},
"Q64": {
"direction": "OUT"
},
"Q65": {
"direction": "OUT"
},
"Q66": {
"direction": "OUT"
},
"Q67": {
"direction": "OUT"
},
"Q70": {
"direction": "OUT"
},
"Q71": {
"direction": "OUT"
},
"Q72": {
"direction": "OUT"
},
"Q73": {
"direction": "OUT"
},
"Q74": {
"direction": "OUT"
},
"Q75": {
"direction": "OUT"
},
"Q76": {
"direction": "OUT"
},
"Q77": {
"direction": "OUT"
},
"Q80": {
"direction": "OUT"
},
"Q81": {
"direction": "OUT"
},
"Q82": {
"direction": "OUT"
},
"Q83": {
"direction": "OUT"
},
"Q84": {
"direction": "OUT"
},
"Q85": {
"direction": "OUT"
},
"Q86": {
"direction": "OUT"
},
"Q87": {
"direction": "OUT"
},
"Q90": {
"direction": "OUT"
},
"Q91": {
"direction": "OUT"
},
"Q92": {
"direction": "OUT"
},
"Q93": {
"direction": "OUT"
},
"Q94": {
"direction": "OUT"
},
"Q95": {
"direction": "OUT"
},
"Q96": {
"direction": "OUT"
},
"Q97": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN0": {
"direction": "IN"
},
"SCANIN1": {
"direction": "IN"
},
"SCANIN2": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"SCANOUT1": {
"direction": "OUT"
},
"SCANOUT2": {
"direction": "OUT"
},
"SCANOUT3": {
"direction": "OUT"
},
"TESTMODEB": {
"direction": "IN"
},
"TESTREADDISB": {
"direction": "IN"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"WREN": {
"direction": "IN"
}
},
"site_pips": {},
"type": "IN_FIFO"
}

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zynq7/site_type_IOB33.json Normal file
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{
"site_pins": {
"DIFFI_IN": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"IBUFDISABLE": {
"direction": "IN"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"PD_INT_EN": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
}
},
"site_pips": {
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "IOB33"
}

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zynq7/site_type_IOB33M.json Normal file
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{
"site_pins": {
"DIFFI_IN": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"IBUFDISABLE": {
"direction": "IN"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"PD_INT_EN": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
}
},
"site_pips": {
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFO_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"O_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "IOB33M"
}

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zynq7/site_type_IOB33S.json Normal file
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{
"site_pins": {
"DIFFI_IN": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"IBUFDISABLE": {
"direction": "IN"
},
"INTERMDISABLE": {
"direction": "IN"
},
"KEEPER_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
},
"O_IN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"PD_INT_EN": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
}
},
"site_pips": {
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFO_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"OUTMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUTMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
}
},
"type": "IOB33S"
}

9
zynq7/site_type_IOPAD.json Normal file
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@ -0,0 +1,9 @@
{
"site_pins": {
"IO": {
"direction": "INOUT"
}
},
"site_pips": {},
"type": "IOPAD"
}

9
zynq7/site_type_IPAD.json Normal file
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@ -0,0 +1,9 @@
{
"site_pins": {
"O": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "IPAD"
}

545
zynq7/site_type_MMCME2_ADV.json Normal file
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@ -0,0 +1,545 @@
{
"site_pins": {
"CLKFBIN": {
"direction": "IN"
},
"CLKFBOUT": {
"direction": "OUT"
},
"CLKFBOUTB": {
"direction": "OUT"
},
"CLKFBSTOPPED": {
"direction": "OUT"
},
"CLKIN1": {
"direction": "IN"
},
"CLKIN2": {
"direction": "IN"
},
"CLKINSEL": {
"direction": "IN"
},
"CLKINSTOPPED": {
"direction": "OUT"
},
"CLKOUT0": {
"direction": "OUT"
},
"CLKOUT0B": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"CLKOUT1B": {
"direction": "OUT"
},
"CLKOUT2": {
"direction": "OUT"
},
"CLKOUT2B": {
"direction": "OUT"
},
"CLKOUT3": {
"direction": "OUT"
},
"CLKOUT3B": {
"direction": "OUT"
},
"CLKOUT4": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"CLKOUT6": {
"direction": "OUT"
},
"DADDR0": {
"direction": "IN"
},
"DADDR1": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"DADDR3": {
"direction": "IN"
},
"DADDR4": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"DCLK": {
"direction": "IN"
},
"DEN": {
"direction": "IN"
},
"DI0": {
"direction": "IN"
},
"DI1": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"DI2": {
"direction": "IN"
},
"DI3": {
"direction": "IN"
},
"DI4": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"DI9": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
},
"PSCLK": {
"direction": "IN"
},
"PSDONE": {
"direction": "OUT"
},
"PSEN": {
"direction": "IN"
},
"PSINCDEC": {
"direction": "IN"
},
"PWRDWN": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"TESTIN16": {
"direction": "IN"
},
"TESTIN17": {
"direction": "IN"
},
"TESTIN18": {
"direction": "IN"
},
"TESTIN19": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN20": {
"direction": "IN"
},
"TESTIN21": {
"direction": "IN"
},
"TESTIN22": {
"direction": "IN"
},
"TESTIN23": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTIN25": {
"direction": "IN"
},
"TESTIN26": {
"direction": "IN"
},
"TESTIN27": {
"direction": "IN"
},
"TESTIN28": {
"direction": "IN"
},
"TESTIN29": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTIN30": {
"direction": "IN"
},
"TESTIN31": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTOUT12": {
"direction": "OUT"
},
"TESTOUT13": {
"direction": "OUT"
},
"TESTOUT14": {
"direction": "OUT"
},
"TESTOUT15": {
"direction": "OUT"
},
"TESTOUT16": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"TESTOUT19": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"TESTOUT21": {
"direction": "OUT"
},
"TESTOUT22": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"TESTOUT26": {
"direction": "OUT"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTOUT28": {
"direction": "OUT"
},
"TESTOUT29": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT30": {
"direction": "OUT"
},
"TESTOUT31": {
"direction": "OUT"
},
"TESTOUT32": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTOUT34": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"TESTOUT36": {
"direction": "OUT"
},
"TESTOUT37": {
"direction": "OUT"
},
"TESTOUT38": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT41": {
"direction": "OUT"
},
"TESTOUT42": {
"direction": "OUT"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"TESTOUT45": {
"direction": "OUT"
},
"TESTOUT46": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTOUT48": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT50": {
"direction": "OUT"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
},
"TESTOUT53": {
"direction": "OUT"
},
"TESTOUT54": {
"direction": "OUT"
},
"TESTOUT55": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"TESTOUT57": {
"direction": "OUT"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTOUT60": {
"direction": "OUT"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT62": {
"direction": "OUT"
},
"TESTOUT63": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTOUT8": {
"direction": "OUT"
},
"TESTOUT9": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
}
},
"site_pips": {
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PSENINV:PSEN": {
"from_pin": "PSEN",
"to_pin": "OUT"
},
"PSENINV:PSEN_B": {
"from_pin": "PSEN_B",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC": {
"from_pin": "PSINCDEC",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC_B": {
"from_pin": "PSINCDEC_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"type": "MMCME2_ADV"
}

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{
"site_pins": {
"CLK": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"CLKDIV": {
"direction": "IN"
},
"CLKDIVB": {
"direction": "IN"
},
"CLKDIVF": {
"direction": "IN"
},
"CLKDIVFB": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"D7": {
"direction": "IN"
},
"D8": {
"direction": "IN"
},
"IOCLKGLITCH": {
"direction": "OUT"
},
"OCE": {
"direction": "IN"
},
"OFB": {
"direction": "OUT"
},
"OQ": {
"direction": "OUT"
},
"REV": {
"direction": "IN"
},
"SHIFTIN1": {
"direction": "IN"
},
"SHIFTIN2": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"T1": {
"direction": "IN"
},
"T2": {
"direction": "IN"
},
"T3": {
"direction": "IN"
},
"T4": {
"direction": "IN"
},
"TBYTEIN": {
"direction": "IN"
},
"TBYTEOUT": {
"direction": "OUT"
},
"TCE": {
"direction": "IN"
},
"TFB": {
"direction": "OUT"
},
"TQ": {
"direction": "OUT"
}
},
"site_pips": {
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"D1INV:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"D1INV:D1_B": {
"from_pin": "D1_B",
"to_pin": "OUT"
},
"D2INV:D2": {
"from_pin": "D2",
"to_pin": "OUT"
},
"D2INV:D2_B": {
"from_pin": "D2_B",
"to_pin": "OUT"
},
"O1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OMUX:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"OMUX:OUTFF": {
"from_pin": "OUTFF",
"to_pin": "OUT"
},
"OQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"T1INV:T1_B": {
"from_pin": "T1_B",
"to_pin": "OUT"
},
"T1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T2INV:T2": {
"from_pin": "T2",
"to_pin": "OUT"
},
"T2INV:T2_B": {
"from_pin": "T2_B",
"to_pin": "OUT"
},
"TCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TMUX:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"TMUX:TFF": {
"from_pin": "TFF",
"to_pin": "OUT"
},
"TQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
}
},
"type": "OLOGICE3"
}

453
zynq7/site_type_OUT_FIFO.json Normal file
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@ -0,0 +1,453 @@
{
"site_pins": {
"ALMOSTEMPTY": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"D00": {
"direction": "IN"
},
"D01": {
"direction": "IN"
},
"D02": {
"direction": "IN"
},
"D03": {
"direction": "IN"
},
"D04": {
"direction": "IN"
},
"D05": {
"direction": "IN"
},
"D06": {
"direction": "IN"
},
"D07": {
"direction": "IN"
},
"D10": {
"direction": "IN"
},
"D11": {
"direction": "IN"
},
"D12": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"D14": {
"direction": "IN"
},
"D15": {
"direction": "IN"
},
"D16": {
"direction": "IN"
},
"D17": {
"direction": "IN"
},
"D20": {
"direction": "IN"
},
"D21": {
"direction": "IN"
},
"D22": {
"direction": "IN"
},
"D23": {
"direction": "IN"
},
"D24": {
"direction": "IN"
},
"D25": {
"direction": "IN"
},
"D26": {
"direction": "IN"
},
"D27": {
"direction": "IN"
},
"D30": {
"direction": "IN"
},
"D31": {
"direction": "IN"
},
"D32": {
"direction": "IN"
},
"D33": {
"direction": "IN"
},
"D34": {
"direction": "IN"
},
"D35": {
"direction": "IN"
},
"D36": {
"direction": "IN"
},
"D37": {
"direction": "IN"
},
"D40": {
"direction": "IN"
},
"D41": {
"direction": "IN"
},
"D42": {
"direction": "IN"
},
"D43": {
"direction": "IN"
},
"D44": {
"direction": "IN"
},
"D45": {
"direction": "IN"
},
"D46": {
"direction": "IN"
},
"D47": {
"direction": "IN"
},
"D50": {
"direction": "IN"
},
"D51": {
"direction": "IN"
},
"D52": {
"direction": "IN"
},
"D53": {
"direction": "IN"
},
"D54": {
"direction": "IN"
},
"D55": {
"direction": "IN"
},
"D56": {
"direction": "IN"
},
"D57": {
"direction": "IN"
},
"D60": {
"direction": "IN"
},
"D61": {
"direction": "IN"
},
"D62": {
"direction": "IN"
},
"D63": {
"direction": "IN"
},
"D64": {
"direction": "IN"
},
"D65": {
"direction": "IN"
},
"D66": {
"direction": "IN"
},
"D67": {
"direction": "IN"
},
"D70": {
"direction": "IN"
},
"D71": {
"direction": "IN"
},
"D72": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D74": {
"direction": "IN"
},
"D75": {
"direction": "IN"
},
"D76": {
"direction": "IN"
},
"D77": {
"direction": "IN"
},
"D80": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"D82": {
"direction": "IN"
},
"D83": {
"direction": "IN"
},
"D84": {
"direction": "IN"
},
"D85": {
"direction": "IN"
},
"D86": {
"direction": "IN"
},
"D87": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"D91": {
"direction": "IN"
},
"D92": {
"direction": "IN"
},
"D93": {
"direction": "IN"
},
"D94": {
"direction": "IN"
},
"D95": {
"direction": "IN"
},
"D96": {
"direction": "IN"
},
"D97": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"Q00": {
"direction": "OUT"
},
"Q01": {
"direction": "OUT"
},
"Q02": {
"direction": "OUT"
},
"Q03": {
"direction": "OUT"
},
"Q10": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
},
"Q12": {
"direction": "OUT"
},
"Q13": {
"direction": "OUT"
},
"Q20": {
"direction": "OUT"
},
"Q21": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"Q23": {
"direction": "OUT"
},
"Q30": {
"direction": "OUT"
},
"Q31": {
"direction": "OUT"
},
"Q32": {
"direction": "OUT"
},
"Q33": {
"direction": "OUT"
},
"Q40": {
"direction": "OUT"
},
"Q41": {
"direction": "OUT"
},
"Q42": {
"direction": "OUT"
},
"Q43": {
"direction": "OUT"
},
"Q50": {
"direction": "OUT"
},
"Q51": {
"direction": "OUT"
},
"Q52": {
"direction": "OUT"
},
"Q53": {
"direction": "OUT"
},
"Q54": {
"direction": "OUT"
},
"Q55": {
"direction": "OUT"
},
"Q56": {
"direction": "OUT"
},
"Q57": {
"direction": "OUT"
},
"Q60": {
"direction": "OUT"
},
"Q61": {
"direction": "OUT"
},
"Q62": {
"direction": "OUT"
},
"Q63": {
"direction": "OUT"
},
"Q64": {
"direction": "OUT"
},
"Q65": {
"direction": "OUT"
},
"Q66": {
"direction": "OUT"
},
"Q67": {
"direction": "OUT"
},
"Q70": {
"direction": "OUT"
},
"Q71": {
"direction": "OUT"
},
"Q72": {
"direction": "OUT"
},
"Q73": {
"direction": "OUT"
},
"Q80": {
"direction": "OUT"
},
"Q81": {
"direction": "OUT"
},
"Q82": {
"direction": "OUT"
},
"Q83": {
"direction": "OUT"
},
"Q90": {
"direction": "OUT"
},
"Q91": {
"direction": "OUT"
},
"Q92": {
"direction": "OUT"
},
"Q93": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN0": {
"direction": "IN"
},
"SCANIN1": {
"direction": "IN"
},
"SCANIN2": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"SCANOUT1": {
"direction": "OUT"
},
"SCANOUT2": {
"direction": "OUT"
},
"SCANOUT3": {
"direction": "OUT"
},
"TESTMODEB": {
"direction": "IN"
},
"TESTREADDISB": {
"direction": "IN"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"WREN": {
"direction": "IN"
}
},
"site_pips": {},
"type": "OUT_FIFO"
}

291
zynq7/site_type_PHASER_IN_PHY.json Normal file
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@ -0,0 +1,291 @@
{
"site_pins": {
"BURSTPENDING": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"COUNTERREADEN": {
"direction": "IN"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"DIVIDERST": {
"direction": "IN"
},
"DQSFOUND": {
"direction": "OUT"
},
"DQSOUTOFRANGE": {
"direction": "OUT"
},
"EDGEADV": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"ENCALIB1": {
"direction": "IN"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"ENSTG1": {
"direction": "IN"
},
"ENSTG1ADJUSTB": {
"direction": "IN"
},
"FINEENABLE": {
"direction": "IN"
},
"FINEINC": {
"direction": "IN"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"FREQREFCLK": {
"direction": "IN"
},
"ICLK": {
"direction": "OUT"
},
"ICLKDIV": {
"direction": "OUT"
},
"ISERDESRST": {
"direction": "OUT"
},
"MEMREFCLK": {
"direction": "IN"
},
"PHASELOCKED": {
"direction": "OUT"
},
"PHASEREFCLK": {
"direction": "IN"
},
"RANKSEL0": {
"direction": "IN"
},
"RANKSEL1": {
"direction": "IN"
},
"RANKSELPHY0": {
"direction": "IN"
},
"RANKSELPHY1": {
"direction": "IN"
},
"RCLK": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"RSTDQSFIND": {
"direction": "IN"
},
"SCANCLK": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"SELCALORSTG1": {
"direction": "IN"
},
"STG1INCDEC": {
"direction": "IN"
},
"STG1LOAD": {
"direction": "IN"
},
"STG1OVERFLOW": {
"direction": "OUT"
},
"STG1READ": {
"direction": "IN"
},
"STG1REGL0": {
"direction": "IN"
},
"STG1REGL1": {
"direction": "IN"
},
"STG1REGL2": {
"direction": "IN"
},
"STG1REGL3": {
"direction": "IN"
},
"STG1REGL4": {
"direction": "IN"
},
"STG1REGL5": {
"direction": "IN"
},
"STG1REGL6": {
"direction": "IN"
},
"STG1REGL7": {
"direction": "IN"
},
"STG1REGL8": {
"direction": "IN"
},
"STG1REGR0": {
"direction": "OUT"
},
"STG1REGR1": {
"direction": "OUT"
},
"STG1REGR2": {
"direction": "OUT"
},
"STG1REGR3": {
"direction": "OUT"
},
"STG1REGR4": {
"direction": "OUT"
},
"STG1REGR5": {
"direction": "OUT"
},
"STG1REGR6": {
"direction": "OUT"
},
"STG1REGR7": {
"direction": "OUT"
},
"STG1REGR8": {
"direction": "OUT"
},
"SYNCIN": {
"direction": "IN"
},
"SYSCLK": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"WRENABLE": {
"direction": "OUT"
}
},
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"type": "PHASER_IN_PHY"
}

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zynq7/site_type_PHASER_OUT_PHY.json Normal file
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{
"site_pins": {
"BURSTPENDING": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"COARSEENABLE": {
"direction": "IN"
},
"COARSEINC": {
"direction": "IN"
},
"COARSEOVERFLOW": {
"direction": "OUT"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"COUNTERLOADVAL6": {
"direction": "IN"
},
"COUNTERLOADVAL7": {
"direction": "IN"
},
"COUNTERLOADVAL8": {
"direction": "IN"
},
"COUNTERREADEN": {
"direction": "IN"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"COUNTERREADVAL6": {
"direction": "OUT"
},
"COUNTERREADVAL7": {
"direction": "OUT"
},
"COUNTERREADVAL8": {
"direction": "OUT"
},
"CTSBUS0": {
"direction": "OUT"
},
"CTSBUS1": {
"direction": "OUT"
},
"DIVIDERST": {
"direction": "IN"
},
"DQSBUS0": {
"direction": "OUT"
},
"DQSBUS1": {
"direction": "OUT"
},
"DTSBUS0": {
"direction": "OUT"
},
"DTSBUS1": {
"direction": "OUT"
},
"EDGEADV": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"ENCALIB1": {
"direction": "IN"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"FINEENABLE": {
"direction": "IN"
},
"FINEINC": {
"direction": "IN"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"FREQREFCLK": {
"direction": "IN"
},
"MEMREFCLK": {
"direction": "IN"
},
"OCLK": {
"direction": "OUT"
},
"OCLKDELAYED": {
"direction": "OUT"
},
"OCLKDIV": {
"direction": "OUT"
},
"OSERDESRST": {
"direction": "OUT"
},
"PHASEREFCLK": {
"direction": "IN"
},
"RDENABLE": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"SCANCLK": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"SELFINEOCLKDELAY": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"SYSCLK": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
}
},
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"type": "PHASER_OUT_PHY"
}

89
zynq7/site_type_PHASER_REF.json Normal file
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{
"site_pins": {
"CLKIN": {
"direction": "IN"
},
"CLKOUT": {
"direction": "OUT"
},
"LOCKED": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
}
},
"site_pips": {
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"type": "PHASER_REF"
}

318
zynq7/site_type_PHY_CONTROL.json Normal file
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{
"site_pins": {
"AUXOUTPUT0": {
"direction": "OUT"
},
"AUXOUTPUT1": {
"direction": "OUT"
},
"AUXOUTPUT2": {
"direction": "OUT"
},
"AUXOUTPUT3": {
"direction": "OUT"
},
"INBURSTPENDING0": {
"direction": "OUT"
},
"INBURSTPENDING1": {
"direction": "OUT"
},
"INBURSTPENDING2": {
"direction": "OUT"
},
"INBURSTPENDING3": {
"direction": "OUT"
},
"INRANKA0": {
"direction": "OUT"
},
"INRANKA1": {
"direction": "OUT"
},
"INRANKB0": {
"direction": "OUT"
},
"INRANKB1": {
"direction": "OUT"
},
"INRANKC0": {
"direction": "OUT"
},
"INRANKC1": {
"direction": "OUT"
},
"INRANKD0": {
"direction": "OUT"
},
"INRANKD1": {
"direction": "OUT"
},
"MEMREFCLK": {
"direction": "IN"
},
"OUTBURSTPENDING0": {
"direction": "OUT"
},
"OUTBURSTPENDING1": {
"direction": "OUT"
},
"OUTBURSTPENDING2": {
"direction": "OUT"
},
"OUTBURSTPENDING3": {
"direction": "OUT"
},
"PCENABLECALIB0": {
"direction": "OUT"
},
"PCENABLECALIB1": {
"direction": "OUT"
},
"PHYCLK": {
"direction": "IN"
},
"PHYCTLALMOSTFULL": {
"direction": "OUT"
},
"PHYCTLEMPTY": {
"direction": "OUT"
},
"PHYCTLFULL": {
"direction": "OUT"
},
"PHYCTLMSTREMPTY": {
"direction": "IN"
},
"PHYCTLREADY": {
"direction": "OUT"
},
"PHYCTLWD0": {
"direction": "IN"
},
"PHYCTLWD1": {
"direction": "IN"
},
"PHYCTLWD10": {
"direction": "IN"
},
"PHYCTLWD11": {
"direction": "IN"
},
"PHYCTLWD12": {
"direction": "IN"
},
"PHYCTLWD13": {
"direction": "IN"
},
"PHYCTLWD14": {
"direction": "IN"
},
"PHYCTLWD15": {
"direction": "IN"
},
"PHYCTLWD16": {
"direction": "IN"
},
"PHYCTLWD17": {
"direction": "IN"
},
"PHYCTLWD18": {
"direction": "IN"
},
"PHYCTLWD19": {
"direction": "IN"
},
"PHYCTLWD2": {
"direction": "IN"
},
"PHYCTLWD20": {
"direction": "IN"
},
"PHYCTLWD21": {
"direction": "IN"
},
"PHYCTLWD22": {
"direction": "IN"
},
"PHYCTLWD23": {
"direction": "IN"
},
"PHYCTLWD24": {
"direction": "IN"
},
"PHYCTLWD25": {
"direction": "IN"
},
"PHYCTLWD26": {
"direction": "IN"
},
"PHYCTLWD27": {
"direction": "IN"
},
"PHYCTLWD28": {
"direction": "IN"
},
"PHYCTLWD29": {
"direction": "IN"
},
"PHYCTLWD3": {
"direction": "IN"
},
"PHYCTLWD30": {
"direction": "IN"
},
"PHYCTLWD31": {
"direction": "IN"
},
"PHYCTLWD4": {
"direction": "IN"
},
"PHYCTLWD5": {
"direction": "IN"
},
"PHYCTLWD6": {
"direction": "IN"
},
"PHYCTLWD7": {
"direction": "IN"
},
"PHYCTLWD8": {
"direction": "IN"
},
"PHYCTLWD9": {
"direction": "IN"
},
"PHYCTLWRENABLE": {
"direction": "IN"
},
"PLLLOCK": {
"direction": "IN"
},
"READCALIBENABLE": {
"direction": "IN"
},
"REFDLLLOCK": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"SCANENABLEN": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"TESTINPUT0": {
"direction": "IN"
},
"TESTINPUT1": {
"direction": "IN"
},
"TESTINPUT10": {
"direction": "IN"
},
"TESTINPUT11": {
"direction": "IN"
},
"TESTINPUT12": {
"direction": "IN"
},
"TESTINPUT13": {
"direction": "IN"
},
"TESTINPUT14": {
"direction": "IN"
},
"TESTINPUT15": {
"direction": "IN"
},
"TESTINPUT2": {
"direction": "IN"
},
"TESTINPUT3": {
"direction": "IN"
},
"TESTINPUT4": {
"direction": "IN"
},
"TESTINPUT5": {
"direction": "IN"
},
"TESTINPUT6": {
"direction": "IN"
},
"TESTINPUT7": {
"direction": "IN"
},
"TESTINPUT8": {
"direction": "IN"
},
"TESTINPUT9": {
"direction": "IN"
},
"TESTOUTPUT0": {
"direction": "OUT"
},
"TESTOUTPUT1": {
"direction": "OUT"
},
"TESTOUTPUT10": {
"direction": "OUT"
},
"TESTOUTPUT11": {
"direction": "OUT"
},
"TESTOUTPUT12": {
"direction": "OUT"
},
"TESTOUTPUT13": {
"direction": "OUT"
},
"TESTOUTPUT14": {
"direction": "OUT"
},
"TESTOUTPUT15": {
"direction": "OUT"
},
"TESTOUTPUT2": {
"direction": "OUT"
},
"TESTOUTPUT3": {
"direction": "OUT"
},
"TESTOUTPUT4": {
"direction": "OUT"
},
"TESTOUTPUT5": {
"direction": "OUT"
},
"TESTOUTPUT6": {
"direction": "OUT"
},
"TESTOUTPUT7": {
"direction": "OUT"
},
"TESTOUTPUT8": {
"direction": "OUT"
},
"TESTOUTPUT9": {
"direction": "OUT"
},
"TESTSELECT0": {
"direction": "IN"
},
"TESTSELECT1": {
"direction": "IN"
},
"TESTSELECT2": {
"direction": "IN"
},
"WRITECALIBENABLE": {
"direction": "IN"
}
},
"site_pips": {},
"type": "PHY_CONTROL"
}

493
zynq7/site_type_PLLE2_ADV.json Normal file
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{
"site_pins": {
"CLKFBIN": {
"direction": "IN"
},
"CLKFBOUT": {
"direction": "OUT"
},
"CLKIN1": {
"direction": "IN"
},
"CLKIN2": {
"direction": "IN"
},
"CLKINSEL": {
"direction": "IN"
},
"CLKOUT0": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"CLKOUT2": {
"direction": "OUT"
},
"CLKOUT3": {
"direction": "OUT"
},
"CLKOUT4": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"DADDR0": {
"direction": "IN"
},
"DADDR1": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"DADDR3": {
"direction": "IN"
},
"DADDR4": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"DCLK": {
"direction": "IN"
},
"DEN": {
"direction": "IN"
},
"DI0": {
"direction": "IN"
},
"DI1": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"DI2": {
"direction": "IN"
},
"DI3": {
"direction": "IN"
},
"DI4": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"DI9": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"TESTIN16": {
"direction": "IN"
},
"TESTIN17": {
"direction": "IN"
},
"TESTIN18": {
"direction": "IN"
},
"TESTIN19": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"TESTIN20": {
"direction": "IN"
},
"TESTIN21": {
"direction": "IN"
},
"TESTIN22": {
"direction": "IN"
},
"TESTIN23": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTIN25": {
"direction": "IN"
},
"TESTIN26": {
"direction": "IN"
},
"TESTIN27": {
"direction": "IN"
},
"TESTIN28": {
"direction": "IN"
},
"TESTIN29": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTIN30": {
"direction": "IN"
},
"TESTIN31": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTOUT12": {
"direction": "OUT"
},
"TESTOUT13": {
"direction": "OUT"
},
"TESTOUT14": {
"direction": "OUT"
},
"TESTOUT15": {
"direction": "OUT"
},
"TESTOUT16": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"TESTOUT19": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"TESTOUT21": {
"direction": "OUT"
},
"TESTOUT22": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"TESTOUT26": {
"direction": "OUT"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTOUT28": {
"direction": "OUT"
},
"TESTOUT29": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT30": {
"direction": "OUT"
},
"TESTOUT31": {
"direction": "OUT"
},
"TESTOUT32": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTOUT34": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"TESTOUT36": {
"direction": "OUT"
},
"TESTOUT37": {
"direction": "OUT"
},
"TESTOUT38": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT41": {
"direction": "OUT"
},
"TESTOUT42": {
"direction": "OUT"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"TESTOUT45": {
"direction": "OUT"
},
"TESTOUT46": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTOUT48": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTOUT50": {
"direction": "OUT"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
},
"TESTOUT53": {
"direction": "OUT"
},
"TESTOUT54": {
"direction": "OUT"
},
"TESTOUT55": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"TESTOUT57": {
"direction": "OUT"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTOUT60": {
"direction": "OUT"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT62": {
"direction": "OUT"
},
"TESTOUT63": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTOUT8": {
"direction": "OUT"
},
"TESTOUT9": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
}
},
"site_pips": {
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"type": "PLLE2_ADV"
}

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zynq7/site_type_PMV2.json Normal file
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{
"site_pins": {
"A0": {
"direction": "IN"
},
"A1": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"EN": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"ODIV2": {
"direction": "OUT"
},
"ODIV4": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "PMV2"
}

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zynq7/site_type_PS7.json Normal file
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zynq7/site_type_RAMB18E1.json Normal file
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{
"site_pins": {
"ADDRARDADDR0": {
"direction": "IN"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"CLKARDCLK": {
"direction": "IN"
},
"CLKBWRCLK": {
"direction": "IN"
},
"DIADI0": {
"direction": "IN"
},
"DIADI1": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"DIADI11": {
"direction": "IN"
},
"DIADI12": {
"direction": "IN"
},
"DIADI13": {
"direction": "IN"
},
"DIADI14": {
"direction": "IN"
},
"DIADI15": {
"direction": "IN"
},
"DIADI2": {
"direction": "IN"
},
"DIADI3": {
"direction": "IN"
},
"DIADI4": {
"direction": "IN"
},
"DIADI5": {
"direction": "IN"
},
"DIADI6": {
"direction": "IN"
},
"DIADI7": {
"direction": "IN"
},
"DIADI8": {
"direction": "IN"
},
"DIADI9": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
},
"DIBDI11": {
"direction": "IN"
},
"DIBDI12": {
"direction": "IN"
},
"DIBDI13": {
"direction": "IN"
},
"DIBDI14": {
"direction": "IN"
},
"DIBDI15": {
"direction": "IN"
},
"DIBDI2": {
"direction": "IN"
},
"DIBDI3": {
"direction": "IN"
},
"DIBDI4": {
"direction": "IN"
},
"DIBDI5": {
"direction": "IN"
},
"DIBDI6": {
"direction": "IN"
},
"DIBDI7": {
"direction": "IN"
},
"DIBDI8": {
"direction": "IN"
},
"DIBDI9": {
"direction": "IN"
},
"DIPADIP0": {
"direction": "IN"
},
"DIPADIP1": {
"direction": "IN"
},
"DIPBDIP0": {
"direction": "IN"
},
"DIPBDIP1": {
"direction": "IN"
},
"DOADO0": {
"direction": "OUT"
},
"DOADO1": {
"direction": "OUT"
},
"DOADO10": {
"direction": "OUT"
},
"DOADO11": {
"direction": "OUT"
},
"DOADO12": {
"direction": "OUT"
},
"DOADO13": {
"direction": "OUT"
},
"DOADO14": {
"direction": "OUT"
},
"DOADO15": {
"direction": "OUT"
},
"DOADO2": {
"direction": "OUT"
},
"DOADO3": {
"direction": "OUT"
},
"DOADO4": {
"direction": "OUT"
},
"DOADO5": {
"direction": "OUT"
},
"DOADO6": {
"direction": "OUT"
},
"DOADO7": {
"direction": "OUT"
},
"DOADO8": {
"direction": "OUT"
},
"DOADO9": {
"direction": "OUT"
},
"DOBDO0": {
"direction": "OUT"
},
"DOBDO1": {
"direction": "OUT"
},
"DOBDO10": {
"direction": "OUT"
},
"DOBDO11": {
"direction": "OUT"
},
"DOBDO12": {
"direction": "OUT"
},
"DOBDO13": {
"direction": "OUT"
},
"DOBDO14": {
"direction": "OUT"
},
"DOBDO15": {
"direction": "OUT"
},
"DOBDO2": {
"direction": "OUT"
},
"DOBDO3": {
"direction": "OUT"
},
"DOBDO4": {
"direction": "OUT"
},
"DOBDO5": {
"direction": "OUT"
},
"DOBDO6": {
"direction": "OUT"
},
"DOBDO7": {
"direction": "OUT"
},
"DOBDO8": {
"direction": "OUT"
},
"DOBDO9": {
"direction": "OUT"
},
"DOPADOP0": {
"direction": "OUT"
},
"DOPADOP1": {
"direction": "OUT"
},
"DOPBDOP0": {
"direction": "OUT"
},
"DOPBDOP1": {
"direction": "OUT"
},
"EMPTY": {
"direction": "OUT"
},
"ENARDEN": {
"direction": "IN"
},
"ENBWREN": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"RDCOUNT0": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"RDCOUNT11": {
"direction": "OUT"
},
"RDCOUNT2": {
"direction": "OUT"
},
"RDCOUNT3": {
"direction": "OUT"
},
"RDCOUNT4": {
"direction": "OUT"
},
"RDCOUNT5": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"RDCOUNT7": {
"direction": "OUT"
},
"RDCOUNT8": {
"direction": "OUT"
},
"RDCOUNT9": {
"direction": "OUT"
},
"RDERR": {
"direction": "OUT"
},
"REGCEAREGCE": {
"direction": "IN"
},
"REGCEB": {
"direction": "IN"
},
"REGCLKARDRCLK": {
"direction": "IN"
},
"REGCLKB": {
"direction": "IN"
},
"RSTRAMARSTRAM": {
"direction": "IN"
},
"RSTRAMB": {
"direction": "IN"
},
"RSTREGARSTREG": {
"direction": "IN"
},
"RSTREGB": {
"direction": "IN"
},
"WEA0": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"WEA2": {
"direction": "IN"
},
"WEA3": {
"direction": "IN"
},
"WEBWE0": {
"direction": "IN"
},
"WEBWE1": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"WEBWE3": {
"direction": "IN"
},
"WEBWE4": {
"direction": "IN"
},
"WEBWE5": {
"direction": "IN"
},
"WEBWE6": {
"direction": "IN"
},
"WEBWE7": {
"direction": "IN"
},
"WRCOUNT0": {
"direction": "OUT"
},
"WRCOUNT1": {
"direction": "OUT"
},
"WRCOUNT10": {
"direction": "OUT"
},
"WRCOUNT11": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"WRCOUNT3": {
"direction": "OUT"
},
"WRCOUNT4": {
"direction": "OUT"
},
"WRCOUNT5": {
"direction": "OUT"
},
"WRCOUNT6": {
"direction": "OUT"
},
"WRCOUNT7": {
"direction": "OUT"
},
"WRCOUNT8": {
"direction": "OUT"
},
"WRCOUNT9": {
"direction": "OUT"
},
"WRERR": {
"direction": "OUT"
}
},
"site_pips": {
"CLKARDCLKINV:CLKARDCLK": {
"from_pin": "CLKARDCLK",
"to_pin": "OUT"
},
"CLKARDCLKINV:CLKARDCLK_B": {
"from_pin": "CLKARDCLK_B",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK": {
"from_pin": "CLKBWRCLK",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK_B": {
"from_pin": "CLKBWRCLK_B",
"to_pin": "OUT"
},
"ENARDENINV:ENARDEN": {
"from_pin": "ENARDEN",
"to_pin": "OUT"
},
"ENARDENINV:ENARDEN_B": {
"from_pin": "ENARDEN_B",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN": {
"from_pin": "ENBWREN",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN_B": {
"from_pin": "ENBWREN_B",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK": {
"from_pin": "REGCLKARDRCLK",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK_B": {
"from_pin": "REGCLKARDRCLK_B",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB": {
"from_pin": "REGCLKB",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB_B": {
"from_pin": "REGCLKB_B",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM": {
"from_pin": "RSTRAMARSTRAM",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": {
"from_pin": "RSTRAMARSTRAM_B",
"to_pin": "OUT"
},
"RSTRAMBINV:RSTRAMB": {
"from_pin": "RSTRAMB",
"to_pin": "OUT"
},
"RSTRAMBINV:RSTRAMB_B": {
"from_pin": "RSTRAMB_B",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG": {
"from_pin": "RSTREGARSTREG",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG_B": {
"from_pin": "RSTREGARSTREG_B",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB": {
"from_pin": "RSTREGB",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB_B": {
"from_pin": "RSTREGB_B",
"to_pin": "OUT"
}
},
"type": "RAMB18E1"
}

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zynq7/site_type_RAMBFIFO36E1.json Normal file
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zynq7/site_type_SLICEL.json Normal file
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{
"site_pins": {
"A": {
"direction": "OUT"
},
"A1": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"A3": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"A5": {
"direction": "IN"
},
"A6": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"AQ": {
"direction": "OUT"
},
"AX": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"B1": {
"direction": "IN"
},
"B2": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"B4": {
"direction": "IN"
},
"B5": {
"direction": "IN"
},
"B6": {
"direction": "IN"
},
"BMUX": {
"direction": "OUT"
},
"BQ": {
"direction": "OUT"
},
"BX": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"C1": {
"direction": "IN"
},
"C2": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"C4": {
"direction": "IN"
},
"C5": {
"direction": "IN"
},
"C6": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"CIN": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"CMUX": {
"direction": "OUT"
},
"COUT": {
"direction": "OUT"
},
"CQ": {
"direction": "OUT"
},
"CX": {
"direction": "IN"
},
"D": {
"direction": "OUT"
},
"D1": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"DQ": {
"direction": "OUT"
},
"DX": {
"direction": "IN"
},
"SR": {
"direction": "IN"
}
},
"site_pips": {
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
}
},
"type": "SLICEL"
}

769
zynq7/site_type_SLICEM.json Normal file
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@ -0,0 +1,769 @@
{
"site_pins": {
"A": {
"direction": "OUT"
},
"A1": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"A3": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"A5": {
"direction": "IN"
},
"A6": {
"direction": "IN"
},
"AI": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"AQ": {
"direction": "OUT"
},
"AX": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"B1": {
"direction": "IN"
},
"B2": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"B4": {
"direction": "IN"
},
"B5": {
"direction": "IN"
},
"B6": {
"direction": "IN"
},
"BI": {
"direction": "IN"
},
"BMUX": {
"direction": "OUT"
},
"BQ": {
"direction": "OUT"
},
"BX": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"C1": {
"direction": "IN"
},
"C2": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"C4": {
"direction": "IN"
},
"C5": {
"direction": "IN"
},
"C6": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"CI": {
"direction": "IN"
},
"CIN": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"CMUX": {
"direction": "OUT"
},
"COUT": {
"direction": "OUT"
},
"CQ": {
"direction": "OUT"
},
"CX": {
"direction": "IN"
},
"D": {
"direction": "OUT"
},
"D1": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"DI": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"DQ": {
"direction": "OUT"
},
"DX": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"WE": {
"direction": "IN"
}
},
"site_pips": {
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"ADI1MUX:AI": {
"from_pin": "AI",
"to_pin": "OUT"
},
"ADI1MUX:BDI1": {
"from_pin": "BDI1",
"to_pin": "OUT"
},
"ADI1MUX:BMC31": {
"from_pin": "BMC31",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BDI1MUX:BI": {
"from_pin": "BI",
"to_pin": "OUT"
},
"BDI1MUX:CMC31": {
"from_pin": "CMC31",
"to_pin": "OUT"
},
"BDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CDI1MUX:CI": {
"from_pin": "CI",
"to_pin": "OUT"
},
"CDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"CDI1MUX:DMC31": {
"from_pin": "DMC31",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"DFFMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"DOUTMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"WA7USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"WA8USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"WEMUX:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"WEMUX:WE": {
"from_pin": "WE",
"to_pin": "OUT"
}
},
"type": "SLICEM"
}

45
zynq7/site_type_STARTUP.json Normal file
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@ -0,0 +1,45 @@
{
"site_pins": {
"CFGCLK": {
"direction": "OUT"
},
"CFGMCLK": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"EOS": {
"direction": "OUT"
},
"GSR": {
"direction": "IN"
},
"GTS": {
"direction": "IN"
},
"KEYCLEARB": {
"direction": "IN"
},
"PACK": {
"direction": "IN"
},
"PREQ": {
"direction": "OUT"
},
"USRCCLKO": {
"direction": "IN"
},
"USRCCLKTS": {
"direction": "IN"
},
"USRDONEO": {
"direction": "IN"
},
"USRDONETS": {
"direction": "IN"
}
},
"site_pips": {},
"type": "STARTUP"
}

12
zynq7/site_type_TIEOFF.json Normal file
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@ -0,0 +1,12 @@
{
"site_pins": {
"HARD0": {
"direction": "OUT"
},
"HARD1": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "TIEOFF"
}

108
zynq7/site_type_USR_ACCESS.json Normal file
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{
"site_pins": {
"CFGCLK": {
"direction": "OUT"
},
"DATA0": {
"direction": "OUT"
},
"DATA1": {
"direction": "OUT"
},
"DATA10": {
"direction": "OUT"
},
"DATA11": {
"direction": "OUT"
},
"DATA12": {
"direction": "OUT"
},
"DATA13": {
"direction": "OUT"
},
"DATA14": {
"direction": "OUT"
},
"DATA15": {
"direction": "OUT"
},
"DATA16": {
"direction": "OUT"
},
"DATA17": {
"direction": "OUT"
},
"DATA18": {
"direction": "OUT"
},
"DATA19": {
"direction": "OUT"
},
"DATA2": {
"direction": "OUT"
},
"DATA20": {
"direction": "OUT"
},
"DATA21": {
"direction": "OUT"
},
"DATA22": {
"direction": "OUT"
},
"DATA23": {
"direction": "OUT"
},
"DATA24": {
"direction": "OUT"
},
"DATA25": {
"direction": "OUT"
},
"DATA26": {
"direction": "OUT"
},
"DATA27": {
"direction": "OUT"
},
"DATA28": {
"direction": "OUT"
},
"DATA29": {
"direction": "OUT"
},
"DATA3": {
"direction": "OUT"
},
"DATA30": {
"direction": "OUT"
},
"DATA31": {
"direction": "OUT"
},
"DATA4": {
"direction": "OUT"
},
"DATA5": {
"direction": "OUT"
},
"DATA6": {
"direction": "OUT"
},
"DATA7": {
"direction": "OUT"
},
"DATA8": {
"direction": "OUT"
},
"DATA9": {
"direction": "OUT"
},
"DATAVALID": {
"direction": "OUT"
}
},
"site_pips": {},
"type": "USR_ACCESS"
}

683
zynq7/site_type_XADC.json Normal file
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{
"site_pins": {
"ALM0": {
"direction": "OUT"
},
"ALM1": {
"direction": "OUT"
},
"ALM2": {
"direction": "OUT"
},
"ALM3": {
"direction": "OUT"
},
"ALM4": {
"direction": "OUT"
},
"ALM5": {
"direction": "OUT"
},
"ALM6": {
"direction": "OUT"
},
"ALM7": {
"direction": "OUT"
},
"BUSY": {
"direction": "OUT"
},
"CHANNEL0": {
"direction": "OUT"
},
"CHANNEL1": {
"direction": "OUT"
},
"CHANNEL2": {
"direction": "OUT"
},
"CHANNEL3": {
"direction": "OUT"
},
"CHANNEL4": {
"direction": "OUT"
},
"CONVST": {
"direction": "IN"
},
"CONVSTCLK": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"DADDR1": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"DADDR3": {
"direction": "IN"
},
"DADDR4": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"DCLK": {
"direction": "IN"
},
"DEN": {
"direction": "IN"
},
"DI0": {
"direction": "IN"
},
"DI1": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"DI2": {
"direction": "IN"
},
"DI3": {
"direction": "IN"
},
"DI4": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"DI9": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"EOC": {
"direction": "OUT"
},
"EOS": {
"direction": "OUT"
},
"JTAGBUSY": {
"direction": "OUT"
},
"JTAGLOCKED": {
"direction": "OUT"
},
"JTAGMODIFIED": {
"direction": "OUT"
},
"MUXADDR0": {
"direction": "OUT"
},
"MUXADDR1": {
"direction": "OUT"
},
"MUXADDR2": {
"direction": "OUT"
},
"MUXADDR3": {
"direction": "OUT"
},
"MUXADDR4": {
"direction": "OUT"
},
"OT": {
"direction": "OUT"
},
"RESET": {
"direction": "IN"
},
"TESTADCCLK0": {
"direction": "IN"
},
"TESTADCCLK1": {
"direction": "IN"
},
"TESTADCCLK2": {
"direction": "IN"
},
"TESTADCCLK3": {
"direction": "IN"
},
"TESTADCIN0": {
"direction": "IN"
},
"TESTADCIN1": {
"direction": "IN"
},
"TESTADCIN10": {
"direction": "IN"
},
"TESTADCIN11": {
"direction": "IN"
},
"TESTADCIN12": {
"direction": "IN"
},
"TESTADCIN13": {
"direction": "IN"
},
"TESTADCIN14": {
"direction": "IN"
},
"TESTADCIN15": {
"direction": "IN"
},
"TESTADCIN16": {
"direction": "IN"
},
"TESTADCIN17": {
"direction": "IN"
},
"TESTADCIN18": {
"direction": "IN"
},
"TESTADCIN19": {
"direction": "IN"
},
"TESTADCIN2": {
"direction": "IN"
},
"TESTADCIN20": {
"direction": "IN"
},
"TESTADCIN21": {
"direction": "IN"
},
"TESTADCIN210": {
"direction": "IN"
},
"TESTADCIN211": {
"direction": "IN"
},
"TESTADCIN212": {
"direction": "IN"
},
"TESTADCIN213": {
"direction": "IN"
},
"TESTADCIN214": {
"direction": "IN"
},
"TESTADCIN215": {
"direction": "IN"
},
"TESTADCIN216": {
"direction": "IN"
},
"TESTADCIN217": {
"direction": "IN"
},
"TESTADCIN218": {
"direction": "IN"
},
"TESTADCIN219": {
"direction": "IN"
},
"TESTADCIN22": {
"direction": "IN"
},
"TESTADCIN23": {
"direction": "IN"
},
"TESTADCIN24": {
"direction": "IN"
},
"TESTADCIN25": {
"direction": "IN"
},
"TESTADCIN26": {
"direction": "IN"
},
"TESTADCIN27": {
"direction": "IN"
},
"TESTADCIN28": {
"direction": "IN"
},
"TESTADCIN29": {
"direction": "IN"
},
"TESTADCIN3": {
"direction": "IN"
},
"TESTADCIN4": {
"direction": "IN"
},
"TESTADCIN5": {
"direction": "IN"
},
"TESTADCIN6": {
"direction": "IN"
},
"TESTADCIN7": {
"direction": "IN"
},
"TESTADCIN8": {
"direction": "IN"
},
"TESTADCIN9": {
"direction": "IN"
},
"TESTADCOUT0": {
"direction": "OUT"
},
"TESTADCOUT1": {
"direction": "OUT"
},
"TESTADCOUT10": {
"direction": "OUT"
},
"TESTADCOUT11": {
"direction": "OUT"
},
"TESTADCOUT12": {
"direction": "OUT"
},
"TESTADCOUT13": {
"direction": "OUT"
},
"TESTADCOUT14": {
"direction": "OUT"
},
"TESTADCOUT15": {
"direction": "OUT"
},
"TESTADCOUT16": {
"direction": "OUT"
},
"TESTADCOUT17": {
"direction": "OUT"
},
"TESTADCOUT18": {
"direction": "OUT"
},
"TESTADCOUT19": {
"direction": "OUT"
},
"TESTADCOUT2": {
"direction": "OUT"
},
"TESTADCOUT3": {
"direction": "OUT"
},
"TESTADCOUT4": {
"direction": "OUT"
},
"TESTADCOUT5": {
"direction": "OUT"
},
"TESTADCOUT6": {
"direction": "OUT"
},
"TESTADCOUT7": {
"direction": "OUT"
},
"TESTADCOUT8": {
"direction": "OUT"
},
"TESTADCOUT9": {
"direction": "OUT"
},
"TESTCAPTURE": {
"direction": "IN"
},
"TESTDB0": {
"direction": "OUT"
},
"TESTDB1": {
"direction": "OUT"
},
"TESTDB10": {
"direction": "OUT"
},
"TESTDB11": {
"direction": "OUT"
},
"TESTDB12": {
"direction": "OUT"
},
"TESTDB13": {
"direction": "OUT"
},
"TESTDB14": {
"direction": "OUT"
},
"TESTDB15": {
"direction": "OUT"
},
"TESTDB2": {
"direction": "OUT"
},
"TESTDB3": {
"direction": "OUT"
},
"TESTDB4": {
"direction": "OUT"
},
"TESTDB5": {
"direction": "OUT"
},
"TESTDB6": {
"direction": "OUT"
},
"TESTDB7": {
"direction": "OUT"
},
"TESTDB8": {
"direction": "OUT"
},
"TESTDB9": {
"direction": "OUT"
},
"TESTDRCK": {
"direction": "IN"
},
"TESTENJTAG": {
"direction": "IN"
},
"TESTRST": {
"direction": "IN"
},
"TESTSCANCLK0": {
"direction": "IN"
},
"TESTSCANCLK1": {
"direction": "IN"
},
"TESTSCANCLK2": {
"direction": "IN"
},
"TESTSCANCLK3": {
"direction": "IN"
},
"TESTSCANCLK4": {
"direction": "IN"
},
"TESTSCANMODE0": {
"direction": "IN"
},
"TESTSCANMODE1": {
"direction": "IN"
},
"TESTSCANMODE2": {
"direction": "IN"
},
"TESTSCANMODE3": {
"direction": "IN"
},
"TESTSCANMODE4": {
"direction": "IN"
},
"TESTSCANRESET": {
"direction": "IN"
},
"TESTSE0": {
"direction": "IN"
},
"TESTSE1": {
"direction": "IN"
},
"TESTSE2": {
"direction": "IN"
},
"TESTSE3": {
"direction": "IN"
},
"TESTSE4": {
"direction": "IN"
},
"TESTSEL": {
"direction": "IN"
},
"TESTSHIFT": {
"direction": "IN"
},
"TESTSI0": {
"direction": "IN"
},
"TESTSI1": {
"direction": "IN"
},
"TESTSI2": {
"direction": "IN"
},
"TESTSI3": {
"direction": "IN"
},
"TESTSI4": {
"direction": "IN"
},
"TESTSO0": {
"direction": "OUT"
},
"TESTSO1": {
"direction": "OUT"
},
"TESTSO2": {
"direction": "OUT"
},
"TESTSO3": {
"direction": "OUT"
},
"TESTSO4": {
"direction": "OUT"
},
"TESTTDI": {
"direction": "IN"
},
"TESTTDO": {
"direction": "OUT"
},
"TESTUPDATE": {
"direction": "IN"
},
"VAUXN0": {
"direction": "IN"
},
"VAUXN1": {
"direction": "IN"
},
"VAUXN10": {
"direction": "IN"
},
"VAUXN11": {
"direction": "IN"
},
"VAUXN12": {
"direction": "IN"
},
"VAUXN13": {
"direction": "IN"
},
"VAUXN14": {
"direction": "IN"
},
"VAUXN15": {
"direction": "IN"
},
"VAUXN2": {
"direction": "IN"
},
"VAUXN3": {
"direction": "IN"
},
"VAUXN4": {
"direction": "IN"
},
"VAUXN5": {
"direction": "IN"
},
"VAUXN6": {
"direction": "IN"
},
"VAUXN7": {
"direction": "IN"
},
"VAUXN8": {
"direction": "IN"
},
"VAUXN9": {
"direction": "IN"
},
"VAUXP0": {
"direction": "IN"
},
"VAUXP1": {
"direction": "IN"
},
"VAUXP10": {
"direction": "IN"
},
"VAUXP11": {
"direction": "IN"
},
"VAUXP12": {
"direction": "IN"
},
"VAUXP13": {
"direction": "IN"
},
"VAUXP14": {
"direction": "IN"
},
"VAUXP15": {
"direction": "IN"
},
"VAUXP2": {
"direction": "IN"
},
"VAUXP3": {
"direction": "IN"
},
"VAUXP4": {
"direction": "IN"
},
"VAUXP5": {
"direction": "IN"
},
"VAUXP6": {
"direction": "IN"
},
"VAUXP7": {
"direction": "IN"
},
"VAUXP8": {
"direction": "IN"
},
"VAUXP9": {
"direction": "IN"
},
"VN": {
"direction": "IN"
},
"VP": {
"direction": "IN"
}
},
"site_pips": {
"CONVSTCLKINV:CONVSTCLK": {
"from_pin": "CONVSTCLK",
"to_pin": "OUT"
},
"CONVSTCLKINV:CONVSTCLK_B": {
"from_pin": "CONVSTCLK_B",
"to_pin": "OUT"
},
"DCLKINV:DCLK": {
"from_pin": "DCLK",
"to_pin": "OUT"
},
"DCLKINV:DCLK_B": {
"from_pin": "DCLK_B",
"to_pin": "OUT"
}
},
"type": "XADC"
}

476
zynq7/tile_type_BRAM_INT_INTERFACE_L.json Normal file
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@ -0,0 +1,476 @@
{
"pips": {
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9"
}
},
"sites": [],
"tile_type": "BRAM_INT_INTERFACE_L",
"wires": [
"INT_INTERFACE_BLOCK_OUTS_L_B0",
"INT_INTERFACE_BLOCK_OUTS_L_B1",
"INT_INTERFACE_BLOCK_OUTS_L_B2",
"INT_INTERFACE_BLOCK_OUTS_L_B3",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_BRAM_IMUX1",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_BRAM_IMUX19",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_BRAM_IMUX32",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_BRAM_UTURN_IMUX0",
"INT_INTERFACE_BRAM_UTURN_IMUX1",
"INT_INTERFACE_BRAM_UTURN_IMUX10",
"INT_INTERFACE_BRAM_UTURN_IMUX11",
"INT_INTERFACE_BRAM_UTURN_IMUX12",
"INT_INTERFACE_BRAM_UTURN_IMUX13",
"INT_INTERFACE_BRAM_UTURN_IMUX14",
"INT_INTERFACE_BRAM_UTURN_IMUX15",
"INT_INTERFACE_BRAM_UTURN_IMUX16",
"INT_INTERFACE_BRAM_UTURN_IMUX17",
"INT_INTERFACE_BRAM_UTURN_IMUX18",
"INT_INTERFACE_BRAM_UTURN_IMUX19",
"INT_INTERFACE_BRAM_UTURN_IMUX2",
"INT_INTERFACE_BRAM_UTURN_IMUX20",
"INT_INTERFACE_BRAM_UTURN_IMUX21",
"INT_INTERFACE_BRAM_UTURN_IMUX22",
"INT_INTERFACE_BRAM_UTURN_IMUX23",
"INT_INTERFACE_BRAM_UTURN_IMUX24",
"INT_INTERFACE_BRAM_UTURN_IMUX25",
"INT_INTERFACE_BRAM_UTURN_IMUX26",
"INT_INTERFACE_BRAM_UTURN_IMUX27",
"INT_INTERFACE_BRAM_UTURN_IMUX28",
"INT_INTERFACE_BRAM_UTURN_IMUX29",
"INT_INTERFACE_BRAM_UTURN_IMUX3",
"INT_INTERFACE_BRAM_UTURN_IMUX30",
"INT_INTERFACE_BRAM_UTURN_IMUX31",
"INT_INTERFACE_BRAM_UTURN_IMUX32",
"INT_INTERFACE_BRAM_UTURN_IMUX33",
"INT_INTERFACE_BRAM_UTURN_IMUX34",
"INT_INTERFACE_BRAM_UTURN_IMUX35",
"INT_INTERFACE_BRAM_UTURN_IMUX36",
"INT_INTERFACE_BRAM_UTURN_IMUX37",
"INT_INTERFACE_BRAM_UTURN_IMUX38",
"INT_INTERFACE_BRAM_UTURN_IMUX39",
"INT_INTERFACE_BRAM_UTURN_IMUX4",
"INT_INTERFACE_BRAM_UTURN_IMUX40",
"INT_INTERFACE_BRAM_UTURN_IMUX41",
"INT_INTERFACE_BRAM_UTURN_IMUX42",
"INT_INTERFACE_BRAM_UTURN_IMUX43",
"INT_INTERFACE_BRAM_UTURN_IMUX44",
"INT_INTERFACE_BRAM_UTURN_IMUX45",
"INT_INTERFACE_BRAM_UTURN_IMUX46",
"INT_INTERFACE_BRAM_UTURN_IMUX47",
"INT_INTERFACE_BRAM_UTURN_IMUX5",
"INT_INTERFACE_BRAM_UTURN_IMUX6",
"INT_INTERFACE_BRAM_UTURN_IMUX7",
"INT_INTERFACE_BRAM_UTURN_IMUX8",
"INT_INTERFACE_BRAM_UTURN_IMUX9",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_LH1",
"INT_INTERFACE_LH10",
"INT_INTERFACE_LH11",
"INT_INTERFACE_LH12",
"INT_INTERFACE_LH2",
"INT_INTERFACE_LH3",
"INT_INTERFACE_LH4",
"INT_INTERFACE_LH5",
"INT_INTERFACE_LH6",
"INT_INTERFACE_LH7",
"INT_INTERFACE_LH8",
"INT_INTERFACE_LH9",
"INT_INTERFACE_LOGIC_OUTS_L0",
"INT_INTERFACE_LOGIC_OUTS_L1",
"INT_INTERFACE_LOGIC_OUTS_L10",
"INT_INTERFACE_LOGIC_OUTS_L11",
"INT_INTERFACE_LOGIC_OUTS_L12",
"INT_INTERFACE_LOGIC_OUTS_L13",
"INT_INTERFACE_LOGIC_OUTS_L14",
"INT_INTERFACE_LOGIC_OUTS_L15",
"INT_INTERFACE_LOGIC_OUTS_L16",
"INT_INTERFACE_LOGIC_OUTS_L17",
"INT_INTERFACE_LOGIC_OUTS_L18",
"INT_INTERFACE_LOGIC_OUTS_L19",
"INT_INTERFACE_LOGIC_OUTS_L2",
"INT_INTERFACE_LOGIC_OUTS_L20",
"INT_INTERFACE_LOGIC_OUTS_L21",
"INT_INTERFACE_LOGIC_OUTS_L22",
"INT_INTERFACE_LOGIC_OUTS_L23",
"INT_INTERFACE_LOGIC_OUTS_L3",
"INT_INTERFACE_LOGIC_OUTS_L4",
"INT_INTERFACE_LOGIC_OUTS_L5",
"INT_INTERFACE_LOGIC_OUTS_L6",
"INT_INTERFACE_LOGIC_OUTS_L7",
"INT_INTERFACE_LOGIC_OUTS_L8",
"INT_INTERFACE_LOGIC_OUTS_L9",
"INT_INTERFACE_LOGIC_OUTS_L_B0",
"INT_INTERFACE_LOGIC_OUTS_L_B1",
"INT_INTERFACE_LOGIC_OUTS_L_B10",
"INT_INTERFACE_LOGIC_OUTS_L_B11",
"INT_INTERFACE_LOGIC_OUTS_L_B12",
"INT_INTERFACE_LOGIC_OUTS_L_B13",
"INT_INTERFACE_LOGIC_OUTS_L_B14",
"INT_INTERFACE_LOGIC_OUTS_L_B15",
"INT_INTERFACE_LOGIC_OUTS_L_B16",
"INT_INTERFACE_LOGIC_OUTS_L_B17",
"INT_INTERFACE_LOGIC_OUTS_L_B18",
"INT_INTERFACE_LOGIC_OUTS_L_B19",
"INT_INTERFACE_LOGIC_OUTS_L_B2",
"INT_INTERFACE_LOGIC_OUTS_L_B20",
"INT_INTERFACE_LOGIC_OUTS_L_B21",
"INT_INTERFACE_LOGIC_OUTS_L_B22",
"INT_INTERFACE_LOGIC_OUTS_L_B23",
"INT_INTERFACE_LOGIC_OUTS_L_B3",
"INT_INTERFACE_LOGIC_OUTS_L_B4",
"INT_INTERFACE_LOGIC_OUTS_L_B5",
"INT_INTERFACE_LOGIC_OUTS_L_B6",
"INT_INTERFACE_LOGIC_OUTS_L_B7",
"INT_INTERFACE_LOGIC_OUTS_L_B8",
"INT_INTERFACE_LOGIC_OUTS_L_B9",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_WW4END3",
"L_INT_INTER_DQS_IOTOPHASER"
]
}

476
zynq7/tile_type_BRAM_INT_INTERFACE_R.json Normal file
View File

@ -0,0 +1,476 @@
{
"pips": {
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
"can_invert": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9"
}
},
"sites": [],
"tile_type": "BRAM_INT_INTERFACE_R",
"wires": [
"INT_INTERFACE_BLOCK_OUTS_B0",
"INT_INTERFACE_BLOCK_OUTS_B1",
"INT_INTERFACE_BLOCK_OUTS_B2",
"INT_INTERFACE_BLOCK_OUTS_B3",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_BRAM_IMUX1",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_BRAM_IMUX19",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_BRAM_IMUX32",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_LH1",
"INT_INTERFACE_LH10",
"INT_INTERFACE_LH11",
"INT_INTERFACE_LH12",
"INT_INTERFACE_LH2",
"INT_INTERFACE_LH3",
"INT_INTERFACE_LH4",
"INT_INTERFACE_LH5",
"INT_INTERFACE_LH6",
"INT_INTERFACE_LH7",
"INT_INTERFACE_LH8",
"INT_INTERFACE_LH9",
"INT_INTERFACE_LOGIC_OUTS0",
"INT_INTERFACE_LOGIC_OUTS1",
"INT_INTERFACE_LOGIC_OUTS10",
"INT_INTERFACE_LOGIC_OUTS11",
"INT_INTERFACE_LOGIC_OUTS12",
"INT_INTERFACE_LOGIC_OUTS13",
"INT_INTERFACE_LOGIC_OUTS14",
"INT_INTERFACE_LOGIC_OUTS15",
"INT_INTERFACE_LOGIC_OUTS16",
"INT_INTERFACE_LOGIC_OUTS17",
"INT_INTERFACE_LOGIC_OUTS18",
"INT_INTERFACE_LOGIC_OUTS19",
"INT_INTERFACE_LOGIC_OUTS2",
"INT_INTERFACE_LOGIC_OUTS20",
"INT_INTERFACE_LOGIC_OUTS21",
"INT_INTERFACE_LOGIC_OUTS22",
"INT_INTERFACE_LOGIC_OUTS23",
"INT_INTERFACE_LOGIC_OUTS3",
"INT_INTERFACE_LOGIC_OUTS4",
"INT_INTERFACE_LOGIC_OUTS5",
"INT_INTERFACE_LOGIC_OUTS6",
"INT_INTERFACE_LOGIC_OUTS7",
"INT_INTERFACE_LOGIC_OUTS8",
"INT_INTERFACE_LOGIC_OUTS9",
"INT_INTERFACE_LOGIC_OUTS_B0",
"INT_INTERFACE_LOGIC_OUTS_B1",
"INT_INTERFACE_LOGIC_OUTS_B10",
"INT_INTERFACE_LOGIC_OUTS_B11",
"INT_INTERFACE_LOGIC_OUTS_B12",
"INT_INTERFACE_LOGIC_OUTS_B13",
"INT_INTERFACE_LOGIC_OUTS_B14",
"INT_INTERFACE_LOGIC_OUTS_B15",
"INT_INTERFACE_LOGIC_OUTS_B16",
"INT_INTERFACE_LOGIC_OUTS_B17",
"INT_INTERFACE_LOGIC_OUTS_B18",
"INT_INTERFACE_LOGIC_OUTS_B19",
"INT_INTERFACE_LOGIC_OUTS_B2",
"INT_INTERFACE_LOGIC_OUTS_B20",
"INT_INTERFACE_LOGIC_OUTS_B21",
"INT_INTERFACE_LOGIC_OUTS_B22",
"INT_INTERFACE_LOGIC_OUTS_B23",
"INT_INTERFACE_LOGIC_OUTS_B3",
"INT_INTERFACE_LOGIC_OUTS_B4",
"INT_INTERFACE_LOGIC_OUTS_B5",
"INT_INTERFACE_LOGIC_OUTS_B6",
"INT_INTERFACE_LOGIC_OUTS_B7",
"INT_INTERFACE_LOGIC_OUTS_B8",
"INT_INTERFACE_LOGIC_OUTS_B9",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_WW4END3",
"L_INT_INTER_DQS_IOTOPHASER"
]
}

9834
zynq7/tile_type_BRAM_L.json Normal file
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9834
zynq7/tile_type_BRAM_R.json Normal file
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71
zynq7/tile_type_BRKH_BRAM.json Normal file
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@ -0,0 +1,71 @@
{
"pips": {},
"sites": [],
"tile_type": "BRKH_BRAM",
"wires": [
"BRKH_BRAM_CASCADEA_L",
"BRKH_BRAM_CASCADEA_R",
"BRKH_BRAM_CASCADEB_L",
"BRKH_BRAM_CASCADEB_R",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9"
]
}

11
zynq7/tile_type_BRKH_CLB.json Normal file
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@ -0,0 +1,11 @@
{
"pips": {},
"sites": [],
"tile_type": "BRKH_CLB",
"wires": [
"BRKH_CLB_COUT0_L",
"BRKH_CLB_COUT0_R",
"BRKH_CLB_COUT1_L",
"BRKH_CLB_COUT1_R"
]
}

135
zynq7/tile_type_BRKH_CLK.json Normal file
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{
"pips": {},
"sites": [],
"tile_type": "BRKH_CLK",
"wires": [
"BRKH_CLK_CK_BUFG_CASC0",
"BRKH_CLK_CK_BUFG_CASC1",
"BRKH_CLK_CK_BUFG_CASC10",
"BRKH_CLK_CK_BUFG_CASC11",
"BRKH_CLK_CK_BUFG_CASC12",
"BRKH_CLK_CK_BUFG_CASC13",
"BRKH_CLK_CK_BUFG_CASC14",
"BRKH_CLK_CK_BUFG_CASC15",
"BRKH_CLK_CK_BUFG_CASC16",
"BRKH_CLK_CK_BUFG_CASC17",
"BRKH_CLK_CK_BUFG_CASC18",
"BRKH_CLK_CK_BUFG_CASC19",
"BRKH_CLK_CK_BUFG_CASC2",
"BRKH_CLK_CK_BUFG_CASC20",
"BRKH_CLK_CK_BUFG_CASC21",
"BRKH_CLK_CK_BUFG_CASC22",
"BRKH_CLK_CK_BUFG_CASC23",
"BRKH_CLK_CK_BUFG_CASC24",
"BRKH_CLK_CK_BUFG_CASC25",
"BRKH_CLK_CK_BUFG_CASC26",
"BRKH_CLK_CK_BUFG_CASC27",
"BRKH_CLK_CK_BUFG_CASC28",
"BRKH_CLK_CK_BUFG_CASC29",
"BRKH_CLK_CK_BUFG_CASC3",
"BRKH_CLK_CK_BUFG_CASC30",
"BRKH_CLK_CK_BUFG_CASC31",
"BRKH_CLK_CK_BUFG_CASC4",
"BRKH_CLK_CK_BUFG_CASC5",
"BRKH_CLK_CK_BUFG_CASC6",
"BRKH_CLK_CK_BUFG_CASC7",
"BRKH_CLK_CK_BUFG_CASC8",
"BRKH_CLK_CK_BUFG_CASC9",
"BRKH_CLK_CK_GCLK0",
"BRKH_CLK_CK_GCLK1",
"BRKH_CLK_CK_GCLK10",
"BRKH_CLK_CK_GCLK11",
"BRKH_CLK_CK_GCLK12",
"BRKH_CLK_CK_GCLK13",
"BRKH_CLK_CK_GCLK14",
"BRKH_CLK_CK_GCLK15",
"BRKH_CLK_CK_GCLK16",
"BRKH_CLK_CK_GCLK17",
"BRKH_CLK_CK_GCLK18",
"BRKH_CLK_CK_GCLK19",
"BRKH_CLK_CK_GCLK2",
"BRKH_CLK_CK_GCLK20",
"BRKH_CLK_CK_GCLK21",
"BRKH_CLK_CK_GCLK22",
"BRKH_CLK_CK_GCLK23",
"BRKH_CLK_CK_GCLK24",
"BRKH_CLK_CK_GCLK25",
"BRKH_CLK_CK_GCLK26",
"BRKH_CLK_CK_GCLK27",
"BRKH_CLK_CK_GCLK28",
"BRKH_CLK_CK_GCLK29",
"BRKH_CLK_CK_GCLK3",
"BRKH_CLK_CK_GCLK30",
"BRKH_CLK_CK_GCLK31",
"BRKH_CLK_CK_GCLK4",
"BRKH_CLK_CK_GCLK5",
"BRKH_CLK_CK_GCLK6",
"BRKH_CLK_CK_GCLK7",
"BRKH_CLK_CK_GCLK8",
"BRKH_CLK_CK_GCLK9",
"BRKH_CLK_R_CK_BUFG_CASC0",
"BRKH_CLK_R_CK_BUFG_CASC1",
"BRKH_CLK_R_CK_BUFG_CASC10",
"BRKH_CLK_R_CK_BUFG_CASC11",
"BRKH_CLK_R_CK_BUFG_CASC12",
"BRKH_CLK_R_CK_BUFG_CASC13",
"BRKH_CLK_R_CK_BUFG_CASC14",
"BRKH_CLK_R_CK_BUFG_CASC15",
"BRKH_CLK_R_CK_BUFG_CASC16",
"BRKH_CLK_R_CK_BUFG_CASC17",
"BRKH_CLK_R_CK_BUFG_CASC18",
"BRKH_CLK_R_CK_BUFG_CASC19",
"BRKH_CLK_R_CK_BUFG_CASC2",
"BRKH_CLK_R_CK_BUFG_CASC20",
"BRKH_CLK_R_CK_BUFG_CASC21",
"BRKH_CLK_R_CK_BUFG_CASC22",
"BRKH_CLK_R_CK_BUFG_CASC23",
"BRKH_CLK_R_CK_BUFG_CASC24",
"BRKH_CLK_R_CK_BUFG_CASC25",
"BRKH_CLK_R_CK_BUFG_CASC26",
"BRKH_CLK_R_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_BUFG_CASC28",
"BRKH_CLK_R_CK_BUFG_CASC29",
"BRKH_CLK_R_CK_BUFG_CASC3",
"BRKH_CLK_R_CK_BUFG_CASC30",
"BRKH_CLK_R_CK_BUFG_CASC31",
"BRKH_CLK_R_CK_BUFG_CASC4",
"BRKH_CLK_R_CK_BUFG_CASC5",
"BRKH_CLK_R_CK_BUFG_CASC6",
"BRKH_CLK_R_CK_BUFG_CASC7",
"BRKH_CLK_R_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_BUFG_CASC9",
"BRKH_CLK_R_CK_GCLK0",
"BRKH_CLK_R_CK_GCLK1",
"BRKH_CLK_R_CK_GCLK10",
"BRKH_CLK_R_CK_GCLK11",
"BRKH_CLK_R_CK_GCLK12",
"BRKH_CLK_R_CK_GCLK13",
"BRKH_CLK_R_CK_GCLK14",
"BRKH_CLK_R_CK_GCLK15",
"BRKH_CLK_R_CK_GCLK16",
"BRKH_CLK_R_CK_GCLK17",
"BRKH_CLK_R_CK_GCLK18",
"BRKH_CLK_R_CK_GCLK19",
"BRKH_CLK_R_CK_GCLK2",
"BRKH_CLK_R_CK_GCLK20",
"BRKH_CLK_R_CK_GCLK21",
"BRKH_CLK_R_CK_GCLK22",
"BRKH_CLK_R_CK_GCLK23",
"BRKH_CLK_R_CK_GCLK24",
"BRKH_CLK_R_CK_GCLK25",
"BRKH_CLK_R_CK_GCLK26",
"BRKH_CLK_R_CK_GCLK27",
"BRKH_CLK_R_CK_GCLK28",
"BRKH_CLK_R_CK_GCLK29",
"BRKH_CLK_R_CK_GCLK3",
"BRKH_CLK_R_CK_GCLK30",
"BRKH_CLK_R_CK_GCLK31",
"BRKH_CLK_R_CK_GCLK4",
"BRKH_CLK_R_CK_GCLK5",
"BRKH_CLK_R_CK_GCLK6",
"BRKH_CLK_R_CK_GCLK7",
"BRKH_CLK_R_CK_GCLK8",
"BRKH_CLK_R_CK_GCLK9"
]
}

16
zynq7/tile_type_BRKH_CMT.json Normal file
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{
"pips": {},
"sites": [],
"tile_type": "BRKH_CMT",
"wires": [
"BRKH_CMT_FREQ_REF_NS0",
"BRKH_CMT_FREQ_REF_NS1",
"BRKH_CMT_FREQ_REF_NS2",
"BRKH_CMT_FREQ_REF_NS3",
"BRKH_CMT_PHASEREF0",
"BRKH_CMT_PHASEREF1",
"BRKH_CMT_PHASEREF_BELOW0",
"BRKH_CMT_PHASEREF_BELOW1",
"BRKH_CMT_PHYCTRL_SYNC_BB"
]
}

105
zynq7/tile_type_BRKH_DSP_L.json Normal file
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{
"pips": {},
"sites": [],
"tile_type": "BRKH_DSP_L",
"wires": [
"BRKH_DSP_ACIN0",
"BRKH_DSP_ACIN1",
"BRKH_DSP_ACIN10",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN12",
"BRKH_DSP_ACIN13",
"BRKH_DSP_ACIN14",
"BRKH_DSP_ACIN15",
"BRKH_DSP_ACIN16",
"BRKH_DSP_ACIN17",
"BRKH_DSP_ACIN18",
"BRKH_DSP_ACIN19",
"BRKH_DSP_ACIN2",
"BRKH_DSP_ACIN20",
"BRKH_DSP_ACIN21",
"BRKH_DSP_ACIN22",
"BRKH_DSP_ACIN23",
"BRKH_DSP_ACIN24",
"BRKH_DSP_ACIN25",
"BRKH_DSP_ACIN26",
"BRKH_DSP_ACIN27",
"BRKH_DSP_ACIN28",
"BRKH_DSP_ACIN29",
"BRKH_DSP_ACIN3",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN5",
"BRKH_DSP_ACIN6",
"BRKH_DSP_ACIN7",
"BRKH_DSP_ACIN8",
"BRKH_DSP_ACIN9",
"BRKH_DSP_BCIN0",
"BRKH_DSP_BCIN1",
"BRKH_DSP_BCIN10",
"BRKH_DSP_BCIN11",
"BRKH_DSP_BCIN12",
"BRKH_DSP_BCIN13",
"BRKH_DSP_BCIN14",
"BRKH_DSP_BCIN15",
"BRKH_DSP_BCIN16",
"BRKH_DSP_BCIN17",
"BRKH_DSP_BCIN2",
"BRKH_DSP_BCIN3",
"BRKH_DSP_BCIN4",
"BRKH_DSP_BCIN5",
"BRKH_DSP_BCIN6",
"BRKH_DSP_BCIN7",
"BRKH_DSP_BCIN8",
"BRKH_DSP_BCIN9",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN1",
"BRKH_DSP_PCIN10",
"BRKH_DSP_PCIN11",
"BRKH_DSP_PCIN12",
"BRKH_DSP_PCIN13",
"BRKH_DSP_PCIN14",
"BRKH_DSP_PCIN15",
"BRKH_DSP_PCIN16",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN18",
"BRKH_DSP_PCIN19",
"BRKH_DSP_PCIN2",
"BRKH_DSP_PCIN20",
"BRKH_DSP_PCIN21",
"BRKH_DSP_PCIN22",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN24",
"BRKH_DSP_PCIN25",
"BRKH_DSP_PCIN26",
"BRKH_DSP_PCIN27",
"BRKH_DSP_PCIN28",
"BRKH_DSP_PCIN29",
"BRKH_DSP_PCIN3",
"BRKH_DSP_PCIN30",
"BRKH_DSP_PCIN31",
"BRKH_DSP_PCIN32",
"BRKH_DSP_PCIN33",
"BRKH_DSP_PCIN34",
"BRKH_DSP_PCIN35",
"BRKH_DSP_PCIN36",
"BRKH_DSP_PCIN37",
"BRKH_DSP_PCIN38",
"BRKH_DSP_PCIN39",
"BRKH_DSP_PCIN4",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN43",
"BRKH_DSP_PCIN44",
"BRKH_DSP_PCIN45",
"BRKH_DSP_PCIN46",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN5",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN7",
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN9"
]
}

105
zynq7/tile_type_BRKH_DSP_R.json Normal file
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{
"pips": {},
"sites": [],
"tile_type": "BRKH_DSP_R",
"wires": [
"BRKH_DSP_ACIN0",
"BRKH_DSP_ACIN1",
"BRKH_DSP_ACIN10",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN12",
"BRKH_DSP_ACIN13",
"BRKH_DSP_ACIN14",
"BRKH_DSP_ACIN15",
"BRKH_DSP_ACIN16",
"BRKH_DSP_ACIN17",
"BRKH_DSP_ACIN18",
"BRKH_DSP_ACIN19",
"BRKH_DSP_ACIN2",
"BRKH_DSP_ACIN20",
"BRKH_DSP_ACIN21",
"BRKH_DSP_ACIN22",
"BRKH_DSP_ACIN23",
"BRKH_DSP_ACIN24",
"BRKH_DSP_ACIN25",
"BRKH_DSP_ACIN26",
"BRKH_DSP_ACIN27",
"BRKH_DSP_ACIN28",
"BRKH_DSP_ACIN29",
"BRKH_DSP_ACIN3",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN5",
"BRKH_DSP_ACIN6",
"BRKH_DSP_ACIN7",
"BRKH_DSP_ACIN8",
"BRKH_DSP_ACIN9",
"BRKH_DSP_BCIN0",
"BRKH_DSP_BCIN1",
"BRKH_DSP_BCIN10",
"BRKH_DSP_BCIN11",
"BRKH_DSP_BCIN12",
"BRKH_DSP_BCIN13",
"BRKH_DSP_BCIN14",
"BRKH_DSP_BCIN15",
"BRKH_DSP_BCIN16",
"BRKH_DSP_BCIN17",
"BRKH_DSP_BCIN2",
"BRKH_DSP_BCIN3",
"BRKH_DSP_BCIN4",
"BRKH_DSP_BCIN5",
"BRKH_DSP_BCIN6",
"BRKH_DSP_BCIN7",
"BRKH_DSP_BCIN8",
"BRKH_DSP_BCIN9",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN1",
"BRKH_DSP_PCIN10",
"BRKH_DSP_PCIN11",
"BRKH_DSP_PCIN12",
"BRKH_DSP_PCIN13",
"BRKH_DSP_PCIN14",
"BRKH_DSP_PCIN15",
"BRKH_DSP_PCIN16",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN18",
"BRKH_DSP_PCIN19",
"BRKH_DSP_PCIN2",
"BRKH_DSP_PCIN20",
"BRKH_DSP_PCIN21",
"BRKH_DSP_PCIN22",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN24",
"BRKH_DSP_PCIN25",
"BRKH_DSP_PCIN26",
"BRKH_DSP_PCIN27",
"BRKH_DSP_PCIN28",
"BRKH_DSP_PCIN29",
"BRKH_DSP_PCIN3",
"BRKH_DSP_PCIN30",
"BRKH_DSP_PCIN31",
"BRKH_DSP_PCIN32",
"BRKH_DSP_PCIN33",
"BRKH_DSP_PCIN34",
"BRKH_DSP_PCIN35",
"BRKH_DSP_PCIN36",
"BRKH_DSP_PCIN37",
"BRKH_DSP_PCIN38",
"BRKH_DSP_PCIN39",
"BRKH_DSP_PCIN4",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN43",
"BRKH_DSP_PCIN44",
"BRKH_DSP_PCIN45",
"BRKH_DSP_PCIN46",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN5",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN7",
"BRKH_DSP_PCIN8",
"BRKH_DSP_PCIN9"
]
}

367
zynq7/tile_type_BRKH_INT.json Normal file
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{
"pips": {
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG0"
},
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG1"
},
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NL1BEG2"
},
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG0"
},
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG1"
},
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG2"
},
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
"can_invert": "0",
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_NR1BEG3"
},
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SL1END0",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END0_SLOW"
},
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SL1END1",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END1_SLOW"
},
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SL1END2",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END2_SLOW"
},
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SL1END3",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SL1END3_SLOW"
},
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SR1END1",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END1_SLOW"
},
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SR1END2",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END2_SLOW"
},
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
"can_invert": "0",
"dst_wire": "BRKH_INT_SR1END3",
"is_directional": "1",
"is_pseudo": "0",
"src_wire": "BRKH_INT_SR1END3_SLOW"
}
},
"sites": [],
"tile_type": "BRKH_INT",
"wires": [
"BRKH_INT_BYP_BOUNCE2",
"BRKH_INT_BYP_BOUNCE3",
"BRKH_INT_BYP_BOUNCE6",
"BRKH_INT_BYP_BOUNCE7",
"BRKH_INT_EL1BEG3",
"BRKH_INT_EL1END_S3_0",
"BRKH_INT_ER1BEG_S0",
"BRKH_INT_ER1END3",
"BRKH_INT_FAN_BOUNCE_S3_0",
"BRKH_INT_FAN_BOUNCE_S3_2",
"BRKH_INT_FAN_BOUNCE_S3_4",
"BRKH_INT_FAN_BOUNCE_S3_6",
"BRKH_INT_LV0",
"BRKH_INT_LV1",
"BRKH_INT_LV10",
"BRKH_INT_LV11",
"BRKH_INT_LV12",
"BRKH_INT_LV13",
"BRKH_INT_LV14",
"BRKH_INT_LV15",
"BRKH_INT_LV16",
"BRKH_INT_LV17",
"BRKH_INT_LV2",
"BRKH_INT_LV3",
"BRKH_INT_LV4",
"BRKH_INT_LV5",
"BRKH_INT_LV6",
"BRKH_INT_LV7",
"BRKH_INT_LV8",
"BRKH_INT_LV9",
"BRKH_INT_LVB1",
"BRKH_INT_LVB10",
"BRKH_INT_LVB11",
"BRKH_INT_LVB12",
"BRKH_INT_LVB2",
"BRKH_INT_LVB3",
"BRKH_INT_LVB4",
"BRKH_INT_LVB5",
"BRKH_INT_LVB6",
"BRKH_INT_LVB7",
"BRKH_INT_LVB8",
"BRKH_INT_LVB9",
"BRKH_INT_LVB_L1",
"BRKH_INT_LVB_L10",
"BRKH_INT_LVB_L11",
"BRKH_INT_LVB_L12",
"BRKH_INT_LVB_L2",
"BRKH_INT_LVB_L3",
"BRKH_INT_LVB_L4",
"BRKH_INT_LVB_L5",
"BRKH_INT_LVB_L6",
"BRKH_INT_LVB_L7",
"BRKH_INT_LVB_L8",
"BRKH_INT_LVB_L9",
"BRKH_INT_L_LV0",
"BRKH_INT_L_LV1",
"BRKH_INT_L_LV10",
"BRKH_INT_L_LV11",
"BRKH_INT_L_LV12",
"BRKH_INT_L_LV13",
"BRKH_INT_L_LV14",
"BRKH_INT_L_LV15",
"BRKH_INT_L_LV16",
"BRKH_INT_L_LV17",
"BRKH_INT_L_LV2",
"BRKH_INT_L_LV3",
"BRKH_INT_L_LV4",
"BRKH_INT_L_LV5",
"BRKH_INT_L_LV6",
"BRKH_INT_L_LV7",
"BRKH_INT_L_LV8",
"BRKH_INT_L_LV9",
"BRKH_INT_NE2BEG0",
"BRKH_INT_NE2BEG1",
"BRKH_INT_NE2BEG2",
"BRKH_INT_NE2BEG3",
"BRKH_INT_NE2END_S3_0",
"BRKH_INT_NE6A0",
"BRKH_INT_NE6A1",
"BRKH_INT_NE6A2",
"BRKH_INT_NE6A3",
"BRKH_INT_NE6B0",
"BRKH_INT_NE6B1",
"BRKH_INT_NE6B2",
"BRKH_INT_NE6B3",
"BRKH_INT_NE6C0",
"BRKH_INT_NE6C1",
"BRKH_INT_NE6C2",
"BRKH_INT_NE6C3",
"BRKH_INT_NE6D0",
"BRKH_INT_NE6D1",
"BRKH_INT_NE6D2",
"BRKH_INT_NE6D3",
"BRKH_INT_NL1BEG0",
"BRKH_INT_NL1BEG0_SLOW",
"BRKH_INT_NL1BEG1",
"BRKH_INT_NL1BEG1_SLOW",
"BRKH_INT_NL1BEG2",
"BRKH_INT_NL1BEG2_SLOW",
"BRKH_INT_NL1END_S3_0",
"BRKH_INT_NN2A0",
"BRKH_INT_NN2A1",
"BRKH_INT_NN2A2",
"BRKH_INT_NN2A3",
"BRKH_INT_NN2BEG0",
"BRKH_INT_NN2BEG1",
"BRKH_INT_NN2BEG2",
"BRKH_INT_NN2BEG3",
"BRKH_INT_NN2END_S2_0",
"BRKH_INT_NN6A0",
"BRKH_INT_NN6A1",
"BRKH_INT_NN6A2",
"BRKH_INT_NN6A3",
"BRKH_INT_NN6B0",
"BRKH_INT_NN6B1",
"BRKH_INT_NN6B2",
"BRKH_INT_NN6B3",
"BRKH_INT_NN6BEG0",
"BRKH_INT_NN6BEG1",
"BRKH_INT_NN6BEG2",
"BRKH_INT_NN6BEG3",
"BRKH_INT_NN6C0",
"BRKH_INT_NN6C1",
"BRKH_INT_NN6C2",
"BRKH_INT_NN6C3",
"BRKH_INT_NN6D0",
"BRKH_INT_NN6D1",
"BRKH_INT_NN6D2",
"BRKH_INT_NN6D3",
"BRKH_INT_NN6E0",
"BRKH_INT_NN6E1",
"BRKH_INT_NN6E2",
"BRKH_INT_NN6E3",
"BRKH_INT_NN6END_S1_0",
"BRKH_INT_NR1BEG0",
"BRKH_INT_NR1BEG0_SLOW",
"BRKH_INT_NR1BEG1",
"BRKH_INT_NR1BEG1_SLOW",
"BRKH_INT_NR1BEG2",
"BRKH_INT_NR1BEG2_SLOW",
"BRKH_INT_NR1BEG3",
"BRKH_INT_NR1BEG3_SLOW",
"BRKH_INT_NW2BEG0",
"BRKH_INT_NW2BEG1",
"BRKH_INT_NW2BEG2",
"BRKH_INT_NW2BEG3",
"BRKH_INT_NW2END_S0_0",
"BRKH_INT_NW6A0",
"BRKH_INT_NW6A1",
"BRKH_INT_NW6A2",
"BRKH_INT_NW6A3",
"BRKH_INT_NW6B0",
"BRKH_INT_NW6B1",
"BRKH_INT_NW6B2",
"BRKH_INT_NW6B3",
"BRKH_INT_NW6C0",
"BRKH_INT_NW6C1",
"BRKH_INT_NW6C2",
"BRKH_INT_NW6C3",
"BRKH_INT_NW6D0",
"BRKH_INT_NW6D1",
"BRKH_INT_NW6D2",
"BRKH_INT_NW6D3",
"BRKH_INT_NW6END_S0_0",
"BRKH_INT_SE2A0",
"BRKH_INT_SE2A1",
"BRKH_INT_SE2A2",
"BRKH_INT_SE2A3",
"BRKH_INT_SE6B0",
"BRKH_INT_SE6B1",
"BRKH_INT_SE6B2",
"BRKH_INT_SE6B3",
"BRKH_INT_SE6C0",
"BRKH_INT_SE6C1",
"BRKH_INT_SE6C2",
"BRKH_INT_SE6C3",
"BRKH_INT_SE6D0",
"BRKH_INT_SE6D1",
"BRKH_INT_SE6D2",
"BRKH_INT_SE6D3",
"BRKH_INT_SE6E0",
"BRKH_INT_SE6E1",
"BRKH_INT_SE6E2",
"BRKH_INT_SE6E3",
"BRKH_INT_SL1END0",
"BRKH_INT_SL1END0_SLOW",
"BRKH_INT_SL1END1",
"BRKH_INT_SL1END1_SLOW",
"BRKH_INT_SL1END2",
"BRKH_INT_SL1END2_SLOW",
"BRKH_INT_SL1END3",
"BRKH_INT_SL1END3_SLOW",
"BRKH_INT_SR1END1",
"BRKH_INT_SR1END1_SLOW",
"BRKH_INT_SR1END2",
"BRKH_INT_SR1END2_SLOW",
"BRKH_INT_SR1END3",
"BRKH_INT_SR1END3_SLOW",
"BRKH_INT_SR1END_N3_3",
"BRKH_INT_SS2A0",
"BRKH_INT_SS2A1",
"BRKH_INT_SS2A2",
"BRKH_INT_SS2A3",
"BRKH_INT_SS2END0",
"BRKH_INT_SS2END1",
"BRKH_INT_SS2END2",
"BRKH_INT_SS2END3",
"BRKH_INT_SS2END_N0_3",
"BRKH_INT_SS6A0",
"BRKH_INT_SS6A1",
"BRKH_INT_SS6A2",
"BRKH_INT_SS6A3",
"BRKH_INT_SS6B0",
"BRKH_INT_SS6B1",
"BRKH_INT_SS6B2",
"BRKH_INT_SS6B3",
"BRKH_INT_SS6C0",
"BRKH_INT_SS6C1",
"BRKH_INT_SS6C2",
"BRKH_INT_SS6C3",
"BRKH_INT_SS6D0",
"BRKH_INT_SS6D1",
"BRKH_INT_SS6D2",
"BRKH_INT_SS6D3",
"BRKH_INT_SS6E0",
"BRKH_INT_SS6E1",
"BRKH_INT_SS6E2",
"BRKH_INT_SS6E3",
"BRKH_INT_SS6END0",
"BRKH_INT_SS6END1",
"BRKH_INT_SS6END2",
"BRKH_INT_SS6END3",
"BRKH_INT_SS6END_N0_3",
"BRKH_INT_SW2A0",
"BRKH_INT_SW2A1",
"BRKH_INT_SW2A2",
"BRKH_INT_SW2A3",
"BRKH_INT_SW2END3",
"BRKH_INT_SW6B0",
"BRKH_INT_SW6B1",
"BRKH_INT_SW6B2",
"BRKH_INT_SW6B3",
"BRKH_INT_SW6C0",
"BRKH_INT_SW6C1",
"BRKH_INT_SW6C2",
"BRKH_INT_SW6C3",
"BRKH_INT_SW6D0",
"BRKH_INT_SW6D1",
"BRKH_INT_SW6D2",
"BRKH_INT_SW6D3",
"BRKH_INT_SW6E0",
"BRKH_INT_SW6E1",
"BRKH_INT_SW6E2",
"BRKH_INT_SW6E3",
"BRKH_INT_SW6END3",
"BRKH_INT_WL1BEG3",
"BRKH_INT_WL1END3",
"BRKH_INT_WR1BEG_S0",
"BRKH_INT_WR1END_S1_0",
"BRKH_INT_WW2END3",
"BRKH_INT_WW4END_S0_0"
]
}

125
zynq7/tile_type_B_TERM_INT.json Normal file
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@ -0,0 +1,125 @@
{
"pips": {},
"sites": [],
"tile_type": "B_TERM_INT",
"wires": [
"B_TERM_UTURN_INT_ER1BEG0",
"B_TERM_UTURN_INT_ER1END_N3_3",
"B_TERM_UTURN_INT_FAN_BOUNCE0",
"B_TERM_UTURN_INT_FAN_BOUNCE2",
"B_TERM_UTURN_INT_FAN_BOUNCE4",
"B_TERM_UTURN_INT_FAN_BOUNCE6",
"B_TERM_UTURN_INT_LV18",
"B_TERM_UTURN_INT_LV2",
"B_TERM_UTURN_INT_LV3",
"B_TERM_UTURN_INT_LV4",
"B_TERM_UTURN_INT_LV5",
"B_TERM_UTURN_INT_LV6",
"B_TERM_UTURN_INT_LV7",
"B_TERM_UTURN_INT_LV8",
"B_TERM_UTURN_INT_LV9",
"B_TERM_UTURN_INT_LVB0",
"B_TERM_UTURN_INT_LVB1",
"B_TERM_UTURN_INT_LVB2",
"B_TERM_UTURN_INT_LVB3",
"B_TERM_UTURN_INT_LVB4",
"B_TERM_UTURN_INT_LVB5",
"B_TERM_UTURN_INT_LVB_L0",
"B_TERM_UTURN_INT_LVB_L1",
"B_TERM_UTURN_INT_LVB_L2",
"B_TERM_UTURN_INT_LVB_L3",
"B_TERM_UTURN_INT_LVB_L4",
"B_TERM_UTURN_INT_LVB_L5",
"B_TERM_UTURN_INT_LV_L18",
"B_TERM_UTURN_INT_LV_L2",
"B_TERM_UTURN_INT_LV_L3",
"B_TERM_UTURN_INT_LV_L4",
"B_TERM_UTURN_INT_LV_L5",
"B_TERM_UTURN_INT_LV_L6",
"B_TERM_UTURN_INT_LV_L7",
"B_TERM_UTURN_INT_LV_L8",
"B_TERM_UTURN_INT_LV_L9",
"B_TERM_UTURN_INT_SE2BEG0",
"B_TERM_UTURN_INT_SE2BEG1",
"B_TERM_UTURN_INT_SE2BEG2",
"B_TERM_UTURN_INT_SE2BEG3",
"B_TERM_UTURN_INT_SE6A0",
"B_TERM_UTURN_INT_SE6A1",
"B_TERM_UTURN_INT_SE6A2",
"B_TERM_UTURN_INT_SE6A3",
"B_TERM_UTURN_INT_SE6B0",
"B_TERM_UTURN_INT_SE6B1",
"B_TERM_UTURN_INT_SE6B2",
"B_TERM_UTURN_INT_SE6B3",
"B_TERM_UTURN_INT_SE6C0",
"B_TERM_UTURN_INT_SE6C1",
"B_TERM_UTURN_INT_SE6C2",
"B_TERM_UTURN_INT_SE6C3",
"B_TERM_UTURN_INT_SE6D0",
"B_TERM_UTURN_INT_SE6D1",
"B_TERM_UTURN_INT_SE6D2",
"B_TERM_UTURN_INT_SE6D3",
"B_TERM_UTURN_INT_SL1BEG0",
"B_TERM_UTURN_INT_SL1BEG1",
"B_TERM_UTURN_INT_SL1BEG2",
"B_TERM_UTURN_INT_SL1BEG3",
"B_TERM_UTURN_INT_SR1BEG1",
"B_TERM_UTURN_INT_SR1BEG2",
"B_TERM_UTURN_INT_SR1BEG3",
"B_TERM_UTURN_INT_SS2A0",
"B_TERM_UTURN_INT_SS2A1",
"B_TERM_UTURN_INT_SS2A2",
"B_TERM_UTURN_INT_SS2A3",
"B_TERM_UTURN_INT_SS2BEG0",
"B_TERM_UTURN_INT_SS2BEG1",
"B_TERM_UTURN_INT_SS2BEG2",
"B_TERM_UTURN_INT_SS2BEG3",
"B_TERM_UTURN_INT_SS6A0",
"B_TERM_UTURN_INT_SS6A1",
"B_TERM_UTURN_INT_SS6A2",
"B_TERM_UTURN_INT_SS6A3",
"B_TERM_UTURN_INT_SS6B0",
"B_TERM_UTURN_INT_SS6B1",
"B_TERM_UTURN_INT_SS6B2",
"B_TERM_UTURN_INT_SS6B3",
"B_TERM_UTURN_INT_SS6BEG0",
"B_TERM_UTURN_INT_SS6BEG1",
"B_TERM_UTURN_INT_SS6BEG2",
"B_TERM_UTURN_INT_SS6BEG3",
"B_TERM_UTURN_INT_SS6C0",
"B_TERM_UTURN_INT_SS6C1",
"B_TERM_UTURN_INT_SS6C2",
"B_TERM_UTURN_INT_SS6C3",
"B_TERM_UTURN_INT_SS6D0",
"B_TERM_UTURN_INT_SS6D1",
"B_TERM_UTURN_INT_SS6D2",
"B_TERM_UTURN_INT_SS6D3",
"B_TERM_UTURN_INT_SS6E0",
"B_TERM_UTURN_INT_SS6E1",
"B_TERM_UTURN_INT_SS6E2",
"B_TERM_UTURN_INT_SS6E3",
"B_TERM_UTURN_INT_SW2BEG0",
"B_TERM_UTURN_INT_SW2BEG1",
"B_TERM_UTURN_INT_SW2BEG2",
"B_TERM_UTURN_INT_SW2BEG3",
"B_TERM_UTURN_INT_SW6A0",
"B_TERM_UTURN_INT_SW6A1",
"B_TERM_UTURN_INT_SW6A2",
"B_TERM_UTURN_INT_SW6A3",
"B_TERM_UTURN_INT_SW6B0",
"B_TERM_UTURN_INT_SW6B1",
"B_TERM_UTURN_INT_SW6B2",
"B_TERM_UTURN_INT_SW6B3",
"B_TERM_UTURN_INT_SW6C0",
"B_TERM_UTURN_INT_SW6C1",
"B_TERM_UTURN_INT_SW6C2",
"B_TERM_UTURN_INT_SW6C3",
"B_TERM_UTURN_INT_SW6D0",
"B_TERM_UTURN_INT_SW6D1",
"B_TERM_UTURN_INT_SW6D2",
"B_TERM_UTURN_INT_SW6D3",
"B_TERM_UTURN_INT_SW6END_N0_3",
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_WR1END0"
]
}

8
zynq7/tile_type_B_TERM_INT_PSS.json Normal file
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@ -0,0 +1,8 @@
{
"pips": {},
"sites": [],
"tile_type": "B_TERM_INT_PSS",
"wires": [
"DUMMYFOO"
]
}

8
zynq7/tile_type_B_TERM_VBRK.json Normal file
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@ -0,0 +1,8 @@
{
"pips": {},
"sites": [],
"tile_type": "B_TERM_VBRK",
"wires": [
"DUMMYFOO"
]
}

4513
zynq7/tile_type_CFG_CENTER_BOT.json Normal file
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7187
zynq7/tile_type_CFG_CENTER_MID.json Normal file
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2590
zynq7/tile_type_CFG_CENTER_TOP.json Normal file
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