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prjxray-db
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Updating DB based on "Bugfix in 013-intpips fuzzer" 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2017-11-15 04:45:48 +00:00 committed by Tim 'mithro' Ansell
parent 5dfba54c9c
commit b699c7765f
4 changed files with 0 additions and 91 deletions
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31
artix7/seg_clbll_int_l.segbits
View File

@ -274,7 +274,6 @@ CLBLL_INT_L.EE4BEG0.LOGIC_OUTS_L18 05_08 06_09
CLBLL_INT_L.EE4BEG0.LOGIC_OUTS_L22 03_10 05_08
CLBLL_INT_L.EE4BEG0.LOGIC_OUTS_L4 01_09 06_09
CLBLL_INT_L.EE4BEG0.LOGIC_OUTS_L8 02_08 06_09
CLBLL_INT_L.EE4BEG0.LV_L0 03_10 04_08
CLBLL_INT_L.EE4BEG0.NE2END0 01_09 03_09
CLBLL_INT_L.EE4BEG0.NE6END0 03_09 04_08
CLBLL_INT_L.EE4BEG0.NN2END0 02_08 03_09
@ -329,7 +328,6 @@ CLBLL_INT_L.EE4BEG3.LOGIC_OUTS_L17 03_58 05_56
CLBLL_INT_L.EE4BEG3.LOGIC_OUTS_L21 05_56 06_57
CLBLL_INT_L.EE4BEG3.LOGIC_OUTS_L3 01_57 06_57
CLBLL_INT_L.EE4BEG3.LOGIC_OUTS_L7 01_57 03_58
CLBLL_INT_L.EE4BEG3.LV_L18 04_56 06_57
CLBLL_INT_L.EE4BEG3.NE2END3 01_57 03_57
CLBLL_INT_L.EE4BEG3.NE6END3 03_57 04_56
CLBLL_INT_L.EE4BEG3.NN2END3 02_56 03_57
@ -1822,22 +1820,6 @@ CLBLL_INT_L.IMUX_L9.SW2END0 16_10 23_10
CLBLL_INT_L.IMUX_L9.WL1END0 17_11 22_10 23_10 24_10
CLBLL_INT_L.IMUX_L9.WR1END0 16_10 21_10 23_10 24_10
CLBLL_INT_L.IMUX_L9.WW2END0 17_11 24_10
CLBLL_INT_L.LVB_L0.NN6END3 00_50
CLBLL_INT_L.LVB_L0.NR1END3 00_50
CLBLL_INT_L.LVB_L0.NW6END3 00_50
CLBLL_INT_L.LVB_L0.WR1END3 00_42 00_50
CLBLL_INT_L.LVB_L12.SE6END3 00_45
CLBLL_INT_L.LVB_L12.SW2END3 00_44
CLBLL_INT_L.LVB_L12.SW6END2 00_45 00_46
CLBLL_INT_L.LV_L0.ER1END0 00_04 00_05
CLBLL_INT_L.LV_L0.NR1END0 00_05
CLBLL_INT_L.LV_L0.NW6END0 00_04
CLBLL_INT_L.LV_L0.SR1BEG_S0 00_05
CLBLL_INT_L.LV_L0.SW6END0 00_05
CLBLL_INT_L.LV_L18.NW6END0 00_01
CLBLL_INT_L.LV_L18.SR1BEG_S0 00_08
CLBLL_INT_L.LV_L18.SW6END0 00_02
CLBLL_INT_L.LV_L18.WW4END0 00_08
CLBLL_INT_L.NE2BEG0.EE2END0 08_04 13_04
CLBLL_INT_L.NE2BEG0.EE4END0 08_04 12_04
CLBLL_INT_L.NE2BEG0.EL1END0 08_05 11_04
@ -1962,7 +1944,6 @@ CLBLL_INT_L.NE6BEG2.LOGIC_OUTS_L16 03_38 05_36
CLBLL_INT_L.NE6BEG2.LOGIC_OUTS_L20 05_36 06_37
CLBLL_INT_L.NE6BEG2.LOGIC_OUTS_L2 01_37 06_37
CLBLL_INT_L.NE6BEG2.LOGIC_OUTS_L6 01_37 03_38
CLBLL_INT_L.NE6BEG2.LVB_L12 04_36 06_37
CLBLL_INT_L.NE6BEG2.NE2END2 01_37 02_37
CLBLL_INT_L.NE6BEG2.NE6END2 02_37 04_36
CLBLL_INT_L.NE6BEG2.NN2END2 02_36 02_37
@ -1981,7 +1962,6 @@ CLBLL_INT_L.NE6BEG3.LOGIC_OUTS_L17 05_52 06_53
CLBLL_INT_L.NE6BEG3.LOGIC_OUTS_L21 03_54 05_52
CLBLL_INT_L.NE6BEG3.LOGIC_OUTS_L3 01_53 03_54
CLBLL_INT_L.NE6BEG3.LOGIC_OUTS_L7 01_53 06_53
CLBLL_INT_L.NE6BEG3.LV_L18 04_52 06_53
CLBLL_INT_L.NE6BEG3.NE2END3 01_53 02_53
CLBLL_INT_L.NE6BEG3.NE6END3 02_53 04_52
CLBLL_INT_L.NE6BEG3.NN2END3 02_52 02_53
@ -2178,7 +2158,6 @@ CLBLL_INT_L.NN6BEG1.LOGIC_OUTS_L19 04_21 06_23
CLBLL_INT_L.NN6BEG1.LOGIC_OUTS_L23 05_22 06_23
CLBLL_INT_L.NN6BEG1.LOGIC_OUTS_L5 02_22 04_21
CLBLL_INT_L.NN6BEG1.LOGIC_OUTS_L9 01_23 04_21
CLBLL_INT_L.NN6BEG1.LV_L9 03_23 05_22
CLBLL_INT_L.NN6BEG1.NE2END1 01_22 02_22
CLBLL_INT_L.NN6BEG1.NE6END1 01_22 03_23
CLBLL_INT_L.NN6BEG1.NN2END1 01_22 01_23
@ -2197,7 +2176,6 @@ CLBLL_INT_L.NN6BEG2.LOGIC_OUTS_L16 05_38 06_39
CLBLL_INT_L.NN6BEG2.LOGIC_OUTS_L20 04_37 06_39
CLBLL_INT_L.NN6BEG2.LOGIC_OUTS_L2 02_38 04_37
CLBLL_INT_L.NN6BEG2.LOGIC_OUTS_L6 02_38 05_38
CLBLL_INT_L.NN6BEG2.LVB_L12 03_39 04_37
CLBLL_INT_L.NN6BEG2.NE2END2 01_38 02_38
CLBLL_INT_L.NN6BEG2.NE6END2 01_38 03_39
CLBLL_INT_L.NN6BEG2.NN2END2 01_38 01_39
@ -2216,7 +2194,6 @@ CLBLL_INT_L.NN6BEG3.LOGIC_OUTS_L17 04_53 06_55
CLBLL_INT_L.NN6BEG3.LOGIC_OUTS_L21 05_54 06_55
CLBLL_INT_L.NN6BEG3.LOGIC_OUTS_L3 02_54 05_54
CLBLL_INT_L.NN6BEG3.LOGIC_OUTS_L7 02_54 04_53
CLBLL_INT_L.NN6BEG3.LV_L18 03_55 04_53
CLBLL_INT_L.NN6BEG3.NE2END3 01_54 02_54
CLBLL_INT_L.NN6BEG3.NE6END3 01_54 03_55
CLBLL_INT_L.NN6BEG3.NN2END3 01_54 01_55
@ -2429,7 +2406,6 @@ CLBLL_INT_L.NW6BEG2.LOGIC_OUTS_L16 04_33 06_35
CLBLL_INT_L.NW6BEG2.LOGIC_OUTS_L20 05_34 06_35
CLBLL_INT_L.NW6BEG2.LOGIC_OUTS_L2 02_34 05_34
CLBLL_INT_L.NW6BEG2.LOGIC_OUTS_L6 02_34 04_33
CLBLL_INT_L.NW6BEG2.LVB_L12 03_35 04_33
CLBLL_INT_L.NW6BEG2.NE2END2 02_34 04_34
CLBLL_INT_L.NW6BEG2.NE6END2 03_35 04_34
CLBLL_INT_L.NW6BEG2.NN2END2 01_35 04_34
@ -2448,7 +2424,6 @@ CLBLL_INT_L.NW6BEG3.LOGIC_OUTS_L17 05_50 06_51
CLBLL_INT_L.NW6BEG3.LOGIC_OUTS_L21 04_49 06_51
CLBLL_INT_L.NW6BEG3.LOGIC_OUTS_L3 02_50 04_49
CLBLL_INT_L.NW6BEG3.LOGIC_OUTS_L7 02_50 05_50
CLBLL_INT_L.NW6BEG3.LV_L18 03_51 04_49
CLBLL_INT_L.NW6BEG3.NE2END3 02_50 04_50
CLBLL_INT_L.NW6BEG3.NE6END3 03_51 04_50
CLBLL_INT_L.NW6BEG3.NN2END3 01_51 04_50
@ -2549,7 +2524,6 @@ CLBLL_INT_L.SE6BEG0.LOGIC_OUTS_L18 04_09 06_11
CLBLL_INT_L.SE6BEG0.LOGIC_OUTS_L22 05_10 06_11
CLBLL_INT_L.SE6BEG0.LOGIC_OUTS_L4 02_10 04_09
CLBLL_INT_L.SE6BEG0.LOGIC_OUTS_L8 01_11 04_09
CLBLL_INT_L.SE6BEG0.LV_L0 03_11 05_10
CLBLL_INT_L.SE6BEG0.NE2END0 02_10 03_08
CLBLL_INT_L.SE6BEG0.NE6END0 03_08 03_11
CLBLL_INT_L.SE6BEG0.NN2END0 01_11 03_08
@ -2862,7 +2836,6 @@ CLBLL_INT_L.SS6BEG0.LOGIC_OUTS_L18 05_14 06_15
CLBLL_INT_L.SS6BEG0.LOGIC_OUTS_L22 04_13 06_15
CLBLL_INT_L.SS6BEG0.LOGIC_OUTS_L4 02_14 05_14
CLBLL_INT_L.SS6BEG0.LOGIC_OUTS_L8 01_15 05_14
CLBLL_INT_L.SS6BEG0.LV_L0 03_15 05_14
CLBLL_INT_L.SS6BEG0.NW2END1 02_14 04_14
CLBLL_INT_L.SS6BEG0.NW6END1 04_14 06_15
CLBLL_INT_L.SS6BEG0.SE2END0 02_14 03_12
@ -2899,7 +2872,6 @@ CLBLL_INT_L.SS6BEG2.LOGIC_OUTS_L16 05_46 06_47
CLBLL_INT_L.SS6BEG2.LOGIC_OUTS_L20 04_45 06_47
CLBLL_INT_L.SS6BEG2.LOGIC_OUTS_L2 02_46 04_45
CLBLL_INT_L.SS6BEG2.LOGIC_OUTS_L6 02_46 05_46
CLBLL_INT_L.SS6BEG2.LVB_L0 03_47 05_46
CLBLL_INT_L.SS6BEG2.NW2END3 02_46 04_46
CLBLL_INT_L.SS6BEG2.NW6END3 04_46 06_47
CLBLL_INT_L.SS6BEG2.SE2END2 02_46 03_44
@ -3015,7 +2987,6 @@ CLBLL_INT_L.SW6BEG0.LOGIC_OUTS_L18 03_14 05_12
CLBLL_INT_L.SW6BEG0.LOGIC_OUTS_L22 05_12 06_13
CLBLL_INT_L.SW6BEG0.LOGIC_OUTS_L4 01_13 03_14
CLBLL_INT_L.SW6BEG0.LOGIC_OUTS_L8 02_12 03_14
CLBLL_INT_L.SW6BEG0.LV_L0 03_14 04_12
CLBLL_INT_L.SW6BEG0.NW2END1 01_13 04_15
CLBLL_INT_L.SW6BEG0.NW6END1 04_15 05_12
CLBLL_INT_L.SW6BEG0.SE2END0 01_13 03_13
@ -3326,7 +3297,6 @@ CLBLL_INT_L.WW4BEG0.LOGIC_OUTS_L18 05_00 06_01
CLBLL_INT_L.WW4BEG0.LOGIC_OUTS_L22 03_02 05_00
CLBLL_INT_L.WW4BEG0.LOGIC_OUTS_L4 01_01 06_01
CLBLL_INT_L.WW4BEG0.LOGIC_OUTS_L8 02_00 06_01
CLBLL_INT_L.WW4BEG0.LV_L0 03_02 04_00
CLBLL_INT_L.WW4BEG0.NE2END0 01_01 04_03
CLBLL_INT_L.WW4BEG0.NE6END0 04_00 04_03
CLBLL_INT_L.WW4BEG0.NN2END0 02_00 04_03
@ -3381,7 +3351,6 @@ CLBLL_INT_L.WW4BEG3.LOGIC_OUTS_L17 03_50 05_48
CLBLL_INT_L.WW4BEG3.LOGIC_OUTS_L21 05_48 06_49
CLBLL_INT_L.WW4BEG3.LOGIC_OUTS_L3 01_49 06_49
CLBLL_INT_L.WW4BEG3.LOGIC_OUTS_L7 01_49 03_50
CLBLL_INT_L.WW4BEG3.LV_L18 04_48 06_49
CLBLL_INT_L.WW4BEG3.NE2END3 01_49 04_51
CLBLL_INT_L.WW4BEG3.NE6END3 04_48 04_51
CLBLL_INT_L.WW4BEG3.NN2END3 02_48 04_51

28
artix7/seg_clbll_int_r.segbits
View File

@ -1821,20 +1821,6 @@ CLBLL_INT_R.IMUX9.SW2END0 16_10 23_10
CLBLL_INT_R.IMUX9.WL1END0 17_11 22_10 23_10 24_10
CLBLL_INT_R.IMUX9.WR1END0 16_10 21_10 23_10 24_10
CLBLL_INT_R.IMUX9.WW2END0 17_11 24_10
CLBLL_INT_R.LV0.ER1END0 00_04 00_05
CLBLL_INT_R.LV0.NR1END0 00_05
CLBLL_INT_R.LV0.NW6END0 00_04
CLBLL_INT_R.LV0.SR1BEG_S0 00_05
CLBLL_INT_R.LV0.SW6END0 00_05
CLBLL_INT_R.LV18.NW6END0 00_01
CLBLL_INT_R.LV18.SR1BEG_S0 00_08
CLBLL_INT_R.LV18.SW6END0 00_02
CLBLL_INT_R.LV18.WW4END0 00_01 00_08
CLBLL_INT_R.LVB0.NE2END2 00_52
CLBLL_INT_R.LVB0.NN6END3 00_50
CLBLL_INT_R.LVB0.NR1END3 00_50
CLBLL_INT_R.LVB0.NW2END2 00_52
CLBLL_INT_R.LVB0.WR1END3 00_42 00_50
CLBLL_INT_R.NE2BEG0.EE2END0 08_04 13_04
CLBLL_INT_R.NE2BEG0.EE4END0 08_04 12_04
CLBLL_INT_R.NE2BEG0.EL1END0 08_05 11_04
@ -1959,7 +1945,6 @@ CLBLL_INT_R.NE6BEG2.LOGIC_OUTS16 03_38 05_36
CLBLL_INT_R.NE6BEG2.LOGIC_OUTS20 05_36 06_37
CLBLL_INT_R.NE6BEG2.LOGIC_OUTS2 01_37 06_37
CLBLL_INT_R.NE6BEG2.LOGIC_OUTS6 01_37 03_38
CLBLL_INT_R.NE6BEG2.LVB12 04_36 06_37
CLBLL_INT_R.NE6BEG2.NE2END2 01_37 02_37
CLBLL_INT_R.NE6BEG2.NE6END2 02_37 04_36
CLBLL_INT_R.NE6BEG2.NN2END2 02_36 02_37
@ -1978,7 +1963,6 @@ CLBLL_INT_R.NE6BEG3.LOGIC_OUTS17 05_52 06_53
CLBLL_INT_R.NE6BEG3.LOGIC_OUTS21 03_54 05_52
CLBLL_INT_R.NE6BEG3.LOGIC_OUTS3 01_53 03_54
CLBLL_INT_R.NE6BEG3.LOGIC_OUTS7 01_53 06_53
CLBLL_INT_R.NE6BEG3.LV18 04_52 06_53
CLBLL_INT_R.NE6BEG3.NE2END3 01_53 02_53
CLBLL_INT_R.NE6BEG3.NE6END3 02_53 04_52
CLBLL_INT_R.NE6BEG3.NN2END3 02_52 02_53
@ -2193,7 +2177,6 @@ CLBLL_INT_R.NN6BEG2.LOGIC_OUTS16 05_38 06_39
CLBLL_INT_R.NN6BEG2.LOGIC_OUTS20 04_37 06_39
CLBLL_INT_R.NN6BEG2.LOGIC_OUTS2 02_38 04_37
CLBLL_INT_R.NN6BEG2.LOGIC_OUTS6 02_38 05_38
CLBLL_INT_R.NN6BEG2.LVB12 03_39 04_37
CLBLL_INT_R.NN6BEG2.NE2END2 01_38 02_38
CLBLL_INT_R.NN6BEG2.NE6END2 01_38 03_39
CLBLL_INT_R.NN6BEG2.NN2END2 01_38 01_39
@ -2212,7 +2195,6 @@ CLBLL_INT_R.NN6BEG3.LOGIC_OUTS17 04_53 06_55
CLBLL_INT_R.NN6BEG3.LOGIC_OUTS21 05_54 06_55
CLBLL_INT_R.NN6BEG3.LOGIC_OUTS3 02_54 05_54
CLBLL_INT_R.NN6BEG3.LOGIC_OUTS7 02_54 04_53
CLBLL_INT_R.NN6BEG3.LV18 03_55 04_53
CLBLL_INT_R.NN6BEG3.NE2END3 01_54 02_54
CLBLL_INT_R.NN6BEG3.NE6END3 01_54 03_55
CLBLL_INT_R.NN6BEG3.NN2END3 01_54 01_55
@ -2425,7 +2407,6 @@ CLBLL_INT_R.NW6BEG2.LOGIC_OUTS16 04_33 06_35
CLBLL_INT_R.NW6BEG2.LOGIC_OUTS20 05_34 06_35
CLBLL_INT_R.NW6BEG2.LOGIC_OUTS2 02_34 05_34
CLBLL_INT_R.NW6BEG2.LOGIC_OUTS6 02_34 04_33
CLBLL_INT_R.NW6BEG2.LVB12 03_35 04_33
CLBLL_INT_R.NW6BEG2.NE2END2 02_34 04_34
CLBLL_INT_R.NW6BEG2.NE6END2 03_35 04_34
CLBLL_INT_R.NW6BEG2.NN2END2 01_35 04_34
@ -2444,7 +2425,6 @@ CLBLL_INT_R.NW6BEG3.LOGIC_OUTS17 05_50 06_51
CLBLL_INT_R.NW6BEG3.LOGIC_OUTS21 04_49 06_51
CLBLL_INT_R.NW6BEG3.LOGIC_OUTS3 02_50 04_49
CLBLL_INT_R.NW6BEG3.LOGIC_OUTS7 02_50 05_50
CLBLL_INT_R.NW6BEG3.LV18 03_51 04_49
CLBLL_INT_R.NW6BEG3.NE2END3 02_50 04_50
CLBLL_INT_R.NW6BEG3.NE6END3 03_51 04_50
CLBLL_INT_R.NW6BEG3.NN2END3 01_51 04_50
@ -2545,7 +2525,6 @@ CLBLL_INT_R.SE6BEG0.LOGIC_OUTS18 04_09 06_11
CLBLL_INT_R.SE6BEG0.LOGIC_OUTS22 05_10 06_11
CLBLL_INT_R.SE6BEG0.LOGIC_OUTS4 02_10 04_09
CLBLL_INT_R.SE6BEG0.LOGIC_OUTS8 01_11 04_09
CLBLL_INT_R.SE6BEG0.LV0 03_11 05_10
CLBLL_INT_R.SE6BEG0.NE2END0 02_10 03_08
CLBLL_INT_R.SE6BEG0.NE6END0 03_08 03_11
CLBLL_INT_R.SE6BEG0.NN2END0 01_11 03_08
@ -2600,7 +2579,6 @@ CLBLL_INT_R.SE6BEG3.LOGIC_OUTS17 05_58 06_59
CLBLL_INT_R.SE6BEG3.LOGIC_OUTS21 04_57 06_59
CLBLL_INT_R.SE6BEG3.LOGIC_OUTS3 02_58 04_57
CLBLL_INT_R.SE6BEG3.LOGIC_OUTS7 02_58 05_58
CLBLL_INT_R.SE6BEG3.LV18 03_59 04_57
CLBLL_INT_R.SE6BEG3.NE2END3 02_58 03_56
CLBLL_INT_R.SE6BEG3.NE6END3 03_56 03_59
CLBLL_INT_R.SE6BEG3.NN2END3 01_59 03_56
@ -2859,7 +2837,6 @@ CLBLL_INT_R.SS6BEG0.LOGIC_OUTS18 05_14 06_15
CLBLL_INT_R.SS6BEG0.LOGIC_OUTS22 04_13 06_15
CLBLL_INT_R.SS6BEG0.LOGIC_OUTS4 02_14 05_14
CLBLL_INT_R.SS6BEG0.LOGIC_OUTS8 01_15 05_14
CLBLL_INT_R.SS6BEG0.LV0 03_15 05_14
CLBLL_INT_R.SS6BEG0.NW2END1 02_14 04_14
CLBLL_INT_R.SS6BEG0.NW6END1 04_14 06_15
CLBLL_INT_R.SS6BEG0.SE2END0 02_14 03_12
@ -2896,7 +2873,6 @@ CLBLL_INT_R.SS6BEG2.LOGIC_OUTS16 05_46 06_47
CLBLL_INT_R.SS6BEG2.LOGIC_OUTS20 04_45 06_47
CLBLL_INT_R.SS6BEG2.LOGIC_OUTS2 02_46 04_45
CLBLL_INT_R.SS6BEG2.LOGIC_OUTS6 02_46 05_46
CLBLL_INT_R.SS6BEG2.LVB0 03_47 05_46
CLBLL_INT_R.SS6BEG2.NW2END3 02_46 04_46
CLBLL_INT_R.SS6BEG2.NW6END3 04_46 06_47
CLBLL_INT_R.SS6BEG2.SE2END2 02_46 03_44
@ -3013,7 +2989,6 @@ CLBLL_INT_R.SW6BEG0.LOGIC_OUTS18 03_14 05_12
CLBLL_INT_R.SW6BEG0.LOGIC_OUTS22 05_12 06_13
CLBLL_INT_R.SW6BEG0.LOGIC_OUTS4 01_13 03_14
CLBLL_INT_R.SW6BEG0.LOGIC_OUTS8 02_12 03_14
CLBLL_INT_R.SW6BEG0.LV0 03_14 04_12
CLBLL_INT_R.SW6BEG0.NW2END1 01_13 04_15
CLBLL_INT_R.SW6BEG0.NW6END1 04_15 05_12
CLBLL_INT_R.SW6BEG0.SE2END0 01_13 03_13
@ -3050,7 +3025,6 @@ CLBLL_INT_R.SW6BEG2.LOGIC_OUTS16 03_46 05_44
CLBLL_INT_R.SW6BEG2.LOGIC_OUTS20 05_44 06_45
CLBLL_INT_R.SW6BEG2.LOGIC_OUTS2 01_45 06_45
CLBLL_INT_R.SW6BEG2.LOGIC_OUTS6 01_45 03_46
CLBLL_INT_R.SW6BEG2.LVB0 03_46 04_44
CLBLL_INT_R.SW6BEG2.NW2END3 01_45 04_47
CLBLL_INT_R.SW6BEG2.NW6END3 04_47 05_44
CLBLL_INT_R.SW6BEG2.SE2END2 01_45 03_45
@ -3324,7 +3298,6 @@ CLBLL_INT_R.WW4BEG0.LOGIC_OUTS18 05_00 06_01
CLBLL_INT_R.WW4BEG0.LOGIC_OUTS22 03_02 05_00
CLBLL_INT_R.WW4BEG0.LOGIC_OUTS4 01_01 06_01
CLBLL_INT_R.WW4BEG0.LOGIC_OUTS8 02_00 06_01
CLBLL_INT_R.WW4BEG0.LV0 03_02 04_00
CLBLL_INT_R.WW4BEG0.NE2END0 01_01 04_03
CLBLL_INT_R.WW4BEG0.NE6END0 04_00 04_03
CLBLL_INT_R.WW4BEG0.NN2END0 02_00 04_03
@ -3379,7 +3352,6 @@ CLBLL_INT_R.WW4BEG3.LOGIC_OUTS17 03_50 05_48
CLBLL_INT_R.WW4BEG3.LOGIC_OUTS21 05_48 06_49
CLBLL_INT_R.WW4BEG3.LOGIC_OUTS3 01_49 06_49
CLBLL_INT_R.WW4BEG3.LOGIC_OUTS7 01_49 03_50
CLBLL_INT_R.WW4BEG3.LV18 04_48 06_49
CLBLL_INT_R.WW4BEG3.NE2END3 01_49 04_51
CLBLL_INT_R.WW4BEG3.NE6END3 04_48 04_51
CLBLL_INT_R.WW4BEG3.NN2END3 02_48 04_51

14
artix7/seg_clblm_int_l.segbits
View File

@ -228,7 +228,6 @@ CLBLM_INT_L.EE4BEG0.LOGIC_OUTS_L18 05_08 06_09
CLBLM_INT_L.EE4BEG0.LOGIC_OUTS_L22 03_10 05_08
CLBLM_INT_L.EE4BEG0.LOGIC_OUTS_L4 01_09 06_09
CLBLM_INT_L.EE4BEG0.LOGIC_OUTS_L8 02_08 06_09
CLBLM_INT_L.EE4BEG0.LV_L0 03_10 04_08
CLBLM_INT_L.EE4BEG0.NE2END0 01_09 03_09
CLBLM_INT_L.EE4BEG0.NN2END0 02_08 03_09
CLBLM_INT_L.EE4BEG0.NN6END0 03_09 05_08
@ -271,7 +270,6 @@ CLBLM_INT_L.EE4BEG3.LOGIC_OUTS_L17 03_58 05_56
CLBLM_INT_L.EE4BEG3.LOGIC_OUTS_L21 05_56 06_57
CLBLM_INT_L.EE4BEG3.LOGIC_OUTS_L3 01_57 06_57
CLBLM_INT_L.EE4BEG3.LOGIC_OUTS_L7 01_57 03_58
CLBLM_INT_L.EE4BEG3.LV_L18 04_56 06_57
CLBLM_INT_L.EE4BEG3.NN2END3 02_56 03_57
CLBLM_INT_L.EE4BEG3.NN6END3 03_57 05_56
CLBLM_INT_L.EE4BEG3.SE2END3 01_57 02_57
@ -1711,12 +1709,6 @@ CLBLM_INT_L.IMUX_L9.SW2END0 16_10 23_10
CLBLM_INT_L.IMUX_L9.WL1END0 17_11 22_10 23_10 24_10
CLBLM_INT_L.IMUX_L9.WR1END0 16_10 21_10 23_10 24_10
CLBLM_INT_L.IMUX_L9.WW2END0 17_11 24_10
CLBLM_INT_L.LV_L0.NR1END0 00_05
CLBLM_INT_L.LV_L0.NW6END0 00_04
CLBLM_INT_L.LV_L0.SR1BEG_S0 00_05
CLBLM_INT_L.LV_L18.SR1BEG_S0 00_08
CLBLM_INT_L.LV_L18.SW6END0 00_02
CLBLM_INT_L.LV_L18.WR1END0 00_01
CLBLM_INT_L.NE2BEG0.EE2END0 08_04 13_04
CLBLM_INT_L.NE2BEG0.EL1END0 08_05 11_04
CLBLM_INT_L.NE2BEG0.ER1END0 05_05 11_04
@ -1837,7 +1829,6 @@ CLBLM_INT_L.NE6BEG3.LOGIC_OUTS_L17 05_52 06_53
CLBLM_INT_L.NE6BEG3.LOGIC_OUTS_L21 03_54 05_52
CLBLM_INT_L.NE6BEG3.LOGIC_OUTS_L3 01_53 03_54
CLBLM_INT_L.NE6BEG3.LOGIC_OUTS_L7 01_53 06_53
CLBLM_INT_L.NE6BEG3.LV_L18 04_52 06_53
CLBLM_INT_L.NE6BEG3.NE2END3 01_53 02_53
CLBLM_INT_L.NE6BEG3.NN2END3 02_52 02_53
CLBLM_INT_L.NE6BEG3.NN6END3 02_53 05_52
@ -2038,7 +2029,6 @@ CLBLM_INT_L.NN6BEG2.LOGIC_OUTS_L16 05_38 06_39
CLBLM_INT_L.NN6BEG2.LOGIC_OUTS_L20 04_37 06_39
CLBLM_INT_L.NN6BEG2.LOGIC_OUTS_L2 02_38 04_37
CLBLM_INT_L.NN6BEG2.LOGIC_OUTS_L6 02_38 05_38
CLBLM_INT_L.NN6BEG2.LVB_L12 03_39 04_37
CLBLM_INT_L.NN6BEG2.NE2END2 01_38 02_38
CLBLM_INT_L.NN6BEG2.NN2END2 01_38 01_39
CLBLM_INT_L.NN6BEG2.NN6END2 01_38 06_39
@ -2054,7 +2044,6 @@ CLBLM_INT_L.NN6BEG3.LOGIC_OUTS_L17 04_53 06_55
CLBLM_INT_L.NN6BEG3.LOGIC_OUTS_L21 05_54 06_55
CLBLM_INT_L.NN6BEG3.LOGIC_OUTS_L3 02_54 05_54
CLBLM_INT_L.NN6BEG3.LOGIC_OUTS_L7 02_54 04_53
CLBLM_INT_L.NN6BEG3.LV_L18 03_55 04_53
CLBLM_INT_L.NN6BEG3.NE2END3 01_54 02_54
CLBLM_INT_L.NN6BEG3.NE6END3 01_54 03_55
CLBLM_INT_L.NN6BEG3.NN2END3 01_54 01_55
@ -2253,7 +2242,6 @@ CLBLM_INT_L.NW6BEG3.LOGIC_OUTS_L11 01_51 05_50
CLBLM_INT_L.NW6BEG3.LOGIC_OUTS_L15 01_51 04_49
CLBLM_INT_L.NW6BEG3.LOGIC_OUTS_L21 04_49 06_51
CLBLM_INT_L.NW6BEG3.LOGIC_OUTS_L3 02_50 04_49
CLBLM_INT_L.NW6BEG3.LV_L18 03_51 04_49
CLBLM_INT_L.NW6BEG3.NN2END3 01_51 04_50
CLBLM_INT_L.NW6BEG3.NN6END3 04_50 06_51
CLBLM_INT_L.NW6BEG3.NW2END3 01_50 02_50
@ -2334,7 +2322,6 @@ CLBLM_INT_L.SE6BEG0.LOGIC_OUTS_L18 04_09 06_11
CLBLM_INT_L.SE6BEG0.LOGIC_OUTS_L22 05_10 06_11
CLBLM_INT_L.SE6BEG0.LOGIC_OUTS_L4 02_10 04_09
CLBLM_INT_L.SE6BEG0.LOGIC_OUTS_L8 01_11 04_09
CLBLM_INT_L.SE6BEG0.LV_L0 03_11 05_10
CLBLM_INT_L.SE6BEG0.NE2END0 02_10 03_08
CLBLM_INT_L.SE6BEG0.NN2END0 01_11 03_08
CLBLM_INT_L.SE6BEG0.NN6END0 03_08 06_11
@ -2599,7 +2586,6 @@ CLBLM_INT_L.SS6BEG0.LOGIC_OUTS_L18 05_14 06_15
CLBLM_INT_L.SS6BEG0.LOGIC_OUTS_L22 04_13 06_15
CLBLM_INT_L.SS6BEG0.LOGIC_OUTS_L4 02_14 05_14
CLBLM_INT_L.SS6BEG0.LOGIC_OUTS_L8 01_15 05_14
CLBLM_INT_L.SS6BEG0.LV_L0 03_15 05_14
CLBLM_INT_L.SS6BEG0.NW2END1 02_14 04_14
CLBLM_INT_L.SS6BEG0.NW6END1 04_14 06_15
CLBLM_INT_L.SS6BEG0.SE2END0 02_14 03_12

18
artix7/seg_clblm_int_r.segbits
View File

@ -267,7 +267,6 @@ CLBLM_INT_R.EE4BEG3.LOGIC_OUTS17 03_58 05_56
CLBLM_INT_R.EE4BEG3.LOGIC_OUTS21 05_56 06_57
CLBLM_INT_R.EE4BEG3.LOGIC_OUTS3 01_57 06_57
CLBLM_INT_R.EE4BEG3.LOGIC_OUTS7 01_57 03_58
CLBLM_INT_R.EE4BEG3.LV18 04_56 06_57
CLBLM_INT_R.EE4BEG3.NE2END3 01_57 03_57
CLBLM_INT_R.EE4BEG3.NN2END3 02_56 03_57
CLBLM_INT_R.EE4BEG3.NN6END3 03_57 05_56
@ -1726,15 +1725,6 @@ CLBLM_INT_R.IMUX9.SW2END0 16_10 23_10
CLBLM_INT_R.IMUX9.WL1END0 17_11 22_10 23_10 24_10
CLBLM_INT_R.IMUX9.WR1END0 16_10 21_10 23_10 24_10
CLBLM_INT_R.IMUX9.WW2END0 17_11 24_10
CLBLM_INT_R.LV0.ER1END0 00_04 00_05
CLBLM_INT_R.LV0.NR1END0 00_05
CLBLM_INT_R.LV0.NW6END0 00_04
CLBLM_INT_R.LV0.SR1BEG_S0 00_05
CLBLM_INT_R.LV18.SR1BEG_S0 00_08
CLBLM_INT_R.LV18.SW6END0 00_02
CLBLM_INT_R.LV18.WR1END0 00_01
CLBLM_INT_R.LV18.WW4END0 00_08
CLBLM_INT_R.LVB0.NN6END3 00_50
CLBLM_INT_R.NE2BEG0.EE2END0 08_04 13_04
CLBLM_INT_R.NE2BEG0.EL1END0 08_05 11_04
CLBLM_INT_R.NE2BEG0.ER1END0 05_05 11_04
@ -1866,7 +1856,6 @@ CLBLM_INT_R.NE6BEG3.LOGIC_OUTS17 05_52 06_53
CLBLM_INT_R.NE6BEG3.LOGIC_OUTS21 03_54 05_52
CLBLM_INT_R.NE6BEG3.LOGIC_OUTS3 01_53 03_54
CLBLM_INT_R.NE6BEG3.LOGIC_OUTS7 01_53 06_53
CLBLM_INT_R.NE6BEG3.LV18 04_52 06_53
CLBLM_INT_R.NE6BEG3.NE2END3 01_53 02_53
CLBLM_INT_R.NE6BEG3.NE6END3 02_53 04_52
CLBLM_INT_R.NE6BEG3.NN2END3 02_52 02_53
@ -2069,7 +2058,6 @@ CLBLM_INT_R.NN6BEG2.LOGIC_OUTS16 05_38 06_39
CLBLM_INT_R.NN6BEG2.LOGIC_OUTS20 04_37 06_39
CLBLM_INT_R.NN6BEG2.LOGIC_OUTS2 02_38 04_37
CLBLM_INT_R.NN6BEG2.LOGIC_OUTS6 02_38 05_38
CLBLM_INT_R.NN6BEG2.LVB12 03_39 04_37
CLBLM_INT_R.NN6BEG2.NE2END2 01_38 02_38
CLBLM_INT_R.NN6BEG2.NE6END2 01_38 03_39
CLBLM_INT_R.NN6BEG2.NN2END2 01_38 01_39
@ -2086,7 +2074,6 @@ CLBLM_INT_R.NN6BEG3.LOGIC_OUTS17 04_53 06_55
CLBLM_INT_R.NN6BEG3.LOGIC_OUTS21 05_54 06_55
CLBLM_INT_R.NN6BEG3.LOGIC_OUTS3 02_54 05_54
CLBLM_INT_R.NN6BEG3.LOGIC_OUTS7 02_54 04_53
CLBLM_INT_R.NN6BEG3.LV18 03_55 04_53
CLBLM_INT_R.NN6BEG3.NE2END3 01_54 02_54
CLBLM_INT_R.NN6BEG3.NE6END3 01_54 03_55
CLBLM_INT_R.NN6BEG3.NN2END3 01_54 01_55
@ -2303,7 +2290,6 @@ CLBLM_INT_R.NW6BEG3.LOGIC_OUTS17 05_50 06_51
CLBLM_INT_R.NW6BEG3.LOGIC_OUTS21 04_49 06_51
CLBLM_INT_R.NW6BEG3.LOGIC_OUTS3 02_50 04_49
CLBLM_INT_R.NW6BEG3.LOGIC_OUTS7 02_50 05_50
CLBLM_INT_R.NW6BEG3.LV18 03_51 04_49
CLBLM_INT_R.NW6BEG3.NE2END3 02_50 04_50
CLBLM_INT_R.NW6BEG3.NN2END3 01_51 04_50
CLBLM_INT_R.NW6BEG3.NN6END3 04_50 06_51
@ -2396,7 +2382,6 @@ CLBLM_INT_R.SE6BEG0.LOGIC_OUTS18 04_09 06_11
CLBLM_INT_R.SE6BEG0.LOGIC_OUTS22 05_10 06_11
CLBLM_INT_R.SE6BEG0.LOGIC_OUTS4 02_10 04_09
CLBLM_INT_R.SE6BEG0.LOGIC_OUTS8 01_11 04_09
CLBLM_INT_R.SE6BEG0.LV0 03_11 05_10
CLBLM_INT_R.SE6BEG0.NE2END0 02_10 03_08
CLBLM_INT_R.SE6BEG0.NN2END0 01_11 03_08
CLBLM_INT_R.SE6BEG0.NN6END0 03_08 06_11
@ -2669,7 +2654,6 @@ CLBLM_INT_R.SS6BEG0.LOGIC_OUTS18 05_14 06_15
CLBLM_INT_R.SS6BEG0.LOGIC_OUTS22 04_13 06_15
CLBLM_INT_R.SS6BEG0.LOGIC_OUTS4 02_14 05_14
CLBLM_INT_R.SS6BEG0.LOGIC_OUTS8 01_15 05_14
CLBLM_INT_R.SS6BEG0.LV0 03_15 05_14
CLBLM_INT_R.SS6BEG0.NW2END1 02_14 04_14
CLBLM_INT_R.SS6BEG0.NW6END1 04_14 06_15
CLBLM_INT_R.SS6BEG0.SE2END0 02_14 03_12
@ -2704,7 +2688,6 @@ CLBLM_INT_R.SS6BEG2.LOGIC_OUTS16 05_46 06_47
CLBLM_INT_R.SS6BEG2.LOGIC_OUTS20 04_45 06_47
CLBLM_INT_R.SS6BEG2.LOGIC_OUTS2 02_46 04_45
CLBLM_INT_R.SS6BEG2.LOGIC_OUTS6 02_46 05_46
CLBLM_INT_R.SS6BEG2.LVB0 03_47 05_46
CLBLM_INT_R.SS6BEG2.NW2END3 02_46 04_46
CLBLM_INT_R.SS6BEG2.NW6END3 04_46 06_47
CLBLM_INT_R.SS6BEG2.SE2END2 02_46 03_44
@ -2816,7 +2799,6 @@ CLBLM_INT_R.SW6BEG0.LOGIC_OUTS18 03_14 05_12
CLBLM_INT_R.SW6BEG0.LOGIC_OUTS22 05_12 06_13
CLBLM_INT_R.SW6BEG0.LOGIC_OUTS4 01_13 03_14
CLBLM_INT_R.SW6BEG0.LOGIC_OUTS8 02_12 03_14
CLBLM_INT_R.SW6BEG0.LV0 03_14 04_12
CLBLM_INT_R.SW6BEG0.NW2END1 01_13 04_15
CLBLM_INT_R.SW6BEG0.NW6END1 04_15 05_12
CLBLM_INT_R.SW6BEG0.SE2END0 01_13 03_13