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prjxray-db
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Updating DB based on "Add 071-ppips" 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2017-11-26 03:23:47 +01:00
parent 6c3fbee971
commit b327fb4b53
6 changed files with 602 additions and 0 deletions
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94
artix7/ppips_clbll_l.db Normal file
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CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A always
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B always
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C always
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A always
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B always
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C always
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

94
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CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A always
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B always
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C always
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A always
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B always
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C always
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

99
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CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A always
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B always
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C always
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A always
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B always
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C always
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

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CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A always
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B always
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C always
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A always
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B always
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C always
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

108
artix7/ppips_int_l.db Normal file
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@ -0,0 +1,108 @@
INT_L.FAN_ALT0.VCC_WIRE default
INT_L.FAN_ALT1.VCC_WIRE default
INT_L.FAN_ALT2.VCC_WIRE default
INT_L.FAN_ALT3.VCC_WIRE default
INT_L.FAN_ALT4.VCC_WIRE default
INT_L.FAN_ALT5.VCC_WIRE default
INT_L.FAN_ALT6.VCC_WIRE default
INT_L.FAN_ALT7.VCC_WIRE default
INT_L.BYP_ALT0.VCC_WIRE default
INT_L.BYP_ALT1.VCC_WIRE default
INT_L.BYP_ALT2.VCC_WIRE default
INT_L.BYP_ALT3.VCC_WIRE default
INT_L.BYP_ALT4.VCC_WIRE default
INT_L.BYP_ALT5.VCC_WIRE default
INT_L.BYP_ALT6.VCC_WIRE default
INT_L.BYP_ALT7.VCC_WIRE default
INT_L.IMUX_L0.VCC_WIRE default
INT_L.IMUX_L1.VCC_WIRE default
INT_L.IMUX_L2.VCC_WIRE default
INT_L.IMUX_L3.VCC_WIRE default
INT_L.IMUX_L4.VCC_WIRE default
INT_L.IMUX_L5.VCC_WIRE default
INT_L.IMUX_L6.VCC_WIRE default
INT_L.IMUX_L7.VCC_WIRE default
INT_L.IMUX_L8.VCC_WIRE default
INT_L.IMUX_L9.VCC_WIRE default
INT_L.IMUX_L10.VCC_WIRE default
INT_L.IMUX_L11.VCC_WIRE default
INT_L.IMUX_L12.VCC_WIRE default
INT_L.IMUX_L13.VCC_WIRE default
INT_L.IMUX_L14.VCC_WIRE default
INT_L.IMUX_L15.VCC_WIRE default
INT_L.IMUX_L16.VCC_WIRE default
INT_L.IMUX_L17.VCC_WIRE default
INT_L.IMUX_L18.VCC_WIRE default
INT_L.IMUX_L19.VCC_WIRE default
INT_L.IMUX_L20.VCC_WIRE default
INT_L.IMUX_L21.VCC_WIRE default
INT_L.IMUX_L22.VCC_WIRE default
INT_L.IMUX_L23.VCC_WIRE default
INT_L.IMUX_L24.VCC_WIRE default
INT_L.IMUX_L25.VCC_WIRE default
INT_L.IMUX_L26.VCC_WIRE default
INT_L.IMUX_L27.VCC_WIRE default
INT_L.IMUX_L28.VCC_WIRE default
INT_L.IMUX_L29.VCC_WIRE default
INT_L.IMUX_L30.VCC_WIRE default
INT_L.IMUX_L31.VCC_WIRE default
INT_L.IMUX_L32.VCC_WIRE default
INT_L.IMUX_L33.VCC_WIRE default
INT_L.IMUX_L34.VCC_WIRE default
INT_L.IMUX_L35.VCC_WIRE default
INT_L.IMUX_L36.VCC_WIRE default
INT_L.IMUX_L37.VCC_WIRE default
INT_L.IMUX_L38.VCC_WIRE default
INT_L.IMUX_L39.VCC_WIRE default
INT_L.IMUX_L40.VCC_WIRE default
INT_L.IMUX_L41.VCC_WIRE default
INT_L.IMUX_L42.VCC_WIRE default
INT_L.IMUX_L43.VCC_WIRE default
INT_L.IMUX_L44.VCC_WIRE default
INT_L.IMUX_L45.VCC_WIRE default
INT_L.IMUX_L46.VCC_WIRE default
INT_L.IMUX_L47.VCC_WIRE default
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
INT_L.BYP_BOUNCE3.BYP_ALT3 always
INT_L.BYP_BOUNCE4.BYP_ALT4 always
INT_L.BYP_BOUNCE5.BYP_ALT5 always
INT_L.BYP_BOUNCE6.BYP_ALT6 always
INT_L.BYP_BOUNCE7.BYP_ALT7 always
INT_L.BYP_L0.BYP_ALT0 always
INT_L.BYP_L1.BYP_ALT1 always
INT_L.BYP_L2.BYP_ALT2 always
INT_L.BYP_L3.BYP_ALT3 always
INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
INT_L.FAN_BOUNCE3.FAN_ALT3 always
INT_L.FAN_BOUNCE4.FAN_ALT4 always
INT_L.FAN_BOUNCE5.FAN_ALT5 always
INT_L.FAN_BOUNCE6.FAN_ALT6 always
INT_L.FAN_BOUNCE7.FAN_ALT7 always
INT_L.FAN_L0.FAN_ALT0 always
INT_L.FAN_L1.FAN_ALT1 always
INT_L.FAN_L2.FAN_ALT2 always
INT_L.FAN_L3.FAN_ALT3 always
INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always

108
artix7/ppips_int_r.db Normal file
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@ -0,0 +1,108 @@
INT_R.FAN_ALT0.VCC_WIRE default
INT_R.FAN_ALT1.VCC_WIRE default
INT_R.FAN_ALT2.VCC_WIRE default
INT_R.FAN_ALT3.VCC_WIRE default
INT_R.FAN_ALT4.VCC_WIRE default
INT_R.FAN_ALT5.VCC_WIRE default
INT_R.FAN_ALT6.VCC_WIRE default
INT_R.FAN_ALT7.VCC_WIRE default
INT_R.BYP_ALT0.VCC_WIRE default
INT_R.BYP_ALT1.VCC_WIRE default
INT_R.BYP_ALT2.VCC_WIRE default
INT_R.BYP_ALT3.VCC_WIRE default
INT_R.BYP_ALT4.VCC_WIRE default
INT_R.BYP_ALT5.VCC_WIRE default
INT_R.BYP_ALT6.VCC_WIRE default
INT_R.BYP_ALT7.VCC_WIRE default
INT_R.IMUX0.VCC_WIRE default
INT_R.IMUX1.VCC_WIRE default
INT_R.IMUX2.VCC_WIRE default
INT_R.IMUX3.VCC_WIRE default
INT_R.IMUX4.VCC_WIRE default
INT_R.IMUX5.VCC_WIRE default
INT_R.IMUX6.VCC_WIRE default
INT_R.IMUX7.VCC_WIRE default
INT_R.IMUX8.VCC_WIRE default
INT_R.IMUX9.VCC_WIRE default
INT_R.IMUX10.VCC_WIRE default
INT_R.IMUX11.VCC_WIRE default
INT_R.IMUX12.VCC_WIRE default
INT_R.IMUX13.VCC_WIRE default
INT_R.IMUX14.VCC_WIRE default
INT_R.IMUX15.VCC_WIRE default
INT_R.IMUX16.VCC_WIRE default
INT_R.IMUX17.VCC_WIRE default
INT_R.IMUX18.VCC_WIRE default
INT_R.IMUX19.VCC_WIRE default
INT_R.IMUX20.VCC_WIRE default
INT_R.IMUX21.VCC_WIRE default
INT_R.IMUX22.VCC_WIRE default
INT_R.IMUX23.VCC_WIRE default
INT_R.IMUX24.VCC_WIRE default
INT_R.IMUX25.VCC_WIRE default
INT_R.IMUX26.VCC_WIRE default
INT_R.IMUX27.VCC_WIRE default
INT_R.IMUX28.VCC_WIRE default
INT_R.IMUX29.VCC_WIRE default
INT_R.IMUX30.VCC_WIRE default
INT_R.IMUX31.VCC_WIRE default
INT_R.IMUX32.VCC_WIRE default
INT_R.IMUX33.VCC_WIRE default
INT_R.IMUX34.VCC_WIRE default
INT_R.IMUX35.VCC_WIRE default
INT_R.IMUX36.VCC_WIRE default
INT_R.IMUX37.VCC_WIRE default
INT_R.IMUX38.VCC_WIRE default
INT_R.IMUX39.VCC_WIRE default
INT_R.IMUX40.VCC_WIRE default
INT_R.IMUX41.VCC_WIRE default
INT_R.IMUX42.VCC_WIRE default
INT_R.IMUX43.VCC_WIRE default
INT_R.IMUX44.VCC_WIRE default
INT_R.IMUX45.VCC_WIRE default
INT_R.IMUX46.VCC_WIRE default
INT_R.IMUX47.VCC_WIRE default
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
INT_R.BYP_BOUNCE3.BYP_ALT3 always
INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
INT_R.FAN_BOUNCE3.FAN_ALT3 always
INT_R.FAN_BOUNCE4.FAN_ALT4 always
INT_R.FAN_BOUNCE5.FAN_ALT5 always
INT_R.FAN_BOUNCE6.FAN_ALT6 always
INT_R.FAN_BOUNCE7.FAN_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.GCLK_B0_EAST.GCLK_B0 always
INT_R.GCLK_B0_WEST.GCLK_B0 always
INT_R.GCLK_B1_EAST.GCLK_B1 always
INT_R.GCLK_B1_WEST.GCLK_B1 always
INT_R.GCLK_B2_EAST.GCLK_B2 always
INT_R.GCLK_B2_WEST.GCLK_B2 always
INT_R.GCLK_B3_EAST.GCLK_B3 always
INT_R.GCLK_B3_WEST.GCLK_B3 always
INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always