artix7: HCLK_IOI3 BUFIO_Yn.IN_USE, the RCLK2IOn regional-clock leaf, and the DMUX I2IOCLK default position

Rows minted by fuzzer 039-hclk-config extended with a BUFIO half and
with
consumed BUFRs (companion prjxray PR), 100 specimens, seeded from this
database with the fuzzer's own rows stripped and the mask emptied; the
40 pre-existing 039 rows come back byte-identical.

BUFIO_Y{0..3}.IN_USE (2 bits each): identical whether the BUFIO is fed
from a clock-capable pin (I2IOCLK leg) or from the region's MMCM
(IOCLK_PLL leg), so they are IN_USE proper, not the route.  Disjoint
from every existing row.

HCLK_IOI_RCLK2IO{n}.HCLK_IOI_CK_BUFRCLK{n} (1 bit each): the leaf that
carries a BUFR's regional clock down into the IOI column.  The database
listed these four pips as 'always' (no bits) - 039 never connected a
BUFR output, so the leaf was never exercised.  They do carry a bit each:
32_29 / 30_31 / 31_19 / 28_17 for RCLK 0/1/2/3, from the fuzzer with
consumed BUFRs, and independently from Vivado 2026.1 goldens (one BUFR
per slot, xc7a35tcsg324-1) which show exactly that one otherwise-unknown
bit per slot.  With 'always' in place a BUFR whose output is used would
assemble with the leaf disabled - a valid-looking bitstream with a dead
regional clock.  The four 'always' entries are retired.

HCLK_IOI_IO_PLL_CLK{n}_DMUX <- I2IOCLK_{TOP0,TOP1,BOT0,BOT1}: the DMUX's
pin-clock position sets no bit - it is the all-zero (default) position.
Measured by re-tagging the same 100 specimens per site and source:
SRC_MMCM resolves to exactly the four existing IOCLK_PLL DMUX rows
(which also fixes the site->DMUX map: Y0<->2, Y1<->3, Y2<->0, Y3<->1),
SRC_CCIO to zero candidates on all four; nine Vivado goldens with a
pin-fed BUFR through that DMUX leave no unknown bit on the leg.  Added
as 'default' pseudo-pips (the INT_L.BYP_ALT*.VCC_WIRE convention).
Until now nextpnr's route for the most ordinary BUFR - a clock on a pin
- died in fasm2frames on this key (openXC7/nextpnr-xilinx#149).

Verified: fasm2frames on the features nextpnr emits for IBUF->BUFR->ODDR
(I2IOCLK_TOP0, RCLK_BEFORE_DIV3.RCLK0, RCLK2RCLK3, RCLK2IO3, BUFR_Y1
IN_USE+D5) fails on this database as published and assembles with these
rows, setting the expected bits.

artix7/mask_hclk_ioi3.db

@@ -1,3 +1,6 @@
+bit 28_17
+bit 30_31
+bit 31_19
 bit 31_20
 bit 32_16
 bit 32_17
@@ -6,6 +9,7 @@ bit 32_20
 bit 32_22
 bit 32_26
 bit 32_28
+bit 32_29
 bit 32_30
 bit 33_14
 bit 33_15
@@ -26,15 +30,40 @@ bit 33_30
 bit 33_31
 bit 34_15
 bit 34_16
+bit 34_17
+bit 34_18
 bit 34_23
 bit 34_24
+bit 34_25
+bit 34_26
 bit 34_31
+bit 35_16
+bit 35_17
+bit 35_18
 bit 35_19
 bit 35_21
 bit 35_23
 bit 35_24
 bit 35_25
+bit 35_26
+bit 35_27
+bit 36_14
+bit 36_16
+bit 36_17
+bit 36_18
+bit 36_20
+bit 36_21
 bit 36_24
 bit 36_25
 bit 36_26
 bit 36_27
+bit 36_28
+bit 36_29
+bit 36_31
+bit 37_14
+bit 37_16
+bit 37_17
+bit 37_18
+bit 37_21
+bit 37_22
+bit 37_31

artix7/ppips_hclk_ioi3.db

@@ -2,9 +2,13 @@ HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
 HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
 HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
 HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX.HCLK_IOI_I2IOCLK_TOP0 default
 HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX.HCLK_IOI_I2IOCLK_TOP1 default
 HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX.HCLK_IOI_I2IOCLK_BOT0 default
 HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX.HCLK_IOI_I2IOCLK_BOT1 default
 HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
 HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
 HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
@@ -26,10 +30,6 @@ HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
 HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
 HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
 HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
-HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
-HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
-HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
-HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 always
 HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
 HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
 HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always

artix7/segbits_hclk_ioi3.db

@@ -1,3 +1,7 @@
+HCLK_IOI3.BUFIO_Y0.IN_USE 36_16 36_18
+HCLK_IOI3.BUFIO_Y1.IN_USE 37_16 37_18
+HCLK_IOI3.BUFIO_Y2.IN_USE 36_31 37_31
+HCLK_IOI3.BUFIO_Y3.IN_USE 36_21 37_22
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.BYPASS !32_22 !33_18 !33_19 !33_20 !33_21
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.D1 32_22 33_18 !33_19 !33_20 !33_21
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.D2 32_22 33_18 !33_19 !33_20 33_21
@@ -242,6 +246,10 @@ HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK0 32_16 32_19
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK1 32_19 35_21
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK2 31_20 32_19
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK3 32_19 35_19
+HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 32_29
+HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 30_31
+HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 31_19
+HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 28_17
 HCLK_IOI3.LVDS_25_IN_USE 38_23 38_24 38_25 41_14 41_15 41_17 41_18 41_27 41_28 41_29
 HCLK_IOI3.ONLY_DIFF_IN_USE 38_27 39_23 40_25 40_27 40_29 40_30 41_16 41_31
 HCLK_IOI3.STEPDOWN 38_15 39_14 39_15 39_16

artix7/segbits_hclk_ioi3.origin_info.db

@@ -1,3 +1,7 @@
+HCLK_IOI3.BUFIO_Y0.IN_USE origin:039-hclk-config 36_16 36_18
+HCLK_IOI3.BUFIO_Y1.IN_USE origin:039-hclk-config 37_16 37_18
+HCLK_IOI3.BUFIO_Y2.IN_USE origin:039-hclk-config 36_31 37_31
+HCLK_IOI3.BUFIO_Y3.IN_USE origin:039-hclk-config 36_21 37_22
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.BYPASS origin:039-hclk-config !32_22 !33_18 !33_19 !33_20 !33_21
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.D1 origin:039-hclk-config !33_19 !33_20 !33_21 32_22 33_18
 HCLK_IOI3.BUFR_Y0.BUFR_DIVIDE.D2 origin:039-hclk-config !33_19 !33_20 32_22 33_18 33_21
@@ -242,6 +246,10 @@ HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK0 origin:047-hclk-ioi-pips 32_1
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK1 origin:047-hclk-ioi-pips 32_19 35_21
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK2 origin:047-hclk-ioi-pips 31_20 32_19
 HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK3 origin:047-hclk-ioi-pips 32_19 35_19
+HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 origin:039-hclk-config 32_29
+HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 origin:039-hclk-config 30_31
+HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 origin:039-hclk-config 31_19
+HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 origin:039-hclk-config 28_17
 HCLK_IOI3.LVDS_25_IN_USE origin:030-iob 38_23 38_24 38_25 41_14 41_15 41_17 41_18 41_27 41_28 41_29
 HCLK_IOI3.ONLY_DIFF_IN_USE origin:030-iob 38_27 39_23 40_25 40_27 40_29 40_30 41_16 41_31
 HCLK_IOI3.STEPDOWN origin:030-iob 38_15 39_14 39_15 39_16