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prjxray-db
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Updating Artix and Kintex based on "erge pull request #1268 from litghost/fix_tilegrid". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2020-03-11 11:07:28 -07:00
parent 63a423105a
commit adac87c656
21 changed files with 7294 additions and 1064 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
Info.md
View File

@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Sun 23 Feb 2020 06:01:05 AM UTC (2020-02-23T06:01:05+00:00).
Last updated on Wed 11 Mar 2020 06:08:13 PM UTC (2020-03-11T18:08:13+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [64379fff](https://github.com/SymbiFlow/prjxray/commit/64379fff5638e2da46aa2b50a1cb7bccc24a8ed2).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [2f274142](https://github.com/SymbiFlow/prjxray/commit/2f2741422ef174d62941f381b9e4ed51b3e521cb).
Latest commit was;
```
commit 64379fff5638e2da46aa2b50a1cb7bccc24a8ed2
Merge: 586acfef 9e21e951
commit 2f2741422ef174d62941f381b9e4ed51b3e521cb
Merge: 717a956d 8964ad3b
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Sat Feb 22 09:02:10 2020 -0800
Date: Tue Mar 10 07:41:54 2020 -0700
Merge pull request #1250 from litghost/fix_remap
Merge pull request #1268 from litghost/fix_tilegrid
Fix remap on new 074 code.
Convert CLB/CLB_INT tilegrid fuzzer to workaround prohibited locations.
```
@ -59,7 +59,7 @@ Date: Sat Feb 22 09:02:10 2020 -0800
### Settings
Created using following [settings/artix7.sh (sha256: 51184f624609564b925e9c029ae13326b7163f65679b5c5e13dbd00144df3732)](https://github.com/SymbiFlow/prjxray/blob/64379fff5638e2da46aa2b50a1cb7bccc24a8ed2/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 51184f624609564b925e9c029ae13326b7163f65679b5c5e13dbd00144df3732)](https://github.com/SymbiFlow/prjxray/blob/2f2741422ef174d62941f381b9e4ed51b3e521cb/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -153,13 +153,13 @@ Results have checksums;
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
* [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6 ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
* [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6 ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
* [`2c1f7fcba20a4545e1fa58318b49a3d22c09ec5383992925eae0800744afbb93 ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
* [`8f4f17231c2ce4ff883c2e50f86725ebc625d284fd67e1dc380edef8f9e1a163 ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
@ -262,9 +262,9 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`3381c3961dffe42e31c1f2f3607b4043a7bd28d4ce3f2e6e2903c16a3ee07416 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`851e9031af73305cda8b6c94f702e1857aa4fb3bfc47a9c0065f5318c2e7ed03 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`269c2bbc9742169a90681004876c30a3bb97dd20a7683bfd10f45444e1becd02 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`4353f1e8c4ca1325b429808e7f1aa0b84677dafe962d8e73074092e7d2d6cada ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`cb6ad1ff288077f7430c25ac016d00daf3b5c36dca3f8d5367ea52cc6501b51d ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`48b1c11e82e86433446051994d90436b1dba054fe41f8fe43bf18b9a468f6b49 ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`cf4f6a2b44d13e094f588464a902c315080d2150a522e4241c82ca201a4771e0 ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@ -507,13 +507,13 @@ Results have checksums;
* [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3 ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv)
* [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42 ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json)
* [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97 ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml)
* [`08c3cb4912d57d0f9702f752d48bc8b4ad1c74caccb3dd27413b86bc3cc4c3bd ./artix7/xc7a200tffg1156-1/tileconn.json`](./artix7/xc7a200tffg1156-1/tileconn.json)
* [`029f62c6c8cffb64d41aab8bc47743a41f6b4d5889c398a88c22503bf1dda91b ./artix7/xc7a200tffg1156-1/tilegrid.json`](./artix7/xc7a200tffg1156-1/tilegrid.json)
* [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617 ./artix7/xc7a200tffg1156-1/tileconn.json`](./artix7/xc7a200tffg1156-1/tileconn.json)
* [`43881d45249d5df8f6de87fe61588b419d3553ae80ce65af321cc3e543dd8ed0 ./artix7/xc7a200tffg1156-1/tilegrid.json`](./artix7/xc7a200tffg1156-1/tilegrid.json)
* [`05ee7ad4ee7b7afd4872ab847708778fedbb76f1ebf9d3659fc4c02bd709064a ./artix7/xc7a200tsbg484-1/package_pins.csv`](./artix7/xc7a200tsbg484-1/package_pins.csv)
* [`3261e1163801969f3bfa443040729d1b19a7f5f71c96263e582ffdc0e67b3aa4 ./artix7/xc7a200tsbg484-1/part.json`](./artix7/xc7a200tsbg484-1/part.json)
* [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97 ./artix7/xc7a200tsbg484-1/part.yaml`](./artix7/xc7a200tsbg484-1/part.yaml)
* [`08c3cb4912d57d0f9702f752d48bc8b4ad1c74caccb3dd27413b86bc3cc4c3bd ./artix7/xc7a200tsbg484-1/tileconn.json`](./artix7/xc7a200tsbg484-1/tileconn.json)
* [`029f62c6c8cffb64d41aab8bc47743a41f6b4d5889c398a88c22503bf1dda91b ./artix7/xc7a200tsbg484-1/tilegrid.json`](./artix7/xc7a200tsbg484-1/tilegrid.json)
* [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617 ./artix7/xc7a200tsbg484-1/tileconn.json`](./artix7/xc7a200tsbg484-1/tileconn.json)
* [`43881d45249d5df8f6de87fe61588b419d3553ae80ce65af321cc3e543dd8ed0 ./artix7/xc7a200tsbg484-1/tilegrid.json`](./artix7/xc7a200tsbg484-1/tilegrid.json)
* [`89d8d472bad8232a422a5d52f6dec96215269aad78a16281ed7d2f9cc71e3a71 ./artix7/xc7a35tcpg236-1/package_pins.csv`](./artix7/xc7a35tcpg236-1/package_pins.csv)
* [`be8a8ab158cf85d4135c64a54577412cc1a99833c11ce331a303d90425b673f2 ./artix7/xc7a35tcpg236-1/part.json`](./artix7/xc7a35tcpg236-1/part.json)
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1/part.yaml`](./artix7/xc7a35tcpg236-1/part.yaml)
@ -540,7 +540,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: 845b1414faf8d98843ae2886a273625000548289cc8f0d3635c94599d38cdb81)](https://github.com/SymbiFlow/prjxray/blob/64379fff5638e2da46aa2b50a1cb7bccc24a8ed2/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: 845b1414faf8d98843ae2886a273625000548289cc8f0d3635c94599d38cdb81)](https://github.com/SymbiFlow/prjxray/blob/2f2741422ef174d62941f381b9e4ed51b3e521cb/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -612,13 +612,13 @@ Results have checksums;
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db)
* [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6 ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
* [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6 ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
* [`e9c5e8644b7f426944df2adaecb6e4813097034cfe78ab469d9b675e169b60d4 ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
* [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8 ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
@ -717,9 +717,9 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`d7619b1d57cb11a1dda3cdc91f54795a5952d1432f137fb14e3f3cbcac148d17 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`59a4194efa018abc07b9068b19d2e180cba12d7e4d708eaf26bec3500322d0f3 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`5aed4ef9daf29424041f171748a83360e154f6abd438f5919af8e0451e48c586 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`ebec703e15dc0bf1d308d4abf336e3114b8d3e031fbecd69bcd5a11c52ddad88 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`cb6ad1ff288077f7430c25ac016d00daf3b5c36dca3f8d5367ea52cc6501b51d ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`48b1c11e82e86433446051994d90436b1dba054fe41f8fe43bf18b9a468f6b49 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`87adc9bb57b446e57722145e6461085763a5f0e690558e96c2581ea623b36071 ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
@ -912,7 +912,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: b2055ef65885124f2f229a181100b6b73852464aa260b38691a4d84aa351475b)](https://github.com/SymbiFlow/prjxray/blob/64379fff5638e2da46aa2b50a1cb7bccc24a8ed2/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: b2055ef65885124f2f229a181100b6b73852464aa260b38691a4d84aa351475b)](https://github.com/SymbiFlow/prjxray/blob/2f2741422ef174d62941f381b9e4ed51b3e521cb/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z020clg484-1"

2
artix7/mask_lioi3.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_lioi3_tbytesrc.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_lioi3_tbyteterm.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3_tbytesrc.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3_tbyteterm.db
View File

@ -3,11 +3,11 @@ bit 25_08
bit 25_20
bit 25_21
bit 25_23
bit 25_24
bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

14
artix7/segbits_int_l.origin_info.db
View File

@ -170,7 +170,7 @@ INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63
INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -301,7 +301,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@ -396,7 +396,7 @@ INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@ -1897,7 +1897,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_L.EE4BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_41 04_42
INT_L.EE4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_41 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -2253,7 +2253,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@ -2662,7 +2662,7 @@ INT_L.NW6BEG0.LOGIC_OUTS_L18 origin:050-pip-seed 05_01 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@ -2887,7 +2887,7 @@ INT_L.SE6BEG3.LH0 origin:056-pip-rem 04_59 06_58
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58

8
artix7/segbits_int_r.origin_info.db
View File

@ -332,7 +332,7 @@ INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -2253,7 +2253,7 @@ INT_R.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_R.NE6BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_53 04_54
INT_R.NE6BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_53 07_53
INT_R.NE6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_52 07_53
@ -2491,7 +2491,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07

684
artix7/xc7a200tffg1156-1/tileconn.json
View File

@ -101263,6 +101263,514 @@
]
]
},
{
"grid_deltas": [
-1,
0
],
"tile_types": [
"CLBLL_L",
"GTP_INT_INT_TERM_L"
],
"wire_pairs": [
[
"CLBLL_EE2A0",
"L_TERM_INT_WW2A0"
],
[
"CLBLL_EE2A1",
"L_TERM_INT_WW2A1"
],
[
"CLBLL_EE2A2",
"L_TERM_INT_WW2A2"
],
[
"CLBLL_EE2A3",
"L_TERM_INT_WW2A3"
],
[
"CLBLL_EE2BEG0",
"L_TERM_INT_WW2BEG0"
],
[
"CLBLL_EE2BEG1",
"L_TERM_INT_WW2BEG1"
],
[
"CLBLL_EE2BEG2",
"L_TERM_INT_WW2BEG2"
],
[
"CLBLL_EE2BEG3",
"L_TERM_INT_WW2BEG3"
],
[
"CLBLL_EE4A0",
"L_TERM_INT_WW4A0"
],
[
"CLBLL_EE4A1",
"L_TERM_INT_WW4A1"
],
[
"CLBLL_EE4A2",
"L_TERM_INT_WW4A2"
],
[
"CLBLL_EE4A3",
"L_TERM_INT_WW4A3"
],
[
"CLBLL_EE4B0",
"L_TERM_INT_WW4B0"
],
[
"CLBLL_EE4B1",
"L_TERM_INT_WW4B1"
],
[
"CLBLL_EE4B2",
"L_TERM_INT_WW4B2"
],
[
"CLBLL_EE4B3",
"L_TERM_INT_WW4B3"
],
[
"CLBLL_EE4BEG0",
"L_TERM_INT_WW4BEG0"
],
[
"CLBLL_EE4BEG1",
"L_TERM_INT_WW4BEG1"
],
[
"CLBLL_EE4BEG2",
"L_TERM_INT_WW4BEG2"
],
[
"CLBLL_EE4BEG3",
"L_TERM_INT_WW4BEG3"
],
[
"CLBLL_EE4C0",
"L_TERM_INT_WW4C0"
],
[
"CLBLL_EE4C1",
"L_TERM_INT_WW4C1"
],
[
"CLBLL_EE4C2",
"L_TERM_INT_WW4C2"
],
[
"CLBLL_EE4C3",
"L_TERM_INT_WW4C3"
],
[
"CLBLL_EL1BEG0",
"L_TERM_INT_WL1BEG0"
],
[
"CLBLL_EL1BEG1",
"L_TERM_INT_WL1BEG1"
],
[
"CLBLL_EL1BEG2",
"L_TERM_INT_WL1BEG2"
],
[
"CLBLL_EL1BEG3",
"L_TERM_INT_WR1BEG2"
],
[
"CLBLL_ER1BEG0",
"L_TERM_INT_WR1BEG0"
],
[
"CLBLL_ER1BEG1",
"L_TERM_INT_WR1BEG1"
],
[
"CLBLL_ER1BEG2",
"L_TERM_INT_WR1BEG3"
],
[
"CLBLL_ER1BEG3",
"L_TERM_INT_WL1BEG3"
],
[
"CLBLL_LH1",
"L_TERM_INT_LH0"
],
[
"CLBLL_LH2",
"L_TERM_INT_LH1"
],
[
"CLBLL_LH3",
"L_TERM_INT_LH2"
],
[
"CLBLL_LH4",
"L_TERM_INT_LH3"
],
[
"CLBLL_LH5",
"L_TERM_INT_LH4"
],
[
"CLBLL_LH6",
"L_TERM_INT_LH5"
],
[
"CLBLL_LH7",
"L_TERM_INT_LH5"
],
[
"CLBLL_LH8",
"L_TERM_INT_LH4"
],
[
"CLBLL_LH9",
"L_TERM_INT_LH3"
],
[
"CLBLL_LH10",
"L_TERM_INT_LH2"
],
[
"CLBLL_LH11",
"L_TERM_INT_LH1"
],
[
"CLBLL_LH12",
"L_TERM_INT_LH0"
],
[
"CLBLL_NE2A0",
"L_TERM_INT_NW2BEG0"
],
[
"CLBLL_NE2A1",
"L_TERM_INT_NW2BEG1"
],
[
"CLBLL_NE2A2",
"L_TERM_INT_NW2BEG2"
],
[
"CLBLL_NE2A3",
"L_TERM_INT_NW2BEG3"
],
[
"CLBLL_NE4BEG0",
"L_TERM_INT_NW4BEG0"
],
[
"CLBLL_NE4BEG1",
"L_TERM_INT_NW4BEG1"
],
[
"CLBLL_NE4BEG2",
"L_TERM_INT_NW4BEG2"
],
[
"CLBLL_NE4BEG3",
"L_TERM_INT_NW4BEG3"
],
[
"CLBLL_NE4C0",
"L_TERM_INT_NW4C0"
],
[
"CLBLL_NE4C1",
"L_TERM_INT_NW4C1"
],
[
"CLBLL_NE4C2",
"L_TERM_INT_NW4C2"
],
[
"CLBLL_NE4C3",
"L_TERM_INT_NW4C3"
],
[
"CLBLL_NW2A0",
"L_TERM_INT_NW2BEG0"
],
[
"CLBLL_NW2A1",
"L_TERM_INT_NW2BEG1"
],
[
"CLBLL_NW2A2",
"L_TERM_INT_NW2BEG2"
],
[
"CLBLL_NW2A3",
"L_TERM_INT_NW2BEG3"
],
[
"CLBLL_NW4A0",
"L_TERM_INT_NW4BEG0"
],
[
"CLBLL_NW4A1",
"L_TERM_INT_NW4BEG1"
],
[
"CLBLL_NW4A2",
"L_TERM_INT_NW4BEG2"
],
[
"CLBLL_NW4A3",
"L_TERM_INT_NW4BEG3"
],
[
"CLBLL_NW4END0",
"L_TERM_INT_NW4C0"
],
[
"CLBLL_NW4END1",
"L_TERM_INT_NW4C1"
],
[
"CLBLL_NW4END2",
"L_TERM_INT_NW4C2"
],
[
"CLBLL_NW4END3",
"L_TERM_INT_NW4C3"
],
[
"CLBLL_SE2A0",
"L_TERM_INT_SW2BEG0"
],
[
"CLBLL_SE2A1",
"L_TERM_INT_SW2BEG1"
],
[
"CLBLL_SE2A2",
"L_TERM_INT_SW2BEG2"
],
[
"CLBLL_SE2A3",
"L_TERM_INT_SW2BEG3"
],
[
"CLBLL_SE4BEG0",
"L_TERM_INT_SW4BEG0"
],
[
"CLBLL_SE4BEG1",
"L_TERM_INT_SW4BEG1"
],
[
"CLBLL_SE4BEG2",
"L_TERM_INT_SW4BEG2"
],
[
"CLBLL_SE4BEG3",
"L_TERM_INT_SW4BEG3"
],
[
"CLBLL_SE4C0",
"L_TERM_INT_SW4C0"
],
[
"CLBLL_SE4C1",
"L_TERM_INT_SW4C1"
],
[
"CLBLL_SE4C2",
"L_TERM_INT_SW4C2"
],
[
"CLBLL_SE4C3",
"L_TERM_INT_SW4C3"
],
[
"CLBLL_SW2A0",
"L_TERM_INT_SW2BEG0"
],
[
"CLBLL_SW2A1",
"L_TERM_INT_SW2BEG1"
],
[
"CLBLL_SW2A2",
"L_TERM_INT_SW2BEG2"
],
[
"CLBLL_SW2A3",
"L_TERM_INT_SW2BEG3"
],
[
"CLBLL_SW4A0",
"L_TERM_INT_SW4BEG0"
],
[
"CLBLL_SW4A1",
"L_TERM_INT_SW4BEG1"
],
[
"CLBLL_SW4A2",
"L_TERM_INT_SW4BEG2"
],
[
"CLBLL_SW4A3",
"L_TERM_INT_SW4BEG3"
],
[
"CLBLL_SW4END0",
"L_TERM_INT_SW4C0"
],
[
"CLBLL_SW4END1",
"L_TERM_INT_SW4C1"
],
[
"CLBLL_SW4END2",
"L_TERM_INT_SW4C2"
],
[
"CLBLL_SW4END3",
"L_TERM_INT_SW4C3"
],
[
"CLBLL_WL1END0",
"L_TERM_INT_WL1BEG0"
],
[
"CLBLL_WL1END1",
"L_TERM_INT_WL1BEG1"
],
[
"CLBLL_WL1END2",
"L_TERM_INT_WL1BEG2"
],
[
"CLBLL_WL1END3",
"L_TERM_INT_WR1BEG2"
],
[
"CLBLL_WR1END0",
"L_TERM_INT_WR1BEG0"
],
[
"CLBLL_WR1END1",
"L_TERM_INT_WR1BEG1"
],
[
"CLBLL_WR1END2",
"L_TERM_INT_WR1BEG3"
],
[
"CLBLL_WR1END3",
"L_TERM_INT_WL1BEG3"
],
[
"CLBLL_WW2A0",
"L_TERM_INT_WW2BEG0"
],
[
"CLBLL_WW2A1",
"L_TERM_INT_WW2BEG1"
],
[
"CLBLL_WW2A2",
"L_TERM_INT_WW2BEG2"
],
[
"CLBLL_WW2A3",
"L_TERM_INT_WW2BEG3"
],
[
"CLBLL_WW2END0",
"L_TERM_INT_WW2A0"
],
[
"CLBLL_WW2END1",
"L_TERM_INT_WW2A1"
],
[
"CLBLL_WW2END2",
"L_TERM_INT_WW2A2"
],
[
"CLBLL_WW2END3",
"L_TERM_INT_WW2A3"
],
[
"CLBLL_WW4A0",
"L_TERM_INT_WW4BEG0"
],
[
"CLBLL_WW4A1",
"L_TERM_INT_WW4BEG1"
],
[
"CLBLL_WW4A2",
"L_TERM_INT_WW4BEG2"
],
[
"CLBLL_WW4A3",
"L_TERM_INT_WW4BEG3"
],
[
"CLBLL_WW4B0",
"L_TERM_INT_WW4A0"
],
[
"CLBLL_WW4B1",
"L_TERM_INT_WW4A1"
],
[
"CLBLL_WW4B2",
"L_TERM_INT_WW4A2"
],
[
"CLBLL_WW4B3",
"L_TERM_INT_WW4A3"
],
[
"CLBLL_WW4C0",
"L_TERM_INT_WW4B0"
],
[
"CLBLL_WW4C1",
"L_TERM_INT_WW4B1"
],
[
"CLBLL_WW4C2",
"L_TERM_INT_WW4B2"
],
[
"CLBLL_WW4C3",
"L_TERM_INT_WW4B3"
],
[
"CLBLL_WW4END0",
"L_TERM_INT_WW4C0"
],
[
"CLBLL_WW4END1",
"L_TERM_INT_WW4C1"
],
[
"CLBLL_WW4END2",
"L_TERM_INT_WW4C2"
],
[
"CLBLL_WW4END3",
"L_TERM_INT_WW4C3"
]
]
},
{
"grid_deltas": [
0,
@ -382821,6 +383329,54 @@
"VBRK"
],
"wire_pairs": [
[
"R_TERM_INT_LH0",
"VBRK_LH1"
],
[
"R_TERM_INT_LH0",
"VBRK_LH12"
],
[
"R_TERM_INT_LH1",
"VBRK_LH2"
],
[
"R_TERM_INT_LH1",
"VBRK_LH11"
],
[
"R_TERM_INT_LH2",
"VBRK_LH3"
],
[
"R_TERM_INT_LH2",
"VBRK_LH10"
],
[
"R_TERM_INT_LH3",
"VBRK_LH4"
],
[
"R_TERM_INT_LH3",
"VBRK_LH9"
],
[
"R_TERM_INT_LH4",
"VBRK_LH5"
],
[
"R_TERM_INT_LH4",
"VBRK_LH8"
],
[
"R_TERM_INT_LH5",
"VBRK_LH6"
],
[
"R_TERM_INT_LH5",
"VBRK_LH7"
],
[
"R_TERM_INT_NW2A0",
"VBRK_NE2A0"
@ -383140,6 +383696,134 @@
[
"R_TERM_INT_WW2END3",
"VBRK_WW2END3"
],
[
"R_TERM_INT_WW4A0",
"VBRK_EE4BEG0"
],
[
"R_TERM_INT_WW4A0",
"VBRK_WW4A0"
],
[
"R_TERM_INT_WW4A1",
"VBRK_EE4BEG1"
],
[
"R_TERM_INT_WW4A1",
"VBRK_WW4A1"
],
[
"R_TERM_INT_WW4A2",
"VBRK_EE4BEG2"
],
[
"R_TERM_INT_WW4A2",
"VBRK_WW4A2"
],
[
"R_TERM_INT_WW4A3",
"VBRK_EE4BEG3"
],
[
"R_TERM_INT_WW4A3",
"VBRK_WW4A3"
],
[
"R_TERM_INT_WW4B0",
"VBRK_EE4A0"
],
[
"R_TERM_INT_WW4B0",
"VBRK_WW4B0"
],
[
"R_TERM_INT_WW4B1",
"VBRK_EE4A1"
],
[
"R_TERM_INT_WW4B1",
"VBRK_WW4B1"
],
[
"R_TERM_INT_WW4B2",
"VBRK_EE4A2"
],
[
"R_TERM_INT_WW4B2",
"VBRK_WW4B2"
],
[
"R_TERM_INT_WW4B3",
"VBRK_EE4A3"
],
[
"R_TERM_INT_WW4B3",
"VBRK_WW4B3"
],
[
"R_TERM_INT_WW4C0",
"VBRK_EE4B0"
],
[
"R_TERM_INT_WW4C0",
"VBRK_WW4C0"
],
[
"R_TERM_INT_WW4C1",
"VBRK_EE4B1"
],
[
"R_TERM_INT_WW4C1",
"VBRK_WW4C1"
],
[
"R_TERM_INT_WW4C2",
"VBRK_EE4B2"
],
[
"R_TERM_INT_WW4C2",
"VBRK_WW4C2"
],
[
"R_TERM_INT_WW4C3",
"VBRK_EE4B3"
],
[
"R_TERM_INT_WW4C3",
"VBRK_WW4C3"
],
[
"R_TERM_INT_WW4END0",
"VBRK_EE4C0"
],
[
"R_TERM_INT_WW4END0",
"VBRK_WW4END0"
],
[
"R_TERM_INT_WW4END1",
"VBRK_EE4C1"
],
[
"R_TERM_INT_WW4END1",
"VBRK_WW4END1"
],
[
"R_TERM_INT_WW4END2",
"VBRK_EE4C2"
],
[
"R_TERM_INT_WW4END2",
"VBRK_WW4END2"
],
[
"R_TERM_INT_WW4END3",
"VBRK_EE4C3"
],
[
"R_TERM_INT_WW4END3",
"VBRK_WW4END3"
]
]
},

3436
artix7/xc7a200tffg1156-1/tilegrid.json
View File

File diff suppressed because it is too large Load Diff

684
artix7/xc7a200tsbg484-1/tileconn.json
View File

@ -101263,6 +101263,514 @@
]
]
},
{
"grid_deltas": [
-1,
0
],
"tile_types": [
"CLBLL_L",
"GTP_INT_INT_TERM_L"
],
"wire_pairs": [
[
"CLBLL_EE2A0",
"L_TERM_INT_WW2A0"
],
[
"CLBLL_EE2A1",
"L_TERM_INT_WW2A1"
],
[
"CLBLL_EE2A2",
"L_TERM_INT_WW2A2"
],
[
"CLBLL_EE2A3",
"L_TERM_INT_WW2A3"
],
[
"CLBLL_EE2BEG0",
"L_TERM_INT_WW2BEG0"
],
[
"CLBLL_EE2BEG1",
"L_TERM_INT_WW2BEG1"
],
[
"CLBLL_EE2BEG2",
"L_TERM_INT_WW2BEG2"
],
[
"CLBLL_EE2BEG3",
"L_TERM_INT_WW2BEG3"
],
[
"CLBLL_EE4A0",
"L_TERM_INT_WW4A0"
],
[
"CLBLL_EE4A1",
"L_TERM_INT_WW4A1"
],
[
"CLBLL_EE4A2",
"L_TERM_INT_WW4A2"
],
[
"CLBLL_EE4A3",
"L_TERM_INT_WW4A3"
],
[
"CLBLL_EE4B0",
"L_TERM_INT_WW4B0"
],
[
"CLBLL_EE4B1",
"L_TERM_INT_WW4B1"
],
[
"CLBLL_EE4B2",
"L_TERM_INT_WW4B2"
],
[
"CLBLL_EE4B3",
"L_TERM_INT_WW4B3"
],
[
"CLBLL_EE4BEG0",
"L_TERM_INT_WW4BEG0"
],
[
"CLBLL_EE4BEG1",
"L_TERM_INT_WW4BEG1"
],
[
"CLBLL_EE4BEG2",
"L_TERM_INT_WW4BEG2"
],
[
"CLBLL_EE4BEG3",
"L_TERM_INT_WW4BEG3"
],
[
"CLBLL_EE4C0",
"L_TERM_INT_WW4C0"
],
[
"CLBLL_EE4C1",
"L_TERM_INT_WW4C1"
],
[
"CLBLL_EE4C2",
"L_TERM_INT_WW4C2"
],
[
"CLBLL_EE4C3",
"L_TERM_INT_WW4C3"
],
[
"CLBLL_EL1BEG0",
"L_TERM_INT_WL1BEG0"
],
[
"CLBLL_EL1BEG1",
"L_TERM_INT_WL1BEG1"
],
[
"CLBLL_EL1BEG2",
"L_TERM_INT_WL1BEG2"
],
[
"CLBLL_EL1BEG3",
"L_TERM_INT_WR1BEG2"
],
[
"CLBLL_ER1BEG0",
"L_TERM_INT_WR1BEG0"
],
[
"CLBLL_ER1BEG1",
"L_TERM_INT_WR1BEG1"
],
[
"CLBLL_ER1BEG2",
"L_TERM_INT_WR1BEG3"
],
[
"CLBLL_ER1BEG3",
"L_TERM_INT_WL1BEG3"
],
[
"CLBLL_LH1",
"L_TERM_INT_LH0"
],
[
"CLBLL_LH2",
"L_TERM_INT_LH1"
],
[
"CLBLL_LH3",
"L_TERM_INT_LH2"
],
[
"CLBLL_LH4",
"L_TERM_INT_LH3"
],
[
"CLBLL_LH5",
"L_TERM_INT_LH4"
],
[
"CLBLL_LH6",
"L_TERM_INT_LH5"
],
[
"CLBLL_LH7",
"L_TERM_INT_LH5"
],
[
"CLBLL_LH8",
"L_TERM_INT_LH4"
],
[
"CLBLL_LH9",
"L_TERM_INT_LH3"
],
[
"CLBLL_LH10",
"L_TERM_INT_LH2"
],
[
"CLBLL_LH11",
"L_TERM_INT_LH1"
],
[
"CLBLL_LH12",
"L_TERM_INT_LH0"
],
[
"CLBLL_NE2A0",
"L_TERM_INT_NW2BEG0"
],
[
"CLBLL_NE2A1",
"L_TERM_INT_NW2BEG1"
],
[
"CLBLL_NE2A2",
"L_TERM_INT_NW2BEG2"
],
[
"CLBLL_NE2A3",
"L_TERM_INT_NW2BEG3"
],
[
"CLBLL_NE4BEG0",
"L_TERM_INT_NW4BEG0"
],
[
"CLBLL_NE4BEG1",
"L_TERM_INT_NW4BEG1"
],
[
"CLBLL_NE4BEG2",
"L_TERM_INT_NW4BEG2"
],
[
"CLBLL_NE4BEG3",
"L_TERM_INT_NW4BEG3"
],
[
"CLBLL_NE4C0",
"L_TERM_INT_NW4C0"
],
[
"CLBLL_NE4C1",
"L_TERM_INT_NW4C1"
],
[
"CLBLL_NE4C2",
"L_TERM_INT_NW4C2"
],
[
"CLBLL_NE4C3",
"L_TERM_INT_NW4C3"
],
[
"CLBLL_NW2A0",
"L_TERM_INT_NW2BEG0"
],
[
"CLBLL_NW2A1",
"L_TERM_INT_NW2BEG1"
],
[
"CLBLL_NW2A2",
"L_TERM_INT_NW2BEG2"
],
[
"CLBLL_NW2A3",
"L_TERM_INT_NW2BEG3"
],
[
"CLBLL_NW4A0",
"L_TERM_INT_NW4BEG0"
],
[
"CLBLL_NW4A1",
"L_TERM_INT_NW4BEG1"
],
[
"CLBLL_NW4A2",
"L_TERM_INT_NW4BEG2"
],
[
"CLBLL_NW4A3",
"L_TERM_INT_NW4BEG3"
],
[
"CLBLL_NW4END0",
"L_TERM_INT_NW4C0"
],
[
"CLBLL_NW4END1",
"L_TERM_INT_NW4C1"
],
[
"CLBLL_NW4END2",
"L_TERM_INT_NW4C2"
],
[
"CLBLL_NW4END3",
"L_TERM_INT_NW4C3"
],
[
"CLBLL_SE2A0",
"L_TERM_INT_SW2BEG0"
],
[
"CLBLL_SE2A1",
"L_TERM_INT_SW2BEG1"
],
[
"CLBLL_SE2A2",
"L_TERM_INT_SW2BEG2"
],
[
"CLBLL_SE2A3",
"L_TERM_INT_SW2BEG3"
],
[
"CLBLL_SE4BEG0",
"L_TERM_INT_SW4BEG0"
],
[
"CLBLL_SE4BEG1",
"L_TERM_INT_SW4BEG1"
],
[
"CLBLL_SE4BEG2",
"L_TERM_INT_SW4BEG2"
],
[
"CLBLL_SE4BEG3",
"L_TERM_INT_SW4BEG3"
],
[
"CLBLL_SE4C0",
"L_TERM_INT_SW4C0"
],
[
"CLBLL_SE4C1",
"L_TERM_INT_SW4C1"
],
[
"CLBLL_SE4C2",
"L_TERM_INT_SW4C2"
],
[
"CLBLL_SE4C3",
"L_TERM_INT_SW4C3"
],
[
"CLBLL_SW2A0",
"L_TERM_INT_SW2BEG0"
],
[
"CLBLL_SW2A1",
"L_TERM_INT_SW2BEG1"
],
[
"CLBLL_SW2A2",
"L_TERM_INT_SW2BEG2"
],
[
"CLBLL_SW2A3",
"L_TERM_INT_SW2BEG3"
],
[
"CLBLL_SW4A0",
"L_TERM_INT_SW4BEG0"
],
[
"CLBLL_SW4A1",
"L_TERM_INT_SW4BEG1"
],
[
"CLBLL_SW4A2",
"L_TERM_INT_SW4BEG2"
],
[
"CLBLL_SW4A3",
"L_TERM_INT_SW4BEG3"
],
[
"CLBLL_SW4END0",
"L_TERM_INT_SW4C0"
],
[
"CLBLL_SW4END1",
"L_TERM_INT_SW4C1"
],
[
"CLBLL_SW4END2",
"L_TERM_INT_SW4C2"
],
[
"CLBLL_SW4END3",
"L_TERM_INT_SW4C3"
],
[
"CLBLL_WL1END0",
"L_TERM_INT_WL1BEG0"
],
[
"CLBLL_WL1END1",
"L_TERM_INT_WL1BEG1"
],
[
"CLBLL_WL1END2",
"L_TERM_INT_WL1BEG2"
],
[
"CLBLL_WL1END3",
"L_TERM_INT_WR1BEG2"
],
[
"CLBLL_WR1END0",
"L_TERM_INT_WR1BEG0"
],
[
"CLBLL_WR1END1",
"L_TERM_INT_WR1BEG1"
],
[
"CLBLL_WR1END2",
"L_TERM_INT_WR1BEG3"
],
[
"CLBLL_WR1END3",
"L_TERM_INT_WL1BEG3"
],
[
"CLBLL_WW2A0",
"L_TERM_INT_WW2BEG0"
],
[
"CLBLL_WW2A1",
"L_TERM_INT_WW2BEG1"
],
[
"CLBLL_WW2A2",
"L_TERM_INT_WW2BEG2"
],
[
"CLBLL_WW2A3",
"L_TERM_INT_WW2BEG3"
],
[
"CLBLL_WW2END0",
"L_TERM_INT_WW2A0"
],
[
"CLBLL_WW2END1",
"L_TERM_INT_WW2A1"
],
[
"CLBLL_WW2END2",
"L_TERM_INT_WW2A2"
],
[
"CLBLL_WW2END3",
"L_TERM_INT_WW2A3"
],
[
"CLBLL_WW4A0",
"L_TERM_INT_WW4BEG0"
],
[
"CLBLL_WW4A1",
"L_TERM_INT_WW4BEG1"
],
[
"CLBLL_WW4A2",
"L_TERM_INT_WW4BEG2"
],
[
"CLBLL_WW4A3",
"L_TERM_INT_WW4BEG3"
],
[
"CLBLL_WW4B0",
"L_TERM_INT_WW4A0"
],
[
"CLBLL_WW4B1",
"L_TERM_INT_WW4A1"
],
[
"CLBLL_WW4B2",
"L_TERM_INT_WW4A2"
],
[
"CLBLL_WW4B3",
"L_TERM_INT_WW4A3"
],
[
"CLBLL_WW4C0",
"L_TERM_INT_WW4B0"
],
[
"CLBLL_WW4C1",
"L_TERM_INT_WW4B1"
],
[
"CLBLL_WW4C2",
"L_TERM_INT_WW4B2"
],
[
"CLBLL_WW4C3",
"L_TERM_INT_WW4B3"
],
[
"CLBLL_WW4END0",
"L_TERM_INT_WW4C0"
],
[
"CLBLL_WW4END1",
"L_TERM_INT_WW4C1"
],
[
"CLBLL_WW4END2",
"L_TERM_INT_WW4C2"
],
[
"CLBLL_WW4END3",
"L_TERM_INT_WW4C3"
]
]
},
{
"grid_deltas": [
0,
@ -382821,6 +383329,54 @@
"VBRK"
],
"wire_pairs": [
[
"R_TERM_INT_LH0",
"VBRK_LH1"
],
[
"R_TERM_INT_LH0",
"VBRK_LH12"
],
[
"R_TERM_INT_LH1",
"VBRK_LH2"
],
[
"R_TERM_INT_LH1",
"VBRK_LH11"
],
[
"R_TERM_INT_LH2",
"VBRK_LH3"
],
[
"R_TERM_INT_LH2",
"VBRK_LH10"
],
[
"R_TERM_INT_LH3",
"VBRK_LH4"
],
[
"R_TERM_INT_LH3",
"VBRK_LH9"
],
[
"R_TERM_INT_LH4",
"VBRK_LH5"
],
[
"R_TERM_INT_LH4",
"VBRK_LH8"
],
[
"R_TERM_INT_LH5",
"VBRK_LH6"
],
[
"R_TERM_INT_LH5",
"VBRK_LH7"
],
[
"R_TERM_INT_NW2A0",
"VBRK_NE2A0"
@ -383140,6 +383696,134 @@
[
"R_TERM_INT_WW2END3",
"VBRK_WW2END3"
],
[
"R_TERM_INT_WW4A0",
"VBRK_EE4BEG0"
],
[
"R_TERM_INT_WW4A0",
"VBRK_WW4A0"
],
[
"R_TERM_INT_WW4A1",
"VBRK_EE4BEG1"
],
[
"R_TERM_INT_WW4A1",
"VBRK_WW4A1"
],
[
"R_TERM_INT_WW4A2",
"VBRK_EE4BEG2"
],
[
"R_TERM_INT_WW4A2",
"VBRK_WW4A2"
],
[
"R_TERM_INT_WW4A3",
"VBRK_EE4BEG3"
],
[
"R_TERM_INT_WW4A3",
"VBRK_WW4A3"
],
[
"R_TERM_INT_WW4B0",
"VBRK_EE4A0"
],
[
"R_TERM_INT_WW4B0",
"VBRK_WW4B0"
],
[
"R_TERM_INT_WW4B1",
"VBRK_EE4A1"
],
[
"R_TERM_INT_WW4B1",
"VBRK_WW4B1"
],
[
"R_TERM_INT_WW4B2",
"VBRK_EE4A2"
],
[
"R_TERM_INT_WW4B2",
"VBRK_WW4B2"
],
[
"R_TERM_INT_WW4B3",
"VBRK_EE4A3"
],
[
"R_TERM_INT_WW4B3",
"VBRK_WW4B3"
],
[
"R_TERM_INT_WW4C0",
"VBRK_EE4B0"
],
[
"R_TERM_INT_WW4C0",
"VBRK_WW4C0"
],
[
"R_TERM_INT_WW4C1",
"VBRK_EE4B1"
],
[
"R_TERM_INT_WW4C1",
"VBRK_WW4C1"
],
[
"R_TERM_INT_WW4C2",
"VBRK_EE4B2"
],
[
"R_TERM_INT_WW4C2",
"VBRK_WW4C2"
],
[
"R_TERM_INT_WW4C3",
"VBRK_EE4B3"
],
[
"R_TERM_INT_WW4C3",
"VBRK_WW4C3"
],
[
"R_TERM_INT_WW4END0",
"VBRK_EE4C0"
],
[
"R_TERM_INT_WW4END0",
"VBRK_WW4END0"
],
[
"R_TERM_INT_WW4END1",
"VBRK_EE4C1"
],
[
"R_TERM_INT_WW4END1",
"VBRK_WW4END1"
],
[
"R_TERM_INT_WW4END2",
"VBRK_EE4C2"
],
[
"R_TERM_INT_WW4END2",
"VBRK_WW4END2"
],
[
"R_TERM_INT_WW4END3",
"VBRK_EE4C3"
],
[
"R_TERM_INT_WW4END3",
"VBRK_WW4END3"
]
]
},

3436
artix7/xc7a200tsbg484-1/tilegrid.json
View File

File diff suppressed because it is too large Load Diff

1
kintex7/mask_lioi3.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

1
kintex7/mask_lioi3_tbytesrc.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

1
kintex7/mask_lioi3_tbyteterm.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

1
kintex7/mask_rioi3.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

1
kintex7/mask_rioi3_tbytesrc.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

1
kintex7/mask_rioi3_tbyteterm.db
View File

@ -15,6 +15,7 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

12
kintex7/segbits_int_l.origin_info.db
View File

@ -301,7 +301,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE4 origin:050-pip-seed !22_00 20_00 23_00 24_00 25_00
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@ -393,7 +393,7 @@ INT_L.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@ -1897,7 +1897,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_L.EE4BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_41 04_42
INT_L.EE4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_41 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -1917,7 +1917,7 @@ INT_L.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@ -3323,7 +3323,7 @@ INT_L.SW6BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 06_44 07_45
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L20 origin:050-pip-seed 04_34 06_32
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

6
kintex7/segbits_int_r.origin_info.db
View File

@ -685,7 +685,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -725,7 +725,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@ -3344,7 +3344,7 @@ INT_R.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61