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Updating all based on "Merge pull request #941 from litghost/fixup_arty_harnes". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-07-11 10:55:21 -07:00
parent 2e4d3dc3b2
commit 8bb6b84629
52 changed files with 4726 additions and 3792 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

112
Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Tue 09 Jul 2019 09:31:53 PM UTC (2019-07-09T21:31:53+00:00).
Last updated on Thu 11 Jul 2019 05:54:48 PM UTC (2019-07-11T17:54:48+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [948a3b2](https://github.com/SymbiFlow/prjxray/commit/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [24d852c](https://github.com/SymbiFlow/prjxray/commit/24d852c016e938ca655222ef44219de465b94d6e).
Latest commit was;
```
commit 948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c
Merge: 219f0f0 e096d9c
Author: Tomasz Michalak <tmichalak@antmicro.com>
Date: Thu Jul 4 23:32:20 2019 +0200
commit 24d852c016e938ca655222ef44219de465b94d6e
Merge: 36af12c 3345f30
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Wed Jul 10 22:52:45 2019 -0700
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress
Merge pull request #941 from litghost/fixup_arty_harnes
Calculate base addresses for HCLK_IOI3 tiles.
Fix D9/B8 in arty-swbut harness.
```
@ -59,7 +59,7 @@ Date: Thu Jul 4 23:32:20 2019 +0200
### Settings
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -142,8 +142,8 @@ Results have checksums;
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_l.origin_info.db`](./artix7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
* [`653d03789df2c691773f96543abe1ed87e932c2791f5073dd20cd8961257da51 ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
* [`653d03789df2c691773f96543abe1ed87e932c2791f5073dd20cd8961257da51 ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
* [`6ce58e9c76af4fe684ab556cacf92d118b75ef0c06f04d286c122fd48c19b49a ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
* [`6ce58e9c76af4fe684ab556cacf92d118b75ef0c06f04d286c122fd48c19b49a ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
@ -199,10 +199,10 @@ Results have checksums;
* [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./artix7/segbits_clbll_l.origin_info.db`](./artix7/segbits_clbll_l.origin_info.db)
* [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./artix7/segbits_clbll_r.origin_info.db`](./artix7/segbits_clbll_r.origin_info.db)
* [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db)
* [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db)
* [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db)
* [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./artix7/segbits_clk_bufg_bot_r.db`](./artix7/segbits_clk_bufg_bot_r.db)
* [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./artix7/segbits_clk_bufg_bot_r.origin_info.db`](./artix7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./artix7/segbits_clk_bufg_rebuf.db`](./artix7/segbits_clk_bufg_rebuf.db)
@ -213,6 +213,10 @@ Results have checksums;
* [`cde71c02d36c0a41d0706b944568ce03c0992ca2853276bc193470ec83d86186 ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
* [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db)
* [`b66f2fcf9007247c5146cca61ddb82b815130d9dc8c54bca75e7f239b5bb64ae ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
* [`e99df1b0ef107704b36091d4e28cd920c55258c609faffb8236eb3d387b1f3e7 ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
* [`308e4b11c5522f29b1ce0fabe136f60ef41268f483286b64a7e1422c9e9c09c6 ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`850a4874662716370ed864e5a851eda2c362d5c51901d3d02cc6735b5b946865 ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
* [`b94347c375638c5f423fcb282b33a692cd4a0500febed8756ea6d438923f051d ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
@ -226,13 +230,13 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`cd7974e166e00e172584a468ae4f27e3d7d38af14e47a4313afff1ae94bbebc7 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`0a0b68b503b23f1fc0fef91d7c92d0c98da7dbcb0635b495babbf6123a074956 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`aec7ff22207dd629b706cf308707cb27ba8aa80271f40138b99675e06284cd23 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`6ece030404b8fd09095382730639d261e0402e2c513bf07d9ec301a7311ceb7e ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`f100a6e9abd51bbddb7aacb810c00b7240b2f50a25b3f331121d923198d43d8f ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
* [`27a74d9eddb6f960a94f107b28343d88dc8c2274de61be865e21e3a8d1f4e9f1 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
* [`5d31fdae73bec297b9ebee977359713181c86077cae89368efd6d74adcfd46c7 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`216bf1f206b5e98e453f2d4b4d64de01788d050238f427c975d9b8559eae55b0 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`90f81fd31255224e6dd4725832c690159a59fb168c83e59fdae10fd6d291ddcb ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`6382b44bc537fca6c822cab52f93a7486b402db753743168a462abbb067662e1 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
* [`f651df59cf27fa9883dd8487653b0f571cb199311106a78e23f7588cc94bf917 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
* [`2bc07bf06b86af1985fe1c76da7bd6d858768dd6d9e99344a3c52d490b797cdb ./artix7/settings.sh`](./artix7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
@ -391,7 +395,7 @@ Results have checksums;
* [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`864eb276f06fa2407d1d48695c9b63704690ec691fd000736174e4ae99ab3f46 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`dce02654691e0f64613054db1fabfcf4d44f02d6090c6117014a07933d5106e0 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
* [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
@ -453,7 +457,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -518,8 +522,8 @@ Results have checksums;
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_hclk_l.origin_info.db`](./kintex7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db)
* [`2739be1268a3e0fcf6d9c95960d3982eea4ca3ee019412166ab30533d9965190 ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
* [`2739be1268a3e0fcf6d9c95960d3982eea4ca3ee019412166ab30533d9965190 ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
* [`3338e1efe9b0d2533d0a8dc8fdd8f5659d94a6919b55847b065484d0f4d90efa ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
* [`3338e1efe9b0d2533d0a8dc8fdd8f5659d94a6919b55847b065484d0f4d90efa ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
@ -571,10 +575,10 @@ Results have checksums;
* [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./kintex7/segbits_clbll_l.origin_info.db`](./kintex7/segbits_clbll_l.origin_info.db)
* [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./kintex7/segbits_clbll_r.origin_info.db`](./kintex7/segbits_clbll_r.origin_info.db)
* [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./kintex7/segbits_clblm_l.origin_info.db`](./kintex7/segbits_clblm_l.origin_info.db)
* [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./kintex7/segbits_clblm_r.origin_info.db`](./kintex7/segbits_clblm_r.origin_info.db)
* [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./kintex7/segbits_clblm_l.origin_info.db`](./kintex7/segbits_clblm_l.origin_info.db)
* [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./kintex7/segbits_clblm_r.origin_info.db`](./kintex7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db)
* [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./kintex7/segbits_clk_bufg_bot_r.origin_info.db`](./kintex7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./kintex7/segbits_clk_bufg_rebuf.db`](./kintex7/segbits_clk_bufg_rebuf.db)
@ -585,6 +589,10 @@ Results have checksums;
* [`396e42f2564290eb1a382c535631ea6f8f73b78121da9664c83688dac46b4765 ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db)
* [`375d8ee4051ac320d23f03f93acc7958b5bd6fdce3f05584179ecddf4fb4388a ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
* [`b4d096345faf6b99198cd8409e38fb49d1572f9ddae4c4539f61014d1c897c8f ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db)
* [`4efe7d3c284d19113eee98ca8e796f1805f1da9f48ddb967ea2ae4dbda87fbcf ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
* [`79bbfd32b228c0c0a42cccec63c7a4e725df3292ecc58bee6cf76a6255e4f3e2 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`a6b47c2013cde02576f18e56b37a0c0915ded789424afd5640a969890f0102d8 ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
* [`bc109f11724511025e1bff37c1af0561b0d6e339df47c068bde36424d8110002 ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
@ -598,13 +606,13 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`ee3b5f2adbd4f3b7d6135dcb4f7183f379fe95e19bbbf59583c1aa801f208677 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`b89e756998ef8ad4e931e0e3ea37606789e496e4b7681b8e8d1967c8be0f4ad6 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`64574afb2e9615d414a0515948f395a8d871403c70ab3ed0d7367f0798cbad95 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`bed06fc405947c72a47a7fbac7adbc220efd2dc8d73f321ed70b8d2490ab745b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`61fef185b5fd5aa46425d9e28b61f0d6b1b4c4a0577f1452801a6531c45bee7b ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`8ec421f8f4ce1bab7e81bcbf0cbdc37fb3f6ed4715bc2fdf75db336805efc53e ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
* [`25338a0bd1e45606e0a868db6989ce6c3bcef6dab0daea700debd5ca597f9f8d ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
* [`1c259198ed7f9d03a4d3e832bd50ef53c404e2a9b4bafd61dfdbff681789f56e ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`7f7678239ee07a0a6e14f485125edcf3113283c32fdf30ef476380a6a03855ec ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`f3d41676543f572882ae48a2fad5f63dfaa3b39be46c051ae167e571f787734f ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`f9ee96e8ec2bc5ec3385894c5f27be07946f4f7e954eac1614cbadc0652948ed ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
* [`1945f23947816d901036e054895b21b7e911554976974601e3e75d112b100e41 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
* [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
@ -771,7 +779,7 @@ Results have checksums;
* [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`f16812056bc9ba5f599e2874acc4ab958f07fd21d763637aba9108d8e75795de ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`f38ea56bdbcda19fa2979a5a3c13e0af26d665a3880ac7ec14607229e8c54252 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
* [`f7b5e70b102e1e3d624f61c470f77374f14136579f69a92c061485fddea92239 ./kintex7/xc7k70tfbg676-2_package_pins.csv`](./kintex7/xc7k70tfbg676-2_package_pins.csv)
@ -781,7 +789,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1"
@ -850,8 +858,8 @@ Results have checksums;
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_l.origin_info.db`](./zynq7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
* [`43d42ac58a77f62efe8e538fb452fffa81427276864b05894feba7f7338cde2d ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`02973a3ddaed35cebdc965205244d155a3b2f031baf25b2bc56380ab932717eb ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`7b316407a6f773f00ce4fc85092843641287fc759b8f25bd9a79d63a5b878650 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`cfcccd307c4d7153897c49744f30674a31342b221be7354388f8d665d3539da3 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
@ -902,10 +910,10 @@ Results have checksums;
* [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db)
* [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db)
* [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db)
* [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
* [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db)
* [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db)
* [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db)
@ -916,6 +924,10 @@ Results have checksums;
* [`eb566cda47e23291d9a3bfdef765233a030d6ff0d8d5debf68e9ade16d2fc6f9 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
* [`724bcea2bc588cf5089840f66c6a813ad6cc9958fec6b5db2d44ef75b8843c14 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
* [`5e5bc3b26dd2cc2632e95f390f87e9a7cc7cfd1f163e20447c02b0e2e111889d ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
* [`69eda3b03d20087c121c15e79559152eeae2619c5a86477ad763be9b63b58f4a ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
* [`302b0d51e98f856a498132119f42c10248345ab5181ab60cabd1f2fcb3c6344f ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
* [`6b205562d2e870f43d7959a05b1b8fbd75bfbb08878bb7ec5239d6b419ce3117 ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
* [`29023fed85b544c2d849067d1c945cb9cdc64fa2f4070acf6496ea132f9f3997 ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
@ -927,13 +939,13 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`8bcecca9f265dc6d40bc00caecfc14a2ea43217ec8ceb36ece26f1572119fae7 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`541c37385792706a1b37a16f09d8ba3a66cfe46a1dba00084e5fce3c74a7ad59 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`ebcae3b19d45466fc0b1c17e9ed4d94166998b9dba75940862c07a8f5788e66a ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`d1ad493bd149ba47ac50a68fef57809d21a1ef36db63725317a12df9266ca8d8 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`caaa32eadfca7d6417a09d5357f8c1eea23bdb325164857de03b8798bdf252bb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`27a74d9eddb6f960a94f107b28343d88dc8c2274de61be865e21e3a8d1f4e9f1 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`a8982b6f0a9d538d10c61c1a90624d3dfb54652ccf1fc5ccc64d27b573b04821 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`f85762b3e63eabe167710bb6d6273810f3a4e3e11d78513677b403db459b9e44 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`b37fd628a5530efb3e2de4bab01b2c9db5917e8083ca9a361700714a45d2cf63 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`6382b44bc537fca6c822cab52f93a7486b402db753743168a462abbb067662e1 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`f651df59cf27fa9883dd8487653b0f571cb199311106a78e23f7588cc94bf917 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
@ -1067,7 +1079,7 @@ Results have checksums;
* [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
* [`ea21496ec29a0041f148c5fa5ce5bc4d81ea7ed0333cf6791b8c46bccca58717 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`4d9d291298a5d9f2077b9d3b6356cf1f61dec188040afd3261f1194a1b7a5a30 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf)
* [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)

647
artix7/mask_liob33.db
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647
artix7/mask_riob33.db
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File diff suppressed because it is too large Load Diff

2
artix7/segbits_clblm_l.db
View File

@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48

2
artix7/segbits_clblm_l.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

2
artix7/segbits_clblm_r.db
View File

@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48

2
artix7/segbits_clblm_r.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

351
artix7/segbits_cmt_top_l_upper_t.db Normal file
View File

@ -0,0 +1,351 @@
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

351
artix7/segbits_cmt_top_l_upper_t.origin_info.db Normal file
View File

@ -0,0 +1,351 @@
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

351
artix7/segbits_cmt_top_r_upper_t.db Normal file
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@ -0,0 +1,351 @@
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07
CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

351
artix7/segbits_cmt_top_r_upper_t.origin_info.db Normal file
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CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

14
artix7/segbits_int_l.origin_info.db
View File

@ -676,7 +676,7 @@ INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
@ -2173,7 +2173,7 @@ INT_L.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_L.NE6BEG3.EE2END3 origin:050-pip-seed 03_52 05_55
INT_L.NE6BEG3.EE4END3 origin:050-pip-seed 05_52 05_55
INT_L.NE6BEG3.LH0 origin:056-pip-rem 04_54 05_52
@ -2191,9 +2191,9 @@ INT_L.NE6BEG3.NN6END3 origin:050-pip-seed 03_53 06_52
INT_L.NE6BEG3.NW2END3 origin:050-pip-seed 02_53 04_53
INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.SE6END3 origin:056-pip-rem 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L13 origin:050-pip-seed 10_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L19 origin:050-pip-seed 08_17 14_17
@ -2827,7 +2827,7 @@ INT_L.SE6BEG3.LV_L18 origin:056-pip-rem 04_59 05_57
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

8
artix7/segbits_int_r.origin_info.db
View File

@ -353,7 +353,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_R.EE4BEG1.EE2END1 origin:050-pip-seed 03_24 03_25
INT_R.EE4BEG1.EE4END1 origin:050-pip-seed 03_25 05_24
INT_R.EE4BEG1.LH6 origin:056-pip-rem 05_24 07_25
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
@ -584,7 +584,7 @@ INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_R.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_R.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
INT_R.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
INT_R.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
@ -3275,7 +3275,7 @@ INT_R.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_R.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_R.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_44 04_46
INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44

10
artix7/segbits_liob33.db
View File

@ -1,6 +1,8 @@
LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -16,8 +18,11 @@ LIOB33.IOB_Y0.IN_ONLY 38_118 39_119 39_125
LIOB33.IOB_Y0.INOUT 30_67
LIOB33.IOB_Y0.INTERMDISABLE.I 39_89
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
@ -63,8 +68,10 @@ LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !3
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y1.IBUFDISABLE.I 39_45
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -80,8 +87,11 @@ LIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
LIOB33.IOB_Y1.INOUT 31_60
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35

10
artix7/segbits_liob33.origin_info.db
View File

@ -1,7 +1,9 @@
LIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -19,7 +21,10 @@ LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
LIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95
@ -63,9 +68,11 @@ LIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -83,7 +90,10 @@ LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
LIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63

10
artix7/segbits_riob33.db
View File

@ -1,6 +1,8 @@
RIOB33.IOB_Y0.IBUFDISABLE.I 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -16,8 +18,11 @@ RIOB33.IOB_Y0.IN_ONLY 38_118 39_119 39_125
RIOB33.IOB_Y0.INOUT 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
@ -63,8 +68,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !3
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -80,8 +87,11 @@ RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35

10
artix7/segbits_riob33.origin_info.db
View File

@ -1,7 +1,9 @@
RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -19,7 +21,10 @@ RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95
@ -63,9 +68,11 @@ RIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -83,7 +90,10 @@ RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63

30
artix7/tilegrid.json
View File

@ -76261,7 +76261,7 @@
"CMT_TOP_L_LOWER_B_X106Y61": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00020080",
"baseaddr": "0x00001500",
"frames": 30,
"offset": 0,
"words": 101
@ -76277,7 +76277,7 @@
"CMT_TOP_L_LOWER_B_X106Y9": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000080",
"baseaddr": "0x00401500",
"frames": 30,
"offset": 0,
"words": 101
@ -76347,8 +76347,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00401500",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 106,
@ -76363,8 +76363,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00001500",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 106,
@ -76377,7 +76377,7 @@
"CMT_TOP_R_LOWER_B_X8Y113": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001500",
"baseaddr": "0x00020080",
"frames": 30,
"offset": 0,
"words": 101
@ -76393,7 +76393,7 @@
"CMT_TOP_R_LOWER_B_X8Y61": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00400080",
"baseaddr": "0x00000080",
"frames": 30,
"offset": 0,
"words": 101
@ -76409,7 +76409,7 @@
"CMT_TOP_R_LOWER_B_X8Y9": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401500",
"baseaddr": "0x00400080",
"frames": 30,
"offset": 0,
"words": 101
@ -76505,8 +76505,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00020080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,
@ -76521,8 +76521,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00400080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,
@ -76537,8 +76537,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00000080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,

718
kintex7/mask_liob33.db
View File

File diff suppressed because it is too large Load Diff

718
kintex7/mask_riob33.db
View File

File diff suppressed because it is too large Load Diff

2
kintex7/segbits_clblm_l.db
View File

@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48

2
kintex7/segbits_clblm_l.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

2
kintex7/segbits_clblm_r.db
View File

@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48

2
kintex7/segbits_clblm_r.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

349
kintex7/segbits_cmt_top_l_upper_t.db Normal file
View File

@ -0,0 +1,349 @@
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

349
kintex7/segbits_cmt_top_l_upper_t.origin_info.db Normal file
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CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

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kintex7/segbits_cmt_top_r_upper_t.db Normal file
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CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07
CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

349
kintex7/segbits_cmt_top_r_upper_t.origin_info.db Normal file
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@ -0,0 +1,349 @@
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

8
kintex7/segbits_int_l.origin_info.db
View File

@ -373,7 +373,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_L.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_L.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -676,7 +676,7 @@ INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

8
kintex7/segbits_int_r.origin_info.db
View File

@ -413,7 +413,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@ -676,7 +676,7 @@ INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_R.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17
@ -3295,7 +3295,7 @@ INT_R.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
INT_R.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
INT_R.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_60 07_61
INT_R.SW6BEG3.LOGIC_OUTS15 origin:050-pip-seed 03_60 04_62

10
kintex7/segbits_liob33.db
View File

@ -1,6 +1,8 @@
LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -15,8 +17,11 @@ LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
LIOB33.IOB_Y0.INOUT 30_67
LIOB33.IOB_Y0.INTERMDISABLE.I 39_89
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
@ -60,8 +65,10 @@ LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !3
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y1.IBUFDISABLE.I 39_45
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -77,8 +84,11 @@ LIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
LIOB33.IOB_Y1.INOUT 31_60
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35

10
kintex7/segbits_liob33.origin_info.db
View File

@ -1,7 +1,9 @@
LIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -18,7 +20,10 @@ LIOB33.IOB_Y0.INOUT origin:030-iob 30_67
LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_127 39_65 39_95
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_125 39_65 39_95
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_119 39_65 39_95
@ -60,9 +65,11 @@ LIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -80,7 +87,10 @@ LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
LIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63

10
kintex7/segbits_riob33.db
View File

@ -1,6 +1,8 @@
RIOB33.IOB_Y0.IBUFDISABLE.I 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -15,8 +17,11 @@ RIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
RIOB33.IOB_Y0.INOUT 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
@ -60,8 +65,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !3
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -77,8 +84,11 @@ RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35

10
kintex7/segbits_riob33.origin_info.db
View File

@ -1,7 +1,9 @@
RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -18,7 +20,10 @@ RIOB33.IOB_Y0.INOUT origin:030-iob 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_125 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_119 39_65 39_95
@ -60,9 +65,11 @@ RIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -80,7 +87,10 @@ RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63

36
kintex7/tilegrid.json
View File

@ -98556,7 +98556,7 @@
"CMT_TOP_L_LOWER_B_X108Y61": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00020080",
"baseaddr": "0x00401500",
"frames": 30,
"offset": 0,
"words": 101
@ -98572,7 +98572,7 @@
"CMT_TOP_L_LOWER_B_X108Y9": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000080",
"baseaddr": "0x00421500",
"frames": 30,
"offset": 0,
"words": 101
@ -98642,8 +98642,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00421500",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 108,
@ -98658,8 +98658,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00401500",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 108,
@ -98672,7 +98672,7 @@
"CMT_TOP_R_LOWER_B_X8Y113": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401500",
"baseaddr": "0x00000080",
"frames": 30,
"offset": 0,
"words": 101
@ -98688,7 +98688,7 @@
"CMT_TOP_R_LOWER_B_X8Y165": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00400080",
"baseaddr": "0x00020080",
"frames": 30,
"offset": 0,
"words": 101
@ -98704,7 +98704,7 @@
"CMT_TOP_R_LOWER_B_X8Y61": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00420080",
"baseaddr": "0x00400080",
"frames": 30,
"offset": 0,
"words": 101
@ -98720,7 +98720,7 @@
"CMT_TOP_R_LOWER_B_X8Y9": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00421500",
"baseaddr": "0x00420080",
"frames": 30,
"offset": 0,
"words": 101
@ -98842,8 +98842,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00000080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,
@ -98858,8 +98858,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00020080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,
@ -98874,8 +98874,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00420080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,
@ -98890,8 +98890,8 @@
"CLB_IO_CLK": {
"baseaddr": "0x00400080",
"frames": 30,
"offset": 0,
"words": 101
"offset": 75,
"words": 26
}
},
"grid_x": 8,

612
zynq7/mask_liob33.db
View File

File diff suppressed because it is too large Load Diff

598
zynq7/mask_riob33.db
View File

File diff suppressed because it is too large Load Diff

2
zynq7/segbits_clblm_l.db
View File

@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48

2
zynq7/segbits_clblm_l.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

2
zynq7/segbits_clblm_r.db
View File

@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48

2
zynq7/segbits_clblm_r.origin_info.db
View File

@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60
@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51

348
zynq7/segbits_cmt_top_l_upper_t.db Normal file
View File

@ -0,0 +1,348 @@
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

348
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CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

344
zynq7/segbits_cmt_top_r_upper_t.db Normal file
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CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215

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zynq7/segbits_cmt_top_r_upper_t.origin_info.db Normal file
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CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43
CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720

6
zynq7/segbits_int_l.origin_info.db
View File

@ -2411,7 +2411,7 @@ INT_L.NN6BEG2.NN6END2 origin:050-pip-seed 02_38 07_39
INT_L.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
INT_L.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
INT_L.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
INT_L.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
INT_L.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
INT_L.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
INT_L.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
INT_L.NN6BEG3.EE2END3 origin:050-pip-seed 02_55 05_54
@ -2431,7 +2431,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44

10
zynq7/segbits_int_r.origin_info.db
View File

@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17
@ -2827,7 +2827,7 @@ INT_R.SE6BEG3.LV18 origin:056-pip-rem 04_59 05_57
INT_R.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_R.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_R.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
INT_R.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_R.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_R.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_R.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_R.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@ -3255,7 +3255,7 @@ INT_R.SW6BEG0.SW6END0 origin:050-pip-seed 03_13 05_12
INT_R.SW6BEG0.WW2END0 origin:050-pip-seed 03_12 05_15
INT_R.SW6BEG0.WW4END1 origin:050-pip-seed 05_12 05_15
INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_29 04_30
INT_R.SW6BEG1.LOGIC_OUTS13 origin:050-pip-seed 03_28 04_30
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_33 07_33
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

10
zynq7/segbits_liob33.db
View File

@ -1,5 +1,7 @@
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -12,8 +14,11 @@ LIOB33.IOB_Y0.IFF.ZSRVAL_Q2 29_75
LIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85
LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
LIOB33.IOB_Y0.OFF.ZINIT_Q 33_97
@ -31,8 +36,10 @@ LIOB33.IOB_Y0.TFF.ZINIT_Q 30_75
LIOB33.IOB_Y0.ZINV_D 29_109
LIOB33.IOB_Y0.IDELMUXE3.0 29_101
LIOB33.IOB_Y0.IFFDELMUXE3.0 28_116
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -45,8 +52,11 @@ LIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
LIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
LIOB33.IOB_Y1.OFF.ZINIT_Q 32_30

10
zynq7/segbits_liob33.origin_info.db
View File

@ -1,6 +1,8 @@
LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -15,7 +17,10 @@ LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 29_93
LIOB33.IOB_Y0.IFFDELMUXE3.0 origin:035-iob-ilogic 28_116
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
LIOB33.IOB_Y0.OFF.ZINIT_Q origin:036-iob-ologic 33_97
@ -31,9 +36,11 @@ LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 30_123
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 31_116
LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -48,7 +55,10 @@ LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 28_34
LIOB33.IOB_Y1.IFFDELMUXE3.0 origin:035-iob-ilogic 29_11
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
LIOB33.IOB_Y1.OFF.ZINIT_Q origin:036-iob-ologic 32_30

10
zynq7/segbits_riob33.db
View File

@ -1,6 +1,8 @@
RIOB33.IOB_Y0.IBUFDISABLE.I 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
@ -16,8 +18,11 @@ RIOB33.IOB_Y0.IN_ONLY 38_118 39_119 39_125
RIOB33.IOB_Y0.INOUT 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
@ -63,8 +68,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !3
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
@ -80,8 +87,11 @@ RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35

10
zynq7/segbits_riob33.origin_info.db
View File

@ -1,7 +1,9 @@
RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82
RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67
RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99
RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76
@ -19,7 +21,10 @@ RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89
RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121
RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95
@ -63,9 +68,11 @@ RIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75
RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109
RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60
RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28
RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51
@ -83,7 +90,10 @@ RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06
RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63

18
zynq7/tilegrid.json
View File

@ -42794,7 +42794,14 @@
"type": "CMT_TOP_L_UPPER_B"
},
"CMT_TOP_L_UPPER_T_X119Y44": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B00",
"frames": 30,
"offset": 75,
"words": 26
}
},
"grid_x": 119,
"grid_y": 60,
"sites": {
@ -42803,7 +42810,14 @@
"type": "CMT_TOP_L_UPPER_T"
},
"CMT_TOP_L_UPPER_T_X119Y96": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B00",
"frames": 30,
"offset": 75,
"words": 26
}
},
"grid_x": 119,
"grid_y": 8,
"sites": {