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arty-a7: add UART harness 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-03-22 16:37:06 -07:00
parent 0b9d5dd89e
commit 85022780e8
6 changed files with 281 additions and 2 deletions
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8
Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Fri Mar 22 22:39:24 UTC 2019 (2019-03-22T22:39:24+00:00).
Last updated on Fri Mar 22 23:47:22 UTC 2019 (2019-03-22T23:47:22+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [5e9211d](https://github.com/SymbiFlow/prjxray/commit/5e9211d57ccc0c1c46088bcf858f8f552fe6301f).
@ -96,7 +96,7 @@ Results have checksums;
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`3aacff527ff9389f20510c56014b7bc2c54116d9d0d3199216743cfbdd09664d ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
* [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
* [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
@ -105,6 +105,10 @@ Results have checksums;
* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`7f92af7280a5e8563dd764c52356e2f914a20b5d413ff1441c546da6101df21c ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
* [`78616f1443dcacb0af37f78ba507c81f0a6115770e538430d5c7382aa48edd6a ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
* [`8df57ddc871785ba1710beb4a14c6ceed706cfb48bfbc425182f2a96742fdd13 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
* [`3e70378bc05fe32951fed4816f634ff35e5f1511d992ebf8e6718d6d8a65943f ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`2e19b7f8aaaf6fd6e891fa16ceb351eaf659202ef512598ec8f518c57d6ab484 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)

9
artix7/harness/README.md
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@ -39,6 +39,7 @@ Description from the [Digilent website](https://store.digilentinc.com/arty-a7-ar
Supported harness configurations;
* [SWBUT](#swbut)
* [PMOD](#pmod)
* [UART](#uart)
## [Basys 3](basys3)
@ -83,3 +84,11 @@ a clock).
Supported boards;
* [Arty A7-35T](#Arty%20A7-35T)
## UART
Harness which maps a board's UART, a reset button, an LED into the region of
interest (plus a clock).
Supported boards;
* [Arty A7-35T](#Arty%20A7-35T)

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artix7/harness/arty-a7/uart/design.bit Normal file
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artix7/harness/arty-a7/uart/design.dcp Normal file
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artix7/harness/arty-a7/uart/design.json Normal file
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@ -0,0 +1,260 @@
{
"info": {
"GRID_X_MAX": 58,
"GRID_X_MIN": 10,
"GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
{
"name": "clk",
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
"pin": "E3",
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
},
{
"name": "din[0]",
"node": "INT_R_X25Y126/WW2BEG1",
"pin": "C2",
"wire": "VBRK_X61Y132/VBRK_WW2END1",
"wires_outside_roi": [
"BRAM_INT_INTERFACE_R_X37Y87/INT_INTERFACE_LH6",
"BRAM_R_X37Y85/BRAM_LH6_2",
"BRKH_INT_X31Y99/BRKH_INT_LV12",
"CLBLL_L_X24Y126/CLBLL_WW2END1",
"CLBLL_L_X26Y123/CLBLL_WW4END3",
"CLBLL_L_X38Y87/CLBLL_LH6",
"CLBLL_L_X40Y87/CLBLL_LH4",
"CLBLL_R_X31Y87/CLBLL_LH12",
"CLBLM_L_X32Y87/CLBLM_LH12",
"CLBLM_L_X36Y87/CLBLM_LH8",
"CLBLM_R_X25Y123/CLBLM_WW4END3",
"CLBLM_R_X33Y87/CLBLM_LH10",
"CLBLM_R_X35Y87/CLBLM_LH8",
"CLBLM_R_X39Y87/CLBLM_LH4",
"CLBLM_R_X41Y87/CLBLM_LH2",
"CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_5",
"CMT_FIFO_L_X107Y97/CMT_FIFO_LH2_0",
"CMT_TOP_L_UPPER_T_X106Y96/CMT_TOP_LH2_0",
"DSP_L_X34Y85/DSP_LH10_2",
"HCLK_R_X110Y78/HCLK_LV5",
"HCLK_R_X64Y130/HCLK_NN2BEG2",
"INT_INTERFACE_L_X34Y87/INT_INTERFACE_LH10",
"INT_INTERFACE_L_X42Y87/INT_INTERFACE_LH2",
"INT_INTERFACE_R_X23Y126/INT_INTERFACE_WW2END1",
"INT_L_X24Y126/WW2A1",
"INT_L_X26Y123/WW4C3",
"INT_L_X30Y123/WW4A3",
"INT_L_X32Y87/LH11",
"INT_L_X34Y87/LH9",
"INT_L_X36Y87/LH7",
"INT_L_X38Y87/LH5",
"INT_L_X40Y87/LH3",
"INT_L_X42Y87/LH1",
"INT_R_X25Y123/NL1BEG2",
"INT_R_X25Y123/WW4END3",
"INT_R_X25Y124/NL1END2",
"INT_R_X25Y124/NN2BEG2",
"INT_R_X25Y125/NN2A2",
"INT_R_X25Y126/NN2END2",
"INT_R_X25Y126/WW2BEG1",
"INT_R_X27Y123/WW4B3",
"INT_R_X31Y100/LV13",
"INT_R_X31Y101/LV14",
"INT_R_X31Y102/LV15",
"INT_R_X31Y103/LV16",
"INT_R_X31Y104/LV17",
"INT_R_X31Y105/LV0",
"INT_R_X31Y105/LV18",
"INT_R_X31Y106/LV1",
"INT_R_X31Y107/LV2",
"INT_R_X31Y108/LV3",
"INT_R_X31Y109/LV4",
"INT_R_X31Y110/LV5",
"INT_R_X31Y111/LV6",
"INT_R_X31Y112/LV7",
"INT_R_X31Y113/LV8",
"INT_R_X31Y114/LV9",
"INT_R_X31Y115/LV10",
"INT_R_X31Y116/LV11",
"INT_R_X31Y117/LV12",
"INT_R_X31Y118/LV13",
"INT_R_X31Y119/LV14",
"INT_R_X31Y120/LV15",
"INT_R_X31Y121/LV16",
"INT_R_X31Y122/LV17",
"INT_R_X31Y123/LV18",
"INT_R_X31Y123/WW4BEG3",
"INT_R_X31Y87/LH12",
"INT_R_X31Y87/LV0",
"INT_R_X31Y88/LV1",
"INT_R_X31Y89/LV2",
"INT_R_X31Y90/LV3",
"INT_R_X31Y91/LV4",
"INT_R_X31Y92/LV5",
"INT_R_X31Y93/LV6",
"INT_R_X31Y94/LV7",
"INT_R_X31Y95/LV8",
"INT_R_X31Y96/LV9",
"INT_R_X31Y97/LV10",
"INT_R_X31Y98/LV11",
"INT_R_X31Y99/LV12",
"INT_R_X33Y87/LH10",
"INT_R_X35Y87/LH8",
"INT_R_X37Y87/LH6",
"INT_R_X39Y87/LH4",
"INT_R_X41Y87/LH2",
"INT_R_X43Y68/LOGIC_OUTS18",
"INT_R_X43Y68/NR1BEG0",
"INT_R_X43Y69/LV0",
"INT_R_X43Y69/NR1END0",
"INT_R_X43Y70/LV1",
"INT_R_X43Y71/LV2",
"INT_R_X43Y72/LV3",
"INT_R_X43Y73/LV4",
"INT_R_X43Y74/LV5",
"INT_R_X43Y75/LV6",
"INT_R_X43Y76/LV7",
"INT_R_X43Y77/LV8",
"INT_R_X43Y78/LV9",
"INT_R_X43Y79/LV10",
"INT_R_X43Y80/LV11",
"INT_R_X43Y81/LV12",
"INT_R_X43Y82/LV13",
"INT_R_X43Y83/LV14",
"INT_R_X43Y84/LV15",
"INT_R_X43Y85/LV16",
"INT_R_X43Y86/LV17",
"INT_R_X43Y87/LH0",
"INT_R_X43Y87/LV18",
"IO_INT_INTERFACE_R_X43Y68/INT_INTERFACE_LOGIC_OUTS18",
"IO_INT_INTERFACE_R_X43Y68/INT_INTERFACE_LOGIC_OUTS_B18",
"PCIE_INT_INTERFACE_L_X30Y123/INT_INTERFACE_WW4B3",
"PCIE_INT_INTERFACE_R_X27Y123/INT_INTERFACE_WW4B3",
"PCIE_TOP_X71Y125/PCIE_WW4B3_3",
"RIOB33_X43Y67/IOB_IBUF0",
"RIOI3_X43Y67/IOI_ILOGIC0_O",
"RIOI3_X43Y67/IOI_LOGIC_OUTS18_1",
"RIOI3_X43Y67/RIOI_I0",
"RIOI3_X43Y67/RIOI_IBUF0",
"RIOI3_X43Y67/RIOI_ILOGIC0_D",
"R_TERM_INT_X112Y71/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X105Y91/VBRK_LH2",
"VBRK_X61Y132/VBRK_WW2END1",
"VBRK_X66Y128/VBRK_WW4END3",
"VBRK_X80Y91/VBRK_LH12",
"VBRK_X85Y91/VBRK_LH10",
"VBRK_X96Y91/VBRK_LH6"
]
},
{
"name": "din[1]",
"node": "INT_L_X0Y102/EE2BEG2",
"pin": "A9",
"wire": "VBRK_X9Y107/VBRK_EE2A2",
"wires_outside_roi": [
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
"INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
"INT_L_X0Y102/EE2BEG2",
"INT_L_X0Y102/SE2END2",
"INT_L_X0Y102/SW2A2",
"INT_L_X0Y103/SE6END2",
"INT_L_X0Y103/SW2BEG2",
"INT_L_X0Y103/SW6E2",
"INT_L_X0Y104/SW6D2",
"INT_L_X0Y105/SW6C2",
"INT_L_X0Y106/SW6B2",
"INT_L_X0Y107/SW6A2",
"INT_L_X0Y119/SE2A3",
"INT_L_X0Y120/EL1END3",
"INT_L_X0Y120/SE2BEG3",
"INT_L_X0Y120/WL1BEG3",
"INT_L_X0Y121/LOGIC_OUTS_L18",
"INT_L_X0Y121/WL1BEG_N3",
"INT_R_X1Y102/EE2A2",
"INT_R_X1Y107/LVB0",
"INT_R_X1Y107/SW6BEG2",
"INT_R_X1Y108/LVB1",
"INT_R_X1Y109/LVB2",
"INT_R_X1Y110/LVB3",
"INT_R_X1Y111/LVB4",
"INT_R_X1Y112/LVB5",
"INT_R_X1Y113/LVB6",
"INT_R_X1Y114/LVB7",
"INT_R_X1Y115/LVB8",
"INT_R_X1Y116/LVB9",
"INT_R_X1Y117/LVB10",
"INT_R_X1Y118/LVB11",
"INT_R_X1Y119/LVB12",
"INT_R_X1Y119/SE2END3",
"IO_INT_INTERFACE_L_X0Y102/INT_INTERFACE_SE2A2",
"IO_INT_INTERFACE_L_X0Y102/INT_INTERFACE_SW2A2",
"IO_INT_INTERFACE_L_X0Y103/INT_INTERFACE_SE4C2",
"IO_INT_INTERFACE_L_X0Y103/INT_INTERFACE_SW4END2",
"IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_EL1BEG3",
"IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_WL1END3",
"IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y121/IOB_IBUF1",
"LIOI3_X0Y121/IOI_ILOGIC1_O",
"LIOI3_X0Y121/IOI_LOGIC_OUTS18_0",
"LIOI3_X0Y121/LIOI_I1",
"LIOI3_X0Y121/LIOI_IBUF1",
"LIOI3_X0Y121/LIOI_ILOGIC1_D",
"L_TERM_INT_X2Y107/L_TERM_INT_SW2BEG2",
"L_TERM_INT_X2Y108/L_TERM_INT_SW4C2",
"L_TERM_INT_X2Y125/L_TERM_INT_WR1BEG2",
"L_TERM_INT_X2Y126/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y107/VBRK_EE2A2"
]
},
{
"name": "dout[0]",
"node": "INT_L_X2Y145/SW6BEG0",
"pin": "T10",
"wire": "VBRK_X9Y151/VBRK_SW4A0",
"wires_outside_roi": [
"CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
"CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_8",
"INT_INTERFACE_R_X1Y145/INT_INTERFACE_SW4A0",
"INT_L_X0Y141/SW6END0",
"INT_R_X1Y141/SW6E0",
"INT_R_X1Y142/SW6D0",
"INT_R_X1Y143/SW6C0",
"INT_R_X1Y144/SW6B0",
"INT_R_X1Y145/SW6A0",
"VBRK_X9Y151/VBRK_SW4A0"
]
},
{
"name": "dout[1]",
"node": "INT_L_X2Y147/SW6BEG0",
"pin": "D10",
"wire": "VBRK_X9Y153/VBRK_SW4A0",
"wires_outside_roi": [
"CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
"CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_10",
"INT_INTERFACE_R_X1Y147/INT_INTERFACE_SW4A0",
"INT_L_X0Y143/SW6END0",
"INT_R_X1Y143/SW6E0",
"INT_R_X1Y144/SW6D0",
"INT_R_X1Y145/SW6C0",
"INT_R_X1Y146/SW6B0",
"INT_R_X1Y147/SW6A0",
"VBRK_X9Y153/VBRK_SW4A0"
]
}
],
"required_features": [
"",
"CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE"
]
}

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artix7/harness/arty-a7/uart/design.txt Normal file
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@ -0,0 +1,6 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 E3 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
din[0] INT_R_X25Y126/WW2BEG1 C2 VBRK_X61Y132/VBRK_WW2END1
din[1] INT_L_X0Y102/EE2BEG2 A9 VBRK_X9Y107/VBRK_EE2A2
dout[0] INT_L_X2Y145/SW6BEG0 T10 VBRK_X9Y151/VBRK_SW4A0
dout[1] INT_L_X2Y147/SW6BEG0 D10 VBRK_X9Y153/VBRK_SW4A0