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Updating artix7 based on "Merge pull request #908 from antmicro/fix-bram-timing-fuzzer". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-06-27 08:57:20 -07:00
parent 82bf5f158c
commit 84a5ffc0d5
144 changed files with 10550 additions and 2091 deletions
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217
Info.md
View File

@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Wed 12 Jun 2019 11:23:43 AM UTC (2019-06-12T11:23:43+00:00).
Last updated on Wed 26 Jun 2019 04:30:12 PM UTC (2019-06-26T16:30:12+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [d31319cc](https://github.com/SymbiFlow/prjxray/commit/d31319ccaa6f6fc4d1106890f9d72d908fa03b52).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [ca6bbee](https://github.com/SymbiFlow/prjxray/commit/ca6bbee1931cc06152f0f94463f830d437160ff7).
Latest commit was;
```
commit d31319ccaa6f6fc4d1106890f9d72d908fa03b52
Merge: 80f42b7e 2ad76619
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Tue Jun 11 14:59:41 2019 -0700
commit ca6bbee1931cc06152f0f94463f830d437160ff7
Merge: b8f6448 6476443
Author: Alessandro Comodi <44773360+acomodi@users.noreply.github.com>
Date: Wed Jun 26 13:00:20 2019 +0200
Merge pull request #879 from litghost/avoid_full_dict_build
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer
Avoid building full speed_model dict.
007-timing: added missing aliases for bram timing
```
@ -59,7 +59,7 @@ Date: Tue Jun 11 14:59:41 2019 -0700
### Settings
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/d31319ccaa6f6fc4d1106890f9d72d908fa03b52/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/ca6bbee1931cc06152f0f94463f830d437160ff7/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -115,44 +115,68 @@ Results have checksums;
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
* [`30b4cfe8b60ccde4423a0bd0d7ad5242bea58d54abf5d15601dd3f390465e821 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_bram_l.origin_info.db`](./artix7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_r.block_ram.db`](./artix7/mask_bram_r.block_ram.db)
* [`30b4cfe8b60ccde4423a0bd0d7ad5242bea58d54abf5d15601dd3f390465e821 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_bram_r.origin_info.db`](./artix7/mask_bram_r.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_clbll_l.origin_info.db`](./artix7/mask_clbll_l.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_clbll_r.origin_info.db`](./artix7/mask_clbll_r.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_clblm_l.origin_info.db`](./artix7/mask_clblm_l.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_clblm_r.origin_info.db`](./artix7/mask_clblm_r.origin_info.db)
* [`a01322f2b03d6e7a29dd225905afe60347f157b8cd48a0e3ad0299a8776774cf ./artix7/mask_clk_bufg_bot_r.db`](./artix7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./artix7/mask_clk_bufg_rebuf.db`](./artix7/mask_clk_bufg_rebuf.db)
* [`a01322f2b03d6e7a29dd225905afe60347f157b8cd48a0e3ad0299a8776774cf ./artix7/mask_clk_bufg_top_r.db`](./artix7/mask_clk_bufg_top_r.db)
* [`492d7880ed2be3ce5479b397a88e012ea0c98e2ba667fa02d1d57acbdf10208f ./artix7/mask_clk_hrow_bot_r.db`](./artix7/mask_clk_hrow_bot_r.db)
* [`8065dd1943464a57b58323eb09fa9d34148e09a3cd0d7d750dc31166ac25164a ./artix7/mask_clk_hrow_top_r.db`](./artix7/mask_clk_hrow_top_r.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_dsp_l.origin_info.db`](./artix7/mask_dsp_l.origin_info.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_dsp_r.origin_info.db`](./artix7/mask_dsp_r.origin_info.db)
* [`be757fb834be7ff84a2873c0ac6621c909a5e85362b397667760edde86616f84 ./artix7/mask_hclk_cmt.db`](./artix7/mask_hclk_cmt.db)
* [`be757fb834be7ff84a2873c0ac6621c909a5e85362b397667760edde86616f84 ./artix7/mask_hclk_cmt_l.db`](./artix7/mask_hclk_cmt_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_l.origin_info.db`](./artix7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
* [`7efda5faeec347ea5d07fcf38fbf8dc3ef36661b77af7837639999bc4b50bc45 ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
* [`7efda5faeec347ea5d07fcf38fbf8dc3ef36661b77af7837639999bc4b50bc45 ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
* [`a5cc4c3bf578f01185d1094a0d6d9ddb4bab241dfbfeaed7615a690932bf3606 ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
* [`a5cc4c3bf578f01185d1094a0d6d9ddb4bab241dfbfeaed7615a690932bf3606 ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_int_interface_r.origin_info.db`](./artix7/ppips_bram_int_interface_r.origin_info.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./artix7/ppips_bram_l.db`](./artix7/ppips_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_l.origin_info.db`](./artix7/ppips_bram_l.origin_info.db)
* [`e58acdfa3cc740d2346dcb5d3a4c13434d459ebdc2ceb655dcb65fd631da4e4d ./artix7/ppips_bram_r.db`](./artix7/ppips_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_r.origin_info.db`](./artix7/ppips_bram_r.origin_info.db)
* [`be58cd551e870914cff515baabe383dc2655f34f5332c395ceb20ca25414dd63 ./artix7/ppips_brkh_int.db`](./artix7/ppips_brkh_int.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_clbll_l.origin_info.db`](./artix7/ppips_clbll_l.origin_info.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./artix7/ppips_clbll_r.db`](./artix7/ppips_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_clbll_r.origin_info.db`](./artix7/ppips_clbll_r.origin_info.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./artix7/ppips_clblm_l.db`](./artix7/ppips_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_clblm_l.origin_info.db`](./artix7/ppips_clblm_l.origin_info.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./artix7/ppips_clblm_r.db`](./artix7/ppips_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_clblm_r.origin_info.db`](./artix7/ppips_clblm_r.origin_info.db)
* [`77fba62caedba6632e55834bbc40ff797181d8825e2f4d55987a04a38a95a6c0 ./artix7/ppips_clk_bufg_bot_r.db`](./artix7/ppips_clk_bufg_bot_r.db)
* [`15dba278ba801744b1ed558220334899fc098acd8e8aff20ab9761249a70e839 ./artix7/ppips_clk_bufg_top_r.db`](./artix7/ppips_clk_bufg_top_r.db)
* [`0dbef414182c3ef9054f4b9bc15c41c435d4bef2db30850add728d3de93749b8 ./artix7/ppips_clk_hrow_bot_r.db`](./artix7/ppips_clk_hrow_bot_r.db)
* [`8774624d8398b6000e80cefbcf5a5bac095e1c8650772c23f9b73448e0df5dbb ./artix7/ppips_clk_hrow_top_r.db`](./artix7/ppips_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_l.db`](./artix7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_l.origin_info.db`](./artix7/ppips_dsp_l.origin_info.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.db`](./artix7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_dsp_r.origin_info.db`](./artix7/ppips_dsp_r.origin_info.db)
* [`b61bbc9db6d0de1141a87d787f5d118be0a244802eed712612ff2aa0b6aeb73a ./artix7/ppips_hclk_l.db`](./artix7/ppips_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_l.origin_info.db`](./artix7/ppips_hclk_l.origin_info.db)
* [`abe795445c031273b59a6a98cbfea3309c4047820cbea352c723138b3111c956 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_hclk_r.origin_info.db`](./artix7/ppips_hclk_r.origin_info.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_int_l.origin_info.db`](./artix7/ppips_int_l.origin_info.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_int_r.origin_info.db`](./artix7/ppips_int_r.origin_info.db)
* [`916e3cea00e0bf8291ae24083696833dc1ff09f06562eccba6f2c73afd267ccb ./artix7/ppips_io_int_interface_l.db`](./artix7/ppips_io_int_interface_l.db)
* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./artix7/ppips_io_int_interface_r.db`](./artix7/ppips_io_int_interface_r.db)
* [`b155fbb8d964a2c3359a8420c0a6fd11aafccaeee92034e78cd16d2c56d4fcf9 ./artix7/ppips_lioi3.db`](./artix7/ppips_lioi3.db)
@ -171,14 +195,14 @@ Results have checksums;
* [`9b40402550b3a34067109372c2217e6bbef0744db204c38e4d7439f3ccba2474 ./artix7/segbits_bram_r.block_ram.origin_info.db`](./artix7/segbits_bram_r.block_ram.origin_info.db)
* [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
* [`83d0ac8050043e2aa67aa0dc2ba60692eef30daf9256503ff70b3e3a6475e3ba ./artix7/segbits_bram_r.origin_info.db`](./artix7/segbits_bram_r.origin_info.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`4ddab18383430522a3aa8d49688487dd0c3895f36f2b9f1fecabfb695d0105e4 ./artix7/segbits_clbll_l.origin_info.db`](./artix7/segbits_clbll_l.origin_info.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`50987c8e8ff9a66860f88e0f3531e92c5738a11613bee61720bae862e04b7787 ./artix7/segbits_clbll_r.origin_info.db`](./artix7/segbits_clbll_r.origin_info.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`467377976169e66212833dd5a92a1b0b19eae348b3fb113f0ea363097872c654 ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`20c664e6d20851c1b05e851ed278958a8d0f8d06697afb5caa70c62d07622575 ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db)
* [`9bf6bdffdc814569a7da53c696e46207aab23ea66c9dd92c47e50a6211dd739b ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./artix7/segbits_clbll_l.origin_info.db`](./artix7/segbits_clbll_l.origin_info.db)
* [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./artix7/segbits_clbll_r.origin_info.db`](./artix7/segbits_clbll_r.origin_info.db)
* [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
* [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db)
* [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
* [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./artix7/segbits_clk_bufg_bot_r.db`](./artix7/segbits_clk_bufg_bot_r.db)
* [`8d17f7e9f3cdf3419760d2b74cd23c04ee560f2f2bc942b718201c445a922c34 ./artix7/segbits_clk_bufg_bot_r.origin_info.db`](./artix7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./artix7/segbits_clk_bufg_rebuf.db`](./artix7/segbits_clk_bufg_rebuf.db)
@ -186,9 +210,9 @@ Results have checksums;
* [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a ./artix7/segbits_clk_bufg_top_r.db`](./artix7/segbits_clk_bufg_top_r.db)
* [`7497f9e1eb6208c157c3c1caeca7b94172a6bb4896e7cd6e3d28cf23c38c2281 ./artix7/segbits_clk_bufg_top_r.origin_info.db`](./artix7/segbits_clk_bufg_top_r.origin_info.db)
* [`4383aafad32f56f21404c5e6092811874f869c920e23a02b57da8c3e739fe2a9 ./artix7/segbits_clk_hrow_bot_r.db`](./artix7/segbits_clk_hrow_bot_r.db)
* [`016f2b46bce14767f32fdfd85cd07a8955e8f5c8f3a6ace557947ac24103c222 ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
* [`cde71c02d36c0a41d0706b944568ce03c0992ca2853276bc193470ec83d86186 ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
* [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db)
* [`3b7d97b353f83bd922446662ad15f652b7d135a5f57e290145b3fb6719115878 ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
* [`b66f2fcf9007247c5146cca61ddb82b815130d9dc8c54bca75e7f239b5bb64ae ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
@ -202,9 +226,9 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`dd0ebe0f4d00c4f4535c573b570baca6b38701af8ba457b28c0d37a802de9277 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`03db54ac91222c5aca52808ff784db5aabc53f4f3055029a1bb153f1926e621b ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`12d72fb4b64a10d66c3df120c7755432455c1e4509e75ee0c4a32337178b7d91 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`d966f992a7eb9d313937f788d7cb1d7ef28d06b371dc5d91a5f20f46d19b9808 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`6ece030404b8fd09095382730639d261e0402e2c513bf07d9ec301a7311ceb7e ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`f100a6e9abd51bbddb7aacb810c00b7240b2f50a25b3f331121d923198d43d8f ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
@ -367,118 +391,53 @@ Results have checksums;
* [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json)
* [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json)
* [`c748caf9267da80149d743f50ffa0684c41f6dcf153ba6fb14ea9f605bd0c7f8 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_INT_INTERFACE_L.sdf`](./artix7/timings/BRAM_INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_INT_INTERFACE_R.sdf`](./artix7/timings/BRAM_INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_BRAM.sdf`](./artix7/timings/BRKH_BRAM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_B_TERM_INT.sdf`](./artix7/timings/BRKH_B_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CLB.sdf`](./artix7/timings/BRKH_CLB.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CLK.sdf`](./artix7/timings/BRKH_CLK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_CMT.sdf`](./artix7/timings/BRKH_CMT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_DSP_L.sdf`](./artix7/timings/BRKH_DSP_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_DSP_R.sdf`](./artix7/timings/BRKH_DSP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_GTX.sdf`](./artix7/timings/BRKH_GTX.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_INT.sdf`](./artix7/timings/BRKH_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/BRKH_TERM_INT.sdf`](./artix7/timings/BRKH_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/B_TERM_INT.sdf`](./artix7/timings/B_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CFG_CENTER_BOT.sdf`](./artix7/timings/CFG_CENTER_BOT.sdf)
* [`8d6db739fe7463bf3806921de087423d59531ab44ff6fc1969c1421a39461bdb ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
* [`46bccf6038256506d6d881704f57db211d44c91dfee61d84e5416d54389ff166 ./artix7/tilegrid.json`](./artix7/tilegrid.json)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf)
* [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf)
* [`6dc7edd0792e8305dd8309933c264512fc6a22f45cf0386422edc219d5a3b20a ./artix7/timings/CFG_CENTER_TOP.sdf`](./artix7/timings/CFG_CENTER_TOP.sdf)
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./artix7/timings/CLBLL_L.sdf`](./artix7/timings/CLBLL_L.sdf)
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./artix7/timings/CLBLL_R.sdf`](./artix7/timings/CLBLL_R.sdf)
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./artix7/timings/CLBLM_L.sdf`](./artix7/timings/CLBLM_L.sdf)
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./artix7/timings/CLBLM_R.sdf`](./artix7/timings/CLBLM_R.sdf)
* [`64317dce36fb887f93b18c4020382cea2d94668f2ffe6417b6bd78787f80001e ./artix7/timings/CLBLL_L.sdf`](./artix7/timings/CLBLL_L.sdf)
* [`64317dce36fb887f93b18c4020382cea2d94668f2ffe6417b6bd78787f80001e ./artix7/timings/CLBLL_R.sdf`](./artix7/timings/CLBLL_R.sdf)
* [`9461f82cd0dbf257bc8efa85899bac3b187962cd3fe5dec44b252a6b37f6b9d9 ./artix7/timings/CLBLM_L.sdf`](./artix7/timings/CLBLM_L.sdf)
* [`9461f82cd0dbf257bc8efa85899bac3b187962cd3fe5dec44b252a6b37f6b9d9 ./artix7/timings/CLBLM_R.sdf`](./artix7/timings/CLBLM_R.sdf)
* [`4389bcb34bbc566f909c9d5d5d7bd4ac600dca5db76f33443319fed56630efa9 ./artix7/timings/CLK_BUFG_BOT_R.sdf`](./artix7/timings/CLK_BUFG_BOT_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_BUFG_REBUF.sdf`](./artix7/timings/CLK_BUFG_REBUF.sdf)
* [`4389bcb34bbc566f909c9d5d5d7bd4ac600dca5db76f33443319fed56630efa9 ./artix7/timings/CLK_BUFG_TOP_R.sdf`](./artix7/timings/CLK_BUFG_TOP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_FEED.sdf`](./artix7/timings/CLK_FEED.sdf)
* [`107282bc35eb94dbd0973c82c576e638917629b83743274f9463c225f8079396 ./artix7/timings/CLK_HROW_BOT_R.sdf`](./artix7/timings/CLK_HROW_BOT_R.sdf)
* [`107282bc35eb94dbd0973c82c576e638917629b83743274f9463c225f8079396 ./artix7/timings/CLK_HROW_TOP_R.sdf`](./artix7/timings/CLK_HROW_TOP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_MTBF2.sdf`](./artix7/timings/CLK_MTBF2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV.sdf`](./artix7/timings/CLK_PMV.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV2.sdf`](./artix7/timings/CLK_PMV2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMV2_SVT.sdf`](./artix7/timings/CLK_PMV2_SVT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_PMVIOB.sdf`](./artix7/timings/CLK_PMVIOB.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CLK_TERM.sdf`](./artix7/timings/CLK_TERM.sdf)
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./artix7/timings/CMT_FIFO_L.sdf`](./artix7/timings/CMT_FIFO_L.sdf)
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./artix7/timings/CMT_FIFO_R.sdf`](./artix7/timings/CMT_FIFO_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CMT_PMV.sdf`](./artix7/timings/CMT_PMV.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/CMT_PMV_L.sdf`](./artix7/timings/CMT_PMV_L.sdf)
* [`8c641a845fdd56842eec7c5fe72ddbd26654593313516137b88dcb5ea83a1920 ./artix7/timings/CMT_TOP_L_LOWER_B.sdf`](./artix7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./artix7/timings/CMT_TOP_L_LOWER_T.sdf`](./artix7/timings/CMT_TOP_L_LOWER_T.sdf)
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./artix7/timings/CMT_TOP_L_UPPER_B.sdf`](./artix7/timings/CMT_TOP_L_UPPER_B.sdf)
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./artix7/timings/CMT_TOP_L_UPPER_T.sdf`](./artix7/timings/CMT_TOP_L_UPPER_T.sdf)
* [`8c641a845fdd56842eec7c5fe72ddbd26654593313516137b88dcb5ea83a1920 ./artix7/timings/CMT_TOP_R_LOWER_B.sdf`](./artix7/timings/CMT_TOP_R_LOWER_B.sdf)
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
* [`6e723a9ad0acfa2a322e4fb2fed8b94c9f188d72bdf4e370e0e79860f1cbba92 ./artix7/timings/GTP_CHANNEL_3.sdf`](./artix7/timings/GTP_CHANNEL_3.sdf)
* [`aa79f422942e6767be523045374d542a4a51262eb7af8a5bd6c64312ff1b2927 ./artix7/timings/GTP_COMMON.sdf`](./artix7/timings/GTP_COMMON.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/GTP_INT_INTERFACE.sdf`](./artix7/timings/GTP_INT_INTERFACE.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_BRAM.sdf`](./artix7/timings/HCLK_BRAM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_CLB.sdf`](./artix7/timings/HCLK_CLB.sdf)
* [`5c9e2c5d7143ad81acc0bfb001d97e14192f0d79bcd444d5a4127b4c8c5080ff ./artix7/timings/HCLK_CMT.sdf`](./artix7/timings/HCLK_CMT.sdf)
* [`5c9e2c5d7143ad81acc0bfb001d97e14192f0d79bcd444d5a4127b4c8c5080ff ./artix7/timings/HCLK_CMT_L.sdf`](./artix7/timings/HCLK_CMT_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_DSP_L.sdf`](./artix7/timings/HCLK_DSP_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_DSP_R.sdf`](./artix7/timings/HCLK_DSP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FEEDTHRU_1.sdf`](./artix7/timings/HCLK_FEEDTHRU_1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FEEDTHRU_2.sdf`](./artix7/timings/HCLK_FEEDTHRU_2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_FIFO_L.sdf`](./artix7/timings/HCLK_FIFO_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_GTX.sdf`](./artix7/timings/HCLK_GTX.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_INT_INTERFACE.sdf`](./artix7/timings/HCLK_INT_INTERFACE.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_IOB.sdf`](./artix7/timings/HCLK_IOB.sdf)
* [`c396e1f4aa219633ad558731183c49ec9e92659b79eeff85b42fdac0de7c2368 ./artix7/timings/CLK_HROW_BOT_R.sdf`](./artix7/timings/CLK_HROW_BOT_R.sdf)
* [`c396e1f4aa219633ad558731183c49ec9e92659b79eeff85b42fdac0de7c2368 ./artix7/timings/CLK_HROW_TOP_R.sdf`](./artix7/timings/CLK_HROW_TOP_R.sdf)
* [`ff96f865bbd65952c73a8b8065c1ba6763ad61c94fe1ba40406dbdd850d4da04 ./artix7/timings/CMT_FIFO_L.sdf`](./artix7/timings/CMT_FIFO_L.sdf)
* [`ff96f865bbd65952c73a8b8065c1ba6763ad61c94fe1ba40406dbdd850d4da04 ./artix7/timings/CMT_FIFO_R.sdf`](./artix7/timings/CMT_FIFO_R.sdf)
* [`668be5d275b3b9522a2e02aa7789bd4df746ddf4eaf14ddb2c29d20ca8f5c751 ./artix7/timings/CMT_TOP_L_LOWER_B.sdf`](./artix7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4 ./artix7/timings/CMT_TOP_L_LOWER_T.sdf`](./artix7/timings/CMT_TOP_L_LOWER_T.sdf)
* [`e56222b18e7fabf7473656f7446958e93373a3bf956ca75968d26f9c652fa14e ./artix7/timings/CMT_TOP_L_UPPER_B.sdf`](./artix7/timings/CMT_TOP_L_UPPER_B.sdf)
* [`24408756edd72f9c82dc2badb3e94e372916c00c407e86a88db1274f8951d721 ./artix7/timings/CMT_TOP_L_UPPER_T.sdf`](./artix7/timings/CMT_TOP_L_UPPER_T.sdf)
* [`668be5d275b3b9522a2e02aa7789bd4df746ddf4eaf14ddb2c29d20ca8f5c751 ./artix7/timings/CMT_TOP_R_LOWER_B.sdf`](./artix7/timings/CMT_TOP_R_LOWER_B.sdf)
* [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4 ./artix7/timings/CMT_TOP_R_LOWER_T.sdf`](./artix7/timings/CMT_TOP_R_LOWER_T.sdf)
* [`e56222b18e7fabf7473656f7446958e93373a3bf956ca75968d26f9c652fa14e ./artix7/timings/CMT_TOP_R_UPPER_B.sdf`](./artix7/timings/CMT_TOP_R_UPPER_B.sdf)
* [`24408756edd72f9c82dc2badb3e94e372916c00c407e86a88db1274f8951d721 ./artix7/timings/CMT_TOP_R_UPPER_T.sdf`](./artix7/timings/CMT_TOP_R_UPPER_T.sdf)
* [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff ./artix7/timings/GTP_CHANNEL_0.sdf`](./artix7/timings/GTP_CHANNEL_0.sdf)
* [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff ./artix7/timings/GTP_CHANNEL_1.sdf`](./artix7/timings/GTP_CHANNEL_1.sdf)
* [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff ./artix7/timings/GTP_CHANNEL_2.sdf`](./artix7/timings/GTP_CHANNEL_2.sdf)
* [`fd93513fb5389752c1f1716bf15c2d3d118666e9f968533bb50d845504deb5ff ./artix7/timings/GTP_CHANNEL_3.sdf`](./artix7/timings/GTP_CHANNEL_3.sdf)
* [`6176fa60f0ceb61a8e70dde3b96c137fa84ba09683d6deedb01486f653fa3552 ./artix7/timings/GTP_COMMON.sdf`](./artix7/timings/GTP_COMMON.sdf)
* [`2e60feee8ddc9e67946362378ff347e1fedd2dbabe346e745a2ea83a6abe0dbf ./artix7/timings/HCLK_CMT.sdf`](./artix7/timings/HCLK_CMT.sdf)
* [`2e60feee8ddc9e67946362378ff347e1fedd2dbabe346e745a2ea83a6abe0dbf ./artix7/timings/HCLK_CMT_L.sdf`](./artix7/timings/HCLK_CMT_L.sdf)
* [`aa457af9f2c18f89df64c0cfedf6374e08fb7e0ef4c671f25c677f2de7430708 ./artix7/timings/HCLK_IOI3.sdf`](./artix7/timings/HCLK_IOI3.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_L.sdf`](./artix7/timings/HCLK_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_L_BOT_UTURN.sdf`](./artix7/timings/HCLK_L_BOT_UTURN.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_R.sdf`](./artix7/timings/HCLK_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_R_BOT_UTURN.sdf`](./artix7/timings/HCLK_R_BOT_UTURN.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_TERM.sdf`](./artix7/timings/HCLK_TERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_TERM_GTX.sdf`](./artix7/timings/HCLK_TERM_GTX.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_VBRK.sdf`](./artix7/timings/HCLK_VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/HCLK_VFRAME.sdf`](./artix7/timings/HCLK_VFRAME.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_FEEDTHRU_1.sdf`](./artix7/timings/INT_FEEDTHRU_1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_FEEDTHRU_2.sdf`](./artix7/timings/INT_FEEDTHRU_2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_INTERFACE_L.sdf`](./artix7/timings/INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_INTERFACE_R.sdf`](./artix7/timings/INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_L.sdf`](./artix7/timings/INT_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/INT_R.sdf`](./artix7/timings/INT_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/IO_INT_INTERFACE_L.sdf`](./artix7/timings/IO_INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/IO_INT_INTERFACE_R.sdf`](./artix7/timings/IO_INT_INTERFACE_R.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./artix7/timings/LIOB33.sdf`](./artix7/timings/LIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./artix7/timings/LIOB33_SING.sdf`](./artix7/timings/LIOB33_SING.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/LIOI3.sdf`](./artix7/timings/LIOI3.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/LIOI3_SING.sdf`](./artix7/timings/LIOI3_SING.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/LIOI3_TBYTESRC.sdf`](./artix7/timings/LIOI3_TBYTESRC.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/LIOI3_TBYTETERM.sdf`](./artix7/timings/LIOI3_TBYTETERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/L_TERM_INT.sdf`](./artix7/timings/L_TERM_INT.sdf)
* [`2af03d31603e237767ecaef977f8b6050c71d32a7632330ac8f42909dc22befc ./artix7/timings/MONITOR_BOT.sdf`](./artix7/timings/MONITOR_BOT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/MONITOR_MID.sdf`](./artix7/timings/MONITOR_MID.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/MONITOR_TOP.sdf`](./artix7/timings/MONITOR_TOP.sdf)
* [`6254f39239a1ba10b6243a77132493992378e52606eb28cf2e2a2d8948b7dbd2 ./artix7/timings/PCIE_BOT.sdf`](./artix7/timings/PCIE_BOT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_INT_INTERFACE_L.sdf`](./artix7/timings/PCIE_INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_INT_INTERFACE_R.sdf`](./artix7/timings/PCIE_INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_NULL.sdf`](./artix7/timings/PCIE_NULL.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/PCIE_TOP.sdf`](./artix7/timings/PCIE_TOP.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/LIOI3.sdf`](./artix7/timings/LIOI3.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/LIOI3_SING.sdf`](./artix7/timings/LIOI3_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/LIOI3_TBYTESRC.sdf`](./artix7/timings/LIOI3_TBYTESRC.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/LIOI3_TBYTETERM.sdf`](./artix7/timings/LIOI3_TBYTETERM.sdf)
* [`8adb21c5b19dc331cfeba427e65c1c15f33fbd7e43427acba206c109f5ce9985 ./artix7/timings/MONITOR_BOT.sdf`](./artix7/timings/MONITOR_BOT.sdf)
* [`5b91b2503c0c84b023463a712c13c61399b59765cce941e39676570cf93a7de6 ./artix7/timings/PCIE_BOT.sdf`](./artix7/timings/PCIE_BOT.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./artix7/timings/RIOB33.sdf`](./artix7/timings/RIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./artix7/timings/RIOB33_SING.sdf`](./artix7/timings/RIOB33_SING.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/RIOI3.sdf`](./artix7/timings/RIOI3.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/RIOI3_SING.sdf`](./artix7/timings/RIOI3_SING.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/RIOI3_TBYTESRC.sdf`](./artix7/timings/RIOI3_TBYTESRC.sdf)
* [`02c0fd3d714b5b7f4ba97d3575ae517360cb6a010f0a2a562a3be824b7d0b401 ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/R_TERM_INT.sdf`](./artix7/timings/R_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/R_TERM_INT_GTX.sdf`](./artix7/timings/R_TERM_INT_GTX.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/TERM_CMT.sdf`](./artix7/timings/TERM_CMT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/T_TERM_INT.sdf`](./artix7/timings/T_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VBRK.sdf`](./artix7/timings/VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VBRK_EXT.sdf`](./artix7/timings/VBRK_EXT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./artix7/timings/VFRAME.sdf`](./artix7/timings/VFRAME.sdf)
* [`bbdb8b53bb1343cefbc977089069d67ef277fa758ae77e06d50aa8de6e503ae2 ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
* [`b0a63e17e651071eec70a4048fc3321d79a8b0f6d430ad323eebc8b624418b0a ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/RIOI3.sdf`](./artix7/timings/RIOI3.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/RIOI3_SING.sdf`](./artix7/timings/RIOI3_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/RIOI3_TBYTESRC.sdf`](./artix7/timings/RIOI3_TBYTESRC.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./artix7/timings/RIOI3_TBYTETERM.sdf`](./artix7/timings/RIOI3_TBYTETERM.sdf)
* [`85ad47e1c4cd40ad8e70e4abefeb88eb648e7b7a2f40ce366851552195a024a7 ./artix7/timings/slicel.sdf`](./artix7/timings/slicel.sdf)
* [`5b1834f0f17f71ce613b907a11f1d93096f20c05acc5f382b05195831e882eb6 ./artix7/timings/slicem.sdf`](./artix7/timings/slicem.sdf)
* [`4c20ee41ea32668919b7d91a7fabe38960e0ee4d5b3b83f1d18102d48895bf1c ./artix7/xc7a35tcpg236-1.json`](./artix7/xc7a35tcpg236-1.json)
* [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml)
* [`ac928ee3c50e91facacb4173fdf70384f56e046bb14581bf75f760e406fe4f78 ./artix7/xc7a35tcpg236-1_package_pins.csv`](./artix7/xc7a35tcpg236-1_package_pins.csv)
@ -494,7 +453,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/d31319ccaa6f6fc4d1106890f9d72d908fa03b52/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/ca6bbee1931cc06152f0f94463f830d437160ff7/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -798,7 +757,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/d31319ccaa6f6fc4d1106890f9d72d908fa03b52/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/ca6bbee1931cc06152f0f94463f830d437160ff7/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1"

4
Makefile
View File

@ -1,14 +1,18 @@
DATABASE_FILES = *.csv *.db *.json *.yaml
TIMINGS_FILES = *.sdf
clean-artix7-db:
rm -f $(addprefix artix7/,$(DATABASE_FILES))
rm -f $(addprefix artix7/timings/,$(TIMINGS_FILES))
clean-kintex7-db:
rm -f $(addprefix kintex7/,$(DATABASE_FILES))
rm -f $(addprefix kintex7/timings/,$(TIMINGS_FILES))
clean-zynq7-db:
rm -f $(addprefix zynq7/,$(DATABASE_FILES))
rm -f $(addprefix zynq7/timings/,$(TIMINGS_FILES))
clean-db: clean-artix7-db clean-kintex7-db clean-zynq7-db
@true

0
artix7/mask_bram_l.origin_info.db Normal file
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0
artix7/mask_bram_r.origin_info.db Normal file
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0
artix7/mask_clbll_l.origin_info.db Normal file
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0
artix7/mask_clbll_r.origin_info.db Normal file
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0
artix7/mask_clblm_l.origin_info.db Normal file
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0
artix7/mask_clblm_r.origin_info.db Normal file
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0
artix7/mask_dsp_l.origin_info.db Normal file
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0
artix7/mask_dsp_r.origin_info.db Normal file
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0
artix7/mask_hclk_l.origin_info.db Normal file
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0
artix7/mask_hclk_r.origin_info.db Normal file
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116
artix7/mask_liob33.db
View File

@ -50,11 +50,11 @@ bit 01_40
bit 01_41
bit 01_42
bit 01_44
bit 01_45
bit 01_50
bit 01_52
bit 01_58
bit 01_64
bit 01_65
bit 01_66
bit 01_68
bit 01_69
@ -70,14 +70,11 @@ bit 01_101
bit 01_102
bit 01_104
bit 01_105
bit 01_106
bit 01_114
bit 01_116
bit 02_02
bit 02_05
bit 02_06
bit 02_07
bit 02_09
bit 02_10
bit 02_11
bit 02_13
bit 02_14
@ -86,21 +83,24 @@ bit 02_18
bit 02_22
bit 02_23
bit 02_30
bit 02_31
bit 02_34
bit 02_35
bit 02_38
bit 02_39
bit 02_46
bit 02_47
bit 02_50
bit 02_51
bit 02_54
bit 02_55
bit 02_62
bit 02_63
bit 02_67
bit 02_69
bit 02_70
bit 02_71
bit 02_74
bit 02_73
bit 02_75
bit 02_77
bit 02_78
bit 02_79
@ -110,15 +110,17 @@ bit 02_87
bit 02_94
bit 02_95
bit 02_98
bit 02_99
bit 02_102
bit 02_103
bit 02_114
bit 02_117
bit 02_115
bit 02_118
bit 02_119
bit 02_126
bit 02_127
bit 03_02
bit 03_05
bit 03_06
bit 03_10
bit 03_13
@ -127,11 +129,10 @@ bit 03_21
bit 03_29
bit 03_36
bit 03_37
bit 03_38
bit 03_45
bit 03_52
bit 03_53
bit 03_54
bit 03_60
bit 03_61
bit 03_62
bit 03_66
@ -144,15 +145,13 @@ bit 03_78
bit 03_86
bit 03_93
bit 03_102
bit 03_109
bit 03_116
bit 03_117
bit 03_118
bit 03_126
bit 04_04
bit 04_05
bit 04_06
bit 04_07
bit 04_10
bit 04_11
bit 04_12
bit 04_14
@ -172,6 +171,7 @@ bit 04_37
bit 04_39
bit 04_44
bit 04_47
bit 04_48
bit 04_51
bit 04_52
bit 04_53
@ -181,12 +181,10 @@ bit 04_66
bit 04_68
bit 04_69
bit 04_70
bit 04_71
bit 04_74
bit 04_75
bit 04_76
bit 04_78
bit 04_79
bit 04_83
bit 04_84
bit 04_85
bit 04_86
@ -200,6 +198,7 @@ bit 04_115
bit 04_116
bit 04_117
bit 04_119
bit 04_124
bit 05_01
bit 05_02
bit 05_05
@ -220,18 +219,19 @@ bit 05_34
bit 05_36
bit 05_37
bit 05_38
bit 05_44
bit 05_46
bit 05_49
bit 05_50
bit 05_52
bit 05_53
bit 05_54
bit 05_58
bit 05_60
bit 05_62
bit 05_63
bit 05_65
bit 05_66
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
@ -240,17 +240,16 @@ bit 05_81
bit 05_82
bit 05_86
bit 05_89
bit 05_90
bit 05_94
bit 05_98
bit 05_101
bit 05_102
bit 05_108
bit 05_113
bit 05_114
bit 05_116
bit 05_117
bit 05_118
bit 05_119
bit 05_126
bit 06_01
bit 06_02
bit 06_03
@ -258,15 +257,15 @@ bit 06_04
bit 06_05
bit 06_06
bit 06_10
bit 06_11
bit 06_12
bit 06_13
bit 06_14
bit 06_15
bit 06_17
bit 06_20
bit 06_21
bit 06_22
bit 06_24
bit 06_27
bit 06_28
bit 06_29
bit 06_30
@ -275,6 +274,7 @@ bit 06_33
bit 06_35
bit 06_36
bit 06_37
bit 06_39
bit 06_43
bit 06_46
bit 06_49
@ -303,11 +303,11 @@ bit 06_79
bit 06_81
bit 06_83
bit 06_84
bit 06_85
bit 06_86
bit 06_89
bit 06_91
bit 06_92
bit 06_93
bit 06_94
bit 06_97
bit 06_99
@ -317,6 +317,7 @@ bit 06_107
bit 06_113
bit 06_115
bit 06_116
bit 06_117
bit 06_119
bit 06_121
bit 06_123
@ -336,11 +337,9 @@ bit 07_14
bit 07_15
bit 07_16
bit 07_19
bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_25
bit 07_26
bit 07_27
bit 07_28
@ -366,7 +365,6 @@ bit 07_54
bit 07_55
bit 07_56
bit 07_58
bit 07_59
bit 07_60
bit 07_62
bit 07_63
@ -378,15 +376,12 @@ bit 07_69
bit 07_70
bit 07_71
bit 07_72
bit 07_73
bit 07_74
bit 07_75
bit 07_76
bit 07_77
bit 07_78
bit 07_79
bit 07_80
bit 07_82
bit 07_83
bit 07_84
bit 07_86
@ -426,7 +421,6 @@ bit 08_07
bit 08_08
bit 08_09
bit 08_10
bit 08_11
bit 08_12
bit 08_13
bit 08_14
@ -434,6 +428,7 @@ bit 08_15
bit 08_16
bit 08_17
bit 08_18
bit 08_19
bit 08_20
bit 08_22
bit 08_23
@ -441,6 +436,7 @@ bit 08_24
bit 08_25
bit 08_26
bit 08_28
bit 08_29
bit 08_30
bit 08_31
bit 08_32
@ -461,7 +457,6 @@ bit 08_49
bit 08_50
bit 08_51
bit 08_52
bit 08_53
bit 08_54
bit 08_55
bit 08_56
@ -497,7 +492,9 @@ bit 08_87
bit 08_88
bit 08_89
bit 08_90
bit 08_91
bit 08_92
bit 08_93
bit 08_94
bit 08_95
bit 08_96
@ -569,7 +566,6 @@ bit 09_49
bit 09_50
bit 09_51
bit 09_52
bit 09_56
bit 09_57
bit 09_58
bit 09_59
@ -590,7 +586,6 @@ bit 09_75
bit 09_76
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
@ -600,10 +595,10 @@ bit 09_91
bit 09_92
bit 09_93
bit 09_94
bit 09_96
bit 09_98
bit 09_99
bit 09_100
bit 09_105
bit 09_106
bit 09_107
bit 09_108
@ -641,6 +636,7 @@ bit 10_17
bit 10_18
bit 10_19
bit 10_20
bit 10_21
bit 10_22
bit 10_23
bit 10_24
@ -656,7 +652,6 @@ bit 10_33
bit 10_34
bit 10_35
bit 10_36
bit 10_37
bit 10_39
bit 10_41
bit 10_42
@ -672,9 +667,7 @@ bit 10_54
bit 10_55
bit 10_57
bit 10_58
bit 10_60
bit 10_61
bit 10_62
bit 10_63
bit 10_64
bit 10_65
@ -710,7 +703,6 @@ bit 10_96
bit 10_97
bit 10_98
bit 10_99
bit 10_100
bit 10_101
bit 10_103
bit 10_104
@ -726,7 +718,6 @@ bit 10_119
bit 10_120
bit 10_121
bit 10_122
bit 10_124
bit 10_125
bit 10_127
bit 11_01
@ -744,7 +735,6 @@ bit 11_16
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_22
bit 11_23
bit 11_25
@ -784,13 +774,11 @@ bit 11_66
bit 11_67
bit 11_69
bit 11_71
bit 11_72
bit 11_73
bit 11_74
bit 11_75
bit 11_77
bit 11_79
bit 11_80
bit 11_81
bit 11_82
bit 11_83
@ -798,7 +786,6 @@ bit 11_87
bit 11_89
bit 11_90
bit 11_91
bit 11_92
bit 11_93
bit 11_95
bit 11_96
@ -833,7 +820,6 @@ bit 12_04
bit 12_05
bit 12_06
bit 12_07
bit 12_08
bit 12_09
bit 12_10
bit 12_11
@ -843,6 +829,7 @@ bit 12_15
bit 12_16
bit 12_17
bit 12_19
bit 12_21
bit 12_22
bit 12_23
bit 12_25
@ -856,7 +843,6 @@ bit 12_32
bit 12_33
bit 12_34
bit 12_35
bit 12_37
bit 12_39
bit 12_41
bit 12_42
@ -869,7 +855,6 @@ bit 12_48
bit 12_49
bit 12_50
bit 12_51
bit 12_52
bit 12_53
bit 12_54
bit 12_55
@ -890,7 +875,6 @@ bit 12_71
bit 12_73
bit 12_74
bit 12_75
bit 12_76
bit 12_77
bit 12_78
bit 12_79
@ -899,6 +883,7 @@ bit 12_82
bit 12_83
bit 12_86
bit 12_87
bit 12_88
bit 12_89
bit 12_90
bit 12_91
@ -909,9 +894,9 @@ bit 12_96
bit 12_97
bit 12_98
bit 12_99
bit 12_100
bit 12_101
bit 12_103
bit 12_104
bit 12_105
bit 12_106
bit 12_107
@ -958,6 +943,7 @@ bit 13_25
bit 13_26
bit 13_27
bit 13_28
bit 13_29
bit 13_30
bit 13_31
bit 13_32
@ -966,6 +952,7 @@ bit 13_34
bit 13_35
bit 13_36
bit 13_37
bit 13_38
bit 13_39
bit 13_41
bit 13_42
@ -992,7 +979,6 @@ bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
bit 13_71
bit 13_72
@ -1000,13 +986,13 @@ bit 13_73
bit 13_74
bit 13_75
bit 13_76
bit 13_77
bit 13_78
bit 13_79
bit 13_80
bit 13_81
bit 13_82
bit 13_83
bit 13_84
bit 13_86
bit 13_87
bit 13_88
@ -1027,7 +1013,6 @@ bit 13_103
bit 13_104
bit 13_105
bit 13_106
bit 13_107
bit 13_108
bit 13_109
bit 13_110
@ -1053,7 +1038,6 @@ bit 14_04
bit 14_05
bit 14_06
bit 14_07
bit 14_08
bit 14_09
bit 14_10
bit 14_11
@ -1062,6 +1046,7 @@ bit 14_13
bit 14_14
bit 14_15
bit 14_16
bit 14_17
bit 14_18
bit 14_19
bit 14_20
@ -1085,7 +1070,6 @@ bit 14_52
bit 14_54
bit 14_58
bit 14_60
bit 14_62
bit 14_64
bit 14_65
bit 14_66
@ -1102,7 +1086,6 @@ bit 14_77
bit 14_78
bit 14_79
bit 14_80
bit 14_81
bit 14_82
bit 14_83
bit 14_84
@ -1149,7 +1132,6 @@ bit 15_17
bit 15_18
bit 15_19
bit 15_20
bit 15_21
bit 15_22
bit 15_23
bit 15_24
@ -1170,7 +1152,6 @@ bit 15_45
bit 15_47
bit 15_49
bit 15_51
bit 15_53
bit 15_55
bit 15_57
bit 15_59
@ -1194,7 +1175,6 @@ bit 15_78
bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_83
bit 15_84
bit 15_85
@ -1218,7 +1198,6 @@ bit 15_109
bit 15_111
bit 15_113
bit 15_115
bit 15_117
bit 15_119
bit 15_121
bit 15_123
@ -1320,6 +1299,7 @@ bit 17_70
bit 17_71
bit 17_73
bit 17_79
bit 17_80
bit 17_85
bit 17_86
bit 17_87
@ -1348,16 +1328,13 @@ bit 18_03
bit 18_06
bit 18_07
bit 18_08
bit 18_09
bit 18_14
bit 18_17
bit 18_20
bit 18_22
bit 18_23
bit 18_25
bit 18_30
bit 18_31
bit 18_33
bit 18_34
bit 18_38
bit 18_39
@ -1429,7 +1406,6 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1440,7 +1416,6 @@ bit 19_67
bit 19_70
bit 19_71
bit 19_72
bit 19_73
bit 19_78
bit 19_81
bit 19_84
@ -1476,6 +1451,7 @@ bit 20_13
bit 20_21
bit 20_22
bit 20_30
bit 20_35
bit 20_38
bit 20_42
bit 20_43
@ -1516,6 +1492,7 @@ bit 21_20
bit 21_21
bit 21_22
bit 21_30
bit 21_31
bit 21_34
bit 21_35
bit 21_38
@ -1549,23 +1526,23 @@ bit 21_116
bit 21_118
bit 21_121
bit 21_122
bit 21_124
bit 21_126
bit 22_02
bit 22_06
bit 22_07
bit 22_09
bit 22_15
bit 22_16
bit 22_21
bit 22_22
bit 22_23
bit 22_24
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_39
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1574,7 +1551,6 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1585,17 +1561,14 @@ bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_80
bit 22_85
bit 22_86
bit 22_87
bit 22_88
bit 22_94
bit 22_95
bit 22_96
bit 22_99
bit 22_102
bit 22_103
bit 22_106
bit 22_107
bit 22_108
@ -1673,7 +1646,6 @@ bit 24_02
bit 24_05
bit 24_06
bit 24_07
bit 24_08
bit 24_09
bit 24_13
bit 24_15
@ -1767,7 +1739,6 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58
@ -1776,7 +1747,6 @@ bit 25_62
bit 25_66
bit 25_70
bit 25_71
bit 25_72
bit 25_73
bit 25_79
bit 25_80

116
artix7/mask_riob33.db
View File

@ -50,11 +50,11 @@ bit 01_40
bit 01_41
bit 01_42
bit 01_44
bit 01_45
bit 01_50
bit 01_52
bit 01_58
bit 01_64
bit 01_65
bit 01_66
bit 01_68
bit 01_69
@ -70,14 +70,11 @@ bit 01_101
bit 01_102
bit 01_104
bit 01_105
bit 01_106
bit 01_114
bit 01_116
bit 02_02
bit 02_05
bit 02_06
bit 02_07
bit 02_09
bit 02_10
bit 02_11
bit 02_13
bit 02_14
@ -86,21 +83,24 @@ bit 02_18
bit 02_22
bit 02_23
bit 02_30
bit 02_31
bit 02_34
bit 02_35
bit 02_38
bit 02_39
bit 02_46
bit 02_47
bit 02_50
bit 02_51
bit 02_54
bit 02_55
bit 02_62
bit 02_63
bit 02_67
bit 02_69
bit 02_70
bit 02_71
bit 02_74
bit 02_73
bit 02_75
bit 02_77
bit 02_78
bit 02_79
@ -110,15 +110,17 @@ bit 02_87
bit 02_94
bit 02_95
bit 02_98
bit 02_99
bit 02_102
bit 02_103
bit 02_114
bit 02_117
bit 02_115
bit 02_118
bit 02_119
bit 02_126
bit 02_127
bit 03_02
bit 03_05
bit 03_06
bit 03_10
bit 03_13
@ -127,11 +129,10 @@ bit 03_21
bit 03_29
bit 03_36
bit 03_37
bit 03_38
bit 03_45
bit 03_52
bit 03_53
bit 03_54
bit 03_60
bit 03_61
bit 03_62
bit 03_66
@ -144,15 +145,13 @@ bit 03_78
bit 03_86
bit 03_93
bit 03_102
bit 03_109
bit 03_116
bit 03_117
bit 03_118
bit 03_126
bit 04_04
bit 04_05
bit 04_06
bit 04_07
bit 04_10
bit 04_11
bit 04_12
bit 04_14
@ -172,6 +171,7 @@ bit 04_37
bit 04_39
bit 04_44
bit 04_47
bit 04_48
bit 04_51
bit 04_52
bit 04_53
@ -181,12 +181,10 @@ bit 04_66
bit 04_68
bit 04_69
bit 04_70
bit 04_71
bit 04_74
bit 04_75
bit 04_76
bit 04_78
bit 04_79
bit 04_83
bit 04_84
bit 04_85
bit 04_86
@ -200,6 +198,7 @@ bit 04_115
bit 04_116
bit 04_117
bit 04_119
bit 04_124
bit 05_01
bit 05_02
bit 05_05
@ -220,18 +219,19 @@ bit 05_34
bit 05_36
bit 05_37
bit 05_38
bit 05_44
bit 05_46
bit 05_49
bit 05_50
bit 05_52
bit 05_53
bit 05_54
bit 05_58
bit 05_60
bit 05_62
bit 05_63
bit 05_65
bit 05_66
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
@ -240,17 +240,16 @@ bit 05_81
bit 05_82
bit 05_86
bit 05_89
bit 05_90
bit 05_94
bit 05_98
bit 05_101
bit 05_102
bit 05_108
bit 05_113
bit 05_114
bit 05_116
bit 05_117
bit 05_118
bit 05_119
bit 05_126
bit 06_01
bit 06_02
bit 06_03
@ -258,15 +257,15 @@ bit 06_04
bit 06_05
bit 06_06
bit 06_10
bit 06_11
bit 06_12
bit 06_13
bit 06_14
bit 06_15
bit 06_17
bit 06_20
bit 06_21
bit 06_22
bit 06_24
bit 06_27
bit 06_28
bit 06_29
bit 06_30
@ -275,6 +274,7 @@ bit 06_33
bit 06_35
bit 06_36
bit 06_37
bit 06_39
bit 06_43
bit 06_46
bit 06_49
@ -303,11 +303,11 @@ bit 06_79
bit 06_81
bit 06_83
bit 06_84
bit 06_85
bit 06_86
bit 06_89
bit 06_91
bit 06_92
bit 06_93
bit 06_94
bit 06_97
bit 06_99
@ -317,6 +317,7 @@ bit 06_107
bit 06_113
bit 06_115
bit 06_116
bit 06_117
bit 06_119
bit 06_121
bit 06_123
@ -336,11 +337,9 @@ bit 07_14
bit 07_15
bit 07_16
bit 07_19
bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_25
bit 07_26
bit 07_27
bit 07_28
@ -366,7 +365,6 @@ bit 07_54
bit 07_55
bit 07_56
bit 07_58
bit 07_59
bit 07_60
bit 07_62
bit 07_63
@ -378,15 +376,12 @@ bit 07_69
bit 07_70
bit 07_71
bit 07_72
bit 07_73
bit 07_74
bit 07_75
bit 07_76
bit 07_77
bit 07_78
bit 07_79
bit 07_80
bit 07_82
bit 07_83
bit 07_84
bit 07_86
@ -426,7 +421,6 @@ bit 08_07
bit 08_08
bit 08_09
bit 08_10
bit 08_11
bit 08_12
bit 08_13
bit 08_14
@ -434,6 +428,7 @@ bit 08_15
bit 08_16
bit 08_17
bit 08_18
bit 08_19
bit 08_20
bit 08_22
bit 08_23
@ -441,6 +436,7 @@ bit 08_24
bit 08_25
bit 08_26
bit 08_28
bit 08_29
bit 08_30
bit 08_31
bit 08_32
@ -461,7 +457,6 @@ bit 08_49
bit 08_50
bit 08_51
bit 08_52
bit 08_53
bit 08_54
bit 08_55
bit 08_56
@ -497,7 +492,9 @@ bit 08_87
bit 08_88
bit 08_89
bit 08_90
bit 08_91
bit 08_92
bit 08_93
bit 08_94
bit 08_95
bit 08_96
@ -569,7 +566,6 @@ bit 09_49
bit 09_50
bit 09_51
bit 09_52
bit 09_56
bit 09_57
bit 09_58
bit 09_59
@ -590,7 +586,6 @@ bit 09_75
bit 09_76
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
@ -600,10 +595,10 @@ bit 09_91
bit 09_92
bit 09_93
bit 09_94
bit 09_96
bit 09_98
bit 09_99
bit 09_100
bit 09_105
bit 09_106
bit 09_107
bit 09_108
@ -641,6 +636,7 @@ bit 10_17
bit 10_18
bit 10_19
bit 10_20
bit 10_21
bit 10_22
bit 10_23
bit 10_24
@ -656,7 +652,6 @@ bit 10_33
bit 10_34
bit 10_35
bit 10_36
bit 10_37
bit 10_39
bit 10_41
bit 10_42
@ -672,9 +667,7 @@ bit 10_54
bit 10_55
bit 10_57
bit 10_58
bit 10_60
bit 10_61
bit 10_62
bit 10_63
bit 10_64
bit 10_65
@ -710,7 +703,6 @@ bit 10_96
bit 10_97
bit 10_98
bit 10_99
bit 10_100
bit 10_101
bit 10_103
bit 10_104
@ -726,7 +718,6 @@ bit 10_119
bit 10_120
bit 10_121
bit 10_122
bit 10_124
bit 10_125
bit 10_127
bit 11_01
@ -744,7 +735,6 @@ bit 11_16
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_22
bit 11_23
bit 11_25
@ -784,13 +774,11 @@ bit 11_66
bit 11_67
bit 11_69
bit 11_71
bit 11_72
bit 11_73
bit 11_74
bit 11_75
bit 11_77
bit 11_79
bit 11_80
bit 11_81
bit 11_82
bit 11_83
@ -798,7 +786,6 @@ bit 11_87
bit 11_89
bit 11_90
bit 11_91
bit 11_92
bit 11_93
bit 11_95
bit 11_96
@ -833,7 +820,6 @@ bit 12_04
bit 12_05
bit 12_06
bit 12_07
bit 12_08
bit 12_09
bit 12_10
bit 12_11
@ -843,6 +829,7 @@ bit 12_15
bit 12_16
bit 12_17
bit 12_19
bit 12_21
bit 12_22
bit 12_23
bit 12_25
@ -856,7 +843,6 @@ bit 12_32
bit 12_33
bit 12_34
bit 12_35
bit 12_37
bit 12_39
bit 12_41
bit 12_42
@ -869,7 +855,6 @@ bit 12_48
bit 12_49
bit 12_50
bit 12_51
bit 12_52
bit 12_53
bit 12_54
bit 12_55
@ -890,7 +875,6 @@ bit 12_71
bit 12_73
bit 12_74
bit 12_75
bit 12_76
bit 12_77
bit 12_78
bit 12_79
@ -899,6 +883,7 @@ bit 12_82
bit 12_83
bit 12_86
bit 12_87
bit 12_88
bit 12_89
bit 12_90
bit 12_91
@ -909,9 +894,9 @@ bit 12_96
bit 12_97
bit 12_98
bit 12_99
bit 12_100
bit 12_101
bit 12_103
bit 12_104
bit 12_105
bit 12_106
bit 12_107
@ -958,6 +943,7 @@ bit 13_25
bit 13_26
bit 13_27
bit 13_28
bit 13_29
bit 13_30
bit 13_31
bit 13_32
@ -966,6 +952,7 @@ bit 13_34
bit 13_35
bit 13_36
bit 13_37
bit 13_38
bit 13_39
bit 13_41
bit 13_42
@ -992,7 +979,6 @@ bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
bit 13_71
bit 13_72
@ -1000,13 +986,13 @@ bit 13_73
bit 13_74
bit 13_75
bit 13_76
bit 13_77
bit 13_78
bit 13_79
bit 13_80
bit 13_81
bit 13_82
bit 13_83
bit 13_84
bit 13_86
bit 13_87
bit 13_88
@ -1027,7 +1013,6 @@ bit 13_103
bit 13_104
bit 13_105
bit 13_106
bit 13_107
bit 13_108
bit 13_109
bit 13_110
@ -1053,7 +1038,6 @@ bit 14_04
bit 14_05
bit 14_06
bit 14_07
bit 14_08
bit 14_09
bit 14_10
bit 14_11
@ -1062,6 +1046,7 @@ bit 14_13
bit 14_14
bit 14_15
bit 14_16
bit 14_17
bit 14_18
bit 14_19
bit 14_20
@ -1085,7 +1070,6 @@ bit 14_52
bit 14_54
bit 14_58
bit 14_60
bit 14_62
bit 14_64
bit 14_65
bit 14_66
@ -1102,7 +1086,6 @@ bit 14_77
bit 14_78
bit 14_79
bit 14_80
bit 14_81
bit 14_82
bit 14_83
bit 14_84
@ -1149,7 +1132,6 @@ bit 15_17
bit 15_18
bit 15_19
bit 15_20
bit 15_21
bit 15_22
bit 15_23
bit 15_24
@ -1170,7 +1152,6 @@ bit 15_45
bit 15_47
bit 15_49
bit 15_51
bit 15_53
bit 15_55
bit 15_57
bit 15_59
@ -1194,7 +1175,6 @@ bit 15_78
bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_83
bit 15_84
bit 15_85
@ -1218,7 +1198,6 @@ bit 15_109
bit 15_111
bit 15_113
bit 15_115
bit 15_117
bit 15_119
bit 15_121
bit 15_123
@ -1320,6 +1299,7 @@ bit 17_70
bit 17_71
bit 17_73
bit 17_79
bit 17_80
bit 17_85
bit 17_86
bit 17_87
@ -1348,16 +1328,13 @@ bit 18_03
bit 18_06
bit 18_07
bit 18_08
bit 18_09
bit 18_14
bit 18_17
bit 18_20
bit 18_22
bit 18_23
bit 18_25
bit 18_30
bit 18_31
bit 18_33
bit 18_34
bit 18_38
bit 18_39
@ -1429,7 +1406,6 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1440,7 +1416,6 @@ bit 19_67
bit 19_70
bit 19_71
bit 19_72
bit 19_73
bit 19_78
bit 19_81
bit 19_84
@ -1476,6 +1451,7 @@ bit 20_13
bit 20_21
bit 20_22
bit 20_30
bit 20_35
bit 20_38
bit 20_42
bit 20_43
@ -1516,6 +1492,7 @@ bit 21_20
bit 21_21
bit 21_22
bit 21_30
bit 21_31
bit 21_34
bit 21_35
bit 21_38
@ -1549,23 +1526,23 @@ bit 21_116
bit 21_118
bit 21_121
bit 21_122
bit 21_124
bit 21_126
bit 22_02
bit 22_06
bit 22_07
bit 22_09
bit 22_15
bit 22_16
bit 22_21
bit 22_22
bit 22_23
bit 22_24
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_39
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1574,7 +1551,6 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1585,17 +1561,14 @@ bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_80
bit 22_85
bit 22_86
bit 22_87
bit 22_88
bit 22_94
bit 22_95
bit 22_96
bit 22_99
bit 22_102
bit 22_103
bit 22_106
bit 22_107
bit 22_108
@ -1673,7 +1646,6 @@ bit 24_02
bit 24_05
bit 24_06
bit 24_07
bit 24_08
bit 24_09
bit 24_13
bit 24_15
@ -1767,7 +1739,6 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58
@ -1776,7 +1747,6 @@ bit 25_62
bit 25_66
bit 25_70
bit 25_71
bit 25_72
bit 25_73
bit 25_79
bit 25_80

0
artix7/ppips_bram_int_interface_l.origin_info.db Normal file
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0
artix7/ppips_bram_int_interface_r.origin_info.db Normal file
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artix7/ppips_bram_l.origin_info.db Normal file
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artix7/ppips_bram_r.origin_info.db Normal file
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artix7/ppips_clbll_l.origin_info.db Normal file
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artix7/ppips_clbll_r.origin_info.db Normal file
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0
artix7/ppips_clblm_l.origin_info.db Normal file
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artix7/ppips_clblm_r.origin_info.db Normal file
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0
artix7/ppips_dsp_l.origin_info.db Normal file
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0
artix7/ppips_dsp_r.origin_info.db Normal file
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0
artix7/ppips_hclk_l.origin_info.db Normal file
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0
artix7/ppips_hclk_r.origin_info.db Normal file
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0
artix7/ppips_int_l.origin_info.db Normal file
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0
artix7/ppips_int_r.origin_info.db Normal file
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2
artix7/segbits_clbll_l.db
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@ -328,6 +328,7 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.NOCLKINV !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
@ -667,6 +668,7 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.NOCLKINV !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13

2
artix7/segbits_clbll_l.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_L.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_L.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
@ -671,6 +672,7 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11

2
artix7/segbits_clbll_r.db
View File

@ -328,6 +328,7 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.NOCLKINV !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
@ -667,6 +668,7 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.NOCLKINV !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13

2
artix7/segbits_clbll_r.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_R.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_R.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
@ -671,6 +672,7 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11

5
artix7/segbits_clblm_l.db
View File

@ -328,6 +328,7 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.NOCLKINV !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
@ -350,6 +351,7 @@ CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
@ -436,6 +438,7 @@ CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
@ -524,6 +527,7 @@ CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
@ -682,6 +686,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.NOCLKINV !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14

5
artix7/segbits_clblm_l.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
@ -350,6 +351,7 @@ CLBLM_L.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
@ -436,6 +438,7 @@ CLBLM_L.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
@ -528,6 +531,7 @@ CLBLM_L.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
@ -686,6 +690,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_L.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_L.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12

5
artix7/segbits_clblm_r.db
View File

@ -328,6 +328,7 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.NOCLKINV !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
@ -350,6 +351,7 @@ CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
@ -436,6 +438,7 @@ CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
@ -524,6 +527,7 @@ CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
@ -682,6 +686,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.NOCLKINV !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14

5
artix7/segbits_clblm_r.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
@ -350,6 +351,7 @@ CLBLM_R.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
@ -436,6 +438,7 @@ CLBLM_R.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
@ -528,6 +531,7 @@ CLBLM_R.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
@ -686,6 +690,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_R.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_R.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12

2700
artix7/segbits_clk_hrow_bot_r.origin_info.db
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2732
artix7/segbits_clk_hrow_top_r.origin_info.db
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File diff suppressed because it is too large Load Diff

320
artix7/segbits_int_l.origin_info.db
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@ -6,9 +6,9 @@ INT_L.BYP_ALT0.ER1END0 origin:050-pip-seed !22_07 17_07 23_07 24_07 25_07
INT_L.BYP_ALT0.FAN_BOUNCE2 origin:050-pip-seed !22_07 21_07 23_07 24_07 25_07
INT_L.BYP_ALT0.FAN_BOUNCE7 origin:050-pip-seed !23_07 21_07 22_07 24_07 25_07
INT_L.BYP_ALT0.GFAN0 origin:054-pip-fan-alt !22_07 !23_07 !25_07 20_07 24_07
INT_L.BYP_ALT0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_07 20_07 23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_07 20_07 22_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_07 !23_07 !24_07 20_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_L.BYP_ALT0.NE2END0 origin:050-pip-seed !22_07 !23_07 !24_07 19_06 25_07
INT_L.BYP_ALT0.NL1END0 origin:050-pip-seed !23_07 18_06 22_07 24_07 25_07
INT_L.BYP_ALT0.NN2END0 origin:050-pip-seed !22_07 !23_07 !25_07 19_06 24_07
@ -30,9 +30,9 @@ INT_L.BYP_ALT1.ER1END0 origin:050-pip-seed !22_15 16_15 23_15 24_15 25_15
INT_L.BYP_ALT1.FAN_BOUNCE5 origin:050-pip-seed !23_15 21_15 22_15 24_15 25_15
INT_L.BYP_ALT1.FAN_BOUNCE6 origin:050-pip-seed !22_15 21_15 23_15 24_15 25_15
INT_L.BYP_ALT1.GFAN0 origin:054-pip-fan-alt !22_15 !23_15 !25_15 20_15 24_15
INT_L.BYP_ALT1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_15 !23_15 !24_15 20_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_15 20_15 23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_15 20_15 22_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_L.BYP_ALT1.NE2END1 origin:050-pip-seed !22_15 !23_15 !24_15 16_15 25_15
INT_L.BYP_ALT1.NL1END1 origin:050-pip-seed !23_15 18_14 22_15 24_15 25_15
INT_L.BYP_ALT1.NN2END1 origin:050-pip-seed !22_15 !23_15 !25_15 16_15 24_15
@ -54,9 +54,9 @@ INT_L.BYP_ALT2.ER1END2 origin:050-pip-seed !22_39 17_39 23_39 24_39 25_39
INT_L.BYP_ALT2.FAN_BOUNCE1 origin:050-pip-seed !23_39 21_39 22_39 24_39 25_39
INT_L.BYP_ALT2.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_39 21_39 23_39 24_39 25_39
INT_L.BYP_ALT2.GFAN1 origin:054-pip-fan-alt !22_39 !23_39 !25_39 20_39 24_39
INT_L.BYP_ALT2.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_39 20_39 22_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_39 20_39 23_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_39 !23_39 !24_39 20_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_L.BYP_ALT2.NE2END2 origin:050-pip-seed !22_39 !23_39 !24_39 19_38 25_39
INT_L.BYP_ALT2.NL1END2 origin:050-pip-seed !23_39 18_38 22_39 24_39 25_39
INT_L.BYP_ALT2.NN2END2 origin:050-pip-seed !22_39 !23_39 !25_39 19_38 24_39
@ -78,9 +78,9 @@ INT_L.BYP_ALT3.ER1END2 origin:050-pip-seed !22_47 16_47 23_47 24_47 25_47
INT_L.BYP_ALT3.FAN_BOUNCE3 origin:050-pip-seed !23_47 21_47 22_47 24_47 25_47
INT_L.BYP_ALT3.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_47 21_47 23_47 24_47 25_47
INT_L.BYP_ALT3.GFAN1 origin:054-pip-fan-alt !22_47 !23_47 !25_47 20_47 24_47
INT_L.BYP_ALT3.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_47 20_47 22_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_47 !23_47 !24_47 20_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_47 20_47 23_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_L.BYP_ALT3.NE2END3 origin:050-pip-seed !22_47 !23_47 !24_47 16_47 25_47
INT_L.BYP_ALT3.NL1BEG_N3 origin:050-pip-seed !23_47 18_46 22_47 24_47 25_47
INT_L.BYP_ALT3.NN2END3 origin:050-pip-seed !22_47 !23_47 !25_47 16_47 24_47
@ -102,9 +102,9 @@ INT_L.BYP_ALT4.ER1END1 origin:050-pip-seed !22_23 17_23 23_23 24_23 25_23
INT_L.BYP_ALT4.FAN_BOUNCE1 origin:050-pip-seed !23_23 21_23 22_23 24_23 25_23
INT_L.BYP_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_23 21_23 23_23 24_23 25_23
INT_L.BYP_ALT4.GFAN0 origin:054-pip-fan-alt !22_23 !23_23 !25_23 20_23 24_23
INT_L.BYP_ALT4.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_23 !23_23 !24_23 20_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_23 20_23 23_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_23 20_23 22_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_L.BYP_ALT4.NE2END1 origin:050-pip-seed !22_23 !23_23 !24_23 19_22 25_23
INT_L.BYP_ALT4.NL1END1 origin:050-pip-seed !23_23 18_22 22_23 24_23 25_23
INT_L.BYP_ALT4.NN2END1 origin:050-pip-seed !22_23 !23_23 !25_23 19_22 24_23
@ -126,9 +126,9 @@ INT_L.BYP_ALT5.ER1END1 origin:050-pip-seed !22_31 16_31 23_31 24_31 25_31
INT_L.BYP_ALT5.FAN_BOUNCE3 origin:050-pip-seed !23_31 21_31 22_31 24_31 25_31
INT_L.BYP_ALT5.FAN_BOUNCE5 origin:050-pip-seed !22_31 21_31 23_31 24_31 25_31
INT_L.BYP_ALT5.GFAN0 origin:054-pip-fan-alt !22_31 !23_31 !25_31 20_31 24_31
INT_L.BYP_ALT5.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_31 20_31 23_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_31 20_31 22_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_31 !23_31 !24_31 20_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_L.BYP_ALT5.NE2END2 origin:050-pip-seed !22_31 !23_31 !24_31 16_31 25_31
INT_L.BYP_ALT5.NL1END2 origin:050-pip-seed !23_31 18_30 22_31 24_31 25_31
INT_L.BYP_ALT5.NN2END2 origin:050-pip-seed !22_31 !23_31 !25_31 16_31 24_31
@ -150,8 +150,8 @@ INT_L.BYP_ALT6.ER1END3 origin:050-pip-seed !22_55 17_55 23_55 24_55 25_55
INT_L.BYP_ALT6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_55 21_55 22_55 24_55 25_55
INT_L.BYP_ALT6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_55 21_55 23_55 24_55 25_55
INT_L.BYP_ALT6.GFAN1 origin:054-pip-fan-alt !22_55 !23_55 !25_55 20_55 24_55
INT_L.BYP_ALT6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_55 20_55 22_55 24_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_55 !23_55 !24_55 20_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_55 20_55 23_55 24_55 25_55
INT_L.BYP_ALT6.NE2END3 origin:050-pip-seed !22_55 !23_55 !24_55 19_54 25_55
INT_L.BYP_ALT6.NL1BEG_N3 origin:050-pip-seed !23_55 18_54 22_55 24_55 25_55
@ -174,8 +174,8 @@ INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_63 !23_63 !24_63 20_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_L.BYP_ALT7.NE2END_S3_0 origin:050-pip-seed !22_63 !23_63 !24_63 16_63 25_63
INT_L.BYP_ALT7.NL1END_S3_0 origin:050-pip-seed !23_63 18_62 22_63 24_63 25_63
@ -373,7 +373,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_L.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_L.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -584,7 +584,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
INT_L.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
INT_L.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
@ -676,9 +676,9 @@ INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_L.FAN_ALT4.NE2END0 origin:050-pip-seed !22_08 !23_08 !25_08 17_08 24_08
@ -806,9 +806,9 @@ INT_L.IMUX_L0.ER1END_N3_3 origin:050-pip-seed !22_01 18_00 23_01 24_01 25_01
INT_L.IMUX_L0.FAN_BOUNCE2 origin:050-pip-seed !22_01 21_01 23_01 24_01 25_01
INT_L.IMUX_L0.FAN_BOUNCE7 origin:050-pip-seed !23_01 21_01 22_01 24_01 25_01
INT_L.IMUX_L0.GFAN0 origin:049-int-imux-gfan !22_01 !23_01 !25_01 20_01 24_01
INT_L.IMUX_L0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_01 20_01 23_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_01 20_01 22_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_01 !23_01 !24_01 20_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_L.IMUX_L0.NE2END0 origin:050-pip-seed !22_01 !23_01 !24_01 16_01 25_01
INT_L.IMUX_L0.NL1END0 origin:050-pip-seed !23_01 17_01 22_01 24_01 25_01
INT_L.IMUX_L0.NN2END0 origin:050-pip-seed !22_01 !23_01 !25_01 16_01 24_01
@ -830,9 +830,9 @@ INT_L.IMUX_L1.ER1END0 origin:050-pip-seed !22_09 19_08 23_09 24_09 25_09
INT_L.IMUX_L1.FAN_BOUNCE5 origin:050-pip-seed !23_09 21_09 22_09 24_09 25_09
INT_L.IMUX_L1.FAN_BOUNCE6 origin:050-pip-seed !22_09 21_09 23_09 24_09 25_09
INT_L.IMUX_L1.GFAN0 origin:049-int-imux-gfan !22_09 !23_09 !25_09 20_09 24_09
INT_L.IMUX_L1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_09 !23_09 !24_09 20_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_09 20_09 23_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_09 20_09 22_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_L.IMUX_L1.NE2END0 origin:050-pip-seed !22_09 !23_09 !24_09 19_08 25_09
INT_L.IMUX_L1.NL1END1 origin:050-pip-seed !23_09 17_09 22_09 24_09 25_09
INT_L.IMUX_L1.NN2END0 origin:050-pip-seed !22_09 !23_09 !25_09 19_08 24_09
@ -854,9 +854,9 @@ INT_L.IMUX_L10.ER1END0 origin:050-pip-seed !23_18 17_18 22_18 24_18 25_18
INT_L.IMUX_L10.FAN_BOUNCE1 origin:050-pip-seed !22_18 20_18 23_18 24_18 25_18
INT_L.IMUX_L10.FAN_BOUNCE7 origin:050-pip-seed !23_18 20_18 22_18 24_18 25_18
INT_L.IMUX_L10.GFAN0 origin:049-int-imux-gfan !22_18 !23_18 !24_18 21_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_18 !23_18 !25_18 21_18 24_18
INT_L.IMUX_L10.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_18 21_18 22_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_18 21_18 23_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_L.IMUX_L10.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_L.IMUX_L10.NE2END1 origin:050-pip-seed !22_18 !23_18 !25_18 17_18 24_18
INT_L.IMUX_L10.NL1END1 origin:050-pip-seed !22_18 16_18 23_18 24_18 25_18
INT_L.IMUX_L10.NN2END1 origin:050-pip-seed !22_18 !23_18 !24_18 17_18 25_18
@ -878,9 +878,9 @@ INT_L.IMUX_L11.ER1END1 origin:050-pip-seed !23_26 18_27 22_26 24_26 25_26
INT_L.IMUX_L11.FAN_BOUNCE3 origin:050-pip-seed !22_26 20_26 23_26 24_26 25_26
INT_L.IMUX_L11.FAN_BOUNCE5 origin:050-pip-seed !23_26 20_26 22_26 24_26 25_26
INT_L.IMUX_L11.GFAN0 origin:049-int-imux-gfan !22_26 !23_26 !24_26 21_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_26 21_26 22_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_26 21_26 23_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_26 !23_26 !25_26 21_26 24_26
INT_L.IMUX_L11.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_L.IMUX_L11.NE2END1 origin:050-pip-seed !22_26 !23_26 !25_26 16_26 24_26
INT_L.IMUX_L11.NL1END2 origin:050-pip-seed !22_26 16_26 23_26 24_26 25_26
INT_L.IMUX_L11.NN2END1 origin:050-pip-seed !22_26 !23_26 !24_26 16_26 25_26
@ -902,9 +902,9 @@ INT_L.IMUX_L12.ER1END1 origin:050-pip-seed !23_34 17_34 22_34 24_34 25_34
INT_L.IMUX_L12.FAN_BOUNCE1 origin:050-pip-seed !22_34 20_34 23_34 24_34 25_34
INT_L.IMUX_L12.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_34 20_34 22_34 24_34 25_34
INT_L.IMUX_L12.GFAN1 origin:049-int-imux-gfan !22_34 !23_34 !24_34 21_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_34 21_34 23_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_34 21_34 22_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_34 !23_34 !25_34 21_34 24_34
INT_L.IMUX_L12.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_L.IMUX_L12.NE2END2 origin:050-pip-seed !22_34 !23_34 !25_34 17_34 24_34
INT_L.IMUX_L12.NL1END2 origin:050-pip-seed !22_34 16_34 23_34 24_34 25_34
INT_L.IMUX_L12.NN2END2 origin:050-pip-seed !22_34 !23_34 !24_34 17_34 25_34
@ -926,9 +926,9 @@ INT_L.IMUX_L13.ER1END2 origin:050-pip-seed !23_42 18_43 22_42 24_42 25_42
INT_L.IMUX_L13.FAN_BOUNCE3 origin:050-pip-seed !22_42 20_42 23_42 24_42 25_42
INT_L.IMUX_L13.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_42 20_42 22_42 24_42 25_42
INT_L.IMUX_L13.GFAN1 origin:049-int-imux-gfan !22_42 !23_42 !24_42 21_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_42 21_42 23_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_42 !23_42 !25_42 21_42 24_42
INT_L.IMUX_L13.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_42 21_42 22_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_L.IMUX_L13.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_L.IMUX_L13.NE2END2 origin:050-pip-seed !22_42 !23_42 !25_42 16_42 24_42
INT_L.IMUX_L13.NL1BEG_N3 origin:050-pip-seed !22_42 16_42 23_42 24_42 25_42
INT_L.IMUX_L13.NN2END2 origin:050-pip-seed !22_42 !23_42 !24_42 16_42 25_42
@ -950,9 +950,9 @@ INT_L.IMUX_L14.ER1END2 origin:050-pip-seed !23_50 17_50 22_50 24_50 25_50
INT_L.IMUX_L14.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_50 20_50 23_50 24_50 25_50
INT_L.IMUX_L14.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_50 20_50 22_50 24_50 25_50
INT_L.IMUX_L14.GFAN1 origin:049-int-imux-gfan !22_50 !23_50 !24_50 21_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_50 21_50 23_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_50 !23_50 !25_50 21_50 24_50
INT_L.IMUX_L14.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_50 21_50 22_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_L.IMUX_L14.NE2END3 origin:050-pip-seed !22_50 !23_50 !25_50 17_50 24_50
INT_L.IMUX_L14.NL1BEG_N3 origin:050-pip-seed !22_50 16_50 23_50 24_50 25_50
INT_L.IMUX_L14.NN2END3 origin:050-pip-seed !22_50 !23_50 !24_50 17_50 25_50
@ -974,9 +974,9 @@ INT_L.IMUX_L15.ER1END3 origin:050-pip-seed !23_58 18_59 22_58 24_58 25_58
INT_L.IMUX_L15.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_58 20_58 23_58 24_58 25_58
INT_L.IMUX_L15.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_58 20_58 22_58 24_58 25_58
INT_L.IMUX_L15.GFAN1 origin:049-int-imux-gfan !22_58 !23_58 !24_58 21_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_58 21_58 23_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_58 !23_58 !25_58 21_58 24_58
INT_L.IMUX_L15.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_58 21_58 22_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_L.IMUX_L15.NE2END3 origin:050-pip-seed !22_58 !23_58 !25_58 16_58 24_58
INT_L.IMUX_L15.NL1END_S3_0 origin:050-pip-seed !22_58 16_58 23_58 24_58 25_58
INT_L.IMUX_L15.NN2END3 origin:050-pip-seed !22_58 !23_58 !24_58 16_58 25_58
@ -998,9 +998,9 @@ INT_L.IMUX_L16.ER1END_N3_3 origin:050-pip-seed !22_03 19_02 23_03 24_03 25_03
INT_L.IMUX_L16.FAN_BOUNCE2 origin:050-pip-seed !22_03 21_03 23_03 24_03 25_03
INT_L.IMUX_L16.FAN_BOUNCE7 origin:050-pip-seed !23_03 21_03 22_03 24_03 25_03
INT_L.IMUX_L16.GFAN0 origin:049-int-imux-gfan !22_03 !23_03 !25_03 20_03 24_03
INT_L.IMUX_L16.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_03 20_03 23_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_03 20_03 22_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_03 !23_03 !24_03 20_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_L.IMUX_L16.NE2END0 origin:050-pip-seed !22_03 !23_03 !24_03 19_02 25_03
INT_L.IMUX_L16.NL1END0 origin:050-pip-seed !23_03 18_02 22_03 24_03 25_03
INT_L.IMUX_L16.NN2END0 origin:050-pip-seed !22_03 !23_03 !25_03 19_02 24_03
@ -1022,9 +1022,9 @@ INT_L.IMUX_L17.ER1END0 origin:050-pip-seed !22_11 16_11 23_11 24_11 25_11
INT_L.IMUX_L17.FAN_BOUNCE5 origin:050-pip-seed !23_11 21_11 22_11 24_11 25_11
INT_L.IMUX_L17.FAN_BOUNCE6 origin:050-pip-seed !22_11 21_11 23_11 24_11 25_11
INT_L.IMUX_L17.GFAN0 origin:049-int-imux-gfan !22_11 !23_11 !25_11 20_11 24_11
INT_L.IMUX_L17.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_11 !23_11 !24_11 20_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_11 20_11 23_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_11 20_11 22_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_L.IMUX_L17.NE2END0 origin:050-pip-seed !22_11 !23_11 !24_11 18_10 25_11
INT_L.IMUX_L17.NL1END1 origin:050-pip-seed !23_11 18_10 22_11 24_11 25_11
INT_L.IMUX_L17.NN2END0 origin:050-pip-seed !22_11 !23_11 !25_11 18_10 24_11
@ -1046,9 +1046,9 @@ INT_L.IMUX_L18.ER1END0 origin:050-pip-seed !22_19 19_18 23_19 24_19 25_19
INT_L.IMUX_L18.FAN_BOUNCE1 origin:050-pip-seed !23_19 21_19 22_19 24_19 25_19
INT_L.IMUX_L18.FAN_BOUNCE7 origin:050-pip-seed !22_19 21_19 23_19 24_19 25_19
INT_L.IMUX_L18.GFAN0 origin:049-int-imux-gfan !22_19 !23_19 !25_19 20_19 24_19
INT_L.IMUX_L18.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_19 !23_19 !24_19 20_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_19 20_19 23_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_19 20_19 22_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_L.IMUX_L18.NE2END1 origin:050-pip-seed !22_19 !23_19 !24_19 19_18 25_19
INT_L.IMUX_L18.NL1END1 origin:050-pip-seed !23_19 18_18 22_19 24_19 25_19
INT_L.IMUX_L18.NN2END1 origin:050-pip-seed !22_19 !23_19 !25_19 19_18 24_19
@ -1070,9 +1070,9 @@ INT_L.IMUX_L19.ER1END1 origin:050-pip-seed !22_27 16_27 23_27 24_27 25_27
INT_L.IMUX_L19.FAN_BOUNCE3 origin:050-pip-seed !23_27 21_27 22_27 24_27 25_27
INT_L.IMUX_L19.FAN_BOUNCE5 origin:050-pip-seed !22_27 21_27 23_27 24_27 25_27
INT_L.IMUX_L19.GFAN0 origin:049-int-imux-gfan !22_27 !23_27 !25_27 20_27 24_27
INT_L.IMUX_L19.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_27 20_27 23_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_27 20_27 22_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_27 !23_27 !24_27 20_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_L.IMUX_L19.NE2END1 origin:050-pip-seed !22_27 !23_27 !24_27 18_26 25_27
INT_L.IMUX_L19.NL1END2 origin:050-pip-seed !23_27 18_26 22_27 24_27 25_27
INT_L.IMUX_L19.NN2END1 origin:050-pip-seed !22_27 !23_27 !25_27 18_26 24_27
@ -1094,9 +1094,9 @@ INT_L.IMUX_L2.ER1END0 origin:050-pip-seed !22_17 18_16 23_17 24_17 25_17
INT_L.IMUX_L2.FAN_BOUNCE1 origin:050-pip-seed !23_17 21_17 22_17 24_17 25_17
INT_L.IMUX_L2.FAN_BOUNCE7 origin:050-pip-seed !22_17 21_17 23_17 24_17 25_17
INT_L.IMUX_L2.GFAN0 origin:049-int-imux-gfan !22_17 !23_17 !25_17 20_17 24_17
INT_L.IMUX_L2.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_17 !23_17 !24_17 20_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_17 20_17 23_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_17 20_17 22_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_L.IMUX_L2.NE2END1 origin:050-pip-seed !22_17 !23_17 !24_17 16_17 25_17
INT_L.IMUX_L2.NL1END1 origin:050-pip-seed !23_17 17_17 22_17 24_17 25_17
INT_L.IMUX_L2.NN2END1 origin:050-pip-seed !22_17 !23_17 !25_17 16_17 24_17
@ -1118,9 +1118,9 @@ INT_L.IMUX_L20.ER1END1 origin:050-pip-seed !22_35 19_34 23_35 24_35 25_35
INT_L.IMUX_L20.FAN_BOUNCE1 origin:050-pip-seed !23_35 21_35 22_35 24_35 25_35
INT_L.IMUX_L20.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_35 21_35 23_35 24_35 25_35
INT_L.IMUX_L20.GFAN1 origin:049-int-imux-gfan !22_35 !23_35 !25_35 20_35 24_35
INT_L.IMUX_L20.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_35 20_35 22_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_35 20_35 23_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_35 !23_35 !24_35 20_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_L.IMUX_L20.NE2END2 origin:050-pip-seed !22_35 !23_35 !24_35 19_34 25_35
INT_L.IMUX_L20.NL1END2 origin:050-pip-seed !23_35 18_34 22_35 24_35 25_35
INT_L.IMUX_L20.NN2END2 origin:050-pip-seed !22_35 !23_35 !25_35 19_34 24_35
@ -1143,8 +1143,8 @@ INT_L.IMUX_L21.FAN_BOUNCE3 origin:050-pip-seed !23_43 21_43 22_43 24_43 25_43
INT_L.IMUX_L21.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_43 21_43 23_43 24_43 25_43
INT_L.IMUX_L21.GFAN1 origin:049-int-imux-gfan !22_43 !23_43 !25_43 20_43 24_43
INT_L.IMUX_L21.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_43 20_43 22_43 24_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_43 !23_43 !24_43 20_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_43 20_43 23_43 24_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_L.IMUX_L21.NE2END2 origin:050-pip-seed !22_43 !23_43 !24_43 18_42 25_43
INT_L.IMUX_L21.NL1BEG_N3 origin:050-pip-seed !23_43 18_42 22_43 24_43 25_43
INT_L.IMUX_L21.NN2END2 origin:050-pip-seed !22_43 !23_43 !25_43 18_42 24_43
@ -1166,9 +1166,9 @@ INT_L.IMUX_L22.ER1END2 origin:050-pip-seed !22_51 19_50 23_51 24_51 25_51
INT_L.IMUX_L22.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_51 21_51 22_51 24_51 25_51
INT_L.IMUX_L22.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_51 21_51 23_51 24_51 25_51
INT_L.IMUX_L22.GFAN1 origin:049-int-imux-gfan !22_51 !23_51 !25_51 20_51 24_51
INT_L.IMUX_L22.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_51 20_51 22_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_51 !23_51 !24_51 20_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_51 20_51 23_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_L.IMUX_L22.NE2END3 origin:050-pip-seed !22_51 !23_51 !24_51 19_50 25_51
INT_L.IMUX_L22.NL1BEG_N3 origin:050-pip-seed !23_51 18_50 22_51 24_51 25_51
INT_L.IMUX_L22.NN2END3 origin:050-pip-seed !22_51 !23_51 !25_51 19_50 24_51
@ -1190,9 +1190,9 @@ INT_L.IMUX_L23.ER1END3 origin:050-pip-seed !22_59 16_59 23_59 24_59 25_59
INT_L.IMUX_L23.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_59 21_59 22_59 24_59 25_59
INT_L.IMUX_L23.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_59 21_59 23_59 24_59 25_59
INT_L.IMUX_L23.GFAN1 origin:049-int-imux-gfan !22_59 !23_59 !25_59 20_59 24_59
INT_L.IMUX_L23.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_59 20_59 22_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_59 !23_59 !24_59 20_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_59 20_59 23_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_L.IMUX_L23.NE2END3 origin:050-pip-seed !22_59 !23_59 !24_59 18_58 25_59
INT_L.IMUX_L23.NL1END_S3_0 origin:050-pip-seed !23_59 18_58 22_59 24_59 25_59
INT_L.IMUX_L23.NN2END3 origin:050-pip-seed !22_59 !23_59 !25_59 18_58 24_59
@ -1214,9 +1214,9 @@ INT_L.IMUX_L24.ER1END0 origin:050-pip-seed !23_04 18_05 22_04 24_04 25_04
INT_L.IMUX_L24.FAN_BOUNCE2 origin:050-pip-seed !23_04 20_04 22_04 24_04 25_04
INT_L.IMUX_L24.FAN_BOUNCE7 origin:050-pip-seed !22_04 20_04 23_04 24_04 25_04
INT_L.IMUX_L24.GFAN0 origin:049-int-imux-gfan !22_04 !23_04 !24_04 21_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_04 21_04 22_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_04 21_04 23_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_04 !23_04 !25_04 21_04 24_04
INT_L.IMUX_L24.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_L.IMUX_L24.NE2END0 origin:050-pip-seed !22_04 !23_04 !25_04 18_05 24_04
INT_L.IMUX_L24.NL1END0 origin:050-pip-seed !22_04 19_05 23_04 24_04 25_04
INT_L.IMUX_L24.NN2END0 origin:050-pip-seed !22_04 !23_04 !24_04 18_05 25_04
@ -1238,9 +1238,9 @@ INT_L.IMUX_L25.ER1END0 origin:050-pip-seed !23_12 17_12 22_12 24_12 25_12
INT_L.IMUX_L25.FAN_BOUNCE5 origin:050-pip-seed !22_12 20_12 23_12 24_12 25_12
INT_L.IMUX_L25.FAN_BOUNCE6 origin:050-pip-seed !23_12 20_12 22_12 24_12 25_12
INT_L.IMUX_L25.GFAN0 origin:049-int-imux-gfan !22_12 !23_12 !24_12 21_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_12 !23_12 !25_12 21_12 24_12
INT_L.IMUX_L25.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_12 21_12 22_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_12 21_12 23_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_L.IMUX_L25.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_L.IMUX_L25.NE2END1 origin:050-pip-seed !22_12 !23_12 !25_12 19_13 24_12
INT_L.IMUX_L25.NL1END1 origin:050-pip-seed !22_12 19_13 23_12 24_12 25_12
INT_L.IMUX_L25.NN2END1 origin:050-pip-seed !22_12 !23_12 !24_12 19_13 25_12
@ -1262,8 +1262,8 @@ INT_L.IMUX_L26.ER1END1 origin:050-pip-seed !23_20 18_21 22_20 24_20 25_20
INT_L.IMUX_L26.FAN_BOUNCE1 origin:050-pip-seed !22_20 20_20 23_20 24_20 25_20
INT_L.IMUX_L26.FAN_BOUNCE7 origin:050-pip-seed !23_20 20_20 22_20 24_20 25_20
INT_L.IMUX_L26.GFAN0 origin:049-int-imux-gfan !22_20 !23_20 !24_20 21_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_20 !23_20 !25_20 21_20 24_20
INT_L.IMUX_L26.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_20 21_20 22_20 24_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_L.IMUX_L26.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_20 21_20 23_20 24_20 25_20
INT_L.IMUX_L26.NE2END1 origin:050-pip-seed !22_20 !23_20 !25_20 18_21 24_20
INT_L.IMUX_L26.NL1END1 origin:050-pip-seed !22_20 19_21 23_20 24_20 25_20
@ -1286,9 +1286,9 @@ INT_L.IMUX_L27.ER1END1 origin:050-pip-seed !23_28 17_28 22_28 24_28 25_28
INT_L.IMUX_L27.FAN_BOUNCE3 origin:050-pip-seed !22_28 20_28 23_28 24_28 25_28
INT_L.IMUX_L27.FAN_BOUNCE5 origin:050-pip-seed !23_28 20_28 22_28 24_28 25_28
INT_L.IMUX_L27.GFAN0 origin:049-int-imux-gfan !22_28 !23_28 !24_28 21_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_28 21_28 22_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_28 21_28 23_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_28 !23_28 !25_28 21_28 24_28
INT_L.IMUX_L27.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_L.IMUX_L27.NE2END2 origin:050-pip-seed !22_28 !23_28 !25_28 19_29 24_28
INT_L.IMUX_L27.NL1END2 origin:050-pip-seed !22_28 19_29 23_28 24_28 25_28
INT_L.IMUX_L27.NN2END2 origin:050-pip-seed !22_28 !23_28 !24_28 19_29 25_28
@ -1311,8 +1311,8 @@ INT_L.IMUX_L28.FAN_BOUNCE1 origin:050-pip-seed !22_36 20_36 23_36 24_36 25_36
INT_L.IMUX_L28.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_36 20_36 22_36 24_36 25_36
INT_L.IMUX_L28.GFAN1 origin:049-int-imux-gfan !22_36 !23_36 !24_36 21_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_36 21_36 23_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_36 21_36 22_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_36 !23_36 !25_36 21_36 24_36
INT_L.IMUX_L28.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_L.IMUX_L28.NE2END2 origin:050-pip-seed !22_36 !23_36 !25_36 18_37 24_36
INT_L.IMUX_L28.NL1END2 origin:050-pip-seed !22_36 19_37 23_36 24_36 25_36
INT_L.IMUX_L28.NN2END2 origin:050-pip-seed !22_36 !23_36 !24_36 18_37 25_36
@ -1334,9 +1334,9 @@ INT_L.IMUX_L29.ER1END2 origin:050-pip-seed !23_44 17_44 22_44 24_44 25_44
INT_L.IMUX_L29.FAN_BOUNCE3 origin:050-pip-seed !22_44 20_44 23_44 24_44 25_44
INT_L.IMUX_L29.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_44 20_44 22_44 24_44 25_44
INT_L.IMUX_L29.GFAN1 origin:049-int-imux-gfan !22_44 !23_44 !24_44 21_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_44 21_44 23_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_44 !23_44 !25_44 21_44 24_44
INT_L.IMUX_L29.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_44 21_44 22_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_L.IMUX_L29.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_L.IMUX_L29.NE2END3 origin:050-pip-seed !22_44 !23_44 !25_44 19_45 24_44
INT_L.IMUX_L29.NL1BEG_N3 origin:050-pip-seed !22_44 19_45 23_44 24_44 25_44
INT_L.IMUX_L29.NN2END3 origin:050-pip-seed !22_44 !23_44 !24_44 19_45 25_44
@ -1358,9 +1358,9 @@ INT_L.IMUX_L3.ER1END1 origin:050-pip-seed !22_25 19_24 23_25 24_25 25_25
INT_L.IMUX_L3.FAN_BOUNCE3 origin:050-pip-seed !23_25 21_25 22_25 24_25 25_25
INT_L.IMUX_L3.FAN_BOUNCE5 origin:050-pip-seed !22_25 21_25 23_25 24_25 25_25
INT_L.IMUX_L3.GFAN0 origin:049-int-imux-gfan !22_25 !23_25 !25_25 20_25 24_25
INT_L.IMUX_L3.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_25 20_25 23_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_25 20_25 22_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_25 !23_25 !24_25 20_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_L.IMUX_L3.NE2END1 origin:050-pip-seed !22_25 !23_25 !24_25 19_24 25_25
INT_L.IMUX_L3.NL1END2 origin:050-pip-seed !23_25 17_25 22_25 24_25 25_25
INT_L.IMUX_L3.NN2END1 origin:050-pip-seed !22_25 !23_25 !25_25 19_24 24_25
@ -1382,9 +1382,9 @@ INT_L.IMUX_L30.ER1END3 origin:050-pip-seed !23_52 18_53 22_52 24_52 25_52
INT_L.IMUX_L30.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_52 20_52 23_52 24_52 25_52
INT_L.IMUX_L30.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_52 20_52 22_52 24_52 25_52
INT_L.IMUX_L30.GFAN1 origin:049-int-imux-gfan !22_52 !23_52 !24_52 21_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_52 21_52 23_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_52 !23_52 !25_52 21_52 24_52
INT_L.IMUX_L30.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_52 21_52 22_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_L.IMUX_L30.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_L.IMUX_L30.NE2END3 origin:050-pip-seed !22_52 !23_52 !25_52 18_53 24_52
INT_L.IMUX_L30.NL1BEG_N3 origin:050-pip-seed !22_52 19_53 23_52 24_52 25_52
INT_L.IMUX_L30.NN2END3 origin:050-pip-seed !22_52 !23_52 !24_52 18_53 25_52
@ -1406,9 +1406,9 @@ INT_L.IMUX_L31.ER1END3 origin:050-pip-seed !23_60 17_60 22_60 24_60 25_60
INT_L.IMUX_L31.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_60 20_60 23_60 24_60 25_60
INT_L.IMUX_L31.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_60 20_60 22_60 24_60 25_60
INT_L.IMUX_L31.GFAN1 origin:049-int-imux-gfan !22_60 !23_60 !24_60 21_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_60 21_60 23_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_60 !23_60 !25_60 21_60 24_60
INT_L.IMUX_L31.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_60 21_60 22_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_L.IMUX_L31.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_L.IMUX_L31.NE2END_S3_0 origin:050-pip-seed !22_60 !23_60 !25_60 19_61 24_60
INT_L.IMUX_L31.NL1END_S3_0 origin:050-pip-seed !22_60 19_61 23_60 24_60 25_60
INT_L.IMUX_L31.NN2END_S2_0 origin:050-pip-seed !22_60 !23_60 !24_60 19_61 25_60
@ -1430,8 +1430,8 @@ INT_L.IMUX_L32.ER1END0 origin:050-pip-seed !22_05 16_05 23_05 24_05 25_05
INT_L.IMUX_L32.FAN_BOUNCE2 origin:050-pip-seed !22_05 21_05 23_05 24_05 25_05
INT_L.IMUX_L32.FAN_BOUNCE7 origin:050-pip-seed !23_05 21_05 22_05 24_05 25_05
INT_L.IMUX_L32.GFAN0 origin:049-int-imux-gfan !22_05 !23_05 !25_05 20_05 24_05
INT_L.IMUX_L32.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_05 20_05 23_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_05 20_05 22_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_05 !23_05 !24_05 20_05 25_05
INT_L.IMUX_L32.NE2END0 origin:050-pip-seed !22_05 !23_05 !24_05 16_05 25_05
INT_L.IMUX_L32.NL1END0 origin:050-pip-seed !23_05 17_05 22_05 24_05 25_05
@ -1455,8 +1455,8 @@ INT_L.IMUX_L33.FAN_BOUNCE5 origin:050-pip-seed !23_13 21_13 22_13 24_13 25_13
INT_L.IMUX_L33.FAN_BOUNCE6 origin:050-pip-seed !22_13 21_13 23_13 24_13 25_13
INT_L.IMUX_L33.GFAN0 origin:049-int-imux-gfan !22_13 !23_13 !25_13 20_13 24_13
INT_L.IMUX_L33.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_13 !23_13 !24_13 20_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_13 20_13 23_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_13 20_13 22_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_L.IMUX_L33.NE2END1 origin:050-pip-seed !22_13 !23_13 !24_13 17_13 25_13
INT_L.IMUX_L33.NL1END1 origin:050-pip-seed !23_13 17_13 22_13 24_13 25_13
INT_L.IMUX_L33.NN2END1 origin:050-pip-seed !22_13 !23_13 !25_13 17_13 24_13
@ -1478,9 +1478,9 @@ INT_L.IMUX_L34.ER1END1 origin:050-pip-seed !22_21 16_21 23_21 24_21 25_21
INT_L.IMUX_L34.FAN_BOUNCE1 origin:050-pip-seed !23_21 21_21 22_21 24_21 25_21
INT_L.IMUX_L34.FAN_BOUNCE7 origin:050-pip-seed !22_21 21_21 23_21 24_21 25_21
INT_L.IMUX_L34.GFAN0 origin:049-int-imux-gfan !22_21 !23_21 !25_21 20_21 24_21
INT_L.IMUX_L34.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_21 !23_21 !24_21 20_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_21 20_21 23_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_21 20_21 22_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_L.IMUX_L34.NE2END1 origin:050-pip-seed !22_21 !23_21 !24_21 16_21 25_21
INT_L.IMUX_L34.NL1END1 origin:050-pip-seed !23_21 17_21 22_21 24_21 25_21
INT_L.IMUX_L34.NN2END1 origin:050-pip-seed !22_21 !23_21 !25_21 16_21 24_21
@ -1502,9 +1502,9 @@ INT_L.IMUX_L35.ER1END1 origin:050-pip-seed !22_29 19_28 23_29 24_29 25_29
INT_L.IMUX_L35.FAN_BOUNCE3 origin:050-pip-seed !23_29 21_29 22_29 24_29 25_29
INT_L.IMUX_L35.FAN_BOUNCE5 origin:050-pip-seed !22_29 21_29 23_29 24_29 25_29
INT_L.IMUX_L35.GFAN0 origin:049-int-imux-gfan !22_29 !23_29 !25_29 20_29 24_29
INT_L.IMUX_L35.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_29 20_29 23_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_29 20_29 22_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_29 !23_29 !24_29 20_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_L.IMUX_L35.NE2END2 origin:050-pip-seed !22_29 !23_29 !24_29 17_29 25_29
INT_L.IMUX_L35.NL1END2 origin:050-pip-seed !23_29 17_29 22_29 24_29 25_29
INT_L.IMUX_L35.NN2END2 origin:050-pip-seed !22_29 !23_29 !25_29 17_29 24_29
@ -1526,9 +1526,9 @@ INT_L.IMUX_L36.ER1END2 origin:050-pip-seed !22_37 16_37 23_37 24_37 25_37
INT_L.IMUX_L36.FAN_BOUNCE1 origin:050-pip-seed !23_37 21_37 22_37 24_37 25_37
INT_L.IMUX_L36.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_37 21_37 23_37 24_37 25_37
INT_L.IMUX_L36.GFAN1 origin:049-int-imux-gfan !22_37 !23_37 !25_37 20_37 24_37
INT_L.IMUX_L36.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_37 20_37 22_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_37 20_37 23_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_37 !23_37 !24_37 20_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_L.IMUX_L36.NE2END2 origin:050-pip-seed !22_37 !23_37 !24_37 16_37 25_37
INT_L.IMUX_L36.NL1END2 origin:050-pip-seed !23_37 17_37 22_37 24_37 25_37
INT_L.IMUX_L36.NN2END2 origin:050-pip-seed !22_37 !23_37 !25_37 16_37 24_37
@ -1550,9 +1550,9 @@ INT_L.IMUX_L37.ER1END2 origin:050-pip-seed !22_45 19_44 23_45 24_45 25_45
INT_L.IMUX_L37.FAN_BOUNCE3 origin:050-pip-seed !23_45 21_45 22_45 24_45 25_45
INT_L.IMUX_L37.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_45 21_45 23_45 24_45 25_45
INT_L.IMUX_L37.GFAN1 origin:049-int-imux-gfan !22_45 !23_45 !25_45 20_45 24_45
INT_L.IMUX_L37.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_45 20_45 22_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_45 !23_45 !24_45 20_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_45 20_45 23_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_L.IMUX_L37.NE2END3 origin:050-pip-seed !22_45 !23_45 !24_45 17_45 25_45
INT_L.IMUX_L37.NL1BEG_N3 origin:050-pip-seed !23_45 17_45 22_45 24_45 25_45
INT_L.IMUX_L37.NN2END3 origin:050-pip-seed !22_45 !23_45 !25_45 17_45 24_45
@ -1574,9 +1574,9 @@ INT_L.IMUX_L38.ER1END3 origin:050-pip-seed !22_53 16_53 23_53 24_53 25_53
INT_L.IMUX_L38.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_53 21_53 22_53 24_53 25_53
INT_L.IMUX_L38.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_53 21_53 23_53 24_53 25_53
INT_L.IMUX_L38.GFAN1 origin:049-int-imux-gfan !22_53 !23_53 !25_53 20_53 24_53
INT_L.IMUX_L38.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_53 20_53 22_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_53 !23_53 !24_53 20_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_53 20_53 23_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_L.IMUX_L38.NE2END3 origin:050-pip-seed !22_53 !23_53 !24_53 16_53 25_53
INT_L.IMUX_L38.NL1BEG_N3 origin:050-pip-seed !23_53 17_53 22_53 24_53 25_53
INT_L.IMUX_L38.NN2END3 origin:050-pip-seed !22_53 !23_53 !25_53 16_53 24_53
@ -1598,9 +1598,9 @@ INT_L.IMUX_L39.ER1END3 origin:050-pip-seed !22_61 19_60 23_61 24_61 25_61
INT_L.IMUX_L39.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_61 21_61 22_61 24_61 25_61
INT_L.IMUX_L39.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_61 21_61 23_61 24_61 25_61
INT_L.IMUX_L39.GFAN1 origin:049-int-imux-gfan !22_61 !23_61 !25_61 20_61 24_61
INT_L.IMUX_L39.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_61 20_61 22_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_61 !23_61 !24_61 20_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_61 20_61 23_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_L.IMUX_L39.NE2END_S3_0 origin:050-pip-seed !22_61 !23_61 !24_61 17_61 25_61
INT_L.IMUX_L39.NL1END_S3_0 origin:050-pip-seed !23_61 17_61 22_61 24_61 25_61
INT_L.IMUX_L39.NN2END_S2_0 origin:050-pip-seed !22_61 !23_61 !25_61 17_61 24_61
@ -1622,9 +1622,9 @@ INT_L.IMUX_L4.ER1END1 origin:050-pip-seed !22_33 18_32 23_33 24_33 25_33
INT_L.IMUX_L4.FAN_BOUNCE1 origin:050-pip-seed !23_33 21_33 22_33 24_33 25_33
INT_L.IMUX_L4.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_33 21_33 23_33 24_33 25_33
INT_L.IMUX_L4.GFAN1 origin:049-int-imux-gfan !22_33 !23_33 !25_33 20_33 24_33
INT_L.IMUX_L4.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_33 20_33 22_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_33 20_33 23_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_33 !23_33 !24_33 20_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_L.IMUX_L4.NE2END2 origin:050-pip-seed !22_33 !23_33 !24_33 16_33 25_33
INT_L.IMUX_L4.NL1END2 origin:050-pip-seed !23_33 17_33 22_33 24_33 25_33
INT_L.IMUX_L4.NN2END2 origin:050-pip-seed !22_33 !23_33 !25_33 16_33 24_33
@ -1646,9 +1646,9 @@ INT_L.IMUX_L40.ER1END0 origin:050-pip-seed !23_06 19_07 22_06 24_06 25_06
INT_L.IMUX_L40.FAN_BOUNCE2 origin:050-pip-seed !23_06 20_06 22_06 24_06 25_06
INT_L.IMUX_L40.FAN_BOUNCE7 origin:050-pip-seed !22_06 20_06 23_06 24_06 25_06
INT_L.IMUX_L40.GFAN0 origin:049-int-imux-gfan !22_06 !23_06 !24_06 21_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_06 21_06 22_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_06 21_06 23_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_06 !23_06 !25_06 21_06 24_06
INT_L.IMUX_L40.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_L.IMUX_L40.NE2END0 origin:050-pip-seed !22_06 !23_06 !25_06 17_06 24_06
INT_L.IMUX_L40.NL1END0 origin:050-pip-seed !22_06 16_06 23_06 24_06 25_06
INT_L.IMUX_L40.NN2END0 origin:050-pip-seed !22_06 !23_06 !24_06 17_06 25_06
@ -1670,9 +1670,9 @@ INT_L.IMUX_L41.ER1END0 origin:050-pip-seed !23_14 18_15 22_14 24_14 25_14
INT_L.IMUX_L41.FAN_BOUNCE5 origin:050-pip-seed !22_14 20_14 23_14 24_14 25_14
INT_L.IMUX_L41.FAN_BOUNCE6 origin:050-pip-seed !23_14 20_14 22_14 24_14 25_14
INT_L.IMUX_L41.GFAN0 origin:049-int-imux-gfan !22_14 !23_14 !24_14 21_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_14 !23_14 !25_14 21_14 24_14
INT_L.IMUX_L41.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_14 21_14 22_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_14 21_14 23_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_L.IMUX_L41.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_L.IMUX_L41.NE2END1 origin:050-pip-seed !22_14 !23_14 !25_14 18_15 24_14
INT_L.IMUX_L41.NL1END1 origin:050-pip-seed !22_14 16_14 23_14 24_14 25_14
INT_L.IMUX_L41.NN2END1 origin:050-pip-seed !22_14 !23_14 !24_14 18_15 25_14
@ -1695,8 +1695,8 @@ INT_L.IMUX_L42.FAN_BOUNCE1 origin:050-pip-seed !22_22 20_22 23_22 24_22 25_22
INT_L.IMUX_L42.FAN_BOUNCE7 origin:050-pip-seed !23_22 20_22 22_22 24_22 25_22
INT_L.IMUX_L42.GFAN0 origin:049-int-imux-gfan !22_22 !23_22 !24_22 21_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 21_22 24_22
INT_L.IMUX_L42.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_22 21_22 22_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_22 21_22 23_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_L.IMUX_L42.NE2END1 origin:050-pip-seed !22_22 !23_22 !25_22 17_22 24_22
INT_L.IMUX_L42.NL1END1 origin:050-pip-seed !22_22 16_22 23_22 24_22 25_22
INT_L.IMUX_L42.NN2END1 origin:050-pip-seed !22_22 !23_22 !24_22 17_22 25_22
@ -1718,8 +1718,8 @@ INT_L.IMUX_L43.ER1END1 origin:050-pip-seed !23_30 18_31 22_30 24_30 25_30
INT_L.IMUX_L43.FAN_BOUNCE3 origin:050-pip-seed !22_30 20_30 23_30 24_30 25_30
INT_L.IMUX_L43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
INT_L.IMUX_L43.GFAN0 origin:049-int-imux-gfan !22_30 !23_30 !24_30 21_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_30 21_30 22_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_30 21_30 23_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
INT_L.IMUX_L43.NE2END2 origin:050-pip-seed !22_30 !23_30 !25_30 18_31 24_30
INT_L.IMUX_L43.NL1END2 origin:050-pip-seed !22_30 16_30 23_30 24_30 25_30
@ -1742,9 +1742,9 @@ INT_L.IMUX_L44.ER1END2 origin:050-pip-seed !23_38 19_39 22_38 24_38 25_38
INT_L.IMUX_L44.FAN_BOUNCE1 origin:050-pip-seed !22_38 20_38 23_38 24_38 25_38
INT_L.IMUX_L44.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_38 20_38 22_38 24_38 25_38
INT_L.IMUX_L44.GFAN1 origin:049-int-imux-gfan !22_38 !23_38 !24_38 21_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_38 21_38 23_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_38 21_38 22_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_38 !23_38 !25_38 21_38 24_38
INT_L.IMUX_L44.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_L.IMUX_L44.NE2END2 origin:050-pip-seed !22_38 !23_38 !25_38 17_38 24_38
INT_L.IMUX_L44.NL1END2 origin:050-pip-seed !22_38 16_38 23_38 24_38 25_38
INT_L.IMUX_L44.NN2END2 origin:050-pip-seed !22_38 !23_38 !24_38 17_38 25_38
@ -1766,9 +1766,9 @@ INT_L.IMUX_L45.ER1END2 origin:050-pip-seed !23_46 18_47 22_46 24_46 25_46
INT_L.IMUX_L45.FAN_BOUNCE3 origin:050-pip-seed !22_46 20_46 23_46 24_46 25_46
INT_L.IMUX_L45.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_46 20_46 22_46 24_46 25_46
INT_L.IMUX_L45.GFAN1 origin:049-int-imux-gfan !22_46 !23_46 !24_46 21_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_46 21_46 23_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_46 !23_46 !25_46 21_46 24_46
INT_L.IMUX_L45.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_46 21_46 22_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_L.IMUX_L45.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_L.IMUX_L45.NE2END3 origin:050-pip-seed !22_46 !23_46 !25_46 18_47 24_46
INT_L.IMUX_L45.NL1BEG_N3 origin:050-pip-seed !22_46 16_46 23_46 24_46 25_46
INT_L.IMUX_L45.NN2END3 origin:050-pip-seed !22_46 !23_46 !24_46 18_47 25_46
@ -1791,8 +1791,8 @@ INT_L.IMUX_L46.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_54 20_54 23_54 24_54 25_5
INT_L.IMUX_L46.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_54 20_54 22_54 24_54 25_54
INT_L.IMUX_L46.GFAN1 origin:049-int-imux-gfan !22_54 !23_54 !24_54 21_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_54 21_54 23_54 24_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_54 !23_54 !25_54 21_54 24_54
INT_L.IMUX_L46.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_54 21_54 22_54 24_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_L.IMUX_L46.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_L.IMUX_L46.NE2END3 origin:050-pip-seed !22_54 !23_54 !25_54 17_54 24_54
INT_L.IMUX_L46.NL1BEG_N3 origin:050-pip-seed !22_54 16_54 23_54 24_54 25_54
INT_L.IMUX_L46.NN2END3 origin:050-pip-seed !22_54 !23_54 !24_54 17_54 25_54
@ -1815,8 +1815,8 @@ INT_L.IMUX_L47.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_62 20_62 23_62 24_62 25_6
INT_L.IMUX_L47.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_62 20_62 22_62 24_62 25_62
INT_L.IMUX_L47.GFAN1 origin:049-int-imux-gfan !22_62 !23_62 !24_62 21_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_62 21_62 23_62 24_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_62 !23_62 !25_62 21_62 24_62
INT_L.IMUX_L47.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_62 21_62 22_62 24_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_L.IMUX_L47.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_L.IMUX_L47.NE2END_S3_0 origin:050-pip-seed !22_62 !23_62 !25_62 18_63 24_62
INT_L.IMUX_L47.NL1END_S3_0 origin:050-pip-seed !22_62 16_62 23_62 24_62 25_62
INT_L.IMUX_L47.NN2END_S2_0 origin:050-pip-seed !22_62 !23_62 !24_62 18_63 25_62
@ -1838,9 +1838,9 @@ INT_L.IMUX_L5.ER1END2 origin:050-pip-seed !22_41 19_40 23_41 24_41 25_41
INT_L.IMUX_L5.FAN_BOUNCE3 origin:050-pip-seed !23_41 21_41 22_41 24_41 25_41
INT_L.IMUX_L5.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_41 21_41 23_41 24_41 25_41
INT_L.IMUX_L5.GFAN1 origin:049-int-imux-gfan !22_41 !23_41 !25_41 20_41 24_41
INT_L.IMUX_L5.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_41 20_41 22_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_41 !23_41 !24_41 20_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_41 20_41 23_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_L.IMUX_L5.NE2END2 origin:050-pip-seed !22_41 !23_41 !24_41 19_40 25_41
INT_L.IMUX_L5.NL1BEG_N3 origin:050-pip-seed !23_41 17_41 22_41 24_41 25_41
INT_L.IMUX_L5.NN2END2 origin:050-pip-seed !22_41 !23_41 !25_41 19_40 24_41
@ -1862,9 +1862,9 @@ INT_L.IMUX_L6.ER1END2 origin:050-pip-seed !22_49 18_48 23_49 24_49 25_49
INT_L.IMUX_L6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_49 21_49 22_49 24_49 25_49
INT_L.IMUX_L6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_49 21_49 23_49 24_49 25_49
INT_L.IMUX_L6.GFAN1 origin:049-int-imux-gfan !22_49 !23_49 !25_49 20_49 24_49
INT_L.IMUX_L6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_49 20_49 22_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_49 !23_49 !24_49 20_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_49 20_49 23_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_L.IMUX_L6.NE2END3 origin:050-pip-seed !22_49 !23_49 !24_49 16_49 25_49
INT_L.IMUX_L6.NL1BEG_N3 origin:050-pip-seed !23_49 17_49 22_49 24_49 25_49
INT_L.IMUX_L6.NN2END3 origin:050-pip-seed !22_49 !23_49 !25_49 16_49 24_49
@ -1886,9 +1886,9 @@ INT_L.IMUX_L7.ER1END3 origin:050-pip-seed !22_57 19_56 23_57 24_57 25_57
INT_L.IMUX_L7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_57 21_57 22_57 24_57 25_57
INT_L.IMUX_L7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_57 21_57 23_57 24_57 25_57
INT_L.IMUX_L7.GFAN1 origin:049-int-imux-gfan !22_57 !23_57 !25_57 20_57 24_57
INT_L.IMUX_L7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_57 20_57 22_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_57 !23_57 !24_57 20_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_57 20_57 23_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_L.IMUX_L7.NE2END3 origin:050-pip-seed !22_57 !23_57 !24_57 19_56 25_57
INT_L.IMUX_L7.NL1END_S3_0 origin:050-pip-seed !23_57 17_57 22_57 24_57 25_57
INT_L.IMUX_L7.NN2END3 origin:050-pip-seed !22_57 !23_57 !25_57 19_56 24_57
@ -1910,9 +1910,9 @@ INT_L.IMUX_L8.ER1END_N3_3 origin:050-pip-seed !23_02 17_02 22_02 24_02 25_02
INT_L.IMUX_L8.FAN_BOUNCE2 origin:050-pip-seed !23_02 20_02 22_02 24_02 25_02
INT_L.IMUX_L8.FAN_BOUNCE7 origin:050-pip-seed !22_02 20_02 23_02 24_02 25_02
INT_L.IMUX_L8.GFAN0 origin:049-int-imux-gfan !22_02 !23_02 !24_02 21_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_02 21_02 22_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_02 21_02 23_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_02 !23_02 !25_02 21_02 24_02
INT_L.IMUX_L8.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_L.IMUX_L8.NE2END0 origin:050-pip-seed !22_02 !23_02 !25_02 17_02 24_02
INT_L.IMUX_L8.NL1END0 origin:050-pip-seed !22_02 16_02 23_02 24_02 25_02
INT_L.IMUX_L8.NN2END0 origin:050-pip-seed !22_02 !23_02 !24_02 17_02 25_02
@ -1934,8 +1934,8 @@ INT_L.IMUX_L9.ER1END0 origin:050-pip-seed !23_10 18_11 22_10 24_10 25_10
INT_L.IMUX_L9.FAN_BOUNCE5 origin:050-pip-seed !22_10 20_10 23_10 24_10 25_10
INT_L.IMUX_L9.FAN_BOUNCE6 origin:050-pip-seed !23_10 20_10 22_10 24_10 25_10
INT_L.IMUX_L9.GFAN0 origin:049-int-imux-gfan !22_10 !23_10 !24_10 21_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_10 !23_10 !25_10 21_10 24_10
INT_L.IMUX_L9.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_10 21_10 22_10 24_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_L.IMUX_L9.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_10 21_10 23_10 24_10 25_10
INT_L.IMUX_L9.NE2END0 origin:050-pip-seed !22_10 !23_10 !25_10 16_10 24_10
INT_L.IMUX_L9.NL1END1 origin:050-pip-seed !22_10 16_10 23_10 24_10 25_10
@ -2193,7 +2193,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L13 origin:050-pip-seed 10_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L19 origin:050-pip-seed 08_17 14_17
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
@ -3295,7 +3295,7 @@ INT_L.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
INT_L.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
INT_L.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_L.SW6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L15 origin:050-pip-seed 03_60 04_62
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

320
artix7/segbits_int_r.origin_info.db
View File

@ -6,9 +6,9 @@ INT_R.BYP_ALT0.ER1END0 origin:050-pip-seed !22_07 17_07 23_07 24_07 25_07
INT_R.BYP_ALT0.FAN_BOUNCE2 origin:050-pip-seed !22_07 21_07 23_07 24_07 25_07
INT_R.BYP_ALT0.FAN_BOUNCE7 origin:050-pip-seed !23_07 21_07 22_07 24_07 25_07
INT_R.BYP_ALT0.GFAN0 origin:054-pip-fan-alt !22_07 !23_07 !25_07 20_07 24_07
INT_R.BYP_ALT0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_07 20_07 23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_07 20_07 22_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_07 !23_07 !24_07 20_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_R.BYP_ALT0.NE2END0 origin:050-pip-seed !22_07 !23_07 !24_07 19_06 25_07
INT_R.BYP_ALT0.NL1END0 origin:050-pip-seed !23_07 18_06 22_07 24_07 25_07
INT_R.BYP_ALT0.NN2END0 origin:050-pip-seed !22_07 !23_07 !25_07 19_06 24_07
@ -30,9 +30,9 @@ INT_R.BYP_ALT1.ER1END0 origin:050-pip-seed !22_15 16_15 23_15 24_15 25_15
INT_R.BYP_ALT1.FAN_BOUNCE5 origin:050-pip-seed !23_15 21_15 22_15 24_15 25_15
INT_R.BYP_ALT1.FAN_BOUNCE6 origin:050-pip-seed !22_15 21_15 23_15 24_15 25_15
INT_R.BYP_ALT1.GFAN0 origin:054-pip-fan-alt !22_15 !23_15 !25_15 20_15 24_15
INT_R.BYP_ALT1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_15 !23_15 !24_15 20_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_15 20_15 23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_15 20_15 22_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_R.BYP_ALT1.NE2END1 origin:050-pip-seed !22_15 !23_15 !24_15 16_15 25_15
INT_R.BYP_ALT1.NL1END1 origin:050-pip-seed !23_15 18_14 22_15 24_15 25_15
INT_R.BYP_ALT1.NN2END1 origin:050-pip-seed !22_15 !23_15 !25_15 16_15 24_15
@ -54,9 +54,9 @@ INT_R.BYP_ALT2.ER1END2 origin:050-pip-seed !22_39 17_39 23_39 24_39 25_39
INT_R.BYP_ALT2.FAN_BOUNCE1 origin:050-pip-seed !23_39 21_39 22_39 24_39 25_39
INT_R.BYP_ALT2.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_39 21_39 23_39 24_39 25_39
INT_R.BYP_ALT2.GFAN1 origin:054-pip-fan-alt !22_39 !23_39 !25_39 20_39 24_39
INT_R.BYP_ALT2.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_39 20_39 22_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_39 20_39 23_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_39 !23_39 !24_39 20_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_R.BYP_ALT2.NE2END2 origin:050-pip-seed !22_39 !23_39 !24_39 19_38 25_39
INT_R.BYP_ALT2.NL1END2 origin:050-pip-seed !23_39 18_38 22_39 24_39 25_39
INT_R.BYP_ALT2.NN2END2 origin:050-pip-seed !22_39 !23_39 !25_39 19_38 24_39
@ -78,9 +78,9 @@ INT_R.BYP_ALT3.ER1END2 origin:050-pip-seed !22_47 16_47 23_47 24_47 25_47
INT_R.BYP_ALT3.FAN_BOUNCE3 origin:050-pip-seed !23_47 21_47 22_47 24_47 25_47
INT_R.BYP_ALT3.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_47 21_47 23_47 24_47 25_47
INT_R.BYP_ALT3.GFAN1 origin:054-pip-fan-alt !22_47 !23_47 !25_47 20_47 24_47
INT_R.BYP_ALT3.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_47 20_47 22_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_47 !23_47 !24_47 20_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_47 20_47 23_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_R.BYP_ALT3.NE2END3 origin:050-pip-seed !22_47 !23_47 !24_47 16_47 25_47
INT_R.BYP_ALT3.NL1BEG_N3 origin:050-pip-seed !23_47 18_46 22_47 24_47 25_47
INT_R.BYP_ALT3.NN2END3 origin:050-pip-seed !22_47 !23_47 !25_47 16_47 24_47
@ -102,9 +102,9 @@ INT_R.BYP_ALT4.ER1END1 origin:050-pip-seed !22_23 17_23 23_23 24_23 25_23
INT_R.BYP_ALT4.FAN_BOUNCE1 origin:050-pip-seed !23_23 21_23 22_23 24_23 25_23
INT_R.BYP_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_23 21_23 23_23 24_23 25_23
INT_R.BYP_ALT4.GFAN0 origin:054-pip-fan-alt !22_23 !23_23 !25_23 20_23 24_23
INT_R.BYP_ALT4.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_23 !23_23 !24_23 20_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_23 20_23 23_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_23 20_23 22_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_R.BYP_ALT4.NE2END1 origin:050-pip-seed !22_23 !23_23 !24_23 19_22 25_23
INT_R.BYP_ALT4.NL1END1 origin:050-pip-seed !23_23 18_22 22_23 24_23 25_23
INT_R.BYP_ALT4.NN2END1 origin:050-pip-seed !22_23 !23_23 !25_23 19_22 24_23
@ -126,9 +126,9 @@ INT_R.BYP_ALT5.ER1END1 origin:050-pip-seed !22_31 16_31 23_31 24_31 25_31
INT_R.BYP_ALT5.FAN_BOUNCE3 origin:050-pip-seed !23_31 21_31 22_31 24_31 25_31
INT_R.BYP_ALT5.FAN_BOUNCE5 origin:050-pip-seed !22_31 21_31 23_31 24_31 25_31
INT_R.BYP_ALT5.GFAN0 origin:054-pip-fan-alt !22_31 !23_31 !25_31 20_31 24_31
INT_R.BYP_ALT5.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_31 20_31 23_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_31 20_31 22_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_31 !23_31 !24_31 20_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_R.BYP_ALT5.NE2END2 origin:050-pip-seed !22_31 !23_31 !24_31 16_31 25_31
INT_R.BYP_ALT5.NL1END2 origin:050-pip-seed !23_31 18_30 22_31 24_31 25_31
INT_R.BYP_ALT5.NN2END2 origin:050-pip-seed !22_31 !23_31 !25_31 16_31 24_31
@ -150,8 +150,8 @@ INT_R.BYP_ALT6.ER1END3 origin:050-pip-seed !22_55 17_55 23_55 24_55 25_55
INT_R.BYP_ALT6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_55 21_55 22_55 24_55 25_55
INT_R.BYP_ALT6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_55 21_55 23_55 24_55 25_55
INT_R.BYP_ALT6.GFAN1 origin:054-pip-fan-alt !22_55 !23_55 !25_55 20_55 24_55
INT_R.BYP_ALT6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_55 20_55 22_55 24_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_55 !23_55 !24_55 20_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_55 20_55 23_55 24_55 25_55
INT_R.BYP_ALT6.NE2END3 origin:050-pip-seed !22_55 !23_55 !24_55 19_54 25_55
INT_R.BYP_ALT6.NL1BEG_N3 origin:050-pip-seed !23_55 18_54 22_55 24_55 25_55
@ -174,8 +174,8 @@ INT_R.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_R.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_R.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
INT_R.BYP_ALT7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_63 20_63 22_63 24_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_63 !23_63 !24_63 20_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_R.BYP_ALT7.NE2END_S3_0 origin:050-pip-seed !22_63 !23_63 !24_63 16_63 25_63
INT_R.BYP_ALT7.NL1END_S3_0 origin:050-pip-seed !23_63 18_62 22_63 24_63 25_63
@ -373,7 +373,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_R.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
@ -413,7 +413,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@ -676,9 +676,9 @@ INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_R.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_R.FAN_ALT4.NE2END0 origin:050-pip-seed !22_08 !23_08 !25_08 17_08 24_08
@ -806,9 +806,9 @@ INT_R.IMUX0.ER1END_N3_3 origin:050-pip-seed !22_01 18_00 23_01 24_01 25_01
INT_R.IMUX0.FAN_BOUNCE2 origin:050-pip-seed !22_01 21_01 23_01 24_01 25_01
INT_R.IMUX0.FAN_BOUNCE7 origin:050-pip-seed !23_01 21_01 22_01 24_01 25_01
INT_R.IMUX0.GFAN0 origin:049-int-imux-gfan !22_01 !23_01 !25_01 20_01 24_01
INT_R.IMUX0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_01 20_01 23_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_01 20_01 22_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_01 !23_01 !24_01 20_01 25_01
INT_R.IMUX0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_R.IMUX0.NE2END0 origin:050-pip-seed !22_01 !23_01 !24_01 16_01 25_01
INT_R.IMUX0.NL1END0 origin:050-pip-seed !23_01 17_01 22_01 24_01 25_01
INT_R.IMUX0.NN2END0 origin:050-pip-seed !22_01 !23_01 !25_01 16_01 24_01
@ -830,9 +830,9 @@ INT_R.IMUX1.ER1END0 origin:050-pip-seed !22_09 19_08 23_09 24_09 25_09
INT_R.IMUX1.FAN_BOUNCE5 origin:050-pip-seed !23_09 21_09 22_09 24_09 25_09
INT_R.IMUX1.FAN_BOUNCE6 origin:050-pip-seed !22_09 21_09 23_09 24_09 25_09
INT_R.IMUX1.GFAN0 origin:049-int-imux-gfan !22_09 !23_09 !25_09 20_09 24_09
INT_R.IMUX1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_09 !23_09 !24_09 20_09 25_09
INT_R.IMUX1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_09 20_09 23_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_09 20_09 22_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_R.IMUX1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_R.IMUX1.NE2END0 origin:050-pip-seed !22_09 !23_09 !24_09 19_08 25_09
INT_R.IMUX1.NL1END1 origin:050-pip-seed !23_09 17_09 22_09 24_09 25_09
INT_R.IMUX1.NN2END0 origin:050-pip-seed !22_09 !23_09 !25_09 19_08 24_09
@ -854,9 +854,9 @@ INT_R.IMUX10.ER1END0 origin:050-pip-seed !23_18 17_18 22_18 24_18 25_18
INT_R.IMUX10.FAN_BOUNCE1 origin:050-pip-seed !22_18 20_18 23_18 24_18 25_18
INT_R.IMUX10.FAN_BOUNCE7 origin:050-pip-seed !23_18 20_18 22_18 24_18 25_18
INT_R.IMUX10.GFAN0 origin:049-int-imux-gfan !22_18 !23_18 !24_18 21_18 25_18
INT_R.IMUX10.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_18 !23_18 !25_18 21_18 24_18
INT_R.IMUX10.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_18 21_18 22_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_18 21_18 23_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_R.IMUX10.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_R.IMUX10.NE2END1 origin:050-pip-seed !22_18 !23_18 !25_18 17_18 24_18
INT_R.IMUX10.NL1END1 origin:050-pip-seed !22_18 16_18 23_18 24_18 25_18
INT_R.IMUX10.NN2END1 origin:050-pip-seed !22_18 !23_18 !24_18 17_18 25_18
@ -878,9 +878,9 @@ INT_R.IMUX11.ER1END1 origin:050-pip-seed !23_26 18_27 22_26 24_26 25_26
INT_R.IMUX11.FAN_BOUNCE3 origin:050-pip-seed !22_26 20_26 23_26 24_26 25_26
INT_R.IMUX11.FAN_BOUNCE5 origin:050-pip-seed !23_26 20_26 22_26 24_26 25_26
INT_R.IMUX11.GFAN0 origin:049-int-imux-gfan !22_26 !23_26 !24_26 21_26 25_26
INT_R.IMUX11.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_26 21_26 22_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_26 21_26 23_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_26 !23_26 !25_26 21_26 24_26
INT_R.IMUX11.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_R.IMUX11.NE2END1 origin:050-pip-seed !22_26 !23_26 !25_26 16_26 24_26
INT_R.IMUX11.NL1END2 origin:050-pip-seed !22_26 16_26 23_26 24_26 25_26
INT_R.IMUX11.NN2END1 origin:050-pip-seed !22_26 !23_26 !24_26 16_26 25_26
@ -902,9 +902,9 @@ INT_R.IMUX12.ER1END1 origin:050-pip-seed !23_34 17_34 22_34 24_34 25_34
INT_R.IMUX12.FAN_BOUNCE1 origin:050-pip-seed !22_34 20_34 23_34 24_34 25_34
INT_R.IMUX12.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_34 20_34 22_34 24_34 25_34
INT_R.IMUX12.GFAN1 origin:049-int-imux-gfan !22_34 !23_34 !24_34 21_34 25_34
INT_R.IMUX12.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_34 21_34 23_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_34 21_34 22_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_34 !23_34 !25_34 21_34 24_34
INT_R.IMUX12.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_R.IMUX12.NE2END2 origin:050-pip-seed !22_34 !23_34 !25_34 17_34 24_34
INT_R.IMUX12.NL1END2 origin:050-pip-seed !22_34 16_34 23_34 24_34 25_34
INT_R.IMUX12.NN2END2 origin:050-pip-seed !22_34 !23_34 !24_34 17_34 25_34
@ -926,9 +926,9 @@ INT_R.IMUX13.ER1END2 origin:050-pip-seed !23_42 18_43 22_42 24_42 25_42
INT_R.IMUX13.FAN_BOUNCE3 origin:050-pip-seed !22_42 20_42 23_42 24_42 25_42
INT_R.IMUX13.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_42 20_42 22_42 24_42 25_42
INT_R.IMUX13.GFAN1 origin:049-int-imux-gfan !22_42 !23_42 !24_42 21_42 25_42
INT_R.IMUX13.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_42 21_42 23_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_42 !23_42 !25_42 21_42 24_42
INT_R.IMUX13.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_42 21_42 22_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_R.IMUX13.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_R.IMUX13.NE2END2 origin:050-pip-seed !22_42 !23_42 !25_42 16_42 24_42
INT_R.IMUX13.NL1BEG_N3 origin:050-pip-seed !22_42 16_42 23_42 24_42 25_42
INT_R.IMUX13.NN2END2 origin:050-pip-seed !22_42 !23_42 !24_42 16_42 25_42
@ -950,9 +950,9 @@ INT_R.IMUX14.ER1END2 origin:050-pip-seed !23_50 17_50 22_50 24_50 25_50
INT_R.IMUX14.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_50 20_50 23_50 24_50 25_50
INT_R.IMUX14.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_50 20_50 22_50 24_50 25_50
INT_R.IMUX14.GFAN1 origin:049-int-imux-gfan !22_50 !23_50 !24_50 21_50 25_50
INT_R.IMUX14.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_50 21_50 23_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_50 !23_50 !25_50 21_50 24_50
INT_R.IMUX14.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_50 21_50 22_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_R.IMUX14.NE2END3 origin:050-pip-seed !22_50 !23_50 !25_50 17_50 24_50
INT_R.IMUX14.NL1BEG_N3 origin:050-pip-seed !22_50 16_50 23_50 24_50 25_50
INT_R.IMUX14.NN2END3 origin:050-pip-seed !22_50 !23_50 !24_50 17_50 25_50
@ -974,9 +974,9 @@ INT_R.IMUX15.ER1END3 origin:050-pip-seed !23_58 18_59 22_58 24_58 25_58
INT_R.IMUX15.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_58 20_58 23_58 24_58 25_58
INT_R.IMUX15.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_58 20_58 22_58 24_58 25_58
INT_R.IMUX15.GFAN1 origin:049-int-imux-gfan !22_58 !23_58 !24_58 21_58 25_58
INT_R.IMUX15.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_58 21_58 23_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_58 !23_58 !25_58 21_58 24_58
INT_R.IMUX15.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_58 21_58 22_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_R.IMUX15.NE2END3 origin:050-pip-seed !22_58 !23_58 !25_58 16_58 24_58
INT_R.IMUX15.NL1END_S3_0 origin:050-pip-seed !22_58 16_58 23_58 24_58 25_58
INT_R.IMUX15.NN2END3 origin:050-pip-seed !22_58 !23_58 !24_58 16_58 25_58
@ -998,9 +998,9 @@ INT_R.IMUX16.ER1END_N3_3 origin:050-pip-seed !22_03 19_02 23_03 24_03 25_03
INT_R.IMUX16.FAN_BOUNCE2 origin:050-pip-seed !22_03 21_03 23_03 24_03 25_03
INT_R.IMUX16.FAN_BOUNCE7 origin:050-pip-seed !23_03 21_03 22_03 24_03 25_03
INT_R.IMUX16.GFAN0 origin:049-int-imux-gfan !22_03 !23_03 !25_03 20_03 24_03
INT_R.IMUX16.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_03 20_03 23_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_03 20_03 22_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_03 !23_03 !24_03 20_03 25_03
INT_R.IMUX16.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_R.IMUX16.NE2END0 origin:050-pip-seed !22_03 !23_03 !24_03 19_02 25_03
INT_R.IMUX16.NL1END0 origin:050-pip-seed !23_03 18_02 22_03 24_03 25_03
INT_R.IMUX16.NN2END0 origin:050-pip-seed !22_03 !23_03 !25_03 19_02 24_03
@ -1022,9 +1022,9 @@ INT_R.IMUX17.ER1END0 origin:050-pip-seed !22_11 16_11 23_11 24_11 25_11
INT_R.IMUX17.FAN_BOUNCE5 origin:050-pip-seed !23_11 21_11 22_11 24_11 25_11
INT_R.IMUX17.FAN_BOUNCE6 origin:050-pip-seed !22_11 21_11 23_11 24_11 25_11
INT_R.IMUX17.GFAN0 origin:049-int-imux-gfan !22_11 !23_11 !25_11 20_11 24_11
INT_R.IMUX17.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_11 !23_11 !24_11 20_11 25_11
INT_R.IMUX17.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_11 20_11 23_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_11 20_11 22_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_R.IMUX17.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_R.IMUX17.NE2END0 origin:050-pip-seed !22_11 !23_11 !24_11 18_10 25_11
INT_R.IMUX17.NL1END1 origin:050-pip-seed !23_11 18_10 22_11 24_11 25_11
INT_R.IMUX17.NN2END0 origin:050-pip-seed !22_11 !23_11 !25_11 18_10 24_11
@ -1046,9 +1046,9 @@ INT_R.IMUX18.ER1END0 origin:050-pip-seed !22_19 19_18 23_19 24_19 25_19
INT_R.IMUX18.FAN_BOUNCE1 origin:050-pip-seed !23_19 21_19 22_19 24_19 25_19
INT_R.IMUX18.FAN_BOUNCE7 origin:050-pip-seed !22_19 21_19 23_19 24_19 25_19
INT_R.IMUX18.GFAN0 origin:049-int-imux-gfan !22_19 !23_19 !25_19 20_19 24_19
INT_R.IMUX18.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_19 !23_19 !24_19 20_19 25_19
INT_R.IMUX18.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_19 20_19 23_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_19 20_19 22_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_R.IMUX18.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_R.IMUX18.NE2END1 origin:050-pip-seed !22_19 !23_19 !24_19 19_18 25_19
INT_R.IMUX18.NL1END1 origin:050-pip-seed !23_19 18_18 22_19 24_19 25_19
INT_R.IMUX18.NN2END1 origin:050-pip-seed !22_19 !23_19 !25_19 19_18 24_19
@ -1070,9 +1070,9 @@ INT_R.IMUX19.ER1END1 origin:050-pip-seed !22_27 16_27 23_27 24_27 25_27
INT_R.IMUX19.FAN_BOUNCE3 origin:050-pip-seed !23_27 21_27 22_27 24_27 25_27
INT_R.IMUX19.FAN_BOUNCE5 origin:050-pip-seed !22_27 21_27 23_27 24_27 25_27
INT_R.IMUX19.GFAN0 origin:049-int-imux-gfan !22_27 !23_27 !25_27 20_27 24_27
INT_R.IMUX19.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_27 20_27 23_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_27 20_27 22_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_27 !23_27 !24_27 20_27 25_27
INT_R.IMUX19.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_R.IMUX19.NE2END1 origin:050-pip-seed !22_27 !23_27 !24_27 18_26 25_27
INT_R.IMUX19.NL1END2 origin:050-pip-seed !23_27 18_26 22_27 24_27 25_27
INT_R.IMUX19.NN2END1 origin:050-pip-seed !22_27 !23_27 !25_27 18_26 24_27
@ -1094,9 +1094,9 @@ INT_R.IMUX2.ER1END0 origin:050-pip-seed !22_17 18_16 23_17 24_17 25_17
INT_R.IMUX2.FAN_BOUNCE1 origin:050-pip-seed !23_17 21_17 22_17 24_17 25_17
INT_R.IMUX2.FAN_BOUNCE7 origin:050-pip-seed !22_17 21_17 23_17 24_17 25_17
INT_R.IMUX2.GFAN0 origin:049-int-imux-gfan !22_17 !23_17 !25_17 20_17 24_17
INT_R.IMUX2.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_17 !23_17 !24_17 20_17 25_17
INT_R.IMUX2.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_17 20_17 23_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_17 20_17 22_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_R.IMUX2.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_R.IMUX2.NE2END1 origin:050-pip-seed !22_17 !23_17 !24_17 16_17 25_17
INT_R.IMUX2.NL1END1 origin:050-pip-seed !23_17 17_17 22_17 24_17 25_17
INT_R.IMUX2.NN2END1 origin:050-pip-seed !22_17 !23_17 !25_17 16_17 24_17
@ -1118,9 +1118,9 @@ INT_R.IMUX20.ER1END1 origin:050-pip-seed !22_35 19_34 23_35 24_35 25_35
INT_R.IMUX20.FAN_BOUNCE1 origin:050-pip-seed !23_35 21_35 22_35 24_35 25_35
INT_R.IMUX20.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_35 21_35 23_35 24_35 25_35
INT_R.IMUX20.GFAN1 origin:049-int-imux-gfan !22_35 !23_35 !25_35 20_35 24_35
INT_R.IMUX20.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_35 20_35 22_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_35 20_35 23_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_35 !23_35 !24_35 20_35 25_35
INT_R.IMUX20.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_R.IMUX20.NE2END2 origin:050-pip-seed !22_35 !23_35 !24_35 19_34 25_35
INT_R.IMUX20.NL1END2 origin:050-pip-seed !23_35 18_34 22_35 24_35 25_35
INT_R.IMUX20.NN2END2 origin:050-pip-seed !22_35 !23_35 !25_35 19_34 24_35
@ -1143,8 +1143,8 @@ INT_R.IMUX21.FAN_BOUNCE3 origin:050-pip-seed !23_43 21_43 22_43 24_43 25_43
INT_R.IMUX21.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_43 21_43 23_43 24_43 25_43
INT_R.IMUX21.GFAN1 origin:049-int-imux-gfan !22_43 !23_43 !25_43 20_43 24_43
INT_R.IMUX21.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_43 20_43 22_43 24_43 25_43
INT_R.IMUX21.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_43 !23_43 !24_43 20_43 25_43
INT_R.IMUX21.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_43 20_43 23_43 24_43 25_43
INT_R.IMUX21.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_R.IMUX21.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_R.IMUX21.NE2END2 origin:050-pip-seed !22_43 !23_43 !24_43 18_42 25_43
INT_R.IMUX21.NL1BEG_N3 origin:050-pip-seed !23_43 18_42 22_43 24_43 25_43
INT_R.IMUX21.NN2END2 origin:050-pip-seed !22_43 !23_43 !25_43 18_42 24_43
@ -1166,9 +1166,9 @@ INT_R.IMUX22.ER1END2 origin:050-pip-seed !22_51 19_50 23_51 24_51 25_51
INT_R.IMUX22.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_51 21_51 22_51 24_51 25_51
INT_R.IMUX22.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_51 21_51 23_51 24_51 25_51
INT_R.IMUX22.GFAN1 origin:049-int-imux-gfan !22_51 !23_51 !25_51 20_51 24_51
INT_R.IMUX22.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_51 20_51 22_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_51 !23_51 !24_51 20_51 25_51
INT_R.IMUX22.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_51 20_51 23_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_R.IMUX22.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_R.IMUX22.NE2END3 origin:050-pip-seed !22_51 !23_51 !24_51 19_50 25_51
INT_R.IMUX22.NL1BEG_N3 origin:050-pip-seed !23_51 18_50 22_51 24_51 25_51
INT_R.IMUX22.NN2END3 origin:050-pip-seed !22_51 !23_51 !25_51 19_50 24_51
@ -1190,9 +1190,9 @@ INT_R.IMUX23.ER1END3 origin:050-pip-seed !22_59 16_59 23_59 24_59 25_59
INT_R.IMUX23.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_59 21_59 22_59 24_59 25_59
INT_R.IMUX23.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_59 21_59 23_59 24_59 25_59
INT_R.IMUX23.GFAN1 origin:049-int-imux-gfan !22_59 !23_59 !25_59 20_59 24_59
INT_R.IMUX23.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_59 20_59 22_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_59 !23_59 !24_59 20_59 25_59
INT_R.IMUX23.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_59 20_59 23_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_R.IMUX23.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_R.IMUX23.NE2END3 origin:050-pip-seed !22_59 !23_59 !24_59 18_58 25_59
INT_R.IMUX23.NL1END_S3_0 origin:050-pip-seed !23_59 18_58 22_59 24_59 25_59
INT_R.IMUX23.NN2END3 origin:050-pip-seed !22_59 !23_59 !25_59 18_58 24_59
@ -1214,9 +1214,9 @@ INT_R.IMUX24.ER1END0 origin:050-pip-seed !23_04 18_05 22_04 24_04 25_04
INT_R.IMUX24.FAN_BOUNCE2 origin:050-pip-seed !23_04 20_04 22_04 24_04 25_04
INT_R.IMUX24.FAN_BOUNCE7 origin:050-pip-seed !22_04 20_04 23_04 24_04 25_04
INT_R.IMUX24.GFAN0 origin:049-int-imux-gfan !22_04 !23_04 !24_04 21_04 25_04
INT_R.IMUX24.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_04 21_04 22_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_04 21_04 23_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_04 !23_04 !25_04 21_04 24_04
INT_R.IMUX24.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_R.IMUX24.NE2END0 origin:050-pip-seed !22_04 !23_04 !25_04 18_05 24_04
INT_R.IMUX24.NL1END0 origin:050-pip-seed !22_04 19_05 23_04 24_04 25_04
INT_R.IMUX24.NN2END0 origin:050-pip-seed !22_04 !23_04 !24_04 18_05 25_04
@ -1238,9 +1238,9 @@ INT_R.IMUX25.ER1END0 origin:050-pip-seed !23_12 17_12 22_12 24_12 25_12
INT_R.IMUX25.FAN_BOUNCE5 origin:050-pip-seed !22_12 20_12 23_12 24_12 25_12
INT_R.IMUX25.FAN_BOUNCE6 origin:050-pip-seed !23_12 20_12 22_12 24_12 25_12
INT_R.IMUX25.GFAN0 origin:049-int-imux-gfan !22_12 !23_12 !24_12 21_12 25_12
INT_R.IMUX25.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_12 !23_12 !25_12 21_12 24_12
INT_R.IMUX25.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_12 21_12 22_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_12 21_12 23_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_R.IMUX25.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_R.IMUX25.NE2END1 origin:050-pip-seed !22_12 !23_12 !25_12 19_13 24_12
INT_R.IMUX25.NL1END1 origin:050-pip-seed !22_12 19_13 23_12 24_12 25_12
INT_R.IMUX25.NN2END1 origin:050-pip-seed !22_12 !23_12 !24_12 19_13 25_12
@ -1262,8 +1262,8 @@ INT_R.IMUX26.ER1END1 origin:050-pip-seed !23_20 18_21 22_20 24_20 25_20
INT_R.IMUX26.FAN_BOUNCE1 origin:050-pip-seed !22_20 20_20 23_20 24_20 25_20
INT_R.IMUX26.FAN_BOUNCE7 origin:050-pip-seed !23_20 20_20 22_20 24_20 25_20
INT_R.IMUX26.GFAN0 origin:049-int-imux-gfan !22_20 !23_20 !24_20 21_20 25_20
INT_R.IMUX26.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_20 !23_20 !25_20 21_20 24_20
INT_R.IMUX26.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_20 21_20 22_20 24_20 25_20
INT_R.IMUX26.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_R.IMUX26.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_R.IMUX26.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_20 21_20 23_20 24_20 25_20
INT_R.IMUX26.NE2END1 origin:050-pip-seed !22_20 !23_20 !25_20 18_21 24_20
INT_R.IMUX26.NL1END1 origin:050-pip-seed !22_20 19_21 23_20 24_20 25_20
@ -1286,9 +1286,9 @@ INT_R.IMUX27.ER1END1 origin:050-pip-seed !23_28 17_28 22_28 24_28 25_28
INT_R.IMUX27.FAN_BOUNCE3 origin:050-pip-seed !22_28 20_28 23_28 24_28 25_28
INT_R.IMUX27.FAN_BOUNCE5 origin:050-pip-seed !23_28 20_28 22_28 24_28 25_28
INT_R.IMUX27.GFAN0 origin:049-int-imux-gfan !22_28 !23_28 !24_28 21_28 25_28
INT_R.IMUX27.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_28 21_28 22_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_28 21_28 23_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_28 !23_28 !25_28 21_28 24_28
INT_R.IMUX27.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_R.IMUX27.NE2END2 origin:050-pip-seed !22_28 !23_28 !25_28 19_29 24_28
INT_R.IMUX27.NL1END2 origin:050-pip-seed !22_28 19_29 23_28 24_28 25_28
INT_R.IMUX27.NN2END2 origin:050-pip-seed !22_28 !23_28 !24_28 19_29 25_28
@ -1311,8 +1311,8 @@ INT_R.IMUX28.FAN_BOUNCE1 origin:050-pip-seed !22_36 20_36 23_36 24_36 25_36
INT_R.IMUX28.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_36 20_36 22_36 24_36 25_36
INT_R.IMUX28.GFAN1 origin:049-int-imux-gfan !22_36 !23_36 !24_36 21_36 25_36
INT_R.IMUX28.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_36 21_36 23_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_36 21_36 22_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_36 !23_36 !25_36 21_36 24_36
INT_R.IMUX28.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_R.IMUX28.NE2END2 origin:050-pip-seed !22_36 !23_36 !25_36 18_37 24_36
INT_R.IMUX28.NL1END2 origin:050-pip-seed !22_36 19_37 23_36 24_36 25_36
INT_R.IMUX28.NN2END2 origin:050-pip-seed !22_36 !23_36 !24_36 18_37 25_36
@ -1334,9 +1334,9 @@ INT_R.IMUX29.ER1END2 origin:050-pip-seed !23_44 17_44 22_44 24_44 25_44
INT_R.IMUX29.FAN_BOUNCE3 origin:050-pip-seed !22_44 20_44 23_44 24_44 25_44
INT_R.IMUX29.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_44 20_44 22_44 24_44 25_44
INT_R.IMUX29.GFAN1 origin:049-int-imux-gfan !22_44 !23_44 !24_44 21_44 25_44
INT_R.IMUX29.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_44 21_44 23_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_44 !23_44 !25_44 21_44 24_44
INT_R.IMUX29.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_44 21_44 22_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_R.IMUX29.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_R.IMUX29.NE2END3 origin:050-pip-seed !22_44 !23_44 !25_44 19_45 24_44
INT_R.IMUX29.NL1BEG_N3 origin:050-pip-seed !22_44 19_45 23_44 24_44 25_44
INT_R.IMUX29.NN2END3 origin:050-pip-seed !22_44 !23_44 !24_44 19_45 25_44
@ -1358,9 +1358,9 @@ INT_R.IMUX3.ER1END1 origin:050-pip-seed !22_25 19_24 23_25 24_25 25_25
INT_R.IMUX3.FAN_BOUNCE3 origin:050-pip-seed !23_25 21_25 22_25 24_25 25_25
INT_R.IMUX3.FAN_BOUNCE5 origin:050-pip-seed !22_25 21_25 23_25 24_25 25_25
INT_R.IMUX3.GFAN0 origin:049-int-imux-gfan !22_25 !23_25 !25_25 20_25 24_25
INT_R.IMUX3.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_25 20_25 23_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_25 20_25 22_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_25 !23_25 !24_25 20_25 25_25
INT_R.IMUX3.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_R.IMUX3.NE2END1 origin:050-pip-seed !22_25 !23_25 !24_25 19_24 25_25
INT_R.IMUX3.NL1END2 origin:050-pip-seed !23_25 17_25 22_25 24_25 25_25
INT_R.IMUX3.NN2END1 origin:050-pip-seed !22_25 !23_25 !25_25 19_24 24_25
@ -1382,9 +1382,9 @@ INT_R.IMUX30.ER1END3 origin:050-pip-seed !23_52 18_53 22_52 24_52 25_52
INT_R.IMUX30.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_52 20_52 23_52 24_52 25_52
INT_R.IMUX30.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_52 20_52 22_52 24_52 25_52
INT_R.IMUX30.GFAN1 origin:049-int-imux-gfan !22_52 !23_52 !24_52 21_52 25_52
INT_R.IMUX30.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_52 21_52 23_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_52 !23_52 !25_52 21_52 24_52
INT_R.IMUX30.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_52 21_52 22_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_R.IMUX30.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_R.IMUX30.NE2END3 origin:050-pip-seed !22_52 !23_52 !25_52 18_53 24_52
INT_R.IMUX30.NL1BEG_N3 origin:050-pip-seed !22_52 19_53 23_52 24_52 25_52
INT_R.IMUX30.NN2END3 origin:050-pip-seed !22_52 !23_52 !24_52 18_53 25_52
@ -1406,9 +1406,9 @@ INT_R.IMUX31.ER1END3 origin:050-pip-seed !23_60 17_60 22_60 24_60 25_60
INT_R.IMUX31.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_60 20_60 23_60 24_60 25_60
INT_R.IMUX31.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_60 20_60 22_60 24_60 25_60
INT_R.IMUX31.GFAN1 origin:049-int-imux-gfan !22_60 !23_60 !24_60 21_60 25_60
INT_R.IMUX31.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_60 21_60 23_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_60 !23_60 !25_60 21_60 24_60
INT_R.IMUX31.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_60 21_60 22_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_R.IMUX31.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_R.IMUX31.NE2END_S3_0 origin:050-pip-seed !22_60 !23_60 !25_60 19_61 24_60
INT_R.IMUX31.NL1END_S3_0 origin:050-pip-seed !22_60 19_61 23_60 24_60 25_60
INT_R.IMUX31.NN2END_S2_0 origin:050-pip-seed !22_60 !23_60 !24_60 19_61 25_60
@ -1430,8 +1430,8 @@ INT_R.IMUX32.ER1END0 origin:050-pip-seed !22_05 16_05 23_05 24_05 25_05
INT_R.IMUX32.FAN_BOUNCE2 origin:050-pip-seed !22_05 21_05 23_05 24_05 25_05
INT_R.IMUX32.FAN_BOUNCE7 origin:050-pip-seed !23_05 21_05 22_05 24_05 25_05
INT_R.IMUX32.GFAN0 origin:049-int-imux-gfan !22_05 !23_05 !25_05 20_05 24_05
INT_R.IMUX32.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_05 20_05 23_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_05 20_05 22_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_05 !23_05 !24_05 20_05 25_05
INT_R.IMUX32.NE2END0 origin:050-pip-seed !22_05 !23_05 !24_05 16_05 25_05
INT_R.IMUX32.NL1END0 origin:050-pip-seed !23_05 17_05 22_05 24_05 25_05
@ -1455,8 +1455,8 @@ INT_R.IMUX33.FAN_BOUNCE5 origin:050-pip-seed !23_13 21_13 22_13 24_13 25_13
INT_R.IMUX33.FAN_BOUNCE6 origin:050-pip-seed !22_13 21_13 23_13 24_13 25_13
INT_R.IMUX33.GFAN0 origin:049-int-imux-gfan !22_13 !23_13 !25_13 20_13 24_13
INT_R.IMUX33.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_13 !23_13 !24_13 20_13 25_13
INT_R.IMUX33.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_13 20_13 23_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_13 20_13 22_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_R.IMUX33.NE2END1 origin:050-pip-seed !22_13 !23_13 !24_13 17_13 25_13
INT_R.IMUX33.NL1END1 origin:050-pip-seed !23_13 17_13 22_13 24_13 25_13
INT_R.IMUX33.NN2END1 origin:050-pip-seed !22_13 !23_13 !25_13 17_13 24_13
@ -1478,9 +1478,9 @@ INT_R.IMUX34.ER1END1 origin:050-pip-seed !22_21 16_21 23_21 24_21 25_21
INT_R.IMUX34.FAN_BOUNCE1 origin:050-pip-seed !23_21 21_21 22_21 24_21 25_21
INT_R.IMUX34.FAN_BOUNCE7 origin:050-pip-seed !22_21 21_21 23_21 24_21 25_21
INT_R.IMUX34.GFAN0 origin:049-int-imux-gfan !22_21 !23_21 !25_21 20_21 24_21
INT_R.IMUX34.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_21 !23_21 !24_21 20_21 25_21
INT_R.IMUX34.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_21 20_21 23_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_21 20_21 22_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_R.IMUX34.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_R.IMUX34.NE2END1 origin:050-pip-seed !22_21 !23_21 !24_21 16_21 25_21
INT_R.IMUX34.NL1END1 origin:050-pip-seed !23_21 17_21 22_21 24_21 25_21
INT_R.IMUX34.NN2END1 origin:050-pip-seed !22_21 !23_21 !25_21 16_21 24_21
@ -1502,9 +1502,9 @@ INT_R.IMUX35.ER1END1 origin:050-pip-seed !22_29 19_28 23_29 24_29 25_29
INT_R.IMUX35.FAN_BOUNCE3 origin:050-pip-seed !23_29 21_29 22_29 24_29 25_29
INT_R.IMUX35.FAN_BOUNCE5 origin:050-pip-seed !22_29 21_29 23_29 24_29 25_29
INT_R.IMUX35.GFAN0 origin:049-int-imux-gfan !22_29 !23_29 !25_29 20_29 24_29
INT_R.IMUX35.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_29 20_29 23_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_29 20_29 22_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_29 !23_29 !24_29 20_29 25_29
INT_R.IMUX35.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_R.IMUX35.NE2END2 origin:050-pip-seed !22_29 !23_29 !24_29 17_29 25_29
INT_R.IMUX35.NL1END2 origin:050-pip-seed !23_29 17_29 22_29 24_29 25_29
INT_R.IMUX35.NN2END2 origin:050-pip-seed !22_29 !23_29 !25_29 17_29 24_29
@ -1526,9 +1526,9 @@ INT_R.IMUX36.ER1END2 origin:050-pip-seed !22_37 16_37 23_37 24_37 25_37
INT_R.IMUX36.FAN_BOUNCE1 origin:050-pip-seed !23_37 21_37 22_37 24_37 25_37
INT_R.IMUX36.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_37 21_37 23_37 24_37 25_37
INT_R.IMUX36.GFAN1 origin:049-int-imux-gfan !22_37 !23_37 !25_37 20_37 24_37
INT_R.IMUX36.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_37 20_37 22_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_37 20_37 23_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_37 !23_37 !24_37 20_37 25_37
INT_R.IMUX36.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_R.IMUX36.NE2END2 origin:050-pip-seed !22_37 !23_37 !24_37 16_37 25_37
INT_R.IMUX36.NL1END2 origin:050-pip-seed !23_37 17_37 22_37 24_37 25_37
INT_R.IMUX36.NN2END2 origin:050-pip-seed !22_37 !23_37 !25_37 16_37 24_37
@ -1550,9 +1550,9 @@ INT_R.IMUX37.ER1END2 origin:050-pip-seed !22_45 19_44 23_45 24_45 25_45
INT_R.IMUX37.FAN_BOUNCE3 origin:050-pip-seed !23_45 21_45 22_45 24_45 25_45
INT_R.IMUX37.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_45 21_45 23_45 24_45 25_45
INT_R.IMUX37.GFAN1 origin:049-int-imux-gfan !22_45 !23_45 !25_45 20_45 24_45
INT_R.IMUX37.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_45 20_45 22_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_45 !23_45 !24_45 20_45 25_45
INT_R.IMUX37.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_45 20_45 23_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_R.IMUX37.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_R.IMUX37.NE2END3 origin:050-pip-seed !22_45 !23_45 !24_45 17_45 25_45
INT_R.IMUX37.NL1BEG_N3 origin:050-pip-seed !23_45 17_45 22_45 24_45 25_45
INT_R.IMUX37.NN2END3 origin:050-pip-seed !22_45 !23_45 !25_45 17_45 24_45
@ -1574,9 +1574,9 @@ INT_R.IMUX38.ER1END3 origin:050-pip-seed !22_53 16_53 23_53 24_53 25_53
INT_R.IMUX38.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_53 21_53 22_53 24_53 25_53
INT_R.IMUX38.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_53 21_53 23_53 24_53 25_53
INT_R.IMUX38.GFAN1 origin:049-int-imux-gfan !22_53 !23_53 !25_53 20_53 24_53
INT_R.IMUX38.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_53 20_53 22_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_53 !23_53 !24_53 20_53 25_53
INT_R.IMUX38.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_53 20_53 23_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_R.IMUX38.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_R.IMUX38.NE2END3 origin:050-pip-seed !22_53 !23_53 !24_53 16_53 25_53
INT_R.IMUX38.NL1BEG_N3 origin:050-pip-seed !23_53 17_53 22_53 24_53 25_53
INT_R.IMUX38.NN2END3 origin:050-pip-seed !22_53 !23_53 !25_53 16_53 24_53
@ -1598,9 +1598,9 @@ INT_R.IMUX39.ER1END3 origin:050-pip-seed !22_61 19_60 23_61 24_61 25_61
INT_R.IMUX39.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_61 21_61 22_61 24_61 25_61
INT_R.IMUX39.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_61 21_61 23_61 24_61 25_61
INT_R.IMUX39.GFAN1 origin:049-int-imux-gfan !22_61 !23_61 !25_61 20_61 24_61
INT_R.IMUX39.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_61 20_61 22_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_61 !23_61 !24_61 20_61 25_61
INT_R.IMUX39.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_61 20_61 23_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_R.IMUX39.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_R.IMUX39.NE2END_S3_0 origin:050-pip-seed !22_61 !23_61 !24_61 17_61 25_61
INT_R.IMUX39.NL1END_S3_0 origin:050-pip-seed !23_61 17_61 22_61 24_61 25_61
INT_R.IMUX39.NN2END_S2_0 origin:050-pip-seed !22_61 !23_61 !25_61 17_61 24_61
@ -1622,9 +1622,9 @@ INT_R.IMUX4.ER1END1 origin:050-pip-seed !22_33 18_32 23_33 24_33 25_33
INT_R.IMUX4.FAN_BOUNCE1 origin:050-pip-seed !23_33 21_33 22_33 24_33 25_33
INT_R.IMUX4.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_33 21_33 23_33 24_33 25_33
INT_R.IMUX4.GFAN1 origin:049-int-imux-gfan !22_33 !23_33 !25_33 20_33 24_33
INT_R.IMUX4.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_33 20_33 22_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_33 20_33 23_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_33 !23_33 !24_33 20_33 25_33
INT_R.IMUX4.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_R.IMUX4.NE2END2 origin:050-pip-seed !22_33 !23_33 !24_33 16_33 25_33
INT_R.IMUX4.NL1END2 origin:050-pip-seed !23_33 17_33 22_33 24_33 25_33
INT_R.IMUX4.NN2END2 origin:050-pip-seed !22_33 !23_33 !25_33 16_33 24_33
@ -1646,9 +1646,9 @@ INT_R.IMUX40.ER1END0 origin:050-pip-seed !23_06 19_07 22_06 24_06 25_06
INT_R.IMUX40.FAN_BOUNCE2 origin:050-pip-seed !23_06 20_06 22_06 24_06 25_06
INT_R.IMUX40.FAN_BOUNCE7 origin:050-pip-seed !22_06 20_06 23_06 24_06 25_06
INT_R.IMUX40.GFAN0 origin:049-int-imux-gfan !22_06 !23_06 !24_06 21_06 25_06
INT_R.IMUX40.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_06 21_06 22_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_06 21_06 23_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_06 !23_06 !25_06 21_06 24_06
INT_R.IMUX40.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_R.IMUX40.NE2END0 origin:050-pip-seed !22_06 !23_06 !25_06 17_06 24_06
INT_R.IMUX40.NL1END0 origin:050-pip-seed !22_06 16_06 23_06 24_06 25_06
INT_R.IMUX40.NN2END0 origin:050-pip-seed !22_06 !23_06 !24_06 17_06 25_06
@ -1670,9 +1670,9 @@ INT_R.IMUX41.ER1END0 origin:050-pip-seed !23_14 18_15 22_14 24_14 25_14
INT_R.IMUX41.FAN_BOUNCE5 origin:050-pip-seed !22_14 20_14 23_14 24_14 25_14
INT_R.IMUX41.FAN_BOUNCE6 origin:050-pip-seed !23_14 20_14 22_14 24_14 25_14
INT_R.IMUX41.GFAN0 origin:049-int-imux-gfan !22_14 !23_14 !24_14 21_14 25_14
INT_R.IMUX41.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_14 !23_14 !25_14 21_14 24_14
INT_R.IMUX41.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_14 21_14 22_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_14 21_14 23_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_R.IMUX41.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_R.IMUX41.NE2END1 origin:050-pip-seed !22_14 !23_14 !25_14 18_15 24_14
INT_R.IMUX41.NL1END1 origin:050-pip-seed !22_14 16_14 23_14 24_14 25_14
INT_R.IMUX41.NN2END1 origin:050-pip-seed !22_14 !23_14 !24_14 18_15 25_14
@ -1695,8 +1695,8 @@ INT_R.IMUX42.FAN_BOUNCE1 origin:050-pip-seed !22_22 20_22 23_22 24_22 25_22
INT_R.IMUX42.FAN_BOUNCE7 origin:050-pip-seed !23_22 20_22 22_22 24_22 25_22
INT_R.IMUX42.GFAN0 origin:049-int-imux-gfan !22_22 !23_22 !24_22 21_22 25_22
INT_R.IMUX42.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 21_22 24_22
INT_R.IMUX42.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_22 21_22 22_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_22 21_22 23_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_R.IMUX42.NE2END1 origin:050-pip-seed !22_22 !23_22 !25_22 17_22 24_22
INT_R.IMUX42.NL1END1 origin:050-pip-seed !22_22 16_22 23_22 24_22 25_22
INT_R.IMUX42.NN2END1 origin:050-pip-seed !22_22 !23_22 !24_22 17_22 25_22
@ -1718,8 +1718,8 @@ INT_R.IMUX43.ER1END1 origin:050-pip-seed !23_30 18_31 22_30 24_30 25_30
INT_R.IMUX43.FAN_BOUNCE3 origin:050-pip-seed !22_30 20_30 23_30 24_30 25_30
INT_R.IMUX43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
INT_R.IMUX43.GFAN0 origin:049-int-imux-gfan !22_30 !23_30 !24_30 21_30 25_30
INT_R.IMUX43.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_30 21_30 22_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_30 21_30 23_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
INT_R.IMUX43.NE2END2 origin:050-pip-seed !22_30 !23_30 !25_30 18_31 24_30
INT_R.IMUX43.NL1END2 origin:050-pip-seed !22_30 16_30 23_30 24_30 25_30
@ -1742,9 +1742,9 @@ INT_R.IMUX44.ER1END2 origin:050-pip-seed !23_38 19_39 22_38 24_38 25_38
INT_R.IMUX44.FAN_BOUNCE1 origin:050-pip-seed !22_38 20_38 23_38 24_38 25_38
INT_R.IMUX44.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_38 20_38 22_38 24_38 25_38
INT_R.IMUX44.GFAN1 origin:049-int-imux-gfan !22_38 !23_38 !24_38 21_38 25_38
INT_R.IMUX44.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_38 21_38 23_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_38 21_38 22_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_38 !23_38 !25_38 21_38 24_38
INT_R.IMUX44.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_R.IMUX44.NE2END2 origin:050-pip-seed !22_38 !23_38 !25_38 17_38 24_38
INT_R.IMUX44.NL1END2 origin:050-pip-seed !22_38 16_38 23_38 24_38 25_38
INT_R.IMUX44.NN2END2 origin:050-pip-seed !22_38 !23_38 !24_38 17_38 25_38
@ -1766,9 +1766,9 @@ INT_R.IMUX45.ER1END2 origin:050-pip-seed !23_46 18_47 22_46 24_46 25_46
INT_R.IMUX45.FAN_BOUNCE3 origin:050-pip-seed !22_46 20_46 23_46 24_46 25_46
INT_R.IMUX45.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_46 20_46 22_46 24_46 25_46
INT_R.IMUX45.GFAN1 origin:049-int-imux-gfan !22_46 !23_46 !24_46 21_46 25_46
INT_R.IMUX45.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_46 21_46 23_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_46 !23_46 !25_46 21_46 24_46
INT_R.IMUX45.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_46 21_46 22_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_R.IMUX45.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_R.IMUX45.NE2END3 origin:050-pip-seed !22_46 !23_46 !25_46 18_47 24_46
INT_R.IMUX45.NL1BEG_N3 origin:050-pip-seed !22_46 16_46 23_46 24_46 25_46
INT_R.IMUX45.NN2END3 origin:050-pip-seed !22_46 !23_46 !24_46 18_47 25_46
@ -1791,8 +1791,8 @@ INT_R.IMUX46.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_54 20_54 23_54 24_54 25_54
INT_R.IMUX46.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_54 20_54 22_54 24_54 25_54
INT_R.IMUX46.GFAN1 origin:049-int-imux-gfan !22_54 !23_54 !24_54 21_54 25_54
INT_R.IMUX46.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_54 21_54 23_54 24_54 25_54
INT_R.IMUX46.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_54 !23_54 !25_54 21_54 24_54
INT_R.IMUX46.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_54 21_54 22_54 24_54 25_54
INT_R.IMUX46.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_R.IMUX46.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_R.IMUX46.NE2END3 origin:050-pip-seed !22_54 !23_54 !25_54 17_54 24_54
INT_R.IMUX46.NL1BEG_N3 origin:050-pip-seed !22_54 16_54 23_54 24_54 25_54
INT_R.IMUX46.NN2END3 origin:050-pip-seed !22_54 !23_54 !24_54 17_54 25_54
@ -1815,8 +1815,8 @@ INT_R.IMUX47.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_62 20_62 23_62 24_62 25_62
INT_R.IMUX47.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_62 20_62 22_62 24_62 25_62
INT_R.IMUX47.GFAN1 origin:049-int-imux-gfan !22_62 !23_62 !24_62 21_62 25_62
INT_R.IMUX47.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_62 21_62 23_62 24_62 25_62
INT_R.IMUX47.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_62 !23_62 !25_62 21_62 24_62
INT_R.IMUX47.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_62 21_62 22_62 24_62 25_62
INT_R.IMUX47.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_R.IMUX47.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_R.IMUX47.NE2END_S3_0 origin:050-pip-seed !22_62 !23_62 !25_62 18_63 24_62
INT_R.IMUX47.NL1END_S3_0 origin:050-pip-seed !22_62 16_62 23_62 24_62 25_62
INT_R.IMUX47.NN2END_S2_0 origin:050-pip-seed !22_62 !23_62 !24_62 18_63 25_62
@ -1838,9 +1838,9 @@ INT_R.IMUX5.ER1END2 origin:050-pip-seed !22_41 19_40 23_41 24_41 25_41
INT_R.IMUX5.FAN_BOUNCE3 origin:050-pip-seed !23_41 21_41 22_41 24_41 25_41
INT_R.IMUX5.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_41 21_41 23_41 24_41 25_41
INT_R.IMUX5.GFAN1 origin:049-int-imux-gfan !22_41 !23_41 !25_41 20_41 24_41
INT_R.IMUX5.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_41 20_41 22_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_41 !23_41 !24_41 20_41 25_41
INT_R.IMUX5.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_41 20_41 23_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_R.IMUX5.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_R.IMUX5.NE2END2 origin:050-pip-seed !22_41 !23_41 !24_41 19_40 25_41
INT_R.IMUX5.NL1BEG_N3 origin:050-pip-seed !23_41 17_41 22_41 24_41 25_41
INT_R.IMUX5.NN2END2 origin:050-pip-seed !22_41 !23_41 !25_41 19_40 24_41
@ -1862,9 +1862,9 @@ INT_R.IMUX6.ER1END2 origin:050-pip-seed !22_49 18_48 23_49 24_49 25_49
INT_R.IMUX6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_49 21_49 22_49 24_49 25_49
INT_R.IMUX6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_49 21_49 23_49 24_49 25_49
INT_R.IMUX6.GFAN1 origin:049-int-imux-gfan !22_49 !23_49 !25_49 20_49 24_49
INT_R.IMUX6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_49 20_49 22_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_49 !23_49 !24_49 20_49 25_49
INT_R.IMUX6.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_49 20_49 23_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_R.IMUX6.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_R.IMUX6.NE2END3 origin:050-pip-seed !22_49 !23_49 !24_49 16_49 25_49
INT_R.IMUX6.NL1BEG_N3 origin:050-pip-seed !23_49 17_49 22_49 24_49 25_49
INT_R.IMUX6.NN2END3 origin:050-pip-seed !22_49 !23_49 !25_49 16_49 24_49
@ -1886,9 +1886,9 @@ INT_R.IMUX7.ER1END3 origin:050-pip-seed !22_57 19_56 23_57 24_57 25_57
INT_R.IMUX7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_57 21_57 22_57 24_57 25_57
INT_R.IMUX7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_57 21_57 23_57 24_57 25_57
INT_R.IMUX7.GFAN1 origin:049-int-imux-gfan !22_57 !23_57 !25_57 20_57 24_57
INT_R.IMUX7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_57 20_57 22_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_57 !23_57 !24_57 20_57 25_57
INT_R.IMUX7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_57 20_57 23_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_R.IMUX7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_R.IMUX7.NE2END3 origin:050-pip-seed !22_57 !23_57 !24_57 19_56 25_57
INT_R.IMUX7.NL1END_S3_0 origin:050-pip-seed !23_57 17_57 22_57 24_57 25_57
INT_R.IMUX7.NN2END3 origin:050-pip-seed !22_57 !23_57 !25_57 19_56 24_57
@ -1910,9 +1910,9 @@ INT_R.IMUX8.ER1END_N3_3 origin:050-pip-seed !23_02 17_02 22_02 24_02 25_02
INT_R.IMUX8.FAN_BOUNCE2 origin:050-pip-seed !23_02 20_02 22_02 24_02 25_02
INT_R.IMUX8.FAN_BOUNCE7 origin:050-pip-seed !22_02 20_02 23_02 24_02 25_02
INT_R.IMUX8.GFAN0 origin:049-int-imux-gfan !22_02 !23_02 !24_02 21_02 25_02
INT_R.IMUX8.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_02 21_02 22_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_02 21_02 23_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_02 !23_02 !25_02 21_02 24_02
INT_R.IMUX8.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_R.IMUX8.NE2END0 origin:050-pip-seed !22_02 !23_02 !25_02 17_02 24_02
INT_R.IMUX8.NL1END0 origin:050-pip-seed !22_02 16_02 23_02 24_02 25_02
INT_R.IMUX8.NN2END0 origin:050-pip-seed !22_02 !23_02 !24_02 17_02 25_02
@ -1934,8 +1934,8 @@ INT_R.IMUX9.ER1END0 origin:050-pip-seed !23_10 18_11 22_10 24_10 25_10
INT_R.IMUX9.FAN_BOUNCE5 origin:050-pip-seed !22_10 20_10 23_10 24_10 25_10
INT_R.IMUX9.FAN_BOUNCE6 origin:050-pip-seed !23_10 20_10 22_10 24_10 25_10
INT_R.IMUX9.GFAN0 origin:049-int-imux-gfan !22_10 !23_10 !24_10 21_10 25_10
INT_R.IMUX9.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts,050-pip-seed !22_10 !23_10 !25_10 21_10 24_10
INT_R.IMUX9.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts,050-pip-seed !23_10 21_10 22_10 24_10 25_10
INT_R.IMUX9.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_R.IMUX9.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_R.IMUX9.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_10 21_10 23_10 24_10 25_10
INT_R.IMUX9.NE2END0 origin:050-pip-seed !22_10 !23_10 !25_10 16_10 24_10
INT_R.IMUX9.NL1END1 origin:050-pip-seed !22_10 16_10 23_10 24_10 25_10
@ -3295,7 +3295,7 @@ INT_R.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
INT_R.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
INT_R.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_60 07_61
INT_R.SW6BEG3.LOGIC_OUTS15 origin:050-pip-seed 03_60 04_62
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_33 07_33
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_49 07_49
INT_R.WW4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_49 04_50
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49

1170
artix7/tilegrid.json
View File

File diff suppressed because it is too large Load Diff

6
artix7/timings/BRAM_INT_INTERFACE_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRAM_INT_INTERFACE_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

336
artix7/timings/BRAM_L.sdf
View File

@ -3,4 +3,340 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "RAMBFIFO36E1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ADDRA15L (posedge CLKARDCLKU) (-0.515::0.357))
(SETUP ADDRA15L (posedge CLKARDCLKU) (-0.357::0.515))
(HOLD ADDRAU (posedge CLKARDCLKU) (-0.566::0.360))
(SETUP ADDRAU (posedge CLKARDCLKU) (-0.360::0.566))
(HOLD ADDRB15L (posedge CLKBWRCLKU) (-0.515::0.357))
(SETUP ADDRB15L (posedge CLKBWRCLKU) (-0.357::0.515))
(HOLD ADDRBU (posedge CLKBWRCLKU) (-0.566::0.360))
(SETUP ADDRBU (posedge CLKBWRCLKU) (-0.360::0.566))
(HOLD WEAU (posedge CLKARDCLKU) (-0.532::0.197))
(SETUP WEAU (posedge CLKARDCLKU) (-0.197::0.532))
(HOLD WEBU (posedge CLKBWRCLKU) (-0.532::0.197))
(SETUP WEBU (posedge CLKBWRCLKU) (-0.197::0.532))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_L_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAL (posedge CLKARDCLKL) (-0.342::0.067))
(SETUP RSTREGAL (posedge CLKARDCLKL) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAU (posedge CLKARDCLKU) (-0.342::0.067))
(SETUP RSTREGAU (posedge CLKARDCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_L_1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge REGCLKBU) (-0.360::0.155))
(SETUP REGCEBU (posedge REGCLKBU) (-0.155::0.360))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge CLKBWRCLKU) (-0.360::0.155))
(SETUP REGCEBU (posedge CLKBWRCLKU) (-0.155::0.360))
(HOLD RSTREGBU (posedge CLKBWRCLKU) (-0.342::0.067))
(SETUP RSTREGBU (posedge CLKBWRCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1_IS18K_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH REGCLKBU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH REGCLKBU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ENARDENU (posedge CLKARDCLKU) (-0.443::0.227))
(SETUP ENARDENU (posedge CLKARDCLKU) (-0.227::0.443))
(HOLD ENBWRENU (posedge CLKBWRCLKU) (-0.443::0.227))
(SETUP ENBWRENU (posedge CLKBWRCLKU) (-0.227::0.443))
(HOLD RSTRAMAU (posedge CLKARDCLKU) (-0.359::0.453))
(SETUP RSTRAMAU (posedge CLKARDCLKU) (-0.453::0.359))
(HOLD RSTRAMBU (posedge CLKBWRCLKU) (-0.359::0.453))
(SETUP RSTRAMBU (posedge CLKBWRCLKU) (-0.453::0.359))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL ALMOSTEMPTY (0.256::0.290)(0.530::0.864))
(IOPATH CLKARDCLKL EMPTY (0.251::0.295)(0.521::0.875))
(IOPATH CLKARDCLKL RDCOUNT (0.318::0.407)(0.660::1.147))
(IOPATH CLKARDCLKL RDERR (0.269::0.313)(0.562::0.981))
(IOPATH CLKBWRCLKL ALMOSTFULL (0.268::0.313)(0.558::0.919))
(IOPATH CLKBWRCLKL FULL (0.266::0.313)(0.555::1.041))
(IOPATH CLKBWRCLKL WRCOUNT (0.340::0.395)(0.701::1.106))
(IOPATH CLKBWRCLKL WRERR (0.265::0.313)(0.549::0.914))
(IOPATH RSTRAMARSTL ALMOSTEMPTY (0.271::0.324)(0.552::0.963))
(IOPATH RSTRAMARSTL ALMOSTFULL (0.284::0.333)(0.585::0.990))
(IOPATH RSTRAMARSTL EMPTY (0.279::0.321)(0.575::0.960))
(IOPATH RSTRAMARSTL FULL (0.283::0.329)(0.586::0.983))
(IOPATH RSTRAMARSTL RDCOUNT (0.315::0.378)(0.637::1.093))
(IOPATH RSTRAMARSTL RDERR (0.292::0.338)(0.594::1.005))
(IOPATH RSTRAMARSTL WRCOUNT (0.322::0.378)(0.660::1.097))
(IOPATH RSTRAMARSTL WRERR (0.287::0.331)(0.587::0.982))
)
)
(TIMINGCHECK
(HOLD ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(SETUP ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(HOLD ENBWRENL (posedge CLKBWRCLKL) (-0.466::0.426))
(SETUP ENBWRENL (posedge CLKBWRCLKL) (-0.426::0.466))
(RECOVERY RSTRAMARSTL (posedge CLKARDCLKL) (0.957::2.368))
(REMOVAL RSTRAMARSTL (posedge CLKARDCLKL) (-2.368::-0.957))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_36_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIADIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPADIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPADIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIBDIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIBDIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPBDIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPBDIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPADOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPADOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPBDOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPBDOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKBWRCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKBWRCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
)

336
artix7/timings/BRAM_R.sdf
View File

@ -3,4 +3,340 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "RAMBFIFO36E1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ADDRA15L (posedge CLKARDCLKU) (-0.515::0.357))
(SETUP ADDRA15L (posedge CLKARDCLKU) (-0.357::0.515))
(HOLD ADDRAU (posedge CLKARDCLKU) (-0.566::0.360))
(SETUP ADDRAU (posedge CLKARDCLKU) (-0.360::0.566))
(HOLD ADDRB15L (posedge CLKBWRCLKU) (-0.515::0.357))
(SETUP ADDRB15L (posedge CLKBWRCLKU) (-0.357::0.515))
(HOLD ADDRBU (posedge CLKBWRCLKU) (-0.566::0.360))
(SETUP ADDRBU (posedge CLKBWRCLKU) (-0.360::0.566))
(HOLD WEAU (posedge CLKARDCLKU) (-0.532::0.197))
(SETUP WEAU (posedge CLKARDCLKU) (-0.197::0.532))
(HOLD WEBU (posedge CLKBWRCLKU) (-0.532::0.197))
(SETUP WEBU (posedge CLKBWRCLKU) (-0.197::0.532))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_L_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAL (posedge CLKARDCLKL) (-0.342::0.067))
(SETUP RSTREGAL (posedge CLKARDCLKL) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAU (posedge CLKARDCLKU) (-0.342::0.067))
(SETUP RSTREGAU (posedge CLKARDCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_L_1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge REGCLKBU) (-0.360::0.155))
(SETUP REGCEBU (posedge REGCLKBU) (-0.155::0.360))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge CLKBWRCLKU) (-0.360::0.155))
(SETUP REGCEBU (posedge CLKBWRCLKU) (-0.155::0.360))
(HOLD RSTREGBU (posedge CLKBWRCLKU) (-0.342::0.067))
(SETUP RSTREGBU (posedge CLKBWRCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1_IS18K_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH REGCLKBU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH REGCLKBU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ENARDENU (posedge CLKARDCLKU) (-0.443::0.227))
(SETUP ENARDENU (posedge CLKARDCLKU) (-0.227::0.443))
(HOLD ENBWRENU (posedge CLKBWRCLKU) (-0.443::0.227))
(SETUP ENBWRENU (posedge CLKBWRCLKU) (-0.227::0.443))
(HOLD RSTRAMAU (posedge CLKARDCLKU) (-0.359::0.453))
(SETUP RSTRAMAU (posedge CLKARDCLKU) (-0.453::0.359))
(HOLD RSTRAMBU (posedge CLKBWRCLKU) (-0.359::0.453))
(SETUP RSTRAMBU (posedge CLKBWRCLKU) (-0.453::0.359))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL ALMOSTEMPTY (0.256::0.290)(0.530::0.864))
(IOPATH CLKARDCLKL EMPTY (0.251::0.295)(0.521::0.875))
(IOPATH CLKARDCLKL RDCOUNT (0.318::0.407)(0.660::1.147))
(IOPATH CLKARDCLKL RDERR (0.269::0.313)(0.562::0.981))
(IOPATH CLKBWRCLKL ALMOSTFULL (0.268::0.313)(0.558::0.919))
(IOPATH CLKBWRCLKL FULL (0.266::0.313)(0.555::1.041))
(IOPATH CLKBWRCLKL WRCOUNT (0.340::0.395)(0.701::1.106))
(IOPATH CLKBWRCLKL WRERR (0.265::0.313)(0.549::0.914))
(IOPATH RSTRAMARSTL ALMOSTEMPTY (0.271::0.324)(0.552::0.963))
(IOPATH RSTRAMARSTL ALMOSTFULL (0.284::0.333)(0.585::0.990))
(IOPATH RSTRAMARSTL EMPTY (0.279::0.321)(0.575::0.960))
(IOPATH RSTRAMARSTL FULL (0.283::0.329)(0.586::0.983))
(IOPATH RSTRAMARSTL RDCOUNT (0.315::0.378)(0.637::1.093))
(IOPATH RSTRAMARSTL RDERR (0.292::0.338)(0.594::1.005))
(IOPATH RSTRAMARSTL WRCOUNT (0.322::0.378)(0.660::1.097))
(IOPATH RSTRAMARSTL WRERR (0.287::0.331)(0.587::0.982))
)
)
(TIMINGCHECK
(HOLD ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(SETUP ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(HOLD ENBWRENL (posedge CLKBWRCLKL) (-0.466::0.426))
(SETUP ENBWRENL (posedge CLKBWRCLKL) (-0.426::0.466))
(RECOVERY RSTRAMARSTL (posedge CLKARDCLKL) (0.957::2.368))
(REMOVAL RSTRAMARSTL (posedge CLKARDCLKL) (-2.368::-0.957))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_36_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIADIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPADIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPADIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIBDIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIBDIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPBDIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPBDIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPADOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPADOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPBDOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPBDOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKBWRCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKBWRCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
)

6
artix7/timings/BRKH_BRAM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_B_TERM_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_CLB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_CLK.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_CMT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_DSP_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_DSP_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_GTX.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/BRKH_TERM_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/B_TERM_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CFG_CENTER_BOT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

15
artix7/timings/CFG_CENTER_MID.sdf
View File

@ -14,19 +14,18 @@
(CELL
(CELLTYPE "ICAP")
(INSTANCE ICAP)
(DELAY
(ABSOLUTE
(IOPATH CLK O (3.616::4.160)(4.520::5.200))
)
)
(TIMINGCHECK
(HOLD CSIB (posedge CLK) (0.000::0.000))
(SETUP CSIB (posedge CLK) (3.390::3.900))
(HOLD I (posedge CLK) (0.000::0.000))
(SETUP I (posedge CLK) (2.237::2.574))
(HOLD RDWRB (posedge CLK) (0.000::0.000))
(SETUP RDWRB (posedge CLK) (5.587::6.427))
)
)
(CELL
(CELLTYPE "ICAP_I")
(INSTANCE ICAP)
(TIMINGCHECK
(HOLD CLK (posedge CLK) (0.000::0.000))
(SETUP CLK (posedge CLK) (2.237::2.574))
)
)
)

42
artix7/timings/CLBLL_L.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)

42
artix7/timings/CLBLL_R.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)

84
artix7/timings/CLBLM_L.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)
@ -720,15 +754,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.184::0.229)(0.455::0.565))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -737,6 +774,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.648::0.804))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -811,15 +853,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.211::0.262))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.197::0.245)(0.489::0.606))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -828,6 +873,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.247::0.308)(0.689::0.855))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -868,6 +918,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.161::0.201)(0.493::0.611))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.645::0.800))
)
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5LRAM")
(INSTANCE SLICEM/A5LUT)

84
artix7/timings/CLBLM_R.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)
@ -720,15 +754,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.184::0.229)(0.455::0.565))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -737,6 +774,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.648::0.804))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -811,15 +853,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.211::0.262))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.197::0.245)(0.489::0.606))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -828,6 +873,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.247::0.308)(0.689::0.855))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -868,6 +918,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.161::0.201)(0.493::0.611))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.645::0.800))
)
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5LRAM")
(INSTANCE SLICEM/A5LUT)

6
artix7/timings/CLK_BUFG_REBUF.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_FEED.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

9
artix7/timings/CLK_HROW_BOT_R.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFHCE")
(INSTANCE BUFHCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.020::0.043)(0.081::0.127))
)
)
)
(CELL
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
(INSTANCE BUFHCE)

9
artix7/timings/CLK_HROW_TOP_R.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFHCE")
(INSTANCE BUFHCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.020::0.043)(0.081::0.127))
)
)
)
(CELL
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
(INSTANCE BUFHCE)

6
artix7/timings/CLK_MTBF2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_PMV.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_PMV2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_PMV2_SVT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_PMVIOB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CLK_TERM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

36
artix7/timings/CMT_FIFO_L.sdf
View File

@ -6,6 +6,24 @@
(CELL
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
(INSTANCE IN_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
(IOPATH RDCLK Q0 (0.142::0.163)(0.517::0.595))
(IOPATH RDCLK Q1 (0.142::0.163)(0.556::0.640))
(IOPATH RDCLK Q2 (0.150::0.173)(0.548::0.630))
(IOPATH RDCLK Q3 (0.154::0.177)(0.583::0.671))
(IOPATH RDCLK Q4 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q5 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q6 (0.142::0.163)(0.492::0.566))
(IOPATH RDCLK Q7 (0.151::0.174)(0.550::0.632))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
(SETUP D0 (posedge WRCLK) (0.473::0.544))
@ -32,6 +50,24 @@
(CELL
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
(INSTANCE OUT_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
(IOPATH RDCLK Q0 (0.145::0.166)(0.586::0.674))
(IOPATH RDCLK Q1 (0.141::0.162)(0.586::0.674))
(IOPATH RDCLK Q2 (0.138::0.159)(0.586::0.674))
(IOPATH RDCLK Q3 (0.143::0.164)(0.586::0.674))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH RDEN Q0 (0.040::0.046)(0.161::0.185))
(IOPATH RDEN Q1 (0.042::0.049)(0.168::0.193))
(IOPATH RDEN Q2 (0.032::0.036)(0.143::0.164))
(IOPATH RDEN Q3 (0.033::0.038)(0.149::0.172))
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
(SETUP D0 (posedge WRCLK) (0.381::0.438))

36
artix7/timings/CMT_FIFO_R.sdf
View File

@ -6,6 +6,24 @@
(CELL
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
(INSTANCE IN_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
(IOPATH RDCLK Q0 (0.142::0.163)(0.517::0.595))
(IOPATH RDCLK Q1 (0.142::0.163)(0.556::0.640))
(IOPATH RDCLK Q2 (0.150::0.173)(0.548::0.630))
(IOPATH RDCLK Q3 (0.154::0.177)(0.583::0.671))
(IOPATH RDCLK Q4 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q5 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q6 (0.142::0.163)(0.492::0.566))
(IOPATH RDCLK Q7 (0.151::0.174)(0.550::0.632))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
(SETUP D0 (posedge WRCLK) (0.473::0.544))
@ -32,6 +50,24 @@
(CELL
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
(INSTANCE OUT_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
(IOPATH RDCLK Q0 (0.145::0.166)(0.586::0.674))
(IOPATH RDCLK Q1 (0.141::0.162)(0.586::0.674))
(IOPATH RDCLK Q2 (0.138::0.159)(0.586::0.674))
(IOPATH RDCLK Q3 (0.143::0.164)(0.586::0.674))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH RDEN Q0 (0.040::0.046)(0.161::0.185))
(IOPATH RDEN Q1 (0.042::0.049)(0.168::0.193))
(IOPATH RDEN Q2 (0.032::0.036)(0.143::0.164))
(IOPATH RDEN Q3 (0.033::0.038)(0.149::0.172))
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
(SETUP D0 (posedge WRCLK) (0.381::0.438))

6
artix7/timings/CMT_PMV.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/CMT_PMV_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

261
artix7/timings/CMT_TOP_L_LOWER_B.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
@ -29,229 +32,229 @@
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

36
artix7/timings/CMT_TOP_L_LOWER_T.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))

53
artix7/timings/CMT_TOP_L_UPPER_B.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -496,6 +510,23 @@
(CELL
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
(INSTANCE PHY_CONTROL)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK AUXOUTPUT (0.265::0.305)(0.542::0.624))
(IOPATH MEMREFCLK INBURSTPENDING (0.316::0.363)(0.689::0.792))
(IOPATH MEMREFCLK INRANKA (0.306::0.353)(0.660::0.759))
(IOPATH MEMREFCLK INRANKB (0.316::0.363)(0.688::0.791))
(IOPATH MEMREFCLK INRANKC (0.319::0.367)(0.697::0.802))
(IOPATH MEMREFCLK INRANKD (0.310::0.357)(0.667::0.768))
(IOPATH MEMREFCLK OUTBURSTPENDING (0.311::0.358)(0.676::0.778))
(IOPATH MEMREFCLK PCENABLECALIB (0.265::0.305)(0.590::0.679))
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
(IOPATH MEMREFCLK TESTOUTPUT (0.504::0.579)(1.131::1.301))
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
)
)
(TIMINGCHECK
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))

132
artix7/timings/CMT_TOP_L_UPPER_T.sdf
View File

@ -8,6 +8,8 @@
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
)
)
@ -23,109 +25,109 @@
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

261
artix7/timings/CMT_TOP_R_LOWER_B.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
@ -29,229 +32,229 @@
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

36
artix7/timings/CMT_TOP_R_LOWER_T.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))

53
artix7/timings/CMT_TOP_R_UPPER_B.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -496,6 +510,23 @@
(CELL
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
(INSTANCE PHY_CONTROL)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK AUXOUTPUT (0.265::0.305)(0.542::0.624))
(IOPATH MEMREFCLK INBURSTPENDING (0.316::0.363)(0.689::0.792))
(IOPATH MEMREFCLK INRANKA (0.306::0.353)(0.660::0.759))
(IOPATH MEMREFCLK INRANKB (0.316::0.363)(0.688::0.791))
(IOPATH MEMREFCLK INRANKC (0.319::0.367)(0.697::0.802))
(IOPATH MEMREFCLK INRANKD (0.310::0.357)(0.667::0.768))
(IOPATH MEMREFCLK OUTBURSTPENDING (0.311::0.358)(0.676::0.778))
(IOPATH MEMREFCLK PCENABLECALIB (0.265::0.305)(0.590::0.679))
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
(IOPATH MEMREFCLK TESTOUTPUT (0.504::0.579)(1.131::1.301))
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
)
)
(TIMINGCHECK
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))

132
artix7/timings/CMT_TOP_R_UPPER_T.sdf
View File

@ -8,6 +8,8 @@
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
)
)
@ -23,109 +25,109 @@
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

138
artix7/timings/GTP_CHANNEL_0.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH DMONITORCLK DMONITOROUT (0.485::0.515)(0.859::0.912))
(IOPATH DRPCLK DRPDO (0.693::0.736)(1.560::1.657))
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
@ -15,6 +18,39 @@
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
(IOPATH RXUSRCLK2 RXBUFSTATUS (0.507::0.538)(1.040::1.104))
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
(IOPATH RXUSRCLK2 RXCHARISCOMMA (0.503::0.534)(1.020::1.083))
(IOPATH RXUSRCLK2 RXCHARISK (0.487::0.517)(1.025::1.088))
(IOPATH RXUSRCLK2 RXCLKCORCNT (0.511::0.543)(0.996::1.058))
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
(IOPATH RXUSRCLK2 RXDATA (0.472::0.501)(1.061::1.127))
(IOPATH RXUSRCLK2 RXDATAVALID (0.547::0.581)(1.112::1.181))
(IOPATH RXUSRCLK2 RXDISPERR (0.509::0.541)(1.073::1.139))
(IOPATH RXUSRCLK2 RXHEADER (0.536::0.569)(1.074::1.141))
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
(IOPATH RXUSRCLK2 RXNOTINTABLE (0.495::0.526)(1.034::1.098))
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
(IOPATH RXUSRCLK2 RXSTARTOFSEQ (0.495::0.526)(0.907::0.963))
(IOPATH RXUSRCLK2 RXSTATUS (0.507::0.538)(1.055::1.120))
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
(IOPATH SCANCLK SCANOUT (0.968::1.114)(2.002::2.304))
(IOPATH TXUSRCLK2 TXBUFSTATUS (0.472::0.501)(1.000::1.062))
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
(IOPATH TXUSRCLK2 TXRUNDISP (0.493::0.524)(1.015::1.078))
)
)
(TIMINGCHECK
@ -109,67 +145,107 @@
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
@ -178,6 +254,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK) (0.444::0.472))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.466::0.495))
)
)
(CELL
@ -186,16 +264,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK2) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK2) (0.444::0.472))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
(INSTANCE GTPE2_CHANNEL)
(TIMINGCHECK
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.466::0.495))
)
)
)

138
artix7/timings/GTP_CHANNEL_1.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH DMONITORCLK DMONITOROUT (0.485::0.515)(0.859::0.912))
(IOPATH DRPCLK DRPDO (0.693::0.736)(1.560::1.657))
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
@ -15,6 +18,39 @@
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
(IOPATH RXUSRCLK2 RXBUFSTATUS (0.507::0.538)(1.040::1.104))
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
(IOPATH RXUSRCLK2 RXCHARISCOMMA (0.503::0.534)(1.020::1.083))
(IOPATH RXUSRCLK2 RXCHARISK (0.487::0.517)(1.025::1.088))
(IOPATH RXUSRCLK2 RXCLKCORCNT (0.511::0.543)(0.996::1.058))
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
(IOPATH RXUSRCLK2 RXDATA (0.472::0.501)(1.061::1.127))
(IOPATH RXUSRCLK2 RXDATAVALID (0.547::0.581)(1.112::1.181))
(IOPATH RXUSRCLK2 RXDISPERR (0.509::0.541)(1.073::1.139))
(IOPATH RXUSRCLK2 RXHEADER (0.536::0.569)(1.074::1.141))
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
(IOPATH RXUSRCLK2 RXNOTINTABLE (0.495::0.526)(1.034::1.098))
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
(IOPATH RXUSRCLK2 RXSTARTOFSEQ (0.495::0.526)(0.907::0.963))
(IOPATH RXUSRCLK2 RXSTATUS (0.507::0.538)(1.055::1.120))
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
(IOPATH SCANCLK SCANOUT (0.968::1.114)(2.002::2.304))
(IOPATH TXUSRCLK2 TXBUFSTATUS (0.472::0.501)(1.000::1.062))
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
(IOPATH TXUSRCLK2 TXRUNDISP (0.493::0.524)(1.015::1.078))
)
)
(TIMINGCHECK
@ -109,67 +145,107 @@
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
@ -178,6 +254,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK) (0.444::0.472))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.466::0.495))
)
)
(CELL
@ -186,16 +264,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK2) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK2) (0.444::0.472))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
(INSTANCE GTPE2_CHANNEL)
(TIMINGCHECK
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.466::0.495))
)
)
)

138
artix7/timings/GTP_CHANNEL_2.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH DMONITORCLK DMONITOROUT (0.485::0.515)(0.859::0.912))
(IOPATH DRPCLK DRPDO (0.693::0.736)(1.560::1.657))
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
@ -15,6 +18,39 @@
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
(IOPATH RXUSRCLK2 RXBUFSTATUS (0.507::0.538)(1.040::1.104))
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
(IOPATH RXUSRCLK2 RXCHARISCOMMA (0.503::0.534)(1.020::1.083))
(IOPATH RXUSRCLK2 RXCHARISK (0.487::0.517)(1.025::1.088))
(IOPATH RXUSRCLK2 RXCLKCORCNT (0.511::0.543)(0.996::1.058))
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
(IOPATH RXUSRCLK2 RXDATA (0.472::0.501)(1.061::1.127))
(IOPATH RXUSRCLK2 RXDATAVALID (0.547::0.581)(1.112::1.181))
(IOPATH RXUSRCLK2 RXDISPERR (0.509::0.541)(1.073::1.139))
(IOPATH RXUSRCLK2 RXHEADER (0.536::0.569)(1.074::1.141))
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
(IOPATH RXUSRCLK2 RXNOTINTABLE (0.495::0.526)(1.034::1.098))
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
(IOPATH RXUSRCLK2 RXSTARTOFSEQ (0.495::0.526)(0.907::0.963))
(IOPATH RXUSRCLK2 RXSTATUS (0.507::0.538)(1.055::1.120))
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
(IOPATH SCANCLK SCANOUT (0.968::1.114)(2.002::2.304))
(IOPATH TXUSRCLK2 TXBUFSTATUS (0.472::0.501)(1.000::1.062))
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
(IOPATH TXUSRCLK2 TXRUNDISP (0.493::0.524)(1.015::1.078))
)
)
(TIMINGCHECK
@ -109,67 +145,107 @@
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
@ -178,6 +254,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK) (0.444::0.472))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.466::0.495))
)
)
(CELL
@ -186,16 +264,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK2) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK2) (0.444::0.472))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
(INSTANCE GTPE2_CHANNEL)
(TIMINGCHECK
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.466::0.495))
)
)
)

138
artix7/timings/GTP_CHANNEL_3.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH DMONITORCLK DMONITOROUT (0.485::0.515)(0.859::0.912))
(IOPATH DRPCLK DRPDO (0.693::0.736)(1.560::1.657))
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
(IOPATH PMASCANCLK0 PMASCANOUT6 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT0 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK1 PMASCANOUT1 (0.452::0.720)(1.657::2.640))
@ -15,6 +18,39 @@
(IOPATH PMASCANCLK1 PMASCANOUT3 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK2 PMASCANOUT4 (0.452::0.720)(1.657::2.640))
(IOPATH PMASCANCLK3 PMASCANOUT5 (0.452::0.720)(1.657::2.640))
(IOPATH RXUSRCLK2 PHYSTATUS (0.472::0.501)(1.021::1.084))
(IOPATH RXUSRCLK2 RXBUFSTATUS (0.507::0.538)(1.040::1.104))
(IOPATH RXUSRCLK2 RXBYTEISALIGNED (0.490::0.520)(1.012::1.075))
(IOPATH RXUSRCLK2 RXBYTEREALIGN (0.492::0.522)(1.001::1.063))
(IOPATH RXUSRCLK2 RXCHANBONDSEQ (0.449::0.477)(1.030::1.094))
(IOPATH RXUSRCLK2 RXCHANISALIGNED (0.498::0.529)(1.002::1.064))
(IOPATH RXUSRCLK2 RXCHANREALIGN (0.452::0.480)(1.022::1.085))
(IOPATH RXUSRCLK2 RXCHARISCOMMA (0.503::0.534)(1.020::1.083))
(IOPATH RXUSRCLK2 RXCHARISK (0.487::0.517)(1.025::1.088))
(IOPATH RXUSRCLK2 RXCLKCORCNT (0.511::0.543)(0.996::1.058))
(IOPATH RXUSRCLK2 RXCOMINITDET (0.494::0.525)(0.978::1.039))
(IOPATH RXUSRCLK2 RXCOMMADET (0.445::0.473)(0.921::0.978))
(IOPATH RXUSRCLK2 RXCOMSASDET (0.511::0.543)(1.026::1.090))
(IOPATH RXUSRCLK2 RXCOMWAKEDET (0.509::0.541)(1.054::1.119))
(IOPATH RXUSRCLK2 RXDATA (0.472::0.501)(1.061::1.127))
(IOPATH RXUSRCLK2 RXDATAVALID (0.547::0.581)(1.112::1.181))
(IOPATH RXUSRCLK2 RXDISPERR (0.509::0.541)(1.073::1.139))
(IOPATH RXUSRCLK2 RXHEADER (0.536::0.569)(1.074::1.141))
(IOPATH RXUSRCLK2 RXHEADERVALID (0.437::0.464)(0.991::1.052))
(IOPATH RXUSRCLK2 RXNOTINTABLE (0.495::0.526)(1.034::1.098))
(IOPATH RXUSRCLK2 RXPRBSERR (0.470::0.499)(0.955::1.014))
(IOPATH RXUSRCLK2 RXRATEDONE (0.471::0.500)(0.962::1.022))
(IOPATH RXUSRCLK2 RXRESETDONE (0.525::0.558)(0.954::1.013))
(IOPATH RXUSRCLK2 RXSTARTOFSEQ (0.495::0.526)(0.907::0.963))
(IOPATH RXUSRCLK2 RXSTATUS (0.507::0.538)(1.055::1.120))
(IOPATH RXUSRCLK2 RXVALID (0.480::0.510)(1.016::1.079))
(IOPATH SCANCLK SCANOUT (0.968::1.114)(2.002::2.304))
(IOPATH TXUSRCLK2 TXBUFSTATUS (0.472::0.501)(1.000::1.062))
(IOPATH TXUSRCLK2 TXCOMFINISH (0.899::1.055)(1.101::1.293))
(IOPATH TXUSRCLK2 TXGEARBOXREADY (0.470::0.499)(1.026::1.090))
(IOPATH TXUSRCLK2 TXRATEDONE (0.487::0.517)(1.005::1.067))
(IOPATH TXUSRCLK2 TXRESETDONE (0.482::0.512)(0.973::1.033))
(IOPATH TXUSRCLK2 TXRUNDISP (0.493::0.524)(1.015::1.078))
)
)
(TIMINGCHECK
@ -109,67 +145,107 @@
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_FALSE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_FALSE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_16")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_16")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_20")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_20")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK2 RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RX_DATA_WIDTH (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RX_DATA_WIDTH (posedge RXUSRCLK2) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK2) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK2) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_32")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_32")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_RXCHBONDI_GEN_TRUE_RX_DATA_WIDTH_40")
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_GEN_RXUSRCLK_TRUE_RX_DATA_WIDTH_40")
(INSTANCE GTPE2_CHANNEL)
(DELAY
(ABSOLUTE
(IOPATH RXUSRCLK RXCHBONDO (0.532::0.625)(0.979::1.149))
)
)
(TIMINGCHECK
(HOLD RXUSRCLK (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXUSRCLK (posedge RXUSRCLK) (0.328::0.378))
(HOLD RXCHBONDI (posedge RXUSRCLK) (0.159::0.183))
(SETUP RXCHBONDI (posedge RXUSRCLK) (0.328::0.378))
)
)
(CELL
@ -178,6 +254,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK) (0.444::0.472))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK) (0.466::0.495))
)
)
(CELL
@ -186,16 +264,8 @@
(TIMINGCHECK
(HOLD TXPIPPMEN (posedge TXUSRCLK2) (0.121::0.129))
(SETUP TXPIPPMEN (posedge TXUSRCLK2) (0.444::0.472))
)
)
(CELL
(CELLTYPE "GTPE2_CHANNEL_GTPE2_CHANNELGTPE2_CHANNEL_TXPIPPMSTEPSIZE_TXPI_PPMCLK_SEL")
(INSTANCE GTPE2_CHANNEL)
(TIMINGCHECK
(HOLD TXUSRCLK2 (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXUSRCLK2 (posedge TXUSRCLK2) (0.466::0.495))
(HOLD TXUSRCLK (posedge TXUSRCLK) (0.158::0.168))
(SETUP TXUSRCLK (posedge TXUSRCLK) (0.466::0.495))
(HOLD TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.158::0.168))
(SETUP TXPIPPMSTEPSIZE (posedge TXUSRCLK2) (0.466::0.495))
)
)
)

2
artix7/timings/GTP_COMMON.sdf
View File

@ -8,6 +8,8 @@
(INSTANCE GTPE2_COMMON)
(DELAY
(ABSOLUTE
(IOPATH DRPCLK DRPDO (0.693::0.736)(1.560::1.657))
(IOPATH DRPCLK DRPRDY (0.530::0.563)(0.836::0.888))
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))
(IOPATH GTGREFCLK0 REFCLKOUTMONITOR1 (0.452::0.720)(1.657::2.640))
(IOPATH GTGREFCLK1 REFCLKOUTMONITOR0 (0.452::0.720)(1.657::2.640))

6
artix7/timings/GTP_INT_INTERFACE.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_BRAM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_CLB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

9
artix7/timings/HCLK_CMT.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFMRCE")
(INSTANCE BUFMRCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.033::0.035)(0.097::0.103))
)
)
)
(CELL
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
(INSTANCE BUFMRCE)

9
artix7/timings/HCLK_CMT_L.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFMRCE")
(INSTANCE BUFMRCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.033::0.035)(0.097::0.103))
)
)
)
(CELL
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
(INSTANCE BUFMRCE)

6
artix7/timings/HCLK_DSP_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_DSP_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_FEEDTHRU_1.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_FEEDTHRU_2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_FIFO_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
artix7/timings/HCLK_GTX.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

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