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Updating kintex7 based on "Merge pull request #737 from mithro/enable-dsp". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-03-21 19:00:43 -07:00
parent b13ff7f8b3
commit 6a4ef8bc60
33 changed files with 81069 additions and 75351 deletions
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Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Thu Mar 21 21:13:39 UTC 2019 (2019-03-21T21:13:39+00:00).
Last updated on Fri Mar 22 02:00:28 UTC 2019 (2019-03-22T02:00:28+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [c82efce](https://github.com/SymbiFlow/prjxray/commit/c82efce96a5468775289d0892924217369cfa216).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [a7066bb](https://github.com/SymbiFlow/prjxray/commit/a7066bb246ab8c11d3c6313ac25317f2b46d17aa).
Latest commit was;
```
commit c82efce96a5468775289d0892924217369cfa216
Merge: 1775858 5a7102c
Author: litghost <537074+litghost@users.noreply.github.com>
Date: Thu Mar 21 08:26:06 2019 -0700
commit a7066bb246ab8c11d3c6313ac25317f2b46d17aa
Merge: c82efce a041e4e
Author: Tim Ansell <me@mith.ro>
Date: Thu Mar 21 14:18:36 2019 -0700
Merge pull request #735 from SymbiFlow/dependabot/submodules/third_party/googletest-f957bd0
Merge pull request #737 from mithro/enable-dsp
Bump third_party/googletest from `8b6d3f9` to `f957bd0`
Re-enable the DSP fuzzer.
```
@ -59,7 +59,7 @@ Date: Thu Mar 21 08:26:06 2019 -0700
### Settings
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/c82efce96a5468775289d0892924217369cfa216/settings/artix7.sh)
Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/a7066bb246ab8c11d3c6313ac25317f2b46d17aa/settings/artix7.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
@ -344,7 +344,7 @@ Results have checksums;
### Settings
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/c82efce96a5468775289d0892924217369cfa216/settings/kintex7.sh)
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/a7066bb246ab8c11d3c6313ac25317f2b46d17aa/settings/kintex7.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
@ -381,22 +381,24 @@ Results have checksums;
* [`d154b5fc62e0ae17091b880050a7302f4f75fed1008967eb88e2c1e3f13f4792 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_l.block_ram.db`](./kintex7/mask_bram_l.block_ram.db)
* [`0a1777c5cbab388741934b51a2a2b57ffe450200df1d4d2f7051d2680b6c0a83 ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`0a946160b7cc00081d0a4f0b115bef85db44332b89e93ac5dc1f715a98f2272e ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_r.block_ram.db`](./kintex7/mask_bram_r.block_ram.db)
* [`0a1777c5cbab388741934b51a2a2b57ffe450200df1d4d2f7051d2680b6c0a83 ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`0a946160b7cc00081d0a4f0b115bef85db44332b89e93ac5dc1f715a98f2272e ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`ca5d5c0a53c60ea40f75fac03269a5d3722b6c56b8395002453bec5024557e54 ./kintex7/mask_clk_bufg_bot_r.db`](./kintex7/mask_clk_bufg_bot_r.db)
* [`29563155174d4fd17fdf6ae7b4dcd3d83bfc55cba15355bbc751137544c1f0ef ./kintex7/mask_clk_bufg_bot_r.db`](./kintex7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./kintex7/mask_clk_bufg_rebuf.db`](./kintex7/mask_clk_bufg_rebuf.db)
* [`ca5d5c0a53c60ea40f75fac03269a5d3722b6c56b8395002453bec5024557e54 ./kintex7/mask_clk_bufg_top_r.db`](./kintex7/mask_clk_bufg_top_r.db)
* [`29563155174d4fd17fdf6ae7b4dcd3d83bfc55cba15355bbc751137544c1f0ef ./kintex7/mask_clk_bufg_top_r.db`](./kintex7/mask_clk_bufg_top_r.db)
* [`35706a9a25d1213c7143628e41ca5bf3633f37925b20b2f00b1f94a80e879115 ./kintex7/mask_clk_hrow_bot_r.db`](./kintex7/mask_clk_hrow_bot_r.db)
* [`35706a9a25d1213c7143628e41ca5bf3633f37925b20b2f00b1f94a80e879115 ./kintex7/mask_clk_hrow_top_r.db`](./kintex7/mask_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`600de8d5c49959cb5d38b1ec30a179913d636892e4fabaf3de8dedeaa1b6d1e1 ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
* [`600de8d5c49959cb5d38b1ec30a179913d636892e4fabaf3de8dedeaa1b6d1e1 ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./kintex7/ppips_bram_l.db`](./kintex7/ppips_bram_l.db)
@ -405,31 +407,42 @@ Results have checksums;
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db)
* [`77fba62caedba6632e55834bbc40ff797181d8825e2f4d55987a04a38a95a6c0 ./kintex7/ppips_clk_bufg_bot_r.db`](./kintex7/ppips_clk_bufg_bot_r.db)
* [`15dba278ba801744b1ed558220334899fc098acd8e8aff20ab9761249a70e839 ./kintex7/ppips_clk_bufg_top_r.db`](./kintex7/ppips_clk_bufg_top_r.db)
* [`0dbef414182c3ef9054f4b9bc15c41c435d4bef2db30850add728d3de93749b8 ./kintex7/ppips_clk_hrow_bot_r.db`](./kintex7/ppips_clk_hrow_bot_r.db)
* [`8774624d8398b6000e80cefbcf5a5bac095e1c8650772c23f9b73448e0df5dbb ./kintex7/ppips_clk_hrow_top_r.db`](./kintex7/ppips_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_dsp_l.db`](./kintex7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_dsp_r.db`](./kintex7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`f61ce3972e8a3db9dd090a626c018c247788b5ba0946968b641d108de325a0a1 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`d675f037111e500b21acb0b455d77f3b972de1f68643d69a842ea8ffb44db65a ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`cd6ce69c10e481f329308c6ec3d011ca2325a91a27c3567d53de19f7f4bc0229 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`916e3cea00e0bf8291ae24083696833dc1ff09f06562eccba6f2c73afd267ccb ./kintex7/ppips_io_int_interface_l.db`](./kintex7/ppips_io_int_interface_l.db)
* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./kintex7/ppips_io_int_interface_r.db`](./kintex7/ppips_io_int_interface_r.db)
* [`b155fbb8d964a2c3359a8420c0a6fd11aafccaeee92034e78cd16d2c56d4fcf9 ./kintex7/ppips_lioi3.db`](./kintex7/ppips_lioi3.db)
* [`fbe2cd3174bcec467e55558c497717480808149193c2ee80b51be78580356385 ./kintex7/ppips_lioi3_sing.db`](./kintex7/ppips_lioi3_sing.db)
* [`a28a9783e37b9768245b5e48bcf5876b1c625093544b2cce9408d4d3a846cdf3 ./kintex7/ppips_lioi3_tbytesrc.db`](./kintex7/ppips_lioi3_tbytesrc.db)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`6a620f430bcfc6b197da7dd9e9660ac06ef35744b752fe495277915b23198a73 ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db)
* [`b5e65e9c7e93a2d83f34aacf0e052154324afed5d6ba77008e3f79dedc8caf32 ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./kintex7/segbits_clk_bufg_rebuf.db`](./kintex7/segbits_clk_bufg_rebuf.db)
* [`7618b3f1691081ec0d37e32c2533c8b6b637395d7a1779a708637ca547ee4c1b ./kintex7/segbits_clk_bufg_top_r.db`](./kintex7/segbits_clk_bufg_top_r.db)
* [`b90a415459e35584e0a5e59d54a882750d774fcd27921e69f929dcea939e8656 ./kintex7/segbits_clk_hrow_bot_r.db`](./kintex7/segbits_clk_hrow_bot_r.db)
* [`ed55b0098519109e38c9eaf9f47079925c3bcc0c721918efc254e358000b6d06 ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
* [`0124518f026fd29ff7d48e9fe12fd9c5b189e8ca9e1257dc9decb714ee45c27b ./kintex7/segbits_clk_bufg_top_r.db`](./kintex7/segbits_clk_bufg_top_r.db)
* [`27a5fbf2b32339d7ffbc4e10c48cde7eeb4370834dcf72169616bf7f4ae58ebf ./kintex7/segbits_clk_hrow_bot_r.db`](./kintex7/segbits_clk_hrow_bot_r.db)
* [`5c9e452796067b6b3935f5af5dc62d929d98d6090284ede1a27d7136f8da976d ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
* [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`74677110ea4768e641743e8c1cf810c4ffb00c6ea4f09f41144d45f0e89416c7 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`bed06fc405947c72a47a7fbac7adbc220efd2dc8d73f321ed70b8d2490ab745b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`8ec421f8f4ce1bab7e81bcbf0cbdc37fb3f6ed4715bc2fdf75db336805efc53e ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
* [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
@ -596,7 +609,7 @@ Results have checksums;
* [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`fc7d6eb90cb54117f3a92e52394ddb8525cc0b4f3098efa9d1f92a384fea44f1 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`4e1a23768dbd4cab253753d3f2547ce9913a631fab244cdcaa703b31513571fc ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
@ -605,7 +618,7 @@ Results have checksums;
### Settings
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/c82efce96a5468775289d0892924217369cfa216/settings/zynq7.sh)
Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/a7066bb246ab8c11d3c6313ac25317f2b46d17aa/settings/zynq7.sh)
```shell
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1"

417
kintex7/mask_bram_l.db
View File

File diff suppressed because it is too large Load Diff

417
kintex7/mask_bram_r.db
View File

File diff suppressed because it is too large Load Diff

407
kintex7/mask_clk_bufg_bot_r.db
View File

File diff suppressed because it is too large Load Diff

407
kintex7/mask_clk_bufg_top_r.db
View File

File diff suppressed because it is too large Load Diff

414
kintex7/mask_dsp_l.db
View File

@ -0,0 +1,414 @@
bit 00_11
bit 00_35
bit 00_39
bit 00_42
bit 00_75
bit 00_89
bit 00_90
bit 00_99
bit 00_103
bit 00_106
bit 00_139
bit 00_163
bit 00_167
bit 00_170
bit 00_203
bit 00_209
bit 00_217
bit 00_218
bit 00_227
bit 00_231
bit 00_234
bit 00_273
bit 00_293
bit 00_295
bit 00_298
bit 01_14
bit 01_32
bit 01_36
bit 01_37
bit 01_38
bit 01_41
bit 01_78
bit 01_85
bit 01_88
bit 01_96
bit 01_100
bit 01_101
bit 01_102
bit 01_105
bit 01_142
bit 01_160
bit 01_164
bit 01_165
bit 01_166
bit 01_169
bit 01_205
bit 01_206
bit 01_213
bit 01_216
bit 01_224
bit 01_228
bit 01_229
bit 01_230
bit 01_233
bit 01_269
bit 01_288
bit 01_293
bit 01_294
bit 01_296
bit 01_297
bit 20_65
bit 20_73
bit 20_81
bit 20_89
bit 20_129
bit 20_137
bit 20_195
bit 20_203
bit 20_213
bit 20_219
bit 20_293
bit 20_307
bit 20_315
bit 21_70
bit 21_78
bit 21_86
bit 21_94
bit 21_134
bit 21_142
bit 21_194
bit 21_202
bit 21_212
bit 21_218
bit 21_242
bit 21_244
bit 21_292
bit 21_306
bit 21_314
bit 24_65
bit 24_73
bit 24_81
bit 24_89
bit 24_129
bit 24_137
bit 24_195
bit 24_203
bit 24_213
bit 24_219
bit 24_293
bit 24_307
bit 24_315
bit 25_70
bit 25_78
bit 25_86
bit 25_94
bit 25_134
bit 25_142
bit 25_194
bit 25_202
bit 25_212
bit 25_218
bit 25_242
bit 25_244
bit 25_292
bit 25_306
bit 25_314
bit 26_01
bit 26_03
bit 26_04
bit 26_05
bit 26_07
bit 26_09
bit 26_10
bit 26_12
bit 26_17
bit 26_18
bit 26_20
bit 26_22
bit 26_26
bit 26_28
bit 26_29
bit 26_41
bit 26_43
bit 26_45
bit 26_47
bit 26_49
bit 26_51
bit 26_57
bit 26_58
bit 26_59
bit 26_60
bit 26_61
bit 26_62
bit 26_64
bit 26_65
bit 26_66
bit 26_68
bit 26_69
bit 26_72
bit 26_75
bit 26_82
bit 26_86
bit 26_88
bit 26_89
bit 26_90
bit 26_92
bit 26_94
bit 26_96
bit 26_97
bit 26_98
bit 26_101
bit 26_104
bit 26_105
bit 26_106
bit 26_107
bit 26_108
bit 26_110
bit 26_112
bit 26_118
bit 26_127
bit 26_129
bit 26_130
bit 26_132
bit 26_133
bit 26_134
bit 26_135
bit 26_136
bit 26_138
bit 26_139
bit 26_144
bit 26_145
bit 26_146
bit 26_148
bit 26_149
bit 26_151
bit 26_153
bit 26_154
bit 26_155
bit 26_161
bit 26_163
bit 26_164
bit 26_165
bit 26_167
bit 26_169
bit 26_170
bit 26_172
bit 26_177
bit 26_178
bit 26_180
bit 26_182
bit 26_186
bit 26_188
bit 26_189
bit 26_201
bit 26_203
bit 26_205
bit 26_207
bit 26_209
bit 26_211
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_224
bit 26_225
bit 26_226
bit 26_228
bit 26_229
bit 26_232
bit 26_235
bit 26_242
bit 26_246
bit 26_248
bit 26_249
bit 26_250
bit 26_252
bit 26_254
bit 26_256
bit 26_257
bit 26_258
bit 26_261
bit 26_264
bit 26_265
bit 26_266
bit 26_267
bit 26_268
bit 26_270
bit 26_272
bit 26_278
bit 26_287
bit 26_289
bit 26_290
bit 26_292
bit 26_293
bit 26_294
bit 26_295
bit 26_296
bit 26_298
bit 26_299
bit 26_304
bit 26_305
bit 26_306
bit 26_308
bit 26_309
bit 26_311
bit 26_313
bit 26_314
bit 26_315
bit 27_01
bit 27_06
bit 27_08
bit 27_11
bit 27_12
bit 27_13
bit 27_17
bit 27_19
bit 27_21
bit 27_23
bit 27_24
bit 27_26
bit 27_38
bit 27_40
bit 27_42
bit 27_44
bit 27_46
bit 27_48
bit 27_49
bit 27_50
bit 27_51
bit 27_53
bit 27_54
bit 27_56
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_65
bit 27_66
bit 27_67
bit 27_68
bit 27_69
bit 27_71
bit 27_78
bit 27_79
bit 27_80
bit 27_86
bit 27_88
bit 27_90
bit 27_91
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_96
bit 27_101
bit 27_102
bit 27_104
bit 27_106
bit 27_107
bit 27_108
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_118
bit 27_119
bit 27_122
bit 27_125
bit 27_127
bit 27_128
bit 27_131
bit 27_133
bit 27_134
bit 27_135
bit 27_137
bit 27_140
bit 27_144
bit 27_146
bit 27_147
bit 27_150
bit 27_151
bit 27_152
bit 27_154
bit 27_158
bit 27_161
bit 27_166
bit 27_168
bit 27_171
bit 27_172
bit 27_173
bit 27_177
bit 27_179
bit 27_181
bit 27_183
bit 27_184
bit 27_186
bit 27_198
bit 27_200
bit 27_202
bit 27_204
bit 27_206
bit 27_208
bit 27_209
bit 27_210
bit 27_211
bit 27_213
bit 27_214
bit 27_216
bit 27_217
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_225
bit 27_226
bit 27_227
bit 27_228
bit 27_229
bit 27_231
bit 27_238
bit 27_239
bit 27_240
bit 27_246
bit 27_248
bit 27_250
bit 27_251
bit 27_252
bit 27_253
bit 27_254
bit 27_255
bit 27_256
bit 27_261
bit 27_262
bit 27_264
bit 27_266
bit 27_267
bit 27_268
bit 27_270
bit 27_271
bit 27_272
bit 27_273
bit 27_278
bit 27_279
bit 27_282
bit 27_285
bit 27_287
bit 27_288
bit 27_291
bit 27_293
bit 27_294
bit 27_295
bit 27_297
bit 27_300
bit 27_304
bit 27_306
bit 27_307
bit 27_310
bit 27_311
bit 27_312
bit 27_314
bit 27_318

414
kintex7/mask_dsp_r.db
View File

@ -0,0 +1,414 @@
bit 00_11
bit 00_35
bit 00_39
bit 00_42
bit 00_75
bit 00_89
bit 00_90
bit 00_99
bit 00_103
bit 00_106
bit 00_139
bit 00_163
bit 00_167
bit 00_170
bit 00_203
bit 00_209
bit 00_217
bit 00_218
bit 00_227
bit 00_231
bit 00_234
bit 00_273
bit 00_293
bit 00_295
bit 00_298
bit 01_14
bit 01_32
bit 01_36
bit 01_37
bit 01_38
bit 01_41
bit 01_78
bit 01_85
bit 01_88
bit 01_96
bit 01_100
bit 01_101
bit 01_102
bit 01_105
bit 01_142
bit 01_160
bit 01_164
bit 01_165
bit 01_166
bit 01_169
bit 01_205
bit 01_206
bit 01_213
bit 01_216
bit 01_224
bit 01_228
bit 01_229
bit 01_230
bit 01_233
bit 01_269
bit 01_288
bit 01_293
bit 01_294
bit 01_296
bit 01_297
bit 20_65
bit 20_73
bit 20_81
bit 20_89
bit 20_129
bit 20_137
bit 20_195
bit 20_203
bit 20_213
bit 20_219
bit 20_293
bit 20_307
bit 20_315
bit 21_70
bit 21_78
bit 21_86
bit 21_94
bit 21_134
bit 21_142
bit 21_194
bit 21_202
bit 21_212
bit 21_218
bit 21_242
bit 21_244
bit 21_292
bit 21_306
bit 21_314
bit 24_65
bit 24_73
bit 24_81
bit 24_89
bit 24_129
bit 24_137
bit 24_195
bit 24_203
bit 24_213
bit 24_219
bit 24_293
bit 24_307
bit 24_315
bit 25_70
bit 25_78
bit 25_86
bit 25_94
bit 25_134
bit 25_142
bit 25_194
bit 25_202
bit 25_212
bit 25_218
bit 25_242
bit 25_244
bit 25_292
bit 25_306
bit 25_314
bit 26_01
bit 26_03
bit 26_04
bit 26_05
bit 26_07
bit 26_09
bit 26_10
bit 26_12
bit 26_17
bit 26_18
bit 26_20
bit 26_22
bit 26_26
bit 26_28
bit 26_29
bit 26_41
bit 26_43
bit 26_45
bit 26_47
bit 26_49
bit 26_51
bit 26_57
bit 26_58
bit 26_59
bit 26_60
bit 26_61
bit 26_62
bit 26_64
bit 26_65
bit 26_66
bit 26_68
bit 26_69
bit 26_72
bit 26_75
bit 26_82
bit 26_86
bit 26_88
bit 26_89
bit 26_90
bit 26_92
bit 26_94
bit 26_96
bit 26_97
bit 26_98
bit 26_101
bit 26_104
bit 26_105
bit 26_106
bit 26_107
bit 26_108
bit 26_110
bit 26_112
bit 26_118
bit 26_127
bit 26_129
bit 26_130
bit 26_132
bit 26_133
bit 26_134
bit 26_135
bit 26_136
bit 26_138
bit 26_139
bit 26_144
bit 26_145
bit 26_146
bit 26_148
bit 26_149
bit 26_151
bit 26_153
bit 26_154
bit 26_155
bit 26_161
bit 26_163
bit 26_164
bit 26_165
bit 26_167
bit 26_169
bit 26_170
bit 26_172
bit 26_177
bit 26_178
bit 26_180
bit 26_182
bit 26_186
bit 26_188
bit 26_189
bit 26_201
bit 26_203
bit 26_205
bit 26_207
bit 26_209
bit 26_211
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_224
bit 26_225
bit 26_226
bit 26_228
bit 26_229
bit 26_232
bit 26_235
bit 26_242
bit 26_246
bit 26_248
bit 26_249
bit 26_250
bit 26_252
bit 26_254
bit 26_256
bit 26_257
bit 26_258
bit 26_261
bit 26_264
bit 26_265
bit 26_266
bit 26_267
bit 26_268
bit 26_270
bit 26_272
bit 26_278
bit 26_287
bit 26_289
bit 26_290
bit 26_292
bit 26_293
bit 26_294
bit 26_295
bit 26_296
bit 26_298
bit 26_299
bit 26_304
bit 26_305
bit 26_306
bit 26_308
bit 26_309
bit 26_311
bit 26_313
bit 26_314
bit 26_315
bit 27_01
bit 27_06
bit 27_08
bit 27_11
bit 27_12
bit 27_13
bit 27_17
bit 27_19
bit 27_21
bit 27_23
bit 27_24
bit 27_26
bit 27_38
bit 27_40
bit 27_42
bit 27_44
bit 27_46
bit 27_48
bit 27_49
bit 27_50
bit 27_51
bit 27_53
bit 27_54
bit 27_56
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_65
bit 27_66
bit 27_67
bit 27_68
bit 27_69
bit 27_71
bit 27_78
bit 27_79
bit 27_80
bit 27_86
bit 27_88
bit 27_90
bit 27_91
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_96
bit 27_101
bit 27_102
bit 27_104
bit 27_106
bit 27_107
bit 27_108
bit 27_110
bit 27_111
bit 27_112
bit 27_113
bit 27_118
bit 27_119
bit 27_122
bit 27_125
bit 27_127
bit 27_128
bit 27_131
bit 27_133
bit 27_134
bit 27_135
bit 27_137
bit 27_140
bit 27_144
bit 27_146
bit 27_147
bit 27_150
bit 27_151
bit 27_152
bit 27_154
bit 27_158
bit 27_161
bit 27_166
bit 27_168
bit 27_171
bit 27_172
bit 27_173
bit 27_177
bit 27_179
bit 27_181
bit 27_183
bit 27_184
bit 27_186
bit 27_198
bit 27_200
bit 27_202
bit 27_204
bit 27_206
bit 27_208
bit 27_209
bit 27_210
bit 27_211
bit 27_213
bit 27_214
bit 27_216
bit 27_217
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_225
bit 27_226
bit 27_227
bit 27_228
bit 27_229
bit 27_231
bit 27_238
bit 27_239
bit 27_240
bit 27_246
bit 27_248
bit 27_250
bit 27_251
bit 27_252
bit 27_253
bit 27_254
bit 27_255
bit 27_256
bit 27_261
bit 27_262
bit 27_264
bit 27_266
bit 27_267
bit 27_268
bit 27_270
bit 27_271
bit 27_272
bit 27_273
bit 27_278
bit 27_279
bit 27_282
bit 27_285
bit 27_287
bit 27_288
bit 27_291
bit 27_293
bit 27_294
bit 27_295
bit 27_297
bit 27_300
bit 27_304
bit 27_306
bit 27_307
bit 27_310
bit 27_311
bit 27_312
bit 27_314
bit 27_318

1987
kintex7/mask_liob33.db Normal file
View File

File diff suppressed because it is too large Load Diff

1987
kintex7/mask_riob33.db Normal file
View File

File diff suppressed because it is too large Load Diff

128
kintex7/ppips_clk_bufg_bot_r.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_BOT_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always

128
kintex7/ppips_clk_bufg_top_r.db Normal file
View File

@ -0,0 +1,128 @@
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0.CLK_BUFG_BUFGCTRL0_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1.CLK_BUFG_BUFGCTRL1_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2.CLK_BUFG_BUFGCTRL2_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3.CLK_BUFG_BUFGCTRL3_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4.CLK_BUFG_BUFGCTRL4_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5.CLK_BUFG_BUFGCTRL5_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6.CLK_BUFG_BUFGCTRL6_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7.CLK_BUFG_BUFGCTRL7_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8.CLK_BUFG_BUFGCTRL8_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9.CLK_BUFG_BUFGCTRL9_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10.CLK_BUFG_BUFGCTRL10_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11.CLK_BUFG_BUFGCTRL11_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12.CLK_BUFG_BUFGCTRL12_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13.CLK_BUFG_BUFGCTRL13_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14.CLK_BUFG_BUFGCTRL14_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15.CLK_BUFG_BUFGCTRL15_O always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE0.CLK_BUFG_IMUX20_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_CE1.CLK_BUFG_IMUX16_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE0.CLK_BUFG_IMUX12_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_IGNORE1.CLK_BUFG_IMUX8_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S0.CLK_BUFG_IMUX4_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL0_S1.CLK_BUFG_IMUX0_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE0.CLK_BUFG_IMUX21_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_CE1.CLK_BUFG_IMUX17_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE0.CLK_BUFG_IMUX13_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_IGNORE1.CLK_BUFG_IMUX9_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S0.CLK_BUFG_IMUX5_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL1_S1.CLK_BUFG_IMUX1_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE0.CLK_BUFG_IMUX22_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_CE1.CLK_BUFG_IMUX18_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE0.CLK_BUFG_IMUX14_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_IGNORE1.CLK_BUFG_IMUX10_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S0.CLK_BUFG_IMUX6_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL2_S1.CLK_BUFG_IMUX2_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE0.CLK_BUFG_IMUX23_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_CE1.CLK_BUFG_IMUX19_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE0.CLK_BUFG_IMUX15_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_IGNORE1.CLK_BUFG_IMUX11_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S0.CLK_BUFG_IMUX7_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL3_S1.CLK_BUFG_IMUX3_0 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE0.CLK_BUFG_IMUX20_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_CE1.CLK_BUFG_IMUX16_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE0.CLK_BUFG_IMUX12_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_IGNORE1.CLK_BUFG_IMUX8_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S0.CLK_BUFG_IMUX4_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL4_S1.CLK_BUFG_IMUX0_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE0.CLK_BUFG_IMUX21_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_CE1.CLK_BUFG_IMUX17_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE0.CLK_BUFG_IMUX13_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_IGNORE1.CLK_BUFG_IMUX9_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S0.CLK_BUFG_IMUX5_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL5_S1.CLK_BUFG_IMUX1_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE0.CLK_BUFG_IMUX22_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_CE1.CLK_BUFG_IMUX18_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE0.CLK_BUFG_IMUX14_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_IGNORE1.CLK_BUFG_IMUX10_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S0.CLK_BUFG_IMUX6_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL6_S1.CLK_BUFG_IMUX2_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE0.CLK_BUFG_IMUX23_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_CE1.CLK_BUFG_IMUX19_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE0.CLK_BUFG_IMUX15_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_IGNORE1.CLK_BUFG_IMUX11_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S0.CLK_BUFG_IMUX7_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL7_S1.CLK_BUFG_IMUX3_1 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE0.CLK_BUFG_IMUX20_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_CE1.CLK_BUFG_IMUX16_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE0.CLK_BUFG_IMUX12_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_IGNORE1.CLK_BUFG_IMUX8_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S0.CLK_BUFG_IMUX4_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL8_S1.CLK_BUFG_IMUX0_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE0.CLK_BUFG_IMUX21_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_CE1.CLK_BUFG_IMUX17_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE0.CLK_BUFG_IMUX13_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_IGNORE1.CLK_BUFG_IMUX9_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S0.CLK_BUFG_IMUX5_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL9_S1.CLK_BUFG_IMUX1_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE0.CLK_BUFG_IMUX22_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_CE1.CLK_BUFG_IMUX18_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE0.CLK_BUFG_IMUX14_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_IGNORE1.CLK_BUFG_IMUX10_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S0.CLK_BUFG_IMUX6_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL10_S1.CLK_BUFG_IMUX2_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE0.CLK_BUFG_IMUX23_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_CE1.CLK_BUFG_IMUX19_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE0.CLK_BUFG_IMUX15_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_IGNORE1.CLK_BUFG_IMUX11_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S0.CLK_BUFG_IMUX7_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL11_S1.CLK_BUFG_IMUX3_2 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE0.CLK_BUFG_IMUX20_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_CE1.CLK_BUFG_IMUX16_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE0.CLK_BUFG_IMUX12_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_IGNORE1.CLK_BUFG_IMUX8_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S0.CLK_BUFG_IMUX4_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL12_S1.CLK_BUFG_IMUX0_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE0.CLK_BUFG_IMUX21_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_CE1.CLK_BUFG_IMUX17_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE0.CLK_BUFG_IMUX13_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_IGNORE1.CLK_BUFG_IMUX9_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S0.CLK_BUFG_IMUX5_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL13_S1.CLK_BUFG_IMUX1_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE0.CLK_BUFG_IMUX22_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_CE1.CLK_BUFG_IMUX18_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE0.CLK_BUFG_IMUX14_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_IGNORE1.CLK_BUFG_IMUX10_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S0.CLK_BUFG_IMUX6_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL14_S1.CLK_BUFG_IMUX2_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE0.CLK_BUFG_IMUX23_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_CE1.CLK_BUFG_IMUX19_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE0.CLK_BUFG_IMUX15_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_IGNORE1.CLK_BUFG_IMUX11_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S0.CLK_BUFG_IMUX7_3 always
CLK_BUFG_TOP_R.CLK_BUFG_R_BUFGCTRL15_S1.CLK_BUFG_IMUX3_3 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O.CLK_BUFG_BUFGCTRL0_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O.CLK_BUFG_BUFGCTRL1_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O.CLK_BUFG_BUFGCTRL2_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O.CLK_BUFG_BUFGCTRL3_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O.CLK_BUFG_BUFGCTRL4_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O.CLK_BUFG_BUFGCTRL5_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O.CLK_BUFG_BUFGCTRL6_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O.CLK_BUFG_BUFGCTRL7_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O.CLK_BUFG_BUFGCTRL8_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O.CLK_BUFG_BUFGCTRL9_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O.CLK_BUFG_BUFGCTRL10_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O.CLK_BUFG_BUFGCTRL11_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O.CLK_BUFG_BUFGCTRL12_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O.CLK_BUFG_BUFGCTRL13_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O.CLK_BUFG_BUFGCTRL14_I0 always
CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O.CLK_BUFG_BUFGCTRL15_I0 always

168
kintex7/ppips_clk_hrow_bot_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_BOT_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always

168
kintex7/ppips_clk_hrow_top_r.db Normal file
View File

@ -0,0 +1,168 @@
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L0.CLK_HROW_CE_INT_BOT6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L1.CLK_HROW_CE_INT_BOT7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L2.CLK_HROW_CE_INT_BOT8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L3.CLK_HROW_CE_INT_BOT9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L4.CLK_HROW_CE_INT_BOT10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L5.CLK_HROW_CE_INT_BOT11 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L6.CLK_HROW_CE_INT_TOP0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L7.CLK_HROW_CE_INT_TOP1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L8.CLK_HROW_CE_INT_TOP2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L9.CLK_HROW_CE_INT_TOP3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L10.CLK_HROW_CE_INT_TOP4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_L11.CLK_HROW_CE_INT_TOP5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R0.CLK_HROW_CE_INT_BOT0 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R1.CLK_HROW_CE_INT_BOT1 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R2.CLK_HROW_CE_INT_BOT2 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R3.CLK_HROW_CE_INT_BOT3 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R4.CLK_HROW_CE_INT_BOT4 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R5.CLK_HROW_CE_INT_BOT5 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R6.CLK_HROW_CE_INT_TOP6 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R7.CLK_HROW_CE_INT_TOP7 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R8.CLK_HROW_CE_INT_TOP8 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R9.CLK_HROW_CE_INT_TOP9 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R10.CLK_HROW_CE_INT_TOP10 always
CLK_HROW_TOP_R.CLK_HROW_BUFHCE_CE_R11.CLK_HROW_CE_INT_TOP11 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0.CLK_HROW_IMUX0_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1.CLK_HROW_IMUX1_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2.CLK_HROW_IMUX2_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3.CLK_HROW_IMUX3_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4.CLK_HROW_IMUX4_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5.CLK_HROW_IMUX5_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6.CLK_HROW_IMUX6_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7.CLK_HROW_IMUX7_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8.CLK_HROW_IMUX8_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9.CLK_HROW_IMUX9_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10.CLK_HROW_IMUX10_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11.CLK_HROW_IMUX11_3 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0.CLK_HROW_IMUX0_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1.CLK_HROW_IMUX1_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2.CLK_HROW_IMUX2_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3.CLK_HROW_IMUX3_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4.CLK_HROW_IMUX4_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5.CLK_HROW_IMUX5_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6.CLK_HROW_IMUX6_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7.CLK_HROW_IMUX7_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8.CLK_HROW_IMUX8_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9.CLK_HROW_IMUX9_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10.CLK_HROW_IMUX10_4 always
CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11.CLK_HROW_IMUX11_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L0.CLK_HROW_CK_HCLK_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L1.CLK_HROW_CK_HCLK_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L2.CLK_HROW_CK_HCLK_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L3.CLK_HROW_CK_HCLK_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L4.CLK_HROW_CK_HCLK_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L5.CLK_HROW_CK_HCLK_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L6.CLK_HROW_CK_HCLK_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L7.CLK_HROW_CK_HCLK_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L8.CLK_HROW_CK_HCLK_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L9.CLK_HROW_CK_HCLK_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L10.CLK_HROW_CK_HCLK_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_L11.CLK_HROW_CK_HCLK_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R0.CLK_HROW_CK_HCLK_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R1.CLK_HROW_CK_HCLK_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R2.CLK_HROW_CK_HCLK_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R3.CLK_HROW_CK_HCLK_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R4.CLK_HROW_CK_HCLK_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R5.CLK_HROW_CK_HCLK_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R6.CLK_HROW_CK_HCLK_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R7.CLK_HROW_CK_HCLK_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R8.CLK_HROW_CK_HCLK_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R9.CLK_HROW_CK_HCLK_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R10.CLK_HROW_CK_HCLK_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_BUFHCLK_R11.CLK_HROW_CK_HCLK_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST0.CLK_HROW_CK_GCLK_TEST_OUT0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST1.CLK_HROW_CK_GCLK_TEST_OUT1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST2.CLK_HROW_CK_GCLK_TEST_OUT2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST3.CLK_HROW_CK_GCLK_TEST_OUT3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST4.CLK_HROW_CK_GCLK_TEST_OUT4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST5.CLK_HROW_CK_GCLK_TEST_OUT5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST6.CLK_HROW_CK_GCLK_TEST_OUT6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST7.CLK_HROW_CK_GCLK_TEST_OUT7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST8.CLK_HROW_CK_GCLK_TEST_OUT8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST9.CLK_HROW_CK_GCLK_TEST_OUT9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST10.CLK_HROW_CK_GCLK_TEST_OUT10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST11.CLK_HROW_CK_GCLK_TEST_OUT11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST12.CLK_HROW_CK_GCLK_TEST_OUT12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST13.CLK_HROW_CK_GCLK_TEST_OUT13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST14.CLK_HROW_CK_GCLK_TEST_OUT14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST15.CLK_HROW_CK_GCLK_TEST_OUT15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST16.CLK_HROW_CK_GCLK_TEST_OUT16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST17.CLK_HROW_CK_GCLK_TEST_OUT17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST18.CLK_HROW_CK_GCLK_TEST_OUT18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST19.CLK_HROW_CK_GCLK_TEST_OUT19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST20.CLK_HROW_CK_GCLK_TEST_OUT20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST21.CLK_HROW_CK_GCLK_TEST_OUT21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST22.CLK_HROW_CK_GCLK_TEST_OUT22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST23.CLK_HROW_CK_GCLK_TEST_OUT23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST24.CLK_HROW_CK_GCLK_TEST_OUT24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST25.CLK_HROW_CK_GCLK_TEST_OUT25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST26.CLK_HROW_CK_GCLK_TEST_OUT26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST27.CLK_HROW_CK_GCLK_TEST_OUT27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST28.CLK_HROW_CK_GCLK_TEST_OUT28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST29.CLK_HROW_CK_GCLK_TEST_OUT29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST30.CLK_HROW_CK_GCLK_TEST_OUT30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_OUT_TEST31.CLK_HROW_CK_GCLK_TEST_OUT31 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN0.CLK_HROW_CK_GCLK_IN_TEST0 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN1.CLK_HROW_CK_GCLK_IN_TEST1 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN2.CLK_HROW_CK_GCLK_IN_TEST2 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN3.CLK_HROW_CK_GCLK_IN_TEST3 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN4.CLK_HROW_CK_GCLK_IN_TEST4 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN5.CLK_HROW_CK_GCLK_IN_TEST5 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN6.CLK_HROW_CK_GCLK_IN_TEST6 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN7.CLK_HROW_CK_GCLK_IN_TEST7 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN8.CLK_HROW_CK_GCLK_IN_TEST8 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN9.CLK_HROW_CK_GCLK_IN_TEST9 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN10.CLK_HROW_CK_GCLK_IN_TEST10 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN11.CLK_HROW_CK_GCLK_IN_TEST11 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN12.CLK_HROW_CK_GCLK_IN_TEST12 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN13.CLK_HROW_CK_GCLK_IN_TEST13 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN14.CLK_HROW_CK_GCLK_IN_TEST14 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN15.CLK_HROW_CK_GCLK_IN_TEST15 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN16.CLK_HROW_CK_GCLK_IN_TEST16 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN17.CLK_HROW_CK_GCLK_IN_TEST17 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN18.CLK_HROW_CK_GCLK_IN_TEST18 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN19.CLK_HROW_CK_GCLK_IN_TEST19 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN20.CLK_HROW_CK_GCLK_IN_TEST20 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN21.CLK_HROW_CK_GCLK_IN_TEST21 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN22.CLK_HROW_CK_GCLK_IN_TEST22 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN23.CLK_HROW_CK_GCLK_IN_TEST23 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN24.CLK_HROW_CK_GCLK_IN_TEST24 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN25.CLK_HROW_CK_GCLK_IN_TEST25 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN26.CLK_HROW_CK_GCLK_IN_TEST26 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN27.CLK_HROW_CK_GCLK_IN_TEST27 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN28.CLK_HROW_CK_GCLK_IN_TEST28 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN29.CLK_HROW_CK_GCLK_IN_TEST29 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN30.CLK_HROW_CK_GCLK_IN_TEST30 always
CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_IN31.CLK_HROW_CK_GCLK_IN_TEST31 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0.CLK_HROW_CK_MUX_OUT_L0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1.CLK_HROW_CK_MUX_OUT_L1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2.CLK_HROW_CK_MUX_OUT_L2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3.CLK_HROW_CK_MUX_OUT_L3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4.CLK_HROW_CK_MUX_OUT_L4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5.CLK_HROW_CK_MUX_OUT_L5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6.CLK_HROW_CK_MUX_OUT_L6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7.CLK_HROW_CK_MUX_OUT_L7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8.CLK_HROW_CK_MUX_OUT_L8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9.CLK_HROW_CK_MUX_OUT_L9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10.CLK_HROW_CK_MUX_OUT_L10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11.CLK_HROW_CK_MUX_OUT_L11 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0.CLK_HROW_CK_MUX_OUT_R0 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1.CLK_HROW_CK_MUX_OUT_R1 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2.CLK_HROW_CK_MUX_OUT_R2 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3.CLK_HROW_CK_MUX_OUT_R3 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4.CLK_HROW_CK_MUX_OUT_R4 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5.CLK_HROW_CK_MUX_OUT_R5 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6.CLK_HROW_CK_MUX_OUT_R6 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7.CLK_HROW_CK_MUX_OUT_R7 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8.CLK_HROW_CK_MUX_OUT_R8 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9.CLK_HROW_CK_MUX_OUT_R9 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10.CLK_HROW_CK_MUX_OUT_R10 always
CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11.CLK_HROW_CK_MUX_OUT_R11 always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_IN_TEST.CLK_HROW_CK_IN_L_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_OUT.CLK_HROW_CK_IN_L_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_IN_TEST.CLK_HROW_CK_IN_R_TEST_IN always
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_OUT.CLK_HROW_CK_IN_R_OUT_TEST always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0.CLK_HROW_CLK0_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1.CLK_HROW_CLK1_3 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0.CLK_HROW_CLK0_4 always
CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1.CLK_HROW_CLK1_4 always

24
kintex7/ppips_io_int_interface_l.db Normal file
View File

@ -0,0 +1,24 @@
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always

24
kintex7/ppips_io_int_interface_r.db Normal file
View File

@ -0,0 +1,24 @@
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always

165
kintex7/ppips_lioi3.db Normal file
View File

@ -0,0 +1,165 @@
LIOI3.IOI_IDELAYCTRL_RST.IOI_IMUX24_0 always
LIOI3.IOI_IMUX_RC2.IOI_BYP4_1 always
LIOI3.IOI_IMUX_RC3.IOI_BYP3_1 always
LIOI3.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI3.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI3.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI3.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI3.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI3.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3.IOI_LOGIC_OUTS13_0.IOI_IDELAYCTRL_DNPULSEOUT always
LIOI3.IOI_LOGIC_OUTS13_1.IOI_IDELAYCTRL_OUTN1 always
LIOI3.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI3.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI3.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
LIOI3.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3.IOI_LOGIC_OUTS16_0.IOI_IDELAYCTRL_UPPULSEOUT always
LIOI3.IOI_LOGIC_OUTS16_1.IOI_IDELAYCTRL_OUTN65 always
LIOI3.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
LIOI3.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
LIOI3.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI3.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI3.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3.IOI_LOGIC_OUTS22_1.IOI_IDELAYCTRL_RDY always
LIOI3.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI3.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI3.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI3.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI3.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI3.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI3.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI3.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI3.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI3.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3.LIOI_I0.LIOI_IBUF0 always
LIOI3.LIOI_I1.LIOI_IBUF1 always
LIOI3.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
LIOI3.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
LIOI3.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI3.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI3.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI3.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3.LIOI_ISIN11.LIOI_ISOUT10 always
LIOI3.LIOI_ISIN21.LIOI_ISOUT20 always
LIOI3.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI3.LIOI_O1.LIOI_OLOGIC1_OQ always
LIOI3.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI3.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI3.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI3.LIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
LIOI3.LIOI_OLOGIC1_TFB_LOCAL.LIOI_OLOGIC1_TFB always
LIOI3.LIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
LIOI3.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI3.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI3.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3.LIOI_T1.LIOI_OLOGIC1_TQ always
LIOI3.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always

72
kintex7/ppips_lioi3_sing.db Normal file
View File

@ -0,0 +1,72 @@
LIOI3_SING.IOI_LOGIC_OUTS0_0.IOI_ILOGIC0_Q1 always
LIOI3_SING.IOI_LOGIC_OUTS1_0.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_SING.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.IOI_LOGIC_OUTS3_0.IOI_ILOGIC0_Q6 always
LIOI3_SING.IOI_LOGIC_OUTS5_0.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_SING.IOI_LOGIC_OUTS7_0.IOI_ILOGIC0_Q7 always
LIOI3_SING.IOI_LOGIC_OUTS8_0.IOI_ILOGIC0_Q8 always
LIOI3_SING.IOI_LOGIC_OUTS9_0.IOI_ILOGIC0_Q3 always
LIOI3_SING.IOI_LOGIC_OUTS10_0.IOI_ILOGIC0_Q4 always
LIOI3_SING.IOI_LOGIC_OUTS11_0.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_SING.IOI_LOGIC_OUTS14_0.IOI_ILOGIC0_Q5 always
LIOI3_SING.IOI_LOGIC_OUTS15_0.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3_SING.IOI_LOGIC_OUTS18_0.IOI_ILOGIC0_O always
LIOI3_SING.IOI_LOGIC_OUTS19_0.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_SING.IOI_LOGIC_OUTS20_0.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_SING.IOI_LOGIC_OUTS23_0.IOI_ILOGIC0_Q2 always
LIOI3_SING.IOI_IDELAY0_C.IOI_CLK1_0 always
LIOI3_SING.IOI_IDELAY0_CE.IOI_IMUX32_0 always
LIOI3_SING.IOI_IDELAY0_CINVCTRL.IOI_BYP6_0 always
LIOI3_SING.IOI_IDELAY0_DATAIN.IOI_IMUX25_0 always
LIOI3_SING.IOI_IDELAY0_INC.IOI_IMUX26_0 always
LIOI3_SING.IOI_IDELAY0_LD.IOI_IMUX30_0 always
LIOI3_SING.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_SING.IOI_IDELAY0_REGRST.IOI_IMUX12_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_SING.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_SING.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_0 always
LIOI3_SING.IOI_ILOGIC0_CLKDIV.IOI_CLK0_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_SING.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_SING.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_SING.IOI_ILOGIC0_SR.IOI_CTRL1_0 always
LIOI3_SING.IOI_ILOGIC0_CE1.IOI_IMUX5_0 always
LIOI3_SING.IOI_ILOGIC0_CE2.IOI_IMUX14_0 always
LIOI3_SING.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_SING.IOI_OLOGIC0_OCE.IOI_IMUX29_0 always
LIOI3_SING.IOI_OLOGIC0_SR.IOI_CTRL0_0 always
LIOI3_SING.IOI_OLOGIC0_TBYTEIN.IOI_SING_TBYTEIN always
LIOI3_SING.IOI_OLOGIC0_TCE.IOI_IMUX1_0 always
LIOI3_SING.IOI_OLOGIC0_D1.IOI_IMUX34_0 always
LIOI3_SING.IOI_OLOGIC0_D2.IOI_IMUX40_0 always
LIOI3_SING.IOI_OLOGIC0_D3.IOI_IMUX44_0 always
LIOI3_SING.IOI_OLOGIC0_D4.IOI_IMUX42_0 always
LIOI3_SING.IOI_OLOGIC0_D5.IOI_IMUX43_0 always
LIOI3_SING.IOI_OLOGIC0_D6.IOI_IMUX45_0 always
LIOI3_SING.IOI_OLOGIC0_D7.IOI_IMUX46_0 always
LIOI3_SING.IOI_OLOGIC0_D8.IOI_IMUX47_0 always
LIOI3_SING.IOI_OLOGIC0_T1.IOI_IMUX15_0 always
LIOI3_SING.IOI_OLOGIC0_T2.IOI_IMUX7_0 always
LIOI3_SING.IOI_OLOGIC0_T3.IOI_IMUX13_0 always
LIOI3_SING.IOI_OLOGIC0_T4.IOI_IMUX21_0 always
LIOI3_SING.LIOI_DCI_T_TERM0.IOI_IMUX6_0 always
LIOI3_SING.LIOI_IBUF_DISABLE0.IOI_IMUX9_0 always
LIOI3_SING.LIOI_I0.LIOI_IBUF0 always
LIOI3_SING.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
LIOI3_SING.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_SING.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_SING.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_SING.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_SING.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI3_SING.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI3_SING.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI3_SING.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3_SING.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_0 always
LIOI3_SING.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_0 always

158
kintex7/ppips_lioi3_tbytesrc.db Normal file
View File

@ -0,0 +1,158 @@
LIOI3_TBYTESRC.IOI_LOGIC_OUTS0_0.IOI_ILOGIC1_Q1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS0_1.IOI_ILOGIC0_Q1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_0.IOI_IDELAY1_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS1_1.IOI_IDELAY0_CNTVALUEOUT1 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_0.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS2_1.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_0.IOI_ILOGIC1_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS3_1.IOI_ILOGIC0_Q6 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_0.IOI_OLOGIC1_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS5_1.IOI_OLOGIC0_IOCLKGLITCH always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_0.IOI_ILOGIC1_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS7_1.IOI_ILOGIC0_Q7 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_0.IOI_ILOGIC1_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS8_1.IOI_ILOGIC0_Q8 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_0.IOI_ILOGIC1_Q3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS9_1.IOI_ILOGIC0_Q3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS10_0.IOI_ILOGIC1_Q4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS10_1.IOI_ILOGIC0_Q4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS11_0.IOI_IDELAY1_CNTVALUEOUT4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS11_1.IOI_IDELAY0_CNTVALUEOUT4 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS14_0.IOI_ILOGIC1_Q5 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS14_1.IOI_ILOGIC0_Q5 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS15_0.IOI_IDELAY1_CNTVALUEOUT3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS15_1.IOI_IDELAY0_CNTVALUEOUT3 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS18_0.IOI_ILOGIC1_O always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS18_1.IOI_ILOGIC0_O always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS19_0.IOI_IDELAY1_CNTVALUEOUT2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS19_1.IOI_IDELAY0_CNTVALUEOUT2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS20_0.IOI_IDELAY1_CNTVALUEOUT0 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS20_1.IOI_IDELAY0_CNTVALUEOUT0 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS23_0.IOI_ILOGIC1_Q2 always
LIOI3_TBYTESRC.IOI_LOGIC_OUTS23_1.IOI_ILOGIC0_Q2 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE0.IOI_BYP3_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE1.IOI_BYP4_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE2_1.IOI_BYP4_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CE3_1.IOI_BYP3_1 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR0_1.IOI_BYP3_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR1_1.IOI_BYP4_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR2.IOI_BYP4_0 always
LIOI3_TBYTESRC.IOI_RCLK_DIV_CLR3.IOI_BYP3_0 always
LIOI3_TBYTESRC.IOI_TBYTEIN.IOI_OLOGIC1_TBYTEOUT always
LIOI3_TBYTESRC.IOI_IDELAY0_C.IOI_CLK1_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CE.IOI_IMUX32_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CINVCTRL.IOI_BYP6_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_DATAIN.IOI_IMUX25_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_INC.IOI_IMUX26_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LD.IOI_IMUX30_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_LDPIPEEN.IOI_IMUX33_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_REGRST.IOI_IMUX12_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN0.IOI_IMUX41_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN1.IOI_IMUX36_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN2.IOI_IMUX35_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN3.IOI_IMUX38_1 always
LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEIN4.IOI_IMUX39_1 always
LIOI3_TBYTESRC.IOI_IDELAY1_C.IOI_CLK1_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CE.IOI_IMUX32_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CINVCTRL.IOI_BYP6_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_DATAIN.IOI_IMUX25_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_INC.IOI_IMUX26_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LD.IOI_IMUX30_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_LDPIPEEN.IOI_IMUX33_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_REGRST.IOI_IMUX12_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN0.IOI_IMUX41_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN1.IOI_IMUX36_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN2.IOI_IMUX35_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN3.IOI_IMUX38_0 always
LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEIN4.IOI_IMUX39_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_BITSLIP.IOI_IMUX0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CLKDIV.IOI_CLK0_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVPSEL.IOI_IMUX10_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKDIVSEL.IOI_IMUX4_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_DYNCLKSEL.IOI_IMUX37_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_OCLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_ILOGIC0_SR.IOI_CTRL1_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE1.IOI_IMUX5_1 always
LIOI3_TBYTESRC.IOI_ILOGIC0_CE2.IOI_IMUX14_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_BITSLIP.IOI_IMUX0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CLKDIV.IOI_CLK0_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVPSEL.IOI_IMUX10_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKDIVSEL.IOI_IMUX4_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_DYNCLKSEL.IOI_IMUX37_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_OCLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_ILOGIC1_SR.IOI_CTRL1_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE1.IOI_IMUX5_0 always
LIOI3_TBYTESRC.IOI_ILOGIC1_CE2.IOI_IMUX14_0 always
LIOI3_TBYTESRC.IOI_OLOGIC0_CLK.IOI_OCLK_0 always
LIOI3_TBYTESRC.IOI_OLOGIC0_OCE.IOI_IMUX29_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_SR.IOI_CTRL0_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC0_TCE.IOI_IMUX1_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D1.IOI_IMUX34_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D2.IOI_IMUX40_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D3.IOI_IMUX44_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D4.IOI_IMUX42_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D5.IOI_IMUX43_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D6.IOI_IMUX45_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D7.IOI_IMUX46_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_D8.IOI_IMUX47_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T1.IOI_IMUX15_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T2.IOI_IMUX7_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T3.IOI_IMUX13_1 always
LIOI3_TBYTESRC.IOI_OLOGIC0_T4.IOI_IMUX21_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_CLK.IOI_OCLK_1 always
LIOI3_TBYTESRC.IOI_OLOGIC1_OCE.IOI_IMUX29_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_SR.IOI_CTRL0_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEIN.IOI_TBYTEIN always
LIOI3_TBYTESRC.IOI_OLOGIC1_TCE.IOI_IMUX1_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D1.IOI_IMUX34_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D2.IOI_IMUX40_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D3.IOI_IMUX44_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D4.IOI_IMUX42_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D5.IOI_IMUX43_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D6.IOI_IMUX45_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D7.IOI_IMUX46_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_D8.IOI_IMUX47_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T1.IOI_IMUX15_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T2.IOI_IMUX7_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T3.IOI_IMUX13_0 always
LIOI3_TBYTESRC.IOI_OLOGIC1_T4.IOI_IMUX21_0 always
LIOI3_TBYTESRC.LIOI_DCI_T_TERM0.IOI_IMUX6_1 always
LIOI3_TBYTESRC.LIOI_DCI_T_TERM1.IOI_IMUX6_0 always
LIOI3_TBYTESRC.LIOI_I2GCLK_TOP0.IOI_ILOGIC0_O always
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE0.IOI_IMUX9_1 always
LIOI3_TBYTESRC.LIOI_IBUF_DISABLE1.IOI_IMUX9_0 always
LIOI3_TBYTESRC.LIOI_I0.LIOI_IBUF0 always
LIOI3_TBYTESRC.LIOI_I1.LIOI_IBUF1 always
LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT.LIOI_IDELAY0_IDATAIN always
LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN.LIOI_I0 always
LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT.LIOI_IDELAY1_IDATAIN always
LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN.LIOI_I1 always
LIOI3_TBYTESRC.LIOI_ILOGIC0_D.LIOI_I0 always
LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY.LIOI_IDELAY0_DATAOUT always
LIOI3_TBYTESRC.LIOI_ILOGIC0_OFB.LIOI_OLOGIC0_OFB always
LIOI3_TBYTESRC.LIOI_ILOGIC0_TFB.LIOI_OLOGIC0_TFB_LOCAL always
LIOI3_TBYTESRC.LIOI_ILOGIC1_D.LIOI_I1 always
LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY.LIOI_IDELAY1_DATAOUT always
LIOI3_TBYTESRC.LIOI_ILOGIC1_OFB.LIOI_OLOGIC1_OFB always
LIOI3_TBYTESRC.LIOI_ILOGIC1_TFB.LIOI_OLOGIC1_TFB_LOCAL always
LIOI3_TBYTESRC.LIOI_ISIN11.LIOI_ISOUT10 always
LIOI3_TBYTESRC.LIOI_ISIN21.LIOI_ISOUT20 always
LIOI3_TBYTESRC.LIOI_O0.LIOI_OLOGIC0_OQ always
LIOI3_TBYTESRC.LIOI_O1.LIOI_OLOGIC1_OQ always
LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ.IOI_OLOGIC0_D1 always
LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL.LIOI_OLOGIC0_TFB always
LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ.IOI_OLOGIC0_T1 always
LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ.IOI_OLOGIC1_D1 always
LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL.LIOI_OLOGIC1_TFB always
LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ.IOI_OLOGIC1_T1 always
LIOI3_TBYTESRC.LIOI_OSIN10.LIOI_OSOUT11 always
LIOI3_TBYTESRC.LIOI_OSIN20.LIOI_OSOUT21 always
LIOI3_TBYTESRC.LIOI_T0.LIOI_OLOGIC0_TQ always
LIOI3_TBYTESRC.LIOI_T1.LIOI_OLOGIC1_TQ always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY0.IOI_FAN4_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY1.IOI_FAN5_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY0_IFDLY2.IOI_BYP7_1 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY0.IOI_FAN4_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY1.IOI_FAN5_0 always
LIOI3_TBYTESRC.LIOI3_IDELAY1_IFDLY2.IOI_BYP7_0 always

73728
kintex7/segbits_bram_l.block_ram.db
View File

File diff suppressed because it is too large Load Diff

294
kintex7/segbits_bram_l.db
View File

@ -178,6 +178,8 @@ BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_L.CASCOUT_ARD_ACTIVE 26_170
BRAM_L.CASCOUT_BWR_ACTIVE 26_172
BRAM_L.EN_SYN 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] 27_288
@ -210,42 +212,6 @@ BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 27_150
BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -262,42 +228,8 @@ BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.SDP_READ_WIDTH_36 27_48
BRAM_L.RAMB18_Y0.SDP_WRITE_WIDTH_36 27_40
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -312,6 +244,42 @@ BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_L.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_L.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_L.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_L.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -322,46 +290,46 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -378,42 +346,8 @@ BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.SDP_READ_WIDTH_36 27_272
BRAM_L.RAMB18_Y1.SDP_WRITE_WIDTH_36 27_280
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -428,6 +362,42 @@ BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_L.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_L.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_L.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_L.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -438,6 +408,42 @@ BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188

73728
kintex7/segbits_bram_r.block_ram.db
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File diff suppressed because it is too large Load Diff

294
kintex7/segbits_bram_r.db
View File

@ -178,6 +178,8 @@ BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 !26_141 !26_142 !26_143
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 26_269 !26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 !26_269 26_270 26_271
BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 !26_269 !26_270 !26_271
BRAM_R.CASCOUT_ARD_ACTIVE 26_170
BRAM_R.CASCOUT_BWR_ACTIVE 26_172
BRAM_R.EN_SYN 27_171
BRAM_R.FIRST_WORD_FALL_THROUGH 27_170
BRAM_R.ZALMOST_EMPTY_OFFSET[0] 27_288
@ -210,42 +212,6 @@ BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 27_150
BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -262,42 +228,8 @@ BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.SDP_READ_WIDTH_36 27_48
BRAM_R.RAMB18_Y0.SDP_WRITE_WIDTH_36 27_40
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -312,6 +244,42 @@ BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_R.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_R.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_R.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_R.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_R.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_R.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_R.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_R.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_R.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -322,46 +290,46 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -378,42 +346,8 @@ BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.SDP_READ_WIDTH_36 27_272
BRAM_R.RAMB18_Y1.SDP_WRITE_WIDTH_36 27_280
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -428,6 +362,42 @@ BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_R.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_R.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_R.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_R.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_R.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_R.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_R.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_R.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_R.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -438,6 +408,42 @@ BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188

46
kintex7/segbits_clbll_l.db
View File

@ -4,6 +4,12 @@ CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.CY 30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLL_L.SLICEL_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -80,6 +86,12 @@ CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -157,6 +169,12 @@ CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.CY 30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.F7 30_35 30_36 !30_37 !30_38
CLBLL_L.SLICEL_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -234,6 +252,11 @@ CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -320,6 +343,12 @@ CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 31_00 31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O5 30_04 31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.AFFMUX.O6 30_04 !31_00 !31_01 !31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -396,6 +425,12 @@ CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 31_24 31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BFFMUX.O6 31_24 !31_25 !31_26 !31_27
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -473,6 +508,12 @@ CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY 31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.F7 31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 31_36 !31_37 !31_38
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -550,6 +591,11 @@ CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY 30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DFFMUX.O5 30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 31_60 !31_61 !31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62

2
kintex7/segbits_clk_bufg_bot_r.db
View File

@ -152,7 +152,7 @@ CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 07_118 26_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 26_252
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 27_242
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243

2
kintex7/segbits_clk_bufg_top_r.db
View File

@ -152,7 +152,7 @@ CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE 27_240 27_255
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT 27_253
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED 26_241
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED 27_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 07_118 26_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 26_252
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 27_242
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 27_251
CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 27_243

2
kintex7/segbits_clk_hrow_bot_r.db
View File

@ -119,8 +119,6 @@ CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7_ACTIVE 29_117
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8_ACTIVE 28_118
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9_ACTIVE 29_118
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10_ACTIVE 28_80
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11_ACTIVE 29_80
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12_ACTIVE 28_81
CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13_ACTIVE 29_81
CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_CK_IN_L0 26_56 26_60
CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_CK_IN_L1 26_56 27_60

2
kintex7/segbits_clk_hrow_top_r.db
View File

@ -119,8 +119,6 @@ CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7_ACTIVE 29_117
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8_ACTIVE 28_118
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9_ACTIVE 29_118
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10_ACTIVE 28_80
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11_ACTIVE 29_80
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12_ACTIVE 28_81
CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13_ACTIVE 29_81
CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_CK_IN_L0 26_56 26_60
CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_CK_IN_L1 26_56 27_60

192
kintex7/segbits_dsp_l.db
View File

@ -0,0 +1,192 @@
DSP_L.DSP48.DSP_0.MASK[0] 27_01
DSP_L.DSP48.DSP_0.MASK[1] 26_03
DSP_L.DSP48.DSP_0.MASK[2] 27_06
DSP_L.DSP48.DSP_0.MASK[3] 26_07
DSP_L.DSP48.DSP_0.MASK[4] 26_10
DSP_L.DSP48.DSP_0.MASK[5] 27_11
DSP_L.DSP48.DSP_0.MASK[6] 26_18
DSP_L.DSP48.DSP_0.MASK[7] 27_19
DSP_L.DSP48.DSP_0.MASK[8] 26_22
DSP_L.DSP48.DSP_0.MASK[9] 27_23
DSP_L.DSP48.DSP_0.MASK[10] 27_26
DSP_L.DSP48.DSP_0.MASK[11] 26_28
DSP_L.DSP48.DSP_0.MASK[12] 26_41
DSP_L.DSP48.DSP_0.MASK[13] 27_42
DSP_L.DSP48.DSP_0.MASK[14] 26_45
DSP_L.DSP48.DSP_0.MASK[15] 27_46
DSP_L.DSP48.DSP_0.MASK[16] 26_49
DSP_L.DSP48.DSP_0.MASK[17] 27_50
DSP_L.DSP48.DSP_0.MASK[18] 27_57
DSP_L.DSP48.DSP_0.MASK[19] 26_59
DSP_L.DSP48.DSP_0.MASK[20] 26_62
DSP_L.DSP48.DSP_0.MASK[21] 27_63
DSP_L.DSP48.DSP_0.MASK[22] 26_66
DSP_L.DSP48.DSP_0.MASK[23] 27_67
DSP_L.DSP48.DSP_0.MASK[24] 27_86
DSP_L.DSP48.DSP_0.MASK[25] 26_88
DSP_L.DSP48.DSP_0.MASK[26] 27_90
DSP_L.DSP48.DSP_0.MASK[27] 26_92
DSP_L.DSP48.DSP_0.MASK[28] 27_94
DSP_L.DSP48.DSP_0.MASK[29] 26_96
DSP_L.DSP48.DSP_0.MASK[30] 27_102
DSP_L.DSP48.DSP_0.MASK[31] 26_104
DSP_L.DSP48.DSP_0.MASK[32] 27_106
DSP_L.DSP48.DSP_0.MASK[33] 26_108
DSP_L.DSP48.DSP_0.MASK[34] 27_110
DSP_L.DSP48.DSP_0.MASK[35] 26_112
DSP_L.DSP48.DSP_0.MASK[36] 27_127
DSP_L.DSP48.DSP_0.MASK[37] 26_129
DSP_L.DSP48.DSP_0.MASK[38] 26_132
DSP_L.DSP48.DSP_0.MASK[39] 27_133
DSP_L.DSP48.DSP_0.MASK[40] 26_136
DSP_L.DSP48.DSP_0.MASK[41] 27_137
DSP_L.DSP48.DSP_0.MASK[42] 27_144
DSP_L.DSP48.DSP_0.MASK[43] 26_146
DSP_L.DSP48.DSP_0.MASK[44] 26_149
DSP_L.DSP48.DSP_0.MASK[45] 27_150
DSP_L.DSP48.DSP_0.MASK[46] 26_153
DSP_L.DSP48.DSP_0.MASK[47] 26_154
DSP_L.DSP48.DSP_0.PATTERN[0] 26_01
DSP_L.DSP48.DSP_0.PATTERN[1] 26_04
DSP_L.DSP48.DSP_0.PATTERN[2] 26_05
DSP_L.DSP48.DSP_0.PATTERN[3] 27_08
DSP_L.DSP48.DSP_0.PATTERN[4] 26_09
DSP_L.DSP48.DSP_0.PATTERN[5] 26_12
DSP_L.DSP48.DSP_0.PATTERN[6] 27_17
DSP_L.DSP48.DSP_0.PATTERN[7] 26_20
DSP_L.DSP48.DSP_0.PATTERN[8] 27_21
DSP_L.DSP48.DSP_0.PATTERN[9] 27_24
DSP_L.DSP48.DSP_0.PATTERN[10] 26_26
DSP_L.DSP48.DSP_0.PATTERN[11] 26_29
DSP_L.DSP48.DSP_0.PATTERN[12] 27_40
DSP_L.DSP48.DSP_0.PATTERN[13] 26_43
DSP_L.DSP48.DSP_0.PATTERN[14] 27_44
DSP_L.DSP48.DSP_0.PATTERN[15] 26_47
DSP_L.DSP48.DSP_0.PATTERN[16] 27_48
DSP_L.DSP48.DSP_0.PATTERN[17] 26_51
DSP_L.DSP48.DSP_0.PATTERN[18] 26_57
DSP_L.DSP48.DSP_0.PATTERN[19] 26_60
DSP_L.DSP48.DSP_0.PATTERN[20] 27_61
DSP_L.DSP48.DSP_0.PATTERN[21] 26_64
DSP_L.DSP48.DSP_0.PATTERN[22] 27_65
DSP_L.DSP48.DSP_0.PATTERN[23] 26_68
DSP_L.DSP48.DSP_0.PATTERN[24] 26_86
DSP_L.DSP48.DSP_0.PATTERN[25] 27_88
DSP_L.DSP48.DSP_0.PATTERN[26] 26_90
DSP_L.DSP48.DSP_0.PATTERN[27] 27_92
DSP_L.DSP48.DSP_0.PATTERN[28] 26_94
DSP_L.DSP48.DSP_0.PATTERN[29] 26_97
DSP_L.DSP48.DSP_0.PATTERN[30] 27_101
DSP_L.DSP48.DSP_0.PATTERN[31] 27_104
DSP_L.DSP48.DSP_0.PATTERN[32] 26_106
DSP_L.DSP48.DSP_0.PATTERN[33] 27_108
DSP_L.DSP48.DSP_0.PATTERN[34] 26_110
DSP_L.DSP48.DSP_0.PATTERN[35] 27_112
DSP_L.DSP48.DSP_0.PATTERN[36] 26_127
DSP_L.DSP48.DSP_0.PATTERN[37] 26_130
DSP_L.DSP48.DSP_0.PATTERN[38] 27_131
DSP_L.DSP48.DSP_0.PATTERN[39] 26_134
DSP_L.DSP48.DSP_0.PATTERN[40] 27_135
DSP_L.DSP48.DSP_0.PATTERN[41] 26_138
DSP_L.DSP48.DSP_0.PATTERN[42] 26_144
DSP_L.DSP48.DSP_0.PATTERN[43] 27_146
DSP_L.DSP48.DSP_0.PATTERN[44] 26_148
DSP_L.DSP48.DSP_0.PATTERN[45] 26_151
DSP_L.DSP48.DSP_0.PATTERN[46] 27_152
DSP_L.DSP48.DSP_0.PATTERN[47] 26_155
DSP_L.DSP48.DSP_1.MASK[0] 27_161
DSP_L.DSP48.DSP_1.MASK[1] 26_163
DSP_L.DSP48.DSP_1.MASK[2] 27_166
DSP_L.DSP48.DSP_1.MASK[3] 26_167
DSP_L.DSP48.DSP_1.MASK[4] 26_170
DSP_L.DSP48.DSP_1.MASK[5] 27_171
DSP_L.DSP48.DSP_1.MASK[6] 26_178
DSP_L.DSP48.DSP_1.MASK[7] 27_179
DSP_L.DSP48.DSP_1.MASK[8] 26_182
DSP_L.DSP48.DSP_1.MASK[9] 27_183
DSP_L.DSP48.DSP_1.MASK[10] 27_186
DSP_L.DSP48.DSP_1.MASK[11] 26_188
DSP_L.DSP48.DSP_1.MASK[12] 26_201
DSP_L.DSP48.DSP_1.MASK[13] 27_202
DSP_L.DSP48.DSP_1.MASK[14] 26_205
DSP_L.DSP48.DSP_1.MASK[15] 27_206
DSP_L.DSP48.DSP_1.MASK[16] 26_209
DSP_L.DSP48.DSP_1.MASK[17] 27_210
DSP_L.DSP48.DSP_1.MASK[18] 27_217
DSP_L.DSP48.DSP_1.MASK[19] 26_219
DSP_L.DSP48.DSP_1.MASK[20] 26_222
DSP_L.DSP48.DSP_1.MASK[21] 27_223
DSP_L.DSP48.DSP_1.MASK[22] 26_226
DSP_L.DSP48.DSP_1.MASK[23] 27_227
DSP_L.DSP48.DSP_1.MASK[24] 27_246
DSP_L.DSP48.DSP_1.MASK[25] 26_248
DSP_L.DSP48.DSP_1.MASK[26] 27_250
DSP_L.DSP48.DSP_1.MASK[27] 26_252
DSP_L.DSP48.DSP_1.MASK[28] 27_254
DSP_L.DSP48.DSP_1.MASK[29] 26_256
DSP_L.DSP48.DSP_1.MASK[30] 27_262
DSP_L.DSP48.DSP_1.MASK[31] 26_264
DSP_L.DSP48.DSP_1.MASK[32] 27_266
DSP_L.DSP48.DSP_1.MASK[33] 26_268
DSP_L.DSP48.DSP_1.MASK[34] 27_270
DSP_L.DSP48.DSP_1.MASK[35] 26_272
DSP_L.DSP48.DSP_1.MASK[36] 27_287
DSP_L.DSP48.DSP_1.MASK[37] 26_289
DSP_L.DSP48.DSP_1.MASK[38] 26_292
DSP_L.DSP48.DSP_1.MASK[39] 27_293
DSP_L.DSP48.DSP_1.MASK[40] 26_296
DSP_L.DSP48.DSP_1.MASK[41] 27_297
DSP_L.DSP48.DSP_1.MASK[42] 27_304
DSP_L.DSP48.DSP_1.MASK[43] 26_306
DSP_L.DSP48.DSP_1.MASK[44] 26_309
DSP_L.DSP48.DSP_1.MASK[45] 27_310
DSP_L.DSP48.DSP_1.MASK[46] 26_313
DSP_L.DSP48.DSP_1.MASK[47] 26_314
DSP_L.DSP48.DSP_1.PATTERN[0] 26_161
DSP_L.DSP48.DSP_1.PATTERN[1] 26_164
DSP_L.DSP48.DSP_1.PATTERN[2] 26_165
DSP_L.DSP48.DSP_1.PATTERN[3] 27_168
DSP_L.DSP48.DSP_1.PATTERN[4] 26_169
DSP_L.DSP48.DSP_1.PATTERN[5] 26_172
DSP_L.DSP48.DSP_1.PATTERN[6] 27_177
DSP_L.DSP48.DSP_1.PATTERN[7] 26_180
DSP_L.DSP48.DSP_1.PATTERN[8] 27_181
DSP_L.DSP48.DSP_1.PATTERN[9] 27_184
DSP_L.DSP48.DSP_1.PATTERN[10] 26_186
DSP_L.DSP48.DSP_1.PATTERN[11] 26_189
DSP_L.DSP48.DSP_1.PATTERN[12] 27_200
DSP_L.DSP48.DSP_1.PATTERN[13] 26_203
DSP_L.DSP48.DSP_1.PATTERN[14] 27_204
DSP_L.DSP48.DSP_1.PATTERN[15] 26_207
DSP_L.DSP48.DSP_1.PATTERN[16] 27_208
DSP_L.DSP48.DSP_1.PATTERN[17] 26_211
DSP_L.DSP48.DSP_1.PATTERN[18] 26_217
DSP_L.DSP48.DSP_1.PATTERN[19] 26_220
DSP_L.DSP48.DSP_1.PATTERN[20] 27_221
DSP_L.DSP48.DSP_1.PATTERN[21] 26_224
DSP_L.DSP48.DSP_1.PATTERN[22] 27_225
DSP_L.DSP48.DSP_1.PATTERN[23] 26_228
DSP_L.DSP48.DSP_1.PATTERN[24] 26_246
DSP_L.DSP48.DSP_1.PATTERN[25] 27_248
DSP_L.DSP48.DSP_1.PATTERN[26] 26_250
DSP_L.DSP48.DSP_1.PATTERN[27] 27_252
DSP_L.DSP48.DSP_1.PATTERN[28] 26_254
DSP_L.DSP48.DSP_1.PATTERN[29] 26_257
DSP_L.DSP48.DSP_1.PATTERN[30] 27_261
DSP_L.DSP48.DSP_1.PATTERN[31] 27_264
DSP_L.DSP48.DSP_1.PATTERN[32] 26_266
DSP_L.DSP48.DSP_1.PATTERN[33] 27_268
DSP_L.DSP48.DSP_1.PATTERN[34] 26_270
DSP_L.DSP48.DSP_1.PATTERN[35] 27_272
DSP_L.DSP48.DSP_1.PATTERN[36] 26_287
DSP_L.DSP48.DSP_1.PATTERN[37] 26_290
DSP_L.DSP48.DSP_1.PATTERN[38] 27_291
DSP_L.DSP48.DSP_1.PATTERN[39] 26_294
DSP_L.DSP48.DSP_1.PATTERN[40] 27_295
DSP_L.DSP48.DSP_1.PATTERN[41] 26_298
DSP_L.DSP48.DSP_1.PATTERN[42] 26_304
DSP_L.DSP48.DSP_1.PATTERN[43] 27_306
DSP_L.DSP48.DSP_1.PATTERN[44] 26_308
DSP_L.DSP48.DSP_1.PATTERN[45] 26_311
DSP_L.DSP48.DSP_1.PATTERN[46] 27_312
DSP_L.DSP48.DSP_1.PATTERN[47] 26_315

192
kintex7/segbits_dsp_r.db
View File

@ -0,0 +1,192 @@
DSP_R.DSP48.DSP_0.MASK[0] 27_01
DSP_R.DSP48.DSP_0.MASK[1] 26_03
DSP_R.DSP48.DSP_0.MASK[2] 27_06
DSP_R.DSP48.DSP_0.MASK[3] 26_07
DSP_R.DSP48.DSP_0.MASK[4] 26_10
DSP_R.DSP48.DSP_0.MASK[5] 27_11
DSP_R.DSP48.DSP_0.MASK[6] 26_18
DSP_R.DSP48.DSP_0.MASK[7] 27_19
DSP_R.DSP48.DSP_0.MASK[8] 26_22
DSP_R.DSP48.DSP_0.MASK[9] 27_23
DSP_R.DSP48.DSP_0.MASK[10] 27_26
DSP_R.DSP48.DSP_0.MASK[11] 26_28
DSP_R.DSP48.DSP_0.MASK[12] 26_41
DSP_R.DSP48.DSP_0.MASK[13] 27_42
DSP_R.DSP48.DSP_0.MASK[14] 26_45
DSP_R.DSP48.DSP_0.MASK[15] 27_46
DSP_R.DSP48.DSP_0.MASK[16] 26_49
DSP_R.DSP48.DSP_0.MASK[17] 27_50
DSP_R.DSP48.DSP_0.MASK[18] 27_57
DSP_R.DSP48.DSP_0.MASK[19] 26_59
DSP_R.DSP48.DSP_0.MASK[20] 26_62
DSP_R.DSP48.DSP_0.MASK[21] 27_63
DSP_R.DSP48.DSP_0.MASK[22] 26_66
DSP_R.DSP48.DSP_0.MASK[23] 27_67
DSP_R.DSP48.DSP_0.MASK[24] 27_86
DSP_R.DSP48.DSP_0.MASK[25] 26_88
DSP_R.DSP48.DSP_0.MASK[26] 27_90
DSP_R.DSP48.DSP_0.MASK[27] 26_92
DSP_R.DSP48.DSP_0.MASK[28] 27_94
DSP_R.DSP48.DSP_0.MASK[29] 26_96
DSP_R.DSP48.DSP_0.MASK[30] 27_102
DSP_R.DSP48.DSP_0.MASK[31] 26_104
DSP_R.DSP48.DSP_0.MASK[32] 27_106
DSP_R.DSP48.DSP_0.MASK[33] 26_108
DSP_R.DSP48.DSP_0.MASK[34] 27_110
DSP_R.DSP48.DSP_0.MASK[35] 26_112
DSP_R.DSP48.DSP_0.MASK[36] 27_127
DSP_R.DSP48.DSP_0.MASK[37] 26_129
DSP_R.DSP48.DSP_0.MASK[38] 26_132
DSP_R.DSP48.DSP_0.MASK[39] 27_133
DSP_R.DSP48.DSP_0.MASK[40] 26_136
DSP_R.DSP48.DSP_0.MASK[41] 27_137
DSP_R.DSP48.DSP_0.MASK[42] 27_144
DSP_R.DSP48.DSP_0.MASK[43] 26_146
DSP_R.DSP48.DSP_0.MASK[44] 26_149
DSP_R.DSP48.DSP_0.MASK[45] 27_150
DSP_R.DSP48.DSP_0.MASK[46] 26_153
DSP_R.DSP48.DSP_0.MASK[47] 26_154
DSP_R.DSP48.DSP_0.PATTERN[0] 26_01
DSP_R.DSP48.DSP_0.PATTERN[1] 26_04
DSP_R.DSP48.DSP_0.PATTERN[2] 26_05
DSP_R.DSP48.DSP_0.PATTERN[3] 27_08
DSP_R.DSP48.DSP_0.PATTERN[4] 26_09
DSP_R.DSP48.DSP_0.PATTERN[5] 26_12
DSP_R.DSP48.DSP_0.PATTERN[6] 27_17
DSP_R.DSP48.DSP_0.PATTERN[7] 26_20
DSP_R.DSP48.DSP_0.PATTERN[8] 27_21
DSP_R.DSP48.DSP_0.PATTERN[9] 27_24
DSP_R.DSP48.DSP_0.PATTERN[10] 26_26
DSP_R.DSP48.DSP_0.PATTERN[11] 26_29
DSP_R.DSP48.DSP_0.PATTERN[12] 27_40
DSP_R.DSP48.DSP_0.PATTERN[13] 26_43
DSP_R.DSP48.DSP_0.PATTERN[14] 27_44
DSP_R.DSP48.DSP_0.PATTERN[15] 26_47
DSP_R.DSP48.DSP_0.PATTERN[16] 27_48
DSP_R.DSP48.DSP_0.PATTERN[17] 26_51
DSP_R.DSP48.DSP_0.PATTERN[18] 26_57
DSP_R.DSP48.DSP_0.PATTERN[19] 26_60
DSP_R.DSP48.DSP_0.PATTERN[20] 27_61
DSP_R.DSP48.DSP_0.PATTERN[21] 26_64
DSP_R.DSP48.DSP_0.PATTERN[22] 27_65
DSP_R.DSP48.DSP_0.PATTERN[23] 26_68
DSP_R.DSP48.DSP_0.PATTERN[24] 26_86
DSP_R.DSP48.DSP_0.PATTERN[25] 27_88
DSP_R.DSP48.DSP_0.PATTERN[26] 26_90
DSP_R.DSP48.DSP_0.PATTERN[27] 27_92
DSP_R.DSP48.DSP_0.PATTERN[28] 26_94
DSP_R.DSP48.DSP_0.PATTERN[29] 26_97
DSP_R.DSP48.DSP_0.PATTERN[30] 27_101
DSP_R.DSP48.DSP_0.PATTERN[31] 27_104
DSP_R.DSP48.DSP_0.PATTERN[32] 26_106
DSP_R.DSP48.DSP_0.PATTERN[33] 27_108
DSP_R.DSP48.DSP_0.PATTERN[34] 26_110
DSP_R.DSP48.DSP_0.PATTERN[35] 27_112
DSP_R.DSP48.DSP_0.PATTERN[36] 26_127
DSP_R.DSP48.DSP_0.PATTERN[37] 26_130
DSP_R.DSP48.DSP_0.PATTERN[38] 27_131
DSP_R.DSP48.DSP_0.PATTERN[39] 26_134
DSP_R.DSP48.DSP_0.PATTERN[40] 27_135
DSP_R.DSP48.DSP_0.PATTERN[41] 26_138
DSP_R.DSP48.DSP_0.PATTERN[42] 26_144
DSP_R.DSP48.DSP_0.PATTERN[43] 27_146
DSP_R.DSP48.DSP_0.PATTERN[44] 26_148
DSP_R.DSP48.DSP_0.PATTERN[45] 26_151
DSP_R.DSP48.DSP_0.PATTERN[46] 27_152
DSP_R.DSP48.DSP_0.PATTERN[47] 26_155
DSP_R.DSP48.DSP_1.MASK[0] 27_161
DSP_R.DSP48.DSP_1.MASK[1] 26_163
DSP_R.DSP48.DSP_1.MASK[2] 27_166
DSP_R.DSP48.DSP_1.MASK[3] 26_167
DSP_R.DSP48.DSP_1.MASK[4] 26_170
DSP_R.DSP48.DSP_1.MASK[5] 27_171
DSP_R.DSP48.DSP_1.MASK[6] 26_178
DSP_R.DSP48.DSP_1.MASK[7] 27_179
DSP_R.DSP48.DSP_1.MASK[8] 26_182
DSP_R.DSP48.DSP_1.MASK[9] 27_183
DSP_R.DSP48.DSP_1.MASK[10] 27_186
DSP_R.DSP48.DSP_1.MASK[11] 26_188
DSP_R.DSP48.DSP_1.MASK[12] 26_201
DSP_R.DSP48.DSP_1.MASK[13] 27_202
DSP_R.DSP48.DSP_1.MASK[14] 26_205
DSP_R.DSP48.DSP_1.MASK[15] 27_206
DSP_R.DSP48.DSP_1.MASK[16] 26_209
DSP_R.DSP48.DSP_1.MASK[17] 27_210
DSP_R.DSP48.DSP_1.MASK[18] 27_217
DSP_R.DSP48.DSP_1.MASK[19] 26_219
DSP_R.DSP48.DSP_1.MASK[20] 26_222
DSP_R.DSP48.DSP_1.MASK[21] 27_223
DSP_R.DSP48.DSP_1.MASK[22] 26_226
DSP_R.DSP48.DSP_1.MASK[23] 27_227
DSP_R.DSP48.DSP_1.MASK[24] 27_246
DSP_R.DSP48.DSP_1.MASK[25] 26_248
DSP_R.DSP48.DSP_1.MASK[26] 27_250
DSP_R.DSP48.DSP_1.MASK[27] 26_252
DSP_R.DSP48.DSP_1.MASK[28] 27_254
DSP_R.DSP48.DSP_1.MASK[29] 26_256
DSP_R.DSP48.DSP_1.MASK[30] 27_262
DSP_R.DSP48.DSP_1.MASK[31] 26_264
DSP_R.DSP48.DSP_1.MASK[32] 27_266
DSP_R.DSP48.DSP_1.MASK[33] 26_268
DSP_R.DSP48.DSP_1.MASK[34] 27_270
DSP_R.DSP48.DSP_1.MASK[35] 26_272
DSP_R.DSP48.DSP_1.MASK[36] 27_287
DSP_R.DSP48.DSP_1.MASK[37] 26_289
DSP_R.DSP48.DSP_1.MASK[38] 26_292
DSP_R.DSP48.DSP_1.MASK[39] 27_293
DSP_R.DSP48.DSP_1.MASK[40] 26_296
DSP_R.DSP48.DSP_1.MASK[41] 27_297
DSP_R.DSP48.DSP_1.MASK[42] 27_304
DSP_R.DSP48.DSP_1.MASK[43] 26_306
DSP_R.DSP48.DSP_1.MASK[44] 26_309
DSP_R.DSP48.DSP_1.MASK[45] 27_310
DSP_R.DSP48.DSP_1.MASK[46] 26_313
DSP_R.DSP48.DSP_1.MASK[47] 26_314
DSP_R.DSP48.DSP_1.PATTERN[0] 26_161
DSP_R.DSP48.DSP_1.PATTERN[1] 26_164
DSP_R.DSP48.DSP_1.PATTERN[2] 26_165
DSP_R.DSP48.DSP_1.PATTERN[3] 27_168
DSP_R.DSP48.DSP_1.PATTERN[4] 26_169
DSP_R.DSP48.DSP_1.PATTERN[5] 26_172
DSP_R.DSP48.DSP_1.PATTERN[6] 27_177
DSP_R.DSP48.DSP_1.PATTERN[7] 26_180
DSP_R.DSP48.DSP_1.PATTERN[8] 27_181
DSP_R.DSP48.DSP_1.PATTERN[9] 27_184
DSP_R.DSP48.DSP_1.PATTERN[10] 26_186
DSP_R.DSP48.DSP_1.PATTERN[11] 26_189
DSP_R.DSP48.DSP_1.PATTERN[12] 27_200
DSP_R.DSP48.DSP_1.PATTERN[13] 26_203
DSP_R.DSP48.DSP_1.PATTERN[14] 27_204
DSP_R.DSP48.DSP_1.PATTERN[15] 26_207
DSP_R.DSP48.DSP_1.PATTERN[16] 27_208
DSP_R.DSP48.DSP_1.PATTERN[17] 26_211
DSP_R.DSP48.DSP_1.PATTERN[18] 26_217
DSP_R.DSP48.DSP_1.PATTERN[19] 26_220
DSP_R.DSP48.DSP_1.PATTERN[20] 27_221
DSP_R.DSP48.DSP_1.PATTERN[21] 26_224
DSP_R.DSP48.DSP_1.PATTERN[22] 27_225
DSP_R.DSP48.DSP_1.PATTERN[23] 26_228
DSP_R.DSP48.DSP_1.PATTERN[24] 26_246
DSP_R.DSP48.DSP_1.PATTERN[25] 27_248
DSP_R.DSP48.DSP_1.PATTERN[26] 26_250
DSP_R.DSP48.DSP_1.PATTERN[27] 27_252
DSP_R.DSP48.DSP_1.PATTERN[28] 26_254
DSP_R.DSP48.DSP_1.PATTERN[29] 26_257
DSP_R.DSP48.DSP_1.PATTERN[30] 27_261
DSP_R.DSP48.DSP_1.PATTERN[31] 27_264
DSP_R.DSP48.DSP_1.PATTERN[32] 26_266
DSP_R.DSP48.DSP_1.PATTERN[33] 27_268
DSP_R.DSP48.DSP_1.PATTERN[34] 26_270
DSP_R.DSP48.DSP_1.PATTERN[35] 27_272
DSP_R.DSP48.DSP_1.PATTERN[36] 26_287
DSP_R.DSP48.DSP_1.PATTERN[37] 26_290
DSP_R.DSP48.DSP_1.PATTERN[38] 27_291
DSP_R.DSP48.DSP_1.PATTERN[39] 26_294
DSP_R.DSP48.DSP_1.PATTERN[40] 27_295
DSP_R.DSP48.DSP_1.PATTERN[41] 26_298
DSP_R.DSP48.DSP_1.PATTERN[42] 26_304
DSP_R.DSP48.DSP_1.PATTERN[43] 27_306
DSP_R.DSP48.DSP_1.PATTERN[44] 26_308
DSP_R.DSP48.DSP_1.PATTERN[45] 26_311
DSP_R.DSP48.DSP_1.PATTERN[46] 27_312
DSP_R.DSP48.DSP_1.PATTERN[47] 26_315

2
kintex7/segbits_int_r.db
View File

@ -128,7 +128,7 @@ INT_R.BYP_ALT5.LOGIC_OUTS23 20_31 !22_31 !23_31 !24_31 25_31
INT_R.BYP_ALT5.EE2END1 17_31 !22_31 !23_31 24_31 !25_31
INT_R.BYP_ALT5.EL1END2 17_31 22_31 !23_31 24_31 25_31
INT_R.BYP_ALT5.ER1END1 16_31 !22_31 23_31 24_31 25_31
INT_R.BYP_ALT5.GFAN0 20_31 !22_31 !23_31 24_31 !25_31
INT_R.BYP_ALT5.GFAN0 !00_10 !00_11 !01_09 !01_10 01_14 20_31 !22_31 !23_31 24_31 !25_31
INT_R.BYP_ALT5.NE2END2 16_31 !22_31 !23_31 !24_31 25_31
INT_R.BYP_ALT5.NL1END2 18_30 22_31 !23_31 24_31 25_31
INT_R.BYP_ALT5.NN2END2 16_31 !22_31 !23_31 24_31 !25_31

125
kintex7/segbits_liob33.db Normal file
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@ -0,0 +1,125 @@
LIOB33.IOB_Y0.IBUFDISABLE.I 38_82
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
LIOB33.IOB_Y0.IFF.ZINIT_Q3 28_86
LIOB33.IOB_Y0.IFF.ZINIT_Q4 28_94
LIOB33.IOB_Y0.IFF.ZINV_C 28_126 29_123 29_125
LIOB33.IOB_Y0.IFF.ZINV_OCLK 28_64
LIOB33.IOB_Y0.IFF.ZSRVAL_Q1 29_71
LIOB33.IOB_Y0.IFF.ZSRVAL_Q2 29_75
LIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85
LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
LIOB33.IOB_Y0.INOUT 30_67
LIOB33.IOB_Y0.INTERMDISABLE.I 39_89
LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
LIOB33.IOB_Y0.OFF.ZINIT_Q 33_97
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF 32_66
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR 32_70
LIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR 33_69
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 30_127
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 31_126
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 31_124
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 30_121
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 31_120
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 30_123
LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 31_116
LIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
LIOB33.IOB_Y0.SLEW.FAST !38_106 !38_110 !39_105 !39_109
LIOB33.IOB_Y0.SLEW.SLOW 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.TFF.ZINIT_Q 30_75
LIOB33.IOB_Y0.ZINV_D 29_109
LIOB33.IOB_Y0.IDELMUXE3.0 29_101
LIOB33.IOB_Y0.IFFDELMUXE3.0 28_116
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 !39_95 39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y1.IBUFDISABLE.I 39_45
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
LIOB33.IOB_Y1.IFF.ZINIT_Q3 29_41
LIOB33.IOB_Y1.IFF.ZINIT_Q4 29_33
LIOB33.IOB_Y1.IFF.ZINV_C 28_02 28_04 29_01
LIOB33.IOB_Y1.IFF.ZINV_OCLK 29_63
LIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
LIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
LIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
LIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
LIOB33.IOB_Y1.INOUT 31_60
LIOB33.IOB_Y1.INTERMDISABLE.I 38_38
LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
LIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF 33_61
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR 33_57
LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR 32_58
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 31_00
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 30_01
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 30_03
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 31_06
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 30_07
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 31_04
LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 30_11
LIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
LIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
LIOB33.IOB_Y1.PULLTYPE.PULLDOWN !38_34 !39_33 !39_35
LIOB33.IOB_Y1.PULLTYPE.PULLUP 38_34 39_33 !39_35
LIOB33.IOB_Y1.SLEW.FAST !38_18 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.SLEW.SLOW 38_18 38_22 39_17 39_21
LIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
LIOB33.IOB_Y1.ZINV_D 28_18
LIOB33.IOB_Y1.IDELMUXE3.0 28_26
LIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
LIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
LIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63

125
kintex7/segbits_riob33.db Normal file
View File

@ -0,0 +1,125 @@
RIOB33.IOB_Y0.IBUFDISABLE.I 38_82
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98
RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99
RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67
RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72
RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76
RIOB33.IOB_Y0.IFF.ZINIT_Q3 28_86
RIOB33.IOB_Y0.IFF.ZINIT_Q4 28_94
RIOB33.IOB_Y0.IFF.ZINV_C 28_126 29_123 29_125
RIOB33.IOB_Y0.IFF.ZINV_OCLK 28_64
RIOB33.IOB_Y0.IFF.ZSRVAL_Q1 29_71
RIOB33.IOB_Y0.IFF.ZSRVAL_Q2 29_75
RIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85
RIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93
RIOB33.IOB_Y0.INOUT 30_67
RIOB33.IOB_Y0.INTERMDISABLE.I 39_89
RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117
RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115
RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92
RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
RIOB33.IOB_Y0.OFF.ZINIT_Q 33_97
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF 32_66
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR 32_70
RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR 33_69
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 30_127
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 31_126
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 31_124
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 30_121
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 31_120
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 30_123
RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 31_116
RIOB33.IOB_Y0.PULLTYPE.KEEPER 38_92 38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.NONE !38_92 38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLDOWN !38_92 !38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLUP !38_92 38_94 39_93
RIOB33.IOB_Y0.SLEW.FAST !38_106 !38_110 !39_105 !39_109
RIOB33.IOB_Y0.SLEW.SLOW 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.TFF.ZINIT_Q 30_75
RIOB33.IOB_Y0.ZINV_D 29_109
RIOB33.IOB_Y0.IDELMUXE3.0 29_101
RIOB33.IOB_Y0.IFFDELMUXE3.0 28_116
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 39_95 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 39_95 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 31_86 32_66 33_111 38_64 38_112 !38_118 38_126 39_65 39_95 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 31_86 32_66 33_111 38_64 38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 31_86 32_66 33_111 38_64 38_112 !38_118 !38_126 39_65 !39_95 !39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 31_86 32_66 33_111 38_64 38_112 38_118 38_126 39_65 !39_95 39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 31_86 32_66 33_111 38_64 !38_112 38_118 !38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29
RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28
RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60
RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55
RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51
RIOB33.IOB_Y1.IFF.ZINIT_Q3 29_41
RIOB33.IOB_Y1.IFF.ZINIT_Q4 29_33
RIOB33.IOB_Y1.IFF.ZINV_C 28_02 28_04 29_01
RIOB33.IOB_Y1.IFF.ZINV_OCLK 29_63
RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF 33_61
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.DDR 33_57
RIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR 32_58
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 31_00
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 30_01
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 30_03
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 31_06
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 30_07
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 31_04
RIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 30_11
RIOB33.IOB_Y1.PULLTYPE.KEEPER !38_34 39_33 39_35
RIOB33.IOB_Y1.PULLTYPE.NONE !38_34 39_33 !39_35
RIOB33.IOB_Y1.PULLTYPE.PULLDOWN !38_34 !39_33 !39_35
RIOB33.IOB_Y1.PULLTYPE.PULLUP 38_34 39_33 !39_35
RIOB33.IOB_Y1.SLEW.FAST !38_18 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.SLEW.SLOW 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
RIOB33.IOB_Y1.ZINV_D 28_18
RIOB33.IOB_Y1.IDELMUXE3.0 28_26
RIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63

128
kintex7/tilegrid.json
View File

@ -245895,7 +245895,21 @@
"type": "IO_INT_INTERFACE_R"
},
"LIOB33_SING_X0Y0": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "LIOB33"
},
"baseaddr": "0x00420000",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 0,
"grid_y": 207,
"sites": {
@ -245904,7 +245918,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y100": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "LIOB33"
},
"baseaddr": "0x00000000",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 0,
"grid_y": 103,
"sites": {
@ -245913,7 +245941,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y149": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "LIOB33"
},
"baseaddr": "0x00000000",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 0,
"grid_y": 53,
"sites": {
@ -245922,7 +245964,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y150": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "LIOB33"
},
"baseaddr": "0x00020000",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 0,
"grid_y": 51,
"sites": {
@ -245931,7 +245987,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y199": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "LIOB33"
},
"baseaddr": "0x00020000",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 0,
"grid_y": 1,
"sites": {
@ -245940,7 +246010,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y49": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "LIOB33"
},
"baseaddr": "0x00420000",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 0,
"grid_y": 157,
"sites": {
@ -245949,7 +246033,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y50": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y0"
},
"start_offset": 2,
"type": "LIOB33"
},
"baseaddr": "0x00400000",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 0,
"grid_y": 155,
"sites": {
@ -245958,7 +246056,21 @@
"type": "LIOB33_SING"
},
"LIOB33_SING_X0Y99": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"alias": {
"sites": {
"IOB33_Y0": "IOB33_Y1"
},
"start_offset": 0,
"type": "LIOB33"
},
"baseaddr": "0x00400000",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 0,
"grid_y": 105,
"sites": {