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prjxray-db
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Updating all based on "Merge pull request #1207 from SymbiFlow/dependabot/submodules/third_party/googletest-10b1902". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2020-01-27 16:36:50 -08:00
parent 31f51ac5ec
commit 5070230ca4
73 changed files with 2782451 additions and 1320523 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
artix7/harness/basys3/swbut_50/design.json
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@ -3109,22 +3109,17 @@
"CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
"CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_BOT_R_CK_BUFG_CASCO0.CLK_HROW_CK_BUFRCLK_R3",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_CK_BUFRCLK_R3_ACTIVE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y8.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y8.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L8.CLK_HROW_R_CK_GCLK0",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_BOT_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
"CLK_HROW_BOT_R_X60Y26.CLK_HROW_CK_IN_R0_ACTIVE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
"CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CK_BUFRCLK3_USED",
"HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK8_USED",
"HCLK_IOI3_X113Y26.BUFR_Y0.BUFR_DIVIDE.BYPASS",
"HCLK_IOI3_X113Y26.BUFR_Y1.BUFR_DIVIDE.D2",
"HCLK_IOI3_X113Y26.BUFR_Y1.IN_USE",
"HCLK_IOI3_X113Y26.BUFR_Y2.BUFR_DIVIDE.BYPASS",
"HCLK_IOI3_X113Y26.BUFR_Y3.BUFR_DIVIDE.BYPASS",
"HCLK_IOI3_X113Y26.HCLK_IOI_RCLK_BEFORE_DIV3.HCLK_IOI_RCLK0",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_USED",
"HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
"HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED",
"INT_L_X0Y0.IMUX_L34.SS2END1",
"INT_L_X0Y1.IMUX_L34.WW2END0",
"INT_L_X0Y10.LV_L0.NR1END0",
@ -3439,8 +3434,6 @@
"INT_R_X41Y55.SS6BEG0.SE6END0",
"INT_R_X41Y77.ER1BEG1.EE2END0",
"INT_R_X41Y91.SE6BEG0.SE6END0",
"INT_R_X43Y23.BYP_ALT3.GFAN1",
"INT_R_X43Y23.GFAN1.GND_WIRE",
"INT_R_X43Y32.IMUX34.ER1END1",
"INT_R_X43Y37.IMUX34.SL1END1",
"INT_R_X43Y38.IMUX34.SE2END1",

1108
artix7/mask_dsp_l.db
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File diff suppressed because it is too large Load Diff

1126
artix7/mask_dsp_r.db
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File diff suppressed because it is too large Load Diff

2
artix7/mask_lioi3.db
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@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_lioi3_tbytesrc.db
View File

@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_lioi3_tbyteterm.db
View File

@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3.db
View File

@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3_tbytesrc.db
View File

@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

2
artix7/mask_rioi3_tbyteterm.db
View File

@ -1,4 +1,5 @@
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_24
@ -6,6 +7,7 @@ bit 25_31
bit 25_32
bit 25_34
bit 25_35
bit 25_39
bit 25_47
bit 25_48
bit 25_51

72
artix7/segbits_dsp_l.db
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@ -1,6 +1,11 @@
DSP_L.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_L.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_L.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_L.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 27_47
DSP_L.DSP48.DSP_0.MASK[0] 27_01
DSP_L.DSP48.DSP_0.MASK[1] 26_03
DSP_L.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_L.DSP48.DSP_0.PATTERN[44] 26_148
DSP_L.DSP48.DSP_0.PATTERN[45] 26_151
DSP_L.DSP48.DSP_0.PATTERN[46] 27_152
DSP_L.DSP48.DSP_0.PATTERN[47] 26_155
DSP_L.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] 27_75
DSP_L.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_L.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_L.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_L.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 27_207
DSP_L.DSP48.DSP_1.MASK[0] 27_161
DSP_L.DSP48.DSP_1.MASK[1] 26_163
DSP_L.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[44] 26_308
DSP_L.DSP48.DSP_1.PATTERN[45] 26_311
DSP_L.DSP48.DSP_1.PATTERN[46] 27_312
DSP_L.DSP48.DSP_1.PATTERN[47] 26_315
DSP_L.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] 27_235

72
artix7/segbits_dsp_l.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_L.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_L.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_L.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_L.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_L.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_L.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_L.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_L.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_L.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_L.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_L.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_L.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_L.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_L.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_L.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_L.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_L.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

72
artix7/segbits_dsp_r.db
View File

@ -1,6 +1,11 @@
DSP_R.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_R.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_R.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_R.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 27_47
DSP_R.DSP48.DSP_0.MASK[0] 27_01
DSP_R.DSP48.DSP_0.MASK[1] 26_03
DSP_R.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_R.DSP48.DSP_0.PATTERN[44] 26_148
DSP_R.DSP48.DSP_0.PATTERN[45] 26_151
DSP_R.DSP48.DSP_0.PATTERN[46] 27_152
DSP_R.DSP48.DSP_0.PATTERN[47] 26_155
DSP_R.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] 27_75
DSP_R.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_R.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_R.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_R.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 27_207
DSP_R.DSP48.DSP_1.MASK[0] 27_161
DSP_R.DSP48.DSP_1.MASK[1] 26_163
DSP_R.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[44] 26_308
DSP_R.DSP48.DSP_1.PATTERN[45] 26_311
DSP_R.DSP48.DSP_1.PATTERN[46] 27_312
DSP_R.DSP48.DSP_1.PATTERN[47] 26_315
DSP_R.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] 27_235

72
artix7/segbits_dsp_r.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_R.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_R.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_R.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_R.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_R.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_R.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_R.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_R.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_R.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_R.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_R.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_R.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_R.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_R.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_R.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_R.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_R.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

8
artix7/segbits_int_l.origin_info.db
View File

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INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

6
artix7/segbits_int_r.origin_info.db
View File

@ -353,7 +353,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
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0
artix7/xc7a35tcpg236-1_package_pins.csv → artix7/xc7a35tcpg236-1/package_pins.csv
View File

637
artix7/xc7a50tfgg484-1.json → artix7/xc7a35tcpg236-1/part.json
View File

@ -1,88 +1,78 @@
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@ -91,8 +81,14 @@
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@ -157,288 +289,156 @@
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@ -447,13 +447,12 @@
}
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},
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0
artix7/xc7a35tcpg236-1.yaml → artix7/xc7a35tcpg236-1/part.yaml
View File

923756
artix7/tileconn.json → artix7/xc7a35tcpg236-1/tileconn.json
View File

File diff suppressed because it is too large Load Diff

0
artix7/tilegrid.json → artix7/xc7a35tcpg236-1/tilegrid.json
View File

0
artix7/xc7a35tcsg324-1_package_pins.csv → artix7/xc7a35tcsg324-1/package_pins.csv
View File

604
artix7/xc7a35tcsg324-1.json → artix7/xc7a35tcsg324-1/part.json
View File

@ -1,4 +1,13 @@
{
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@ -6,65 +15,20 @@
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@ -73,83 +37,128 @@
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0
artix7/xc7a35tcsg324-1.yaml → artix7/xc7a35tcsg324-1/part.yaml
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artix7/xc7a35tcsg324-1/tileconn.json Normal file
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253176
artix7/xc7a35tcsg324-1/tilegrid.json Normal file
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0
artix7/xc7a50tfgg484-1_package_pins.csv → artix7/xc7a50tfgg484-1/package_pins.csv
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573
artix7/xc7a35tcpg236-1.json → artix7/xc7a50tfgg484-1/part.json
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@ -19,137 +19,137 @@
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@ -176,137 +176,137 @@
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@ -447,12 +447,13 @@
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0
artix7/xc7a50tfgg484-1.yaml → artix7/xc7a50tfgg484-1/part.yaml
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artix7/xc7a50tfgg484-1/tileconn.json Normal file
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253176
artix7/xc7a50tfgg484-1/tilegrid.json Normal file
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1234
kintex7/mask_dsp_l.db
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kintex7/mask_dsp_r.db
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2
kintex7/mask_lioi3.db
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@ -1,5 +1,4 @@
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bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

2
kintex7/mask_lioi3_tbytesrc.db
View File

@ -1,5 +1,4 @@
bit 25_07
bit 25_16
bit 25_20
bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

2
kintex7/mask_lioi3_tbyteterm.db
View File

@ -1,5 +1,4 @@
bit 25_07
bit 25_16
bit 25_20
bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

2
kintex7/mask_rioi3.db
View File

@ -1,5 +1,4 @@
bit 25_07
bit 25_16
bit 25_20
bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

2
kintex7/mask_rioi3_tbytesrc.db
View File

@ -1,5 +1,4 @@
bit 25_07
bit 25_16
bit 25_20
bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

2
kintex7/mask_rioi3_tbyteterm.db
View File

@ -1,5 +1,4 @@
bit 25_07
bit 25_16
bit 25_20
bit 25_21
bit 25_31
@ -16,7 +15,6 @@ bit 25_71
bit 25_84
bit 25_85
bit 25_95
bit 25_96
bit 25_98
bit 25_99
bit 25_111

72
kintex7/segbits_dsp_l.db
View File

@ -1,6 +1,11 @@
DSP_L.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_L.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_L.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_L.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 27_47
DSP_L.DSP48.DSP_0.MASK[0] 27_01
DSP_L.DSP48.DSP_0.MASK[1] 26_03
DSP_L.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_L.DSP48.DSP_0.PATTERN[44] 26_148
DSP_L.DSP48.DSP_0.PATTERN[45] 26_151
DSP_L.DSP48.DSP_0.PATTERN[46] 27_152
DSP_L.DSP48.DSP_0.PATTERN[47] 26_155
DSP_L.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] 27_75
DSP_L.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_L.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_L.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_L.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 27_207
DSP_L.DSP48.DSP_1.MASK[0] 27_161
DSP_L.DSP48.DSP_1.MASK[1] 26_163
DSP_L.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[44] 26_308
DSP_L.DSP48.DSP_1.PATTERN[45] 26_311
DSP_L.DSP48.DSP_1.PATTERN[46] 27_312
DSP_L.DSP48.DSP_1.PATTERN[47] 26_315
DSP_L.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] 27_235

72
kintex7/segbits_dsp_l.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_L.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_L.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_L.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_L.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_L.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_L.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_L.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_L.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_L.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_L.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_L.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_L.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_L.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_L.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_L.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_L.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_L.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

72
kintex7/segbits_dsp_r.db
View File

@ -1,6 +1,11 @@
DSP_R.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_R.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_R.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_R.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 27_47
DSP_R.DSP48.DSP_0.MASK[0] 27_01
DSP_R.DSP48.DSP_0.MASK[1] 26_03
DSP_R.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_R.DSP48.DSP_0.PATTERN[44] 26_148
DSP_R.DSP48.DSP_0.PATTERN[45] 26_151
DSP_R.DSP48.DSP_0.PATTERN[46] 27_152
DSP_R.DSP48.DSP_0.PATTERN[47] 26_155
DSP_R.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] 27_75
DSP_R.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_R.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_R.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_R.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 27_207
DSP_R.DSP48.DSP_1.MASK[0] 27_161
DSP_R.DSP48.DSP_1.MASK[1] 26_163
DSP_R.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[44] 26_308
DSP_R.DSP48.DSP_1.PATTERN[45] 26_311
DSP_R.DSP48.DSP_1.PATTERN[46] 27_312
DSP_R.DSP48.DSP_1.PATTERN[47] 26_315
DSP_R.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] 27_235

72
kintex7/segbits_dsp_r.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_R.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_R.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_R.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_R.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_R.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_R.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_R.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_R.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_R.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_R.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_R.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_R.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_R.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_R.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_R.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_R.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_R.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

12
kintex7/segbits_int_l.origin_info.db
View File

@ -172,7 +172,7 @@ INT_L.BYP_ALT7.EE2END3 origin:050-pip-seed !22_63 !23_63 !25_63 17_63 24_63
INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@ -676,7 +676,7 @@ INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
@ -2193,7 +2193,7 @@ INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L13 origin:050-pip-seed 10_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L19 origin:050-pip-seed 08_17 14_17
@ -2431,7 +2431,7 @@ INT_L.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@ -3295,7 +3295,7 @@ INT_L.SW6BEG2.SW6END2 origin:050-pip-seed 03_45 05_44
INT_L.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47
INT_L.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47
INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_L.SW6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L15 origin:050-pip-seed 03_60 04_62
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

8
kintex7/segbits_int_r.origin_info.db
View File

@ -373,7 +373,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_R.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -2173,7 +2173,7 @@ INT_R.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_R.NE6BEG3.EE2END3 origin:050-pip-seed 03_52 05_55
INT_R.NE6BEG3.EE4END3 origin:050-pip-seed 05_52 05_55
INT_R.NE6BEG3.LH0 origin:056-pip-rem 04_54 05_52
@ -2431,7 +2431,7 @@ INT_R.NN6BEG3.NN6END3 origin:050-pip-seed 02_54 07_55
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_R.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_33 07_33
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

16
kintex7/segbits_liob33.db
View File

@ -15,13 +15,16 @@ LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_1
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135.STEPDOWN 39_95
LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.IN 38_86 39_85 !39_87
LIOB33.IOB_Y0.LVCMOS15_SSTL135.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 !39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127
@ -29,9 +32,8 @@ LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127
LIOB33.IOB_Y0.SSTL135.IN !38_86 39_87
LIOB33.IOB_Y0.SSTL135.IN_DIFF 38_86 39_87
LIOB33.IOB_Y0.SSTL135.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.SSTL135.IN !38_86 !39_85 39_87
LIOB33.IOB_Y0.SSTL135.IN_DIFF 38_86 !39_85 39_87
LIOB33.IOB_Y0.SSTL135.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111
LIOB33.IOB_Y1.IBUFDISABLE.I 39_45
LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07

16
kintex7/segbits_liob33.origin_info.db
View File

@ -9,13 +9,16 @@ LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origi
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135.STEPDOWN origin:030-iob 39_95
LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_119 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_117 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_119 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.IN origin:030-iob !39_87 38_86 39_85
LIOB33.IOB_Y0.LVCMOS15_SSTL135.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_119 39_125 39_65
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_117 39_119 39_65
LIOB33.IOB_Y0.LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_65
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_117 39_65
LIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65
@ -28,9 +31,8 @@ LIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94
LIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93
LIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93
LIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65
LIOB33.IOB_Y0.SSTL135.IN origin:030-iob !38_86 39_87
LIOB33.IOB_Y0.SSTL135.IN_DIFF origin:030-iob 38_86 39_87
LIOB33.IOB_Y0.SSTL135.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125
LIOB33.IOB_Y0.SSTL135.IN origin:030-iob !38_86 !39_85 39_87
LIOB33.IOB_Y0.SSTL135.IN_DIFF origin:030-iob !39_85 38_86 39_87
LIOB33.IOB_Y0.SSTL135.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
LIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84
LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45

16
kintex7/segbits_riob33.db
View File

@ -15,13 +15,16 @@ RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_1
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135.STEPDOWN 39_95
RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 38_112 !38_118 !38_126 39_65 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 39_113 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 38_112 !38_118 38_126 39_65 39_113 !39_117 39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 39_113 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_113 39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.IN 38_86 39_85 !39_87
RIOB33.IOB_Y0.LVCMOS15_SSTL135.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 38_112 !38_118 38_126 39_65 39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18_LVCMOS25.DRIVE.I4 38_64 38_112 38_118 !38_126 39_65 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 38_112 !38_118 !38_126 39_65 !39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 38_112 38_118 38_126 39_65 39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 38_64 !38_112 38_118 !38_126 39_65 39_117 !39_119 !39_125 39_127
@ -29,9 +32,8 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 38_64 !38_112 38_118 !38_126 39_65 !39_117
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 38_64 !38_112 !38_118 38_126 39_65 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 38_64 !38_112 !38_118 38_126 39_65 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED 38_64 38_112 38_118 38_126 39_65 39_113 39_117 39_119 !39_125 39_127
RIOB33.IOB_Y0.SSTL135.IN !38_86 39_87
RIOB33.IOB_Y0.SSTL135.IN_DIFF 38_86 39_87
RIOB33.IOB_Y0.SSTL135.IN_ONLY !38_64 !38_112 38_118 !38_126 !39_65 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.SSTL135.IN !38_86 !39_85 39_87
RIOB33.IOB_Y0.SSTL135.IN_DIFF 38_86 !39_85 39_87
RIOB33.IOB_Y0.SSTL135.SLEW.FAST !38_106 38_110 39_105 39_107 39_109 39_111
RIOB33.IOB_Y1.IBUFDISABLE.I 39_45
RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 38_04 38_06 39_05 39_07

16
kintex7/segbits_riob33.origin_info.db
View File

@ -9,13 +9,16 @@ RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origi
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135.STEPDOWN origin:030-iob 39_95
RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 38_112 38_64 39_119 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_117 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_119 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15_LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 38_112 38_64 39_113 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_113 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.IN origin:030-iob !39_87 38_86 39_85
RIOB33.IOB_Y0.LVCMOS15_SSTL135.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 38_112 38_126 38_64 39_119 39_125 39_65
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 38_112 38_126 38_64 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 38_112 38_126 38_64 39_117 39_119 39_65
RIOB33.IOB_Y0.LVCMOS18_LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 38_112 38_118 38_64 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 38_112 38_64 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 38_112 38_118 38_126 38_64 39_117 39_65
RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_119 !39_125 38_118 38_64 39_117 39_127 39_65
@ -28,9 +31,8 @@ RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94
RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93
RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93
RIOB33.IOB_Y0.SSTL135.DRIVE.I_FIXED origin:030-iob !39_125 38_112 38_118 38_126 38_64 39_113 39_117 39_119 39_127 39_65
RIOB33.IOB_Y0.SSTL135.IN origin:030-iob !38_86 39_87
RIOB33.IOB_Y0.SSTL135.IN_DIFF origin:030-iob 38_86 39_87
RIOB33.IOB_Y0.SSTL135.IN_ONLY origin:030-iob !38_112 !38_126 !38_64 !39_117 !39_127 !39_65 38_118 39_113 39_119 39_125
RIOB33.IOB_Y0.SSTL135.IN origin:030-iob !38_86 !39_85 39_87
RIOB33.IOB_Y0.SSTL135.IN_DIFF origin:030-iob !39_85 38_86 39_87
RIOB33.IOB_Y0.SSTL135.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
RIOB33.IOB_Y0.ZIBUF_LOW_PWR origin:030-iob 38_84
RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45

0
kintex7/xc7k70tfbg676-2_package_pins.csv → kintex7/xc7k70tfbg676-2/package_pins.csv
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814
kintex7/xc7k70tfbg676-2.json → kintex7/xc7k70tfbg676-2/part.json
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File diff suppressed because it is too large Load Diff

0
kintex7/xc7k70tfbg676-2.yaml → kintex7/xc7k70tfbg676-2/part.yaml
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924394
kintex7/tileconn.json → kintex7/xc7k70tfbg676-2/tileconn.json
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File diff suppressed because it is too large Load Diff

0
kintex7/tilegrid.json → kintex7/xc7k70tfbg676-2/tilegrid.json
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1075
zynq7/mask_dsp_l.db
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File diff suppressed because it is too large Load Diff

1008
zynq7/mask_dsp_r.db
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File diff suppressed because it is too large Load Diff

1
zynq7/mask_lioi3.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

1
zynq7/mask_lioi3_tbytesrc.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

1
zynq7/mask_lioi3_tbyteterm.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

1
zynq7/mask_rioi3.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

1
zynq7/mask_rioi3_tbytesrc.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

1
zynq7/mask_rioi3_tbyteterm.db
View File

@ -1,6 +1,5 @@
bit 25_00
bit 25_07
bit 25_08
bit 25_20
bit 25_21
bit 25_23

72
zynq7/segbits_dsp_l.db
View File

@ -1,6 +1,11 @@
DSP_L.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_L.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_L.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_L.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 27_47
DSP_L.DSP48.DSP_0.MASK[0] 27_01
DSP_L.DSP48.DSP_0.MASK[1] 26_03
DSP_L.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_L.DSP48.DSP_0.PATTERN[44] 26_148
DSP_L.DSP48.DSP_0.PATTERN[45] 26_151
DSP_L.DSP48.DSP_0.PATTERN[46] 27_152
DSP_L.DSP48.DSP_0.PATTERN[47] 26_155
DSP_L.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] 27_75
DSP_L.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_L.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_L.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_L.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 27_207
DSP_L.DSP48.DSP_1.MASK[0] 27_161
DSP_L.DSP48.DSP_1.MASK[1] 26_163
DSP_L.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[44] 26_308
DSP_L.DSP48.DSP_1.PATTERN[45] 26_311
DSP_L.DSP48.DSP_1.PATTERN[46] 27_312
DSP_L.DSP48.DSP_1.PATTERN[47] 26_315
DSP_L.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] 27_235

72
zynq7/segbits_dsp_l.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_L.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_L.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_L.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_L.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_L.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_L.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_L.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_L.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_L.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_L.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_L.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_L.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_L.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_L.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_L.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_L.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_L.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_L.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_L.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_L.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_L.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_L.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_L.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_L.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_L.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_L.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 27_93
DSP_L.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_L.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_L.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_L.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_L.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_L.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_L.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_L.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_L.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_L.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_L.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_L.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_L.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_L.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_L.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_L.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_L.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_L.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_L.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_L.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_L.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_L.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_L.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_L.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_L.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_L.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_L.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_L.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_L.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_L.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_L.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_L.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_L.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_L.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_L.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_L.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_L.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_L.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_L.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_L.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_L.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_L.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_L.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_L.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

72
zynq7/segbits_dsp_r.db
View File

@ -1,6 +1,11 @@
DSP_R.DSP48.DSP_0.A_INPUT[0] 27_84
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] 26_78
DSP_R.DSP48.DSP_0.AREG_0 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH 26_78
DSP_R.DSP48.DSP_0.B_INPUT[0] 26_11
DSP_R.DSP48.DSP_0.BREG_0 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 27_47
DSP_R.DSP48.DSP_0.MASK[0] 27_01
DSP_R.DSP48.DSP_0.MASK[1] 26_03
DSP_R.DSP48.DSP_0.MASK[2] 27_06
@ -97,20 +102,50 @@ DSP_R.DSP48.DSP_0.PATTERN[44] 26_148
DSP_R.DSP48.DSP_0.PATTERN[45] 26_151
DSP_R.DSP48.DSP_0.PATTERN[46] 27_152
DSP_R.DSP48.DSP_0.PATTERN[47] 26_155
DSP_R.DSP48.DSP_0.SEL_MASK[1] 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] 26_02 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] 27_75
DSP_R.DSP48.DSP_1.A_INPUT[0] 27_244
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] 26_238
DSP_R.DSP48.DSP_1.AREG_0 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH 26_238
DSP_R.DSP48.DSP_1.B_INPUT[0] 26_171
DSP_R.DSP48.DSP_1.BREG_0 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 27_207
DSP_R.DSP48.DSP_1.MASK[0] 27_161
DSP_R.DSP48.DSP_1.MASK[1] 26_163
DSP_R.DSP48.DSP_1.MASK[2] 27_166
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[44] 26_308
DSP_R.DSP48.DSP_1.PATTERN[45] 26_311
DSP_R.DSP48.DSP_1.PATTERN[46] 27_312
DSP_R.DSP48.DSP_1.PATTERN[47] 26_315
DSP_R.DSP48.DSP_1.SEL_MASK[1] 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] 27_235

72
zynq7/segbits_dsp_r.origin_info.db
View File

@ -1,5 +1,10 @@
DSP_R.DSP48.DSP_0.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.AREG_0 origin:100-dsp-mskpat 26_113 26_137 27_111
DSP_R.DSP48.DSP_0.AREG_2 origin:100-dsp-mskpat 27_136
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_79
DSP_R.DSP48.DSP_0.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_78
DSP_R.DSP48.DSP_0.A_INPUT[0] origin:100-dsp-mskpat 27_84
DSP_R.DSP48.DSP_0.BREG_0 origin:100-dsp-mskpat 26_40 26_48 27_38
DSP_R.DSP48.DSP_0.BREG_2 origin:100-dsp-mskpat 27_47
DSP_R.DSP48.DSP_0.B_INPUT[0] origin:100-dsp-mskpat 26_11
DSP_R.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01
DSP_R.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26
@ -97,19 +102,49 @@ DSP_R.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17
DSP_R.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20
DSP_R.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21
DSP_R.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24
DSP_R.DSP48.DSP_0.SEL_MASK[1] origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_C origin:100-dsp-mskpat 26_83
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_82
DSP_R.DSP48.DSP_0.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_81 27_82
DSP_R.DSP48.DSP_0.USE_DPORT[0] origin:100-dsp-mskpat 26_95
DSP_R.DSP48.DSP_0.USE_SIMD[1] origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_143 27_52
DSP_R.DSP48.DSP_0.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_84
DSP_R.DSP48.DSP_0.ZADREG[0] origin:100-dsp-mskpat 27_95
DSP_R.DSP48.DSP_0.ZALUMODEREG[0] origin:100-dsp-mskpat 26_54
DSP_R.DSP48.DSP_0.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_139
DSP_R.DSP48.DSP_0.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_49
DSP_R.DSP48.DSP_0.ZCARRYINREG[0] origin:100-dsp-mskpat 26_02
DSP_R.DSP48.DSP_0.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_10
DSP_R.DSP48.DSP_0.ZCREG[0] origin:100-dsp-mskpat 26_76
DSP_R.DSP48.DSP_0.ZDREG[0] origin:100-dsp-mskpat 26_02 27_93
DSP_R.DSP48.DSP_0.ZINMODEREG[0] origin:100-dsp-mskpat 26_87
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_58
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_45
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_61
DSP_R.DSP48.DSP_0.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_54
DSP_R.DSP48.DSP_0.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_09
DSP_R.DSP48.DSP_0.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_77
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_118
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_119
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_66
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_69
DSP_R.DSP48.DSP_0.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_53
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_41
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_44
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_29
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_22
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_21
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_19
DSP_R.DSP48.DSP_0.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_13
DSP_R.DSP48.DSP_0.ZMREG[0] origin:100-dsp-mskpat 26_38
DSP_R.DSP48.DSP_0.ZOPMODEREG[0] origin:100-dsp-mskpat 26_25
DSP_R.DSP48.DSP_0.ZPREG[0] origin:100-dsp-mskpat 27_75
DSP_R.DSP48.DSP_1.AUTORESET_PATDET[0] origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.AREG_0 origin:100-dsp-mskpat 26_273 26_297 27_271
DSP_R.DSP48.DSP_1.AREG_2 origin:100-dsp-mskpat 27_296
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET origin:100-dsp-mskpat 26_239
DSP_R.DSP48.DSP_1.AUTORESET_PATDET_RESET_NOT_MATCH origin:100-dsp-mskpat 26_238
DSP_R.DSP48.DSP_1.A_INPUT[0] origin:100-dsp-mskpat 27_244
DSP_R.DSP48.DSP_1.BREG_0 origin:100-dsp-mskpat 26_200 26_208 27_198
DSP_R.DSP48.DSP_1.BREG_2 origin:100-dsp-mskpat 27_207
DSP_R.DSP48.DSP_1.B_INPUT[0] origin:100-dsp-mskpat 26_171
DSP_R.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161
DSP_R.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186
@ -207,14 +242,39 @@ DSP_R.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177
DSP_R.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180
DSP_R.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181
DSP_R.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184
DSP_R.DSP48.DSP_1.SEL_MASK[1] origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_C origin:100-dsp-mskpat 26_243
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE1 origin:100-dsp-mskpat 27_242
DSP_R.DSP48.DSP_1.SEL_MASK_ROUNDING_MODE2 origin:100-dsp-mskpat 27_241 27_242
DSP_R.DSP48.DSP_1.USE_DPORT[0] origin:100-dsp-mskpat 26_255
DSP_R.DSP48.DSP_1.USE_SIMD[1] origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12 origin:100-dsp-mskpat 26_303 27_212
DSP_R.DSP48.DSP_1.USE_SIMD_FOUR12_TWO24 origin:100-dsp-mskpat 26_244
DSP_R.DSP48.DSP_1.ZADREG[0] origin:100-dsp-mskpat 27_255
DSP_R.DSP48.DSP_1.ZALUMODEREG[0] origin:100-dsp-mskpat 26_214
DSP_R.DSP48.DSP_1.ZAREG_2_ACASCREG_1 origin:100-dsp-mskpat 26_299
DSP_R.DSP48.DSP_1.ZBREG_2_BCASCREG_1 origin:100-dsp-mskpat 27_209
DSP_R.DSP48.DSP_1.ZCARRYINREG[0] origin:100-dsp-mskpat 26_162
DSP_R.DSP48.DSP_1.ZCARRYINSELREG[0] origin:100-dsp-mskpat 27_170
DSP_R.DSP48.DSP_1.ZCREG[0] origin:100-dsp-mskpat 26_236
DSP_R.DSP48.DSP_1.ZDREG[0] origin:100-dsp-mskpat 27_253
DSP_R.DSP48.DSP_1.ZINMODEREG[0] origin:100-dsp-mskpat 26_247
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[0] origin:100-dsp-mskpat 27_218
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[1] origin:100-dsp-mskpat 27_205
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[2] origin:100-dsp-mskpat 26_221
DSP_R.DSP48.DSP_1.ZIS_ALUMODE_INVERTED[3] origin:100-dsp-mskpat 27_214
DSP_R.DSP48.DSP_1.ZIS_CARRYIN_INVERTED origin:100-dsp-mskpat 27_169
DSP_R.DSP48.DSP_1.ZIS_CLK_INVERTED origin:100-dsp-mskpat 27_237
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[0] origin:100-dsp-mskpat 27_278
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[1] origin:100-dsp-mskpat 27_279
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[2] origin:100-dsp-mskpat 27_226
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[3] origin:100-dsp-mskpat 27_229
DSP_R.DSP48.DSP_1.ZIS_INMODE_INVERTED[4] origin:100-dsp-mskpat 27_213
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[0] origin:100-dsp-mskpat 27_201
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[1] origin:100-dsp-mskpat 26_204
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[2] origin:100-dsp-mskpat 27_189
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[3] origin:100-dsp-mskpat 27_182
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[4] origin:100-dsp-mskpat 26_181
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[5] origin:100-dsp-mskpat 26_179
DSP_R.DSP48.DSP_1.ZIS_OPMODE_INVERTED[6] origin:100-dsp-mskpat 27_173
DSP_R.DSP48.DSP_1.ZMREG[0] origin:100-dsp-mskpat 26_198
DSP_R.DSP48.DSP_1.ZOPMODEREG[0] origin:100-dsp-mskpat 26_185
DSP_R.DSP48.DSP_1.ZPREG[0] origin:100-dsp-mskpat 27_235

14
zynq7/segbits_int_l.origin_info.db
View File

@ -172,7 +172,7 @@ INT_L.BYP_ALT7.EE2END3 origin:050-pip-seed !22_63 !23_63 !25_63 17_63 24_63
INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
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8
zynq7/segbits_int_r.origin_info.db
View File

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0
zynq7/xc7z010clg400-1_package_pins.csv → zynq7/xc7z010clg400-1/package_pins.csv
View File

554
zynq7/xc7z010clg400-1.json → zynq7/xc7z010clg400-1/part.json
View File

@ -1,4 +1,9 @@
{
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@ -6,192 +11,192 @@
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@ -205,192 +210,192 @@
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@ -398,10 +403,5 @@
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}

0
zynq7/xc7z010clg400-1.yaml → zynq7/xc7z010clg400-1/part.yaml
View File

4
zynq7/xc7z010clg400-1/required_features.fasm Normal file
View File

@ -0,0 +1,4 @@
CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP1
CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP2
CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP3

789152
zynq7/tileconn.json → zynq7/xc7z010clg400-1/tileconn.json
View File

File diff suppressed because it is too large Load Diff

0
zynq7/tilegrid.json → zynq7/xc7z010clg400-1/tilegrid.json
View File