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Updating info based on "Merge pull request #672 from litghost/save_logs_on_success". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-02-23 01:27:40 +00:00
parent 02eaf47e7d
commit 4ac85673b0
5 changed files with 74033 additions and 74033 deletions
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34
Info.md
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@ -37,20 +37,20 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details # Details
Last updated on Fri Feb 22 22:26:23 UTC 2019 (2019-02-22T22:26:23+00:00). Last updated on Sat Feb 23 01:27:39 UTC 2019 (2019-02-23T01:27:39+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [aa88f68](https://github.com/SymbiFlow/prjxray/commit/aa88f68da77b0e139362992aa94d7e8cbdf2fa98). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [78565b6](https://github.com/SymbiFlow/prjxray/commit/78565b6d23bd89cbaf362ea550622b56ba738290).
Latest commit was; Latest commit was;
``` ```
commit aa88f68da77b0e139362992aa94d7e8cbdf2fa98 commit 78565b6d23bd89cbaf362ea550622b56ba738290
Merge: 1e410e6 8536a17 Merge: 8fde4e2 acf7aaf
Author: litghost <537074+litghost@users.noreply.github.com> Author: Tim Ansell <me@mith.ro>
Date: Tue Feb 19 16:48:47 2019 -0800 Date: Fri Feb 22 11:49:51 2019 -0800
Merge pull request #668 from litghost/add_missing_cascade_bits Merge pull request #672 from litghost/save_logs_on_success
Add CASCOUT_*_ACTIVE bits. Save fuzzer logs, even on success.
``` ```
@ -59,7 +59,7 @@ Date: Tue Feb 19 16:48:47 2019 -0800
### Settings ### Settings
Created using following [settings/artix7.sh (sha256: 632f87003df3388761e7f843432ae7cb2eaedeba95245503a09279ef9452db9d)](https://github.com/SymbiFlow/prjxray/blob/aa88f68da77b0e139362992aa94d7e8cbdf2fa98/settings/artix7.sh) Created using following [settings/artix7.sh (sha256: 632f87003df3388761e7f843432ae7cb2eaedeba95245503a09279ef9452db9d)](https://github.com/SymbiFlow/prjxray/blob/78565b6d23bd89cbaf362ea550622b56ba738290/settings/artix7.sh)
```shell ```shell
export XRAY_DATABASE="artix7" export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1" export XRAY_PART="xc7a50tfgg484-1"
@ -105,9 +105,9 @@ Results have checksums;
* [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp) * [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) * [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt) * [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
* [`f2a77cae77031e75a603d89470172ec265f0e125093e4038b8712c675f045d4b ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit) * [`3e70378bc05fe32951fed4816f634ff35e5f1511d992ebf8e6718d6d8a65943f ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
* [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp) * [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`11d15eb449e9f42409e7187c26635d3facb6974cc0172819b4387ada2ff2532c ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json) * [`2e19b7f8aaaf6fd6e891fa16ceb351eaf659202ef512598ec8f518c57d6ab484 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt) * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db) * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
* [`e9cbf256305d67504ac8e1b2548783a49253c14265b53f2e3e6dea96b415f162 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db) * [`e9cbf256305d67504ac8e1b2548783a49253c14265b53f2e3e6dea96b415f162 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
@ -140,10 +140,10 @@ Results have checksums;
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db) * [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db) * [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db) * [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db)
* [`63cab7c6cb50b9a86cd6de4ec02cfba93b99ac622684a1196b3d70adb1472fc1 ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db) * [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`e6569c94ce988c3b15167c8f526e8ed9b1c473caa51fbbbc3d37caf0c27094a0 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db) * [`c31088e5a6d1ce30e87c20825758e25e707baa54d3312885460c1454132ea65e ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
* [`6daa967b706d7fc5cdf597ed9f142df8f3003ded2fee3d622d484b21ceda2827 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db) * [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
* [`d92fdbf8320074b6b98ba23cd01d4dda11385e9802b9d6068931d09def7b03c8 ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db) * [`1f59c8190e4c3fffd0272002d1c46c48de0524bdec3d6359ac1d481c9a37cf7c ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db) * [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db) * [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db) * [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db)
@ -330,7 +330,7 @@ Results have checksums;
### Settings ### Settings
Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/aa88f68da77b0e139362992aa94d7e8cbdf2fa98/settings/kintex7.sh) Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/78565b6d23bd89cbaf362ea550622b56ba738290/settings/kintex7.sh)
```shell ```shell
export XRAY_DATABASE="kintex7" export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2" export XRAY_PART="xc7k70tfbg676-2"
@ -591,7 +591,7 @@ Results have checksums;
### Settings ### Settings
Created using following [settings/zynq7.sh (sha256: 4fda8e53d37070c2ae679944740d8ea38b79c68785ab47e9482e0536d27a8b4f)](https://github.com/SymbiFlow/prjxray/blob/aa88f68da77b0e139362992aa94d7e8cbdf2fa98/settings/zynq7.sh) Created using following [settings/zynq7.sh (sha256: 4fda8e53d37070c2ae679944740d8ea38b79c68785ab47e9482e0536d27a8b4f)](https://github.com/SymbiFlow/prjxray/blob/78565b6d23bd89cbaf362ea550622b56ba738290/settings/zynq7.sh)
```shell ```shell
export XRAY_DATABASE="zynq7" export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z010clg400-1" export XRAY_PART="xc7z010clg400-1"

73728
artix7/segbits_bram_l.block_ram.db
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@ -212,42 +212,6 @@ BRAM_L.RAMB18_Y0.DOA_REG 27_69
BRAM_L.RAMB18_Y0.DOB_REG 27_72 BRAM_L.RAMB18_Y0.DOB_REG 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE 27_150 BRAM_L.RAMB18_Y0.FIFO_MODE 27_150
BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100 BRAM_L.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96 BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96 BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37 BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -264,42 +228,6 @@ BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125 BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -314,6 +242,42 @@ BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61 BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_L.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_L.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_L.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_L.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107 BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112 BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -324,46 +288,46 @@ BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117 BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123 BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_L.RAMB18_Y1.DOA_REG 27_251 BRAM_L.RAMB18_Y1.DOA_REG 27_251
BRAM_L.RAMB18_Y1.DOB_REG 27_248 BRAM_L.RAMB18_Y1.DOB_REG 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE 27_169 BRAM_L.RAMB18_Y1.FIFO_MODE 27_169
BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221 BRAM_L.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224 BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224 BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285 BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -380,42 +344,6 @@ BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195 BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -430,6 +358,42 @@ BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261 BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_L.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_L.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_L.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_L.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213 BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208 BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -440,6 +404,42 @@ BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203 BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197 BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_L.RAMB36.EN_ECC_READ 27_175 BRAM_L.RAMB36.EN_ECC_READ 27_175
BRAM_L.RAMB36.EN_ECC_WRITE 27_162 BRAM_L.RAMB36.EN_ECC_WRITE 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188 BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER 27_188

73728
artix7/segbits_bram_r.block_ram.db
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288
artix7/segbits_bram_r.db
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@ -212,42 +212,6 @@ BRAM_R.RAMB18_Y0.DOA_REG 27_69
BRAM_R.RAMB18_Y0.DOB_REG 27_72 BRAM_R.RAMB18_Y0.DOB_REG 27_72
BRAM_R.RAMB18_Y0.FIFO_MODE 27_150 BRAM_R.RAMB18_Y0.FIFO_MODE 27_150
BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100 BRAM_R.RAMB18_Y0.IN_USE 27_99 27_100
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96 BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_96
BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96 BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_96
BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37 BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 !27_35 !27_36 !27_37
@ -264,42 +228,6 @@ BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE 27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG !27_124
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE 27_125
BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125 BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG !27_125
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64 BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56 BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68 BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
@ -314,6 +242,42 @@ BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 27_59 !27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 !27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 27_59 27_60 !27_61
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61 BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 !27_59 !27_60 27_61
BRAM_R.RAMB18_Y0.ZINIT_A[0] 27_73
BRAM_R.RAMB18_Y0.ZINIT_A[1] 27_65
BRAM_R.RAMB18_Y0.ZINIT_A[2] 27_137
BRAM_R.RAMB18_Y0.ZINIT_A[3] 27_121
BRAM_R.RAMB18_Y0.ZINIT_A[4] 27_105
BRAM_R.RAMB18_Y0.ZINIT_A[5] 27_89
BRAM_R.RAMB18_Y0.ZINIT_A[6] 27_57
BRAM_R.RAMB18_Y0.ZINIT_A[7] 27_41
BRAM_R.RAMB18_Y0.ZINIT_A[8] 27_25
BRAM_R.RAMB18_Y0.ZINIT_A[9] 27_09
BRAM_R.RAMB18_Y0.ZINIT_A[10] 27_129
BRAM_R.RAMB18_Y0.ZINIT_A[11] 27_113
BRAM_R.RAMB18_Y0.ZINIT_A[12] 27_97
BRAM_R.RAMB18_Y0.ZINIT_A[13] 27_81
BRAM_R.RAMB18_Y0.ZINIT_A[14] 27_49
BRAM_R.RAMB18_Y0.ZINIT_A[15] 27_33
BRAM_R.RAMB18_Y0.ZINIT_A[16] 27_17
BRAM_R.RAMB18_Y0.ZINIT_A[17] 27_01
BRAM_R.RAMB18_Y0.ZINIT_B[0] 27_79
BRAM_R.RAMB18_Y0.ZINIT_B[1] 27_71
BRAM_R.RAMB18_Y0.ZINIT_B[2] 27_143
BRAM_R.RAMB18_Y0.ZINIT_B[3] 27_127
BRAM_R.RAMB18_Y0.ZINIT_B[4] 27_111
BRAM_R.RAMB18_Y0.ZINIT_B[5] 27_95
BRAM_R.RAMB18_Y0.ZINIT_B[6] 27_63
BRAM_R.RAMB18_Y0.ZINIT_B[7] 27_47
BRAM_R.RAMB18_Y0.ZINIT_B[8] 27_31
BRAM_R.RAMB18_Y0.ZINIT_B[9] 27_15
BRAM_R.RAMB18_Y0.ZINIT_B[10] 27_135
BRAM_R.RAMB18_Y0.ZINIT_B[11] 27_119
BRAM_R.RAMB18_Y0.ZINIT_B[12] 27_103
BRAM_R.RAMB18_Y0.ZINIT_B[13] 27_87
BRAM_R.RAMB18_Y0.ZINIT_B[14] 27_55
BRAM_R.RAMB18_Y0.ZINIT_B[15] 27_39
BRAM_R.RAMB18_Y0.ZINIT_B[16] 27_23
BRAM_R.RAMB18_Y0.ZINIT_B[17] 27_07
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107 BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109 BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112 BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
@ -324,46 +288,46 @@ BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117 BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120 BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123 BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y0.ZSRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.ZSRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.ZSRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.ZSRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.ZSRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.ZSRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.ZSRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.ZSRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.ZSRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.ZSRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.ZSRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.ZSRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.ZSRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.ZSRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.ZSRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.ZSRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.ZSRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.ZSRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.ZSRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.ZSRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.ZSRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.ZSRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.ZSRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.ZSRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.ZSRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.ZSRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.ZSRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.ZSRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.ZSRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.ZSRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.ZSRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.ZSRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.ZSRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.ZSRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.ZSRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.ZSRVAL_B[17] 27_06
BRAM_R.RAMB18_Y1.DOA_REG 27_251 BRAM_R.RAMB18_Y1.DOA_REG 27_251
BRAM_R.RAMB18_Y1.DOB_REG 27_248 BRAM_R.RAMB18_Y1.DOB_REG 27_248
BRAM_R.RAMB18_Y1.FIFO_MODE 27_169 BRAM_R.RAMB18_Y1.FIFO_MODE 27_169
BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221 BRAM_R.RAMB18_Y1.IN_USE 27_220 27_221
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224 BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE !27_224
BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224 BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE 27_224
BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285 BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 !27_283 !27_284 !27_285
@ -380,42 +344,6 @@ BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE 27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG !27_196
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE 27_195
BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195 BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG !27_195
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256 BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264 BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252 BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
@ -430,6 +358,42 @@ BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 !27_259 !27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 !27_259 27_260 !27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 !27_259 27_260 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261 BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 27_259 !27_260 !27_261
BRAM_R.RAMB18_Y1.ZINIT_A[0] 27_249
BRAM_R.RAMB18_Y1.ZINIT_A[1] 27_241
BRAM_R.RAMB18_Y1.ZINIT_A[2] 27_313
BRAM_R.RAMB18_Y1.ZINIT_A[3] 27_297
BRAM_R.RAMB18_Y1.ZINIT_A[4] 27_281
BRAM_R.RAMB18_Y1.ZINIT_A[5] 27_265
BRAM_R.RAMB18_Y1.ZINIT_A[6] 27_233
BRAM_R.RAMB18_Y1.ZINIT_A[7] 27_217
BRAM_R.RAMB18_Y1.ZINIT_A[8] 27_201
BRAM_R.RAMB18_Y1.ZINIT_A[9] 27_185
BRAM_R.RAMB18_Y1.ZINIT_A[10] 27_305
BRAM_R.RAMB18_Y1.ZINIT_A[11] 27_289
BRAM_R.RAMB18_Y1.ZINIT_A[12] 27_273
BRAM_R.RAMB18_Y1.ZINIT_A[13] 27_257
BRAM_R.RAMB18_Y1.ZINIT_A[14] 27_225
BRAM_R.RAMB18_Y1.ZINIT_A[15] 27_209
BRAM_R.RAMB18_Y1.ZINIT_A[16] 27_193
BRAM_R.RAMB18_Y1.ZINIT_A[17] 27_177
BRAM_R.RAMB18_Y1.ZINIT_B[0] 27_255
BRAM_R.RAMB18_Y1.ZINIT_B[1] 27_247
BRAM_R.RAMB18_Y1.ZINIT_B[2] 27_319
BRAM_R.RAMB18_Y1.ZINIT_B[3] 27_303
BRAM_R.RAMB18_Y1.ZINIT_B[4] 27_287
BRAM_R.RAMB18_Y1.ZINIT_B[5] 27_271
BRAM_R.RAMB18_Y1.ZINIT_B[6] 27_239
BRAM_R.RAMB18_Y1.ZINIT_B[7] 27_223
BRAM_R.RAMB18_Y1.ZINIT_B[8] 27_207
BRAM_R.RAMB18_Y1.ZINIT_B[9] 27_191
BRAM_R.RAMB18_Y1.ZINIT_B[10] 27_311
BRAM_R.RAMB18_Y1.ZINIT_B[11] 27_295
BRAM_R.RAMB18_Y1.ZINIT_B[12] 27_279
BRAM_R.RAMB18_Y1.ZINIT_B[13] 27_263
BRAM_R.RAMB18_Y1.ZINIT_B[14] 27_231
BRAM_R.RAMB18_Y1.ZINIT_B[15] 27_215
BRAM_R.RAMB18_Y1.ZINIT_B[16] 27_199
BRAM_R.RAMB18_Y1.ZINIT_B[17] 27_183
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213 BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211 BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208 BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
@ -440,6 +404,42 @@ BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203 BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200 BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197 BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197
BRAM_R.RAMB18_Y1.ZSRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.ZSRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.ZSRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.ZSRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.ZSRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.ZSRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.ZSRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.ZSRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.ZSRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.ZSRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.ZSRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.ZSRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.ZSRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.ZSRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.ZSRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.ZSRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.ZSRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.ZSRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.ZSRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.ZSRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.ZSRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.ZSRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.ZSRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.ZSRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.ZSRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.ZSRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.ZSRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.ZSRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.ZSRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.ZSRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.ZSRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.ZSRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.ZSRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.ZSRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.ZSRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.ZSRVAL_B[17] 27_182
BRAM_R.RAMB36.EN_ECC_READ 27_175 BRAM_R.RAMB36.EN_ECC_READ 27_175
BRAM_R.RAMB36.EN_ECC_WRITE 27_162 BRAM_R.RAMB36.EN_ECC_WRITE 27_162
BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188 BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER 27_188