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Updating zynq7 based on "Merge pull request #908 from antmicro/fix-bram-timing-fuzzer". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2019-06-27 10:21:35 -07:00
parent 1f764f628e
commit 2d9308a8d8
129 changed files with 7768 additions and 3354 deletions
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Info.md
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@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Thu 27 Jun 2019 05:12:21 PM UTC (2019-06-27T17:12:21+00:00).
Last updated on Thu 27 Jun 2019 05:20:39 PM UTC (2019-06-27T17:20:39+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [ca6bbee](https://github.com/SymbiFlow/prjxray/commit/ca6bbee1931cc06152f0f94463f830d437160ff7).
@ -824,43 +824,67 @@ Results have checksums;
* [`9315fdbbd691414d1cd31b798b080f53bcfe7fefc735f86f9b4d5f013d14c168 ./zynq7/harness/zybo/swbut/design.txt`](./zynq7/harness/zybo/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
* [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_bram_l.origin_info.db`](./zynq7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
* [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_bram_r.origin_info.db`](./zynq7/mask_bram_r.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_clbll_l.origin_info.db`](./zynq7/mask_clbll_l.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_clbll_r.origin_info.db`](./zynq7/mask_clbll_r.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_clblm_l.origin_info.db`](./zynq7/mask_clblm_l.origin_info.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_clblm_r.origin_info.db`](./zynq7/mask_clblm_r.origin_info.db)
* [`061f62437a067bb14f4904e40ca1bf01151eac5bef05867b7caf0c7de087c55e ./zynq7/mask_clk_bufg_bot_r.db`](./zynq7/mask_clk_bufg_bot_r.db)
* [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea ./zynq7/mask_clk_bufg_rebuf.db`](./zynq7/mask_clk_bufg_rebuf.db)
* [`061f62437a067bb14f4904e40ca1bf01151eac5bef05867b7caf0c7de087c55e ./zynq7/mask_clk_bufg_top_r.db`](./zynq7/mask_clk_bufg_top_r.db)
* [`7d5219cfebf382e97dbb774dbb8cf0ba8736edabcd848a913819fd45474beba6 ./zynq7/mask_clk_hrow_bot_r.db`](./zynq7/mask_clk_hrow_bot_r.db)
* [`7d5219cfebf382e97dbb774dbb8cf0ba8736edabcd848a913819fd45474beba6 ./zynq7/mask_clk_hrow_top_r.db`](./zynq7/mask_clk_hrow_top_r.db)
* [`5becf39d0ec36839d159ca614b298465d3e1b0696d33bcfb509cbe72a7058ecf ./zynq7/mask_clk_hrow_bot_r.db`](./zynq7/mask_clk_hrow_bot_r.db)
* [`5becf39d0ec36839d159ca614b298465d3e1b0696d33bcfb509cbe72a7058ecf ./zynq7/mask_clk_hrow_top_r.db`](./zynq7/mask_clk_hrow_top_r.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_l.origin_info.db`](./zynq7/mask_dsp_l.origin_info.db)
* [`aab2e5f20890d805b6a78db6e6fd68d6024a140ac5e960feb4162d7e49582ca8 ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_r.origin_info.db`](./zynq7/mask_dsp_r.origin_info.db)
* [`be757fb834be7ff84a2873c0ac6621c909a5e85362b397667760edde86616f84 ./zynq7/mask_hclk_cmt_l.db`](./zynq7/mask_hclk_cmt_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_l.origin_info.db`](./zynq7/mask_hclk_l.origin_info.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
* [`6e99ef6017891939248e9f03c630155243a819a2e0c4c51b4d78dc5b248c8dea ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`ec6a38f311c53e65c876693548e585b534afa92f4fbee54d61e06729257cb2ec ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
* [`a2dca9f4a757361d06579710be37dbb07acd78eb6224ae4738cdceb5268741c5 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
* [`66f386d399de7e28e4ecba8410a11165bd582fd355e77555ea9939939158e6c5 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
* [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
* [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_int_interface_r.origin_info.db`](./zynq7/ppips_bram_int_interface_r.origin_info.db)
* [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_l.origin_info.db`](./zynq7/ppips_bram_l.origin_info.db)
* [`e58acdfa3cc740d2346dcb5d3a4c13434d459ebdc2ceb655dcb65fd631da4e4d ./zynq7/ppips_bram_r.db`](./zynq7/ppips_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_r.origin_info.db`](./zynq7/ppips_bram_r.origin_info.db)
* [`be58cd551e870914cff515baabe383dc2655f34f5332c395ceb20ca25414dd63 ./zynq7/ppips_brkh_int.db`](./zynq7/ppips_brkh_int.db)
* [`b4ffdb01ca695c7d52f34b88508aef6d596377fcffd7fa5e197212acc4b00e9a ./zynq7/ppips_clbll_l.db`](./zynq7/ppips_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_clbll_l.origin_info.db`](./zynq7/ppips_clbll_l.origin_info.db)
* [`bb75573609f56f082544644ecbb39125d023809340f7a30180cb9df823585009 ./zynq7/ppips_clbll_r.db`](./zynq7/ppips_clbll_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_clbll_r.origin_info.db`](./zynq7/ppips_clbll_r.origin_info.db)
* [`a5357b0c018ac9c8c1f8cccf3c36b69f66ffd0e29039dfadb5a829caafd71a73 ./zynq7/ppips_clblm_l.db`](./zynq7/ppips_clblm_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_clblm_l.origin_info.db`](./zynq7/ppips_clblm_l.origin_info.db)
* [`15424ecbd5816143def2dcb20fc9cfae5ec4e11a1a5cfc1848e71b2904a1a713 ./zynq7/ppips_clblm_r.db`](./zynq7/ppips_clblm_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_clblm_r.origin_info.db`](./zynq7/ppips_clblm_r.origin_info.db)
* [`77fba62caedba6632e55834bbc40ff797181d8825e2f4d55987a04a38a95a6c0 ./zynq7/ppips_clk_bufg_bot_r.db`](./zynq7/ppips_clk_bufg_bot_r.db)
* [`15dba278ba801744b1ed558220334899fc098acd8e8aff20ab9761249a70e839 ./zynq7/ppips_clk_bufg_top_r.db`](./zynq7/ppips_clk_bufg_top_r.db)
* [`0dbef414182c3ef9054f4b9bc15c41c435d4bef2db30850add728d3de93749b8 ./zynq7/ppips_clk_hrow_bot_r.db`](./zynq7/ppips_clk_hrow_bot_r.db)
* [`8774624d8398b6000e80cefbcf5a5bac095e1c8650772c23f9b73448e0df5dbb ./zynq7/ppips_clk_hrow_top_r.db`](./zynq7/ppips_clk_hrow_top_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_l.db`](./zynq7/ppips_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_l.origin_info.db`](./zynq7/ppips_dsp_l.origin_info.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_r.db`](./zynq7/ppips_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_dsp_r.origin_info.db`](./zynq7/ppips_dsp_r.origin_info.db)
* [`b61bbc9db6d0de1141a87d787f5d118be0a244802eed712612ff2aa0b6aeb73a ./zynq7/ppips_hclk_l.db`](./zynq7/ppips_hclk_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_l.origin_info.db`](./zynq7/ppips_hclk_l.origin_info.db)
* [`abe795445c031273b59a6a98cbfea3309c4047820cbea352c723138b3111c956 ./zynq7/ppips_hclk_r.db`](./zynq7/ppips_hclk_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_hclk_r.origin_info.db`](./zynq7/ppips_hclk_r.origin_info.db)
* [`d300ad4128a192e416a958471013b7554f141fd1f816715828b1e5a87838f18d ./zynq7/ppips_int_l.db`](./zynq7/ppips_int_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_int_l.origin_info.db`](./zynq7/ppips_int_l.origin_info.db)
* [`46564e746b8d9e37bf46a68f2915bd1395efb68508d48d336a4dfb9342105285 ./zynq7/ppips_int_r.db`](./zynq7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_int_r.origin_info.db`](./zynq7/ppips_int_r.origin_info.db)
* [`01526db954ab19098931424b8203c98803894b5563b5272fad665f3a75f0bb3b ./zynq7/ppips_io_int_interface_r.db`](./zynq7/ppips_io_int_interface_r.db)
* [`df11ac1c71eefa9c06abe06bc932d36368977543fba9666ee1b36e8417cd9f78 ./zynq7/ppips_rioi3.db`](./zynq7/ppips_rioi3.db)
* [`0c6263c13669085c09a61f25d68786d8f6c9b12b162fe2cd6c9a50114106f739 ./zynq7/ppips_rioi3_sing.db`](./zynq7/ppips_rioi3_sing.db)
@ -874,24 +898,24 @@ Results have checksums;
* [`9b40402550b3a34067109372c2217e6bbef0744db204c38e4d7439f3ccba2474 ./zynq7/segbits_bram_r.block_ram.origin_info.db`](./zynq7/segbits_bram_r.block_ram.origin_info.db)
* [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
* [`83d0ac8050043e2aa67aa0dc2ba60692eef30daf9256503ff70b3e3a6475e3ba ./zynq7/segbits_bram_r.origin_info.db`](./zynq7/segbits_bram_r.origin_info.db)
* [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
* [`4ddab18383430522a3aa8d49688487dd0c3895f36f2b9f1fecabfb695d0105e4 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db)
* [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`50987c8e8ff9a66860f88e0f3531e92c5738a11613bee61720bae862e04b7787 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db)
* [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`467377976169e66212833dd5a92a1b0b19eae348b3fb113f0ea363097872c654 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db)
* [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`20c664e6d20851c1b05e851ed278958a8d0f8d06697afb5caa70c62d07622575 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
* [`9bf6bdffdc814569a7da53c696e46207aab23ea66c9dd92c47e50a6211dd739b ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
* [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db)
* [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db)
* [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db)
* [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db)
* [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db)
* [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
* [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
* [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db)
* [`8d17f7e9f3cdf3419760d2b74cd23c04ee560f2f2bc942b718201c445a922c34 ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db)
* [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db)
* [`8e5cb983e044d31803253720c5496b368d0edb6705008c4cda61c213f9d44511 ./zynq7/segbits_clk_bufg_rebuf.origin_info.db`](./zynq7/segbits_clk_bufg_rebuf.origin_info.db)
* [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a ./zynq7/segbits_clk_bufg_top_r.db`](./zynq7/segbits_clk_bufg_top_r.db)
* [`7497f9e1eb6208c157c3c1caeca7b94172a6bb4896e7cd6e3d28cf23c38c2281 ./zynq7/segbits_clk_bufg_top_r.origin_info.db`](./zynq7/segbits_clk_bufg_top_r.origin_info.db)
* [`4383aafad32f56f21404c5e6092811874f869c920e23a02b57da8c3e739fe2a9 ./zynq7/segbits_clk_hrow_bot_r.db`](./zynq7/segbits_clk_hrow_bot_r.db)
* [`5b5c62b9cf274038a8f58aee5b1dfa715368a20912e0b909ff062b3a328a41a1 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
* [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
* [`04051d28841ff3ec719ebae1182d13ca817cf5eadb039f76a2e12647e1abcf85 ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
* [`1d7c898f5d11b2c3cc02284f0f189e124c3f432510bad2371e53775dd2f9345e ./zynq7/segbits_clk_hrow_bot_r.db`](./zynq7/segbits_clk_hrow_bot_r.db)
* [`eb566cda47e23291d9a3bfdef765233a030d6ff0d8d5debf68e9ade16d2fc6f9 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
* [`724bcea2bc588cf5089840f66c6a813ad6cc9958fec6b5db2d44ef75b8843c14 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
* [`5e5bc3b26dd2cc2632e95f390f87e9a7cc7cfd1f163e20447c02b0e2e111889d ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
* [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
* [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db)
* [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
@ -903,13 +927,13 @@ Results have checksums;
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
* [`df08da95cd2a0e27b13cb69daed140b50865dd3863d155178a23b85681bf7a39 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`b72fc8fc4b0241bc62dc8f583c9e54012a1eaf5f4fd65e34d045dfe2c0f7200a ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
* [`51e9f1cfd54a13565e631837d12482bfaf9f0bb29f6c500b7c2aba27a1290387 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`0f423514157edb733193b23e883a0a35c16ab12ae5f7a86b74a7ef8c7358c74c ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`d1ad493bd149ba47ac50a68fef57809d21a1ef36db63725317a12df9266ca8d8 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`caaa32eadfca7d6417a09d5357f8c1eea23bdb325164857de03b8798bdf252bb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`a674ba036253f38ac8fd6ab2e10039f3d8ecd2a670c50c0610100a9f2a9028c7 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`35c3e42e279228ea12f3e27a874c52d1b1a7169403b3e9a28642698a80b63a3b ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
* [`27a74d9eddb6f960a94f107b28343d88dc8c2274de61be865e21e3a8d1f4e9f1 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh)
* [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
* [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
@ -1043,96 +1067,36 @@ Results have checksums;
* [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json)
* [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json)
* [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json)
* [`15e8ed87d38b9f9b84b52c768df922e5f5be4d860670a768e9230ad8cdca3787 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_L.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_R.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_BRAM.sdf`](./zynq7/timings/BRKH_BRAM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CLB.sdf`](./zynq7/timings/BRKH_CLB.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CLK.sdf`](./zynq7/timings/BRKH_CLK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_CMT.sdf`](./zynq7/timings/BRKH_CMT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_DSP_L.sdf`](./zynq7/timings/BRKH_DSP_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_DSP_R.sdf`](./zynq7/timings/BRKH_DSP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRKH_INT.sdf`](./zynq7/timings/BRKH_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_INT.sdf`](./zynq7/timings/B_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_INT_PSS.sdf`](./zynq7/timings/B_TERM_INT_PSS.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/B_TERM_VBRK.sdf`](./zynq7/timings/B_TERM_VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_CENTER_BOT.sdf`](./zynq7/timings/CFG_CENTER_BOT.sdf)
* [`8d6db739fe7463bf3806921de087423d59531ab44ff6fc1969c1421a39461bdb ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)
* [`ace98637c5f3c9bad9a17e353b239cc87d2119dc86c68e577634b4d5c1458cd4 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf)
* [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf)
* [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)
* [`6dc7edd0792e8305dd8309933c264512fc6a22f45cf0386422edc219d5a3b20a ./zynq7/timings/CFG_CENTER_TOP.sdf`](./zynq7/timings/CFG_CENTER_TOP.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_MID_PELE1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf`](./zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf)
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./zynq7/timings/CLBLL_L.sdf`](./zynq7/timings/CLBLL_L.sdf)
* [`c3811649b513500c04b1297aacc0b714889373899dad4d66dd7f8f5bb034272d ./zynq7/timings/CLBLL_R.sdf`](./zynq7/timings/CLBLL_R.sdf)
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./zynq7/timings/CLBLM_L.sdf`](./zynq7/timings/CLBLM_L.sdf)
* [`aa30bd99d2e521fa5d5c441df3492e15df123d4145eda5269a76a749401ba33b ./zynq7/timings/CLBLM_R.sdf`](./zynq7/timings/CLBLM_R.sdf)
* [`64317dce36fb887f93b18c4020382cea2d94668f2ffe6417b6bd78787f80001e ./zynq7/timings/CLBLL_L.sdf`](./zynq7/timings/CLBLL_L.sdf)
* [`64317dce36fb887f93b18c4020382cea2d94668f2ffe6417b6bd78787f80001e ./zynq7/timings/CLBLL_R.sdf`](./zynq7/timings/CLBLL_R.sdf)
* [`9461f82cd0dbf257bc8efa85899bac3b187962cd3fe5dec44b252a6b37f6b9d9 ./zynq7/timings/CLBLM_L.sdf`](./zynq7/timings/CLBLM_L.sdf)
* [`9461f82cd0dbf257bc8efa85899bac3b187962cd3fe5dec44b252a6b37f6b9d9 ./zynq7/timings/CLBLM_R.sdf`](./zynq7/timings/CLBLM_R.sdf)
* [`0d9e20b4673ed1ad151e9c22f28ac2e456f4cdbf5ba31afe45576152a293fd7a ./zynq7/timings/CLK_BUFG_BOT_R.sdf`](./zynq7/timings/CLK_BUFG_BOT_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_BUFG_REBUF.sdf`](./zynq7/timings/CLK_BUFG_REBUF.sdf)
* [`0d9e20b4673ed1ad151e9c22f28ac2e456f4cdbf5ba31afe45576152a293fd7a ./zynq7/timings/CLK_BUFG_TOP_R.sdf`](./zynq7/timings/CLK_BUFG_TOP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_FEED.sdf`](./zynq7/timings/CLK_FEED.sdf)
* [`590c7ee72599c4d42030ba90c6e352c66d51490112b83f292345bec5c89d94c9 ./zynq7/timings/CLK_HROW_BOT_R.sdf`](./zynq7/timings/CLK_HROW_BOT_R.sdf)
* [`590c7ee72599c4d42030ba90c6e352c66d51490112b83f292345bec5c89d94c9 ./zynq7/timings/CLK_HROW_TOP_R.sdf`](./zynq7/timings/CLK_HROW_TOP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_MTBF2.sdf`](./zynq7/timings/CLK_MTBF2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV.sdf`](./zynq7/timings/CLK_PMV.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV2.sdf`](./zynq7/timings/CLK_PMV2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMV2_SVT.sdf`](./zynq7/timings/CLK_PMV2_SVT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_PMVIOB.sdf`](./zynq7/timings/CLK_PMVIOB.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_TERM.sdf`](./zynq7/timings/CLK_TERM.sdf)
* [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CMT_PMV_L.sdf`](./zynq7/timings/CMT_PMV_L.sdf)
* [`8c641a845fdd56842eec7c5fe72ddbd26654593313516137b88dcb5ea83a1920 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf)
* [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf)
* [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_BRAM.sdf`](./zynq7/timings/HCLK_BRAM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_CLB.sdf`](./zynq7/timings/HCLK_CLB.sdf)
* [`e706cddf4c7392507fcaa790fcde691d58a849f520969a5ea0c2fa7870ef835c ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_DSP_L.sdf`](./zynq7/timings/HCLK_DSP_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_DSP_R.sdf`](./zynq7/timings/HCLK_DSP_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_1.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf`](./zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FEEDTHRU_2.sdf`](./zynq7/timings/HCLK_FEEDTHRU_2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_FIFO_L.sdf`](./zynq7/timings/HCLK_FIFO_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_INT_INTERFACE.sdf`](./zynq7/timings/HCLK_INT_INTERFACE.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_IOB.sdf`](./zynq7/timings/HCLK_IOB.sdf)
* [`db9a3a9e9ba510815d01967898be0fbb1e9125c68526eff864950691e5d0d963 ./zynq7/timings/CLK_HROW_BOT_R.sdf`](./zynq7/timings/CLK_HROW_BOT_R.sdf)
* [`db9a3a9e9ba510815d01967898be0fbb1e9125c68526eff864950691e5d0d963 ./zynq7/timings/CLK_HROW_TOP_R.sdf`](./zynq7/timings/CLK_HROW_TOP_R.sdf)
* [`ff96f865bbd65952c73a8b8065c1ba6763ad61c94fe1ba40406dbdd850d4da04 ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf)
* [`668be5d275b3b9522a2e02aa7789bd4df746ddf4eaf14ddb2c29d20ca8f5c751 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf)
* [`bda848e132cf93158addf5db6e449dd5d79050155bd2ba52ccad7bd3c1607ec4 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf)
* [`e56222b18e7fabf7473656f7446958e93373a3bf956ca75968d26f9c652fa14e ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf)
* [`24408756edd72f9c82dc2badb3e94e372916c00c407e86a88db1274f8951d721 ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf)
* [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3 ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
* [`b5d5ca72d453879fca2bf2470fb0a670ebfb38d6e85cdbfdb3967e2e4f59ee73 ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_L.sdf`](./zynq7/timings/HCLK_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_R.sdf`](./zynq7/timings/HCLK_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_TERM.sdf`](./zynq7/timings/HCLK_TERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_VBRK.sdf`](./zynq7/timings/HCLK_VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/HCLK_VFRAME.sdf`](./zynq7/timings/HCLK_VFRAME.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_FEEDTHRU_1.sdf`](./zynq7/timings/INT_FEEDTHRU_1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_FEEDTHRU_2.sdf`](./zynq7/timings/INT_FEEDTHRU_2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_L.sdf`](./zynq7/timings/INT_INTERFACE_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_PSS_L.sdf`](./zynq7/timings/INT_INTERFACE_PSS_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_INTERFACE_R.sdf`](./zynq7/timings/INT_INTERFACE_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_L.sdf`](./zynq7/timings/INT_L.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/INT_R.sdf`](./zynq7/timings/INT_R.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/IO_INT_INTERFACE_R.sdf`](./zynq7/timings/IO_INT_INTERFACE_R.sdf)
* [`2af03d31603e237767ecaef977f8b6050c71d32a7632330ac8f42909dc22befc ./zynq7/timings/MONITOR_BOT_PELE1.sdf`](./zynq7/timings/MONITOR_BOT_PELE1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/MONITOR_MID_PELE1.sdf`](./zynq7/timings/MONITOR_MID_PELE1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/MONITOR_TOP_PELE1.sdf`](./zynq7/timings/MONITOR_TOP_PELE1.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PCIE_NULL.sdf`](./zynq7/timings/PCIE_NULL.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS0.sdf`](./zynq7/timings/PSS0.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS1.sdf`](./zynq7/timings/PSS1.sdf)
* [`4e807172f038c907022e9b8f3ff1f6e80621a3dc9ee6e132b81b9d976763b5cd ./zynq7/timings/PSS2.sdf`](./zynq7/timings/PSS2.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS3.sdf`](./zynq7/timings/PSS3.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS4.sdf`](./zynq7/timings/PSS4.sdf)
* [`8adb21c5b19dc331cfeba427e65c1c15f33fbd7e43427acba206c109f5ce9985 ./zynq7/timings/MONITOR_BOT_PELE1.sdf`](./zynq7/timings/MONITOR_BOT_PELE1.sdf)
* [`b3a14c405c96a14a029a9ffa97b526d49e49c22d93a892ef053328bb64ef576c ./zynq7/timings/PSS2.sdf`](./zynq7/timings/PSS2.sdf)
* [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./zynq7/timings/RIOB33.sdf`](./zynq7/timings/RIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./zynq7/timings/RIOB33_SING.sdf`](./zynq7/timings/RIOB33_SING.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
* [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/R_TERM_INT.sdf`](./zynq7/timings/R_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/TERM_CMT.sdf`](./zynq7/timings/TERM_CMT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/T_TERM_INT.sdf`](./zynq7/timings/T_TERM_INT.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VBRK.sdf`](./zynq7/timings/VBRK.sdf)
* [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VFRAME.sdf`](./zynq7/timings/VFRAME.sdf)
* [`bbdb8b53bb1343cefbc977089069d67ef277fa758ae77e06d50aa8de6e503ae2 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
* [`b0a63e17e651071eec70a4048fc3321d79a8b0f6d430ad323eebc8b624418b0a ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf)
* [`85ad47e1c4cd40ad8e70e4abefeb88eb648e7b7a2f40ce366851552195a024a7 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
* [`5b1834f0f17f71ce613b907a11f1d93096f20c05acc5f382b05195831e882eb6 ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
* [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json)
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml)
* [`d9914c14b3a8d59c76dd5992c4727e4002acd5e14b32c1afe49f7be8798e4db9 ./zynq7/xc7z010clg400-1_package_pins.csv`](./zynq7/xc7z010clg400-1_package_pins.csv)

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@ -1,96 +1,864 @@
bit 00_209
bit 00_217
bit 00_218
bit 00_219
bit 00_221
bit 00_305
bit 00_310
bit 00_313
bit 00_314
bit 00_315
bit 00_317
bit 01_205
bit 01_213
bit 01_216
bit 01_217
bit 01_218
bit 01_301
bit 01_308
bit 01_309
bit 01_312
bit 01_313
bit 01_314
bit 21_232
bit 21_328
bit 25_232
bit 25_328
bit 26_25
bit 26_26
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_41
bit 26_42
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_57
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_73
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_89
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_105
bit 26_106
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_121
bit 26_122
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_137
bit 26_138
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_163
bit 26_169
bit 26_170
bit 26_171
bit 26_172
bit 26_173
bit 26_174
bit 26_175
bit 26_179
bit 26_185
bit 26_186
bit 26_187
bit 26_188
bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_206
bit 26_207
bit 26_211
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_223
bit 26_227
bit 26_233
bit 26_234
bit 26_235
bit 26_236
bit 26_237
bit 26_238
bit 26_239
bit 26_243
bit 26_249
bit 26_250
bit 26_251
bit 26_252
bit 26_253
bit 26_254
bit 26_255
bit 26_279
bit 26_280
bit 26_281
bit 26_282
bit 26_283
bit 26_284
bit 26_285
bit 26_286
bit 26_287
bit 26_291
bit 26_297
bit 26_298
bit 26_299
bit 26_300
bit 26_301
bit 26_302
bit 26_303
bit 26_307
bit 26_313
bit 26_314
bit 26_315
bit 26_316
bit 26_317
bit 26_318
bit 26_319
bit 26_323
bit 26_329
bit 26_330
bit 26_331
bit 26_332
bit 26_333
bit 26_334
bit 26_335
bit 26_339
bit 26_345
bit 26_346
bit 26_347
bit 26_348
bit 26_349
bit 26_350
bit 26_351
bit 26_355
bit 26_361
bit 26_362
bit 26_363
bit 26_364
bit 26_365
bit 26_366
bit 26_367
bit 26_371
bit 26_377
bit 26_378
bit 26_379
bit 26_380
bit 26_381
bit 26_382
bit 26_383
bit 26_409
bit 26_410
bit 26_412
bit 26_413
bit 26_414
bit 26_415
bit 26_425
bit 26_426
bit 26_428
bit 26_429
bit 26_430
bit 26_431
bit 26_441
bit 26_442
bit 26_444
bit 26_445
bit 26_446
bit 26_447
bit 26_457
bit 26_458
bit 26_460
bit 26_461
bit 26_462
bit 26_463
bit 26_473
bit 26_474
bit 26_476
bit 26_477
bit 26_478
bit 26_479
bit 26_489
bit 26_490
bit 26_492
bit 26_493
bit 26_494
bit 26_495
bit 26_505
bit 26_506
bit 26_508
bit 26_509
bit 26_510
bit 26_511
bit 26_521
bit 26_522
bit 26_524
bit 26_525
bit 26_526
bit 26_527
bit 27_25
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_41
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_73
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_89
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_105
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_121
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_137
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_163
bit 27_166
bit 27_167
bit 27_169
bit 27_170
bit 27_171
bit 27_172
bit 27_173
bit 27_174
bit 27_175
bit 27_179
bit 27_182
bit 27_183
bit 27_185
bit 27_186
bit 27_187
bit 27_188
bit 27_189
bit 27_190
bit 27_191
bit 27_195
bit 27_198
bit 27_199
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_211
bit 27_214
bit 27_215
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_227
bit 27_230
bit 27_231
bit 27_233
bit 27_234
bit 27_235
bit 27_236
bit 27_237
bit 27_238
bit 27_239
bit 27_243
bit 27_246
bit 27_247
bit 27_249
bit 27_250
bit 27_251
bit 27_252
bit 27_253
bit 27_254
bit 27_255
bit 27_279
bit 27_280
bit 27_281
bit 27_282
bit 27_283
bit 27_284
bit 27_285
bit 27_286
bit 27_287
bit 27_291
bit 27_294
bit 27_295
bit 27_297
bit 27_298
bit 27_299
bit 27_300
bit 27_301
bit 27_302
bit 27_303
bit 27_307
bit 27_310
bit 27_311
bit 27_313
bit 27_314
bit 27_315
bit 27_316
bit 27_317
bit 27_318
bit 27_319
bit 27_323
bit 27_326
bit 27_327
bit 27_329
bit 27_330
bit 27_331
bit 27_332
bit 27_333
bit 27_334
bit 27_335
bit 27_339
bit 27_342
bit 27_343
bit 27_345
bit 27_346
bit 27_347
bit 27_348
bit 27_349
bit 27_350
bit 27_351
bit 27_355
bit 27_358
bit 27_359
bit 27_361
bit 27_362
bit 27_363
bit 27_364
bit 27_365
bit 27_366
bit 27_367
bit 27_371
bit 27_374
bit 27_375
bit 27_377
bit 27_378
bit 27_379
bit 27_380
bit 27_381
bit 27_382
bit 27_383
bit 27_409
bit 27_412
bit 27_413
bit 27_414
bit 27_415
bit 27_425
bit 27_428
bit 27_429
bit 27_430
bit 27_431
bit 27_441
bit 27_444
bit 27_445
bit 27_446
bit 27_447
bit 27_457
bit 27_460
bit 27_461
bit 27_462
bit 27_463
bit 27_473
bit 27_476
bit 27_477
bit 27_478
bit 27_479
bit 27_489
bit 27_492
bit 27_493
bit 27_494
bit 27_495
bit 27_505
bit 27_508
bit 27_509
bit 27_510
bit 27_511
bit 27_521
bit 27_524
bit 27_525
bit 27_526
bit 27_527
bit 28_25
bit 28_26
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_41
bit 28_42
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_57
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_73
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_89
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 28_105
bit 28_106
bit 28_108
bit 28_109
bit 28_110
bit 28_111
bit 28_121
bit 28_122
bit 28_124
bit 28_125
bit 28_126
bit 28_127
bit 28_137
bit 28_138
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_163
bit 28_169
bit 28_170
bit 28_171
bit 28_172
bit 28_173
bit 28_174
bit 28_175
bit 28_179
bit 28_185
bit 28_186
bit 28_187
bit 28_188
bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_206
bit 28_207
bit 28_211
bit 28_217
bit 28_218
bit 28_219
bit 28_220
bit 28_221
bit 28_222
bit 28_223
bit 28_227
bit 28_233
bit 28_234
bit 28_235
bit 28_236
bit 28_237
bit 28_238
bit 28_239
bit 28_240
bit 28_241
bit 28_243
bit 28_249
bit 28_250
bit 28_251
bit 28_252
bit 28_253
bit 28_254
bit 28_255
bit 28_270
bit 28_271
bit 28_274
bit 28_275
bit 28_276
bit 28_277
bit 28_278
bit 28_279
bit 28_280
bit 28_281
bit 28_282
bit 28_283
bit 28_284
bit 28_285
bit 28_286
bit 28_287
bit 28_291
bit 28_297
bit 28_298
bit 28_299
bit 28_300
bit 28_301
bit 28_302
bit 28_303
bit 28_307
bit 28_313
bit 28_314
bit 28_315
bit 28_316
bit 28_317
bit 28_318
bit 28_319
bit 28_323
bit 28_329
bit 28_330
bit 28_331
bit 28_332
bit 28_333
bit 28_334
bit 28_335
bit 28_339
bit 28_345
bit 28_346
bit 28_347
bit 28_348
bit 28_349
bit 28_350
bit 28_351
bit 28_355
bit 28_361
bit 28_362
bit 28_363
bit 28_364
bit 28_365
bit 28_366
bit 28_367
bit 28_371
bit 28_377
bit 28_378
bit 28_379
bit 28_380
bit 28_381
bit 28_382
bit 28_383
bit 28_409
bit 28_410
bit 28_412
bit 28_413
bit 28_414
bit 28_415
bit 28_425
bit 28_426
bit 28_428
bit 28_429
bit 28_430
bit 28_431
bit 28_441
bit 28_442
bit 28_444
bit 28_445
bit 28_446
bit 28_447
bit 28_457
bit 28_458
bit 28_460
bit 28_461
bit 28_462
bit 28_463
bit 28_473
bit 28_474
bit 28_476
bit 28_477
bit 28_478
bit 28_479
bit 28_489
bit 28_490
bit 28_492
bit 28_493
bit 28_494
bit 28_495
bit 28_505
bit 28_506
bit 28_508
bit 28_509
bit 28_510
bit 28_511
bit 28_521
bit 28_522
bit 28_524
bit 28_525
bit 28_526
bit 28_527
bit 29_25
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_41
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_57
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_73
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_89
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 29_105
bit 29_108
bit 29_109
bit 29_110
bit 29_111
bit 29_121
bit 29_124
bit 29_125
bit 29_126
bit 29_127
bit 29_137
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_163
bit 29_166
bit 29_167
bit 29_169
bit 29_170
bit 29_171
bit 29_172
bit 29_173
bit 29_174
bit 29_175
bit 29_179
bit 29_182
bit 29_183
bit 29_185
bit 29_186
bit 29_187
bit 29_188
bit 29_189
bit 29_190
bit 29_191
bit 29_195
bit 29_198
bit 29_199
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_211
bit 29_214
bit 29_215
bit 29_217
bit 29_218
bit 29_219
bit 29_220
bit 29_221
bit 29_222
bit 29_223
bit 29_227
bit 29_230
bit 29_231
bit 29_233
bit 29_234
bit 29_235
bit 29_236
bit 29_237
bit 29_238
bit 29_239
bit 29_240
bit 29_241
bit 29_243
bit 29_246
bit 29_247
bit 29_249
bit 29_250
bit 29_251
bit 29_252
bit 29_253
bit 29_254
bit 29_255
bit 29_270
bit 29_271
bit 29_274
bit 29_275
bit 29_276
bit 29_277
bit 29_278
bit 29_279
bit 29_280
bit 29_281
bit 29_282
bit 29_283
bit 29_284
bit 29_285
bit 29_286
bit 29_287
bit 29_291
bit 29_294
bit 29_295
bit 29_297
bit 29_298
bit 29_299
bit 29_300
bit 29_301
bit 29_302
bit 29_303
bit 29_307
bit 29_310
bit 29_311
bit 29_313
bit 29_314
bit 29_315
bit 29_316
bit 29_317
bit 29_318
bit 29_319
bit 29_323
bit 29_326
bit 29_327
bit 29_329
bit 29_330
bit 29_331
bit 29_332
bit 29_333
bit 29_334
bit 29_335
bit 29_339
bit 29_342
bit 29_343
bit 29_345
bit 29_346
bit 29_347
bit 29_348
bit 29_349
bit 29_350
bit 29_351
bit 29_355
bit 29_358
bit 29_359
bit 29_361
bit 29_362
bit 29_363
bit 29_364
bit 29_365
bit 29_366
bit 29_367
bit 29_371
bit 29_374
bit 29_375
bit 29_377
bit 29_378
bit 29_379
bit 29_380
bit 29_381
bit 29_382
bit 29_383
bit 29_409
bit 29_412
bit 29_413
bit 29_414
bit 29_415
bit 29_425
bit 29_428
bit 29_429
bit 29_430
bit 29_431
bit 29_441
bit 29_444
bit 29_445
bit 29_446
bit 29_447
bit 29_457
bit 29_460
bit 29_461
bit 29_462
bit 29_463
bit 29_473
bit 29_476
bit 29_477
bit 29_478
bit 29_479
bit 29_489
bit 29_492
bit 29_493
bit 29_494
bit 29_495
bit 29_505
bit 29_508
bit 29_509
bit 29_510
bit 29_511
bit 29_521
bit 29_524
bit 29_525
bit 29_526
bit 29_527

768
zynq7/mask_clk_hrow_top_r.db
View File

@ -1,96 +1,864 @@
bit 00_209
bit 00_217
bit 00_218
bit 00_219
bit 00_221
bit 00_305
bit 00_310
bit 00_313
bit 00_314
bit 00_315
bit 00_317
bit 01_205
bit 01_213
bit 01_216
bit 01_217
bit 01_218
bit 01_301
bit 01_308
bit 01_309
bit 01_312
bit 01_313
bit 01_314
bit 21_232
bit 21_328
bit 25_232
bit 25_328
bit 26_25
bit 26_26
bit 26_28
bit 26_29
bit 26_30
bit 26_31
bit 26_41
bit 26_42
bit 26_44
bit 26_45
bit 26_46
bit 26_47
bit 26_57
bit 26_58
bit 26_60
bit 26_61
bit 26_62
bit 26_63
bit 26_73
bit 26_74
bit 26_76
bit 26_77
bit 26_78
bit 26_79
bit 26_89
bit 26_90
bit 26_92
bit 26_93
bit 26_94
bit 26_95
bit 26_105
bit 26_106
bit 26_108
bit 26_109
bit 26_110
bit 26_111
bit 26_121
bit 26_122
bit 26_124
bit 26_125
bit 26_126
bit 26_127
bit 26_137
bit 26_138
bit 26_140
bit 26_141
bit 26_142
bit 26_143
bit 26_163
bit 26_169
bit 26_170
bit 26_171
bit 26_172
bit 26_173
bit 26_174
bit 26_175
bit 26_179
bit 26_185
bit 26_186
bit 26_187
bit 26_188
bit 26_189
bit 26_190
bit 26_191
bit 26_195
bit 26_201
bit 26_202
bit 26_203
bit 26_204
bit 26_205
bit 26_206
bit 26_207
bit 26_211
bit 26_217
bit 26_218
bit 26_219
bit 26_220
bit 26_221
bit 26_222
bit 26_223
bit 26_227
bit 26_233
bit 26_234
bit 26_235
bit 26_236
bit 26_237
bit 26_238
bit 26_239
bit 26_243
bit 26_249
bit 26_250
bit 26_251
bit 26_252
bit 26_253
bit 26_254
bit 26_255
bit 26_279
bit 26_280
bit 26_281
bit 26_282
bit 26_283
bit 26_284
bit 26_285
bit 26_286
bit 26_287
bit 26_291
bit 26_297
bit 26_298
bit 26_299
bit 26_300
bit 26_301
bit 26_302
bit 26_303
bit 26_307
bit 26_313
bit 26_314
bit 26_315
bit 26_316
bit 26_317
bit 26_318
bit 26_319
bit 26_323
bit 26_329
bit 26_330
bit 26_331
bit 26_332
bit 26_333
bit 26_334
bit 26_335
bit 26_339
bit 26_345
bit 26_346
bit 26_347
bit 26_348
bit 26_349
bit 26_350
bit 26_351
bit 26_355
bit 26_361
bit 26_362
bit 26_363
bit 26_364
bit 26_365
bit 26_366
bit 26_367
bit 26_371
bit 26_377
bit 26_378
bit 26_379
bit 26_380
bit 26_381
bit 26_382
bit 26_383
bit 26_409
bit 26_410
bit 26_412
bit 26_413
bit 26_414
bit 26_415
bit 26_425
bit 26_426
bit 26_428
bit 26_429
bit 26_430
bit 26_431
bit 26_441
bit 26_442
bit 26_444
bit 26_445
bit 26_446
bit 26_447
bit 26_457
bit 26_458
bit 26_460
bit 26_461
bit 26_462
bit 26_463
bit 26_473
bit 26_474
bit 26_476
bit 26_477
bit 26_478
bit 26_479
bit 26_489
bit 26_490
bit 26_492
bit 26_493
bit 26_494
bit 26_495
bit 26_505
bit 26_506
bit 26_508
bit 26_509
bit 26_510
bit 26_511
bit 26_521
bit 26_522
bit 26_524
bit 26_525
bit 26_526
bit 26_527
bit 27_25
bit 27_28
bit 27_29
bit 27_30
bit 27_31
bit 27_41
bit 27_44
bit 27_45
bit 27_46
bit 27_47
bit 27_57
bit 27_60
bit 27_61
bit 27_62
bit 27_63
bit 27_73
bit 27_76
bit 27_77
bit 27_78
bit 27_79
bit 27_89
bit 27_92
bit 27_93
bit 27_94
bit 27_95
bit 27_105
bit 27_108
bit 27_109
bit 27_110
bit 27_111
bit 27_121
bit 27_124
bit 27_125
bit 27_126
bit 27_127
bit 27_137
bit 27_140
bit 27_141
bit 27_142
bit 27_143
bit 27_163
bit 27_166
bit 27_167
bit 27_169
bit 27_170
bit 27_171
bit 27_172
bit 27_173
bit 27_174
bit 27_175
bit 27_179
bit 27_182
bit 27_183
bit 27_185
bit 27_186
bit 27_187
bit 27_188
bit 27_189
bit 27_190
bit 27_191
bit 27_195
bit 27_198
bit 27_199
bit 27_201
bit 27_202
bit 27_203
bit 27_204
bit 27_205
bit 27_206
bit 27_207
bit 27_211
bit 27_214
bit 27_215
bit 27_217
bit 27_218
bit 27_219
bit 27_220
bit 27_221
bit 27_222
bit 27_223
bit 27_227
bit 27_230
bit 27_231
bit 27_233
bit 27_234
bit 27_235
bit 27_236
bit 27_237
bit 27_238
bit 27_239
bit 27_243
bit 27_246
bit 27_247
bit 27_249
bit 27_250
bit 27_251
bit 27_252
bit 27_253
bit 27_254
bit 27_255
bit 27_279
bit 27_280
bit 27_281
bit 27_282
bit 27_283
bit 27_284
bit 27_285
bit 27_286
bit 27_287
bit 27_291
bit 27_294
bit 27_295
bit 27_297
bit 27_298
bit 27_299
bit 27_300
bit 27_301
bit 27_302
bit 27_303
bit 27_307
bit 27_310
bit 27_311
bit 27_313
bit 27_314
bit 27_315
bit 27_316
bit 27_317
bit 27_318
bit 27_319
bit 27_323
bit 27_326
bit 27_327
bit 27_329
bit 27_330
bit 27_331
bit 27_332
bit 27_333
bit 27_334
bit 27_335
bit 27_339
bit 27_342
bit 27_343
bit 27_345
bit 27_346
bit 27_347
bit 27_348
bit 27_349
bit 27_350
bit 27_351
bit 27_355
bit 27_358
bit 27_359
bit 27_361
bit 27_362
bit 27_363
bit 27_364
bit 27_365
bit 27_366
bit 27_367
bit 27_371
bit 27_374
bit 27_375
bit 27_377
bit 27_378
bit 27_379
bit 27_380
bit 27_381
bit 27_382
bit 27_383
bit 27_409
bit 27_412
bit 27_413
bit 27_414
bit 27_415
bit 27_425
bit 27_428
bit 27_429
bit 27_430
bit 27_431
bit 27_441
bit 27_444
bit 27_445
bit 27_446
bit 27_447
bit 27_457
bit 27_460
bit 27_461
bit 27_462
bit 27_463
bit 27_473
bit 27_476
bit 27_477
bit 27_478
bit 27_479
bit 27_489
bit 27_492
bit 27_493
bit 27_494
bit 27_495
bit 27_505
bit 27_508
bit 27_509
bit 27_510
bit 27_511
bit 27_521
bit 27_524
bit 27_525
bit 27_526
bit 27_527
bit 28_25
bit 28_26
bit 28_28
bit 28_29
bit 28_30
bit 28_31
bit 28_41
bit 28_42
bit 28_44
bit 28_45
bit 28_46
bit 28_47
bit 28_57
bit 28_58
bit 28_60
bit 28_61
bit 28_62
bit 28_63
bit 28_73
bit 28_74
bit 28_76
bit 28_77
bit 28_78
bit 28_79
bit 28_89
bit 28_90
bit 28_92
bit 28_93
bit 28_94
bit 28_95
bit 28_105
bit 28_106
bit 28_108
bit 28_109
bit 28_110
bit 28_111
bit 28_121
bit 28_122
bit 28_124
bit 28_125
bit 28_126
bit 28_127
bit 28_137
bit 28_138
bit 28_140
bit 28_141
bit 28_142
bit 28_143
bit 28_163
bit 28_169
bit 28_170
bit 28_171
bit 28_172
bit 28_173
bit 28_174
bit 28_175
bit 28_179
bit 28_185
bit 28_186
bit 28_187
bit 28_188
bit 28_189
bit 28_190
bit 28_191
bit 28_195
bit 28_201
bit 28_202
bit 28_203
bit 28_204
bit 28_205
bit 28_206
bit 28_207
bit 28_211
bit 28_217
bit 28_218
bit 28_219
bit 28_220
bit 28_221
bit 28_222
bit 28_223
bit 28_227
bit 28_233
bit 28_234
bit 28_235
bit 28_236
bit 28_237
bit 28_238
bit 28_239
bit 28_240
bit 28_241
bit 28_243
bit 28_249
bit 28_250
bit 28_251
bit 28_252
bit 28_253
bit 28_254
bit 28_255
bit 28_270
bit 28_271
bit 28_274
bit 28_275
bit 28_276
bit 28_277
bit 28_278
bit 28_279
bit 28_280
bit 28_281
bit 28_282
bit 28_283
bit 28_284
bit 28_285
bit 28_286
bit 28_287
bit 28_291
bit 28_297
bit 28_298
bit 28_299
bit 28_300
bit 28_301
bit 28_302
bit 28_303
bit 28_307
bit 28_313
bit 28_314
bit 28_315
bit 28_316
bit 28_317
bit 28_318
bit 28_319
bit 28_323
bit 28_329
bit 28_330
bit 28_331
bit 28_332
bit 28_333
bit 28_334
bit 28_335
bit 28_339
bit 28_345
bit 28_346
bit 28_347
bit 28_348
bit 28_349
bit 28_350
bit 28_351
bit 28_355
bit 28_361
bit 28_362
bit 28_363
bit 28_364
bit 28_365
bit 28_366
bit 28_367
bit 28_371
bit 28_377
bit 28_378
bit 28_379
bit 28_380
bit 28_381
bit 28_382
bit 28_383
bit 28_409
bit 28_410
bit 28_412
bit 28_413
bit 28_414
bit 28_415
bit 28_425
bit 28_426
bit 28_428
bit 28_429
bit 28_430
bit 28_431
bit 28_441
bit 28_442
bit 28_444
bit 28_445
bit 28_446
bit 28_447
bit 28_457
bit 28_458
bit 28_460
bit 28_461
bit 28_462
bit 28_463
bit 28_473
bit 28_474
bit 28_476
bit 28_477
bit 28_478
bit 28_479
bit 28_489
bit 28_490
bit 28_492
bit 28_493
bit 28_494
bit 28_495
bit 28_505
bit 28_506
bit 28_508
bit 28_509
bit 28_510
bit 28_511
bit 28_521
bit 28_522
bit 28_524
bit 28_525
bit 28_526
bit 28_527
bit 29_25
bit 29_28
bit 29_29
bit 29_30
bit 29_31
bit 29_41
bit 29_44
bit 29_45
bit 29_46
bit 29_47
bit 29_57
bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 29_73
bit 29_76
bit 29_77
bit 29_78
bit 29_79
bit 29_89
bit 29_92
bit 29_93
bit 29_94
bit 29_95
bit 29_105
bit 29_108
bit 29_109
bit 29_110
bit 29_111
bit 29_121
bit 29_124
bit 29_125
bit 29_126
bit 29_127
bit 29_137
bit 29_140
bit 29_141
bit 29_142
bit 29_143
bit 29_163
bit 29_166
bit 29_167
bit 29_169
bit 29_170
bit 29_171
bit 29_172
bit 29_173
bit 29_174
bit 29_175
bit 29_179
bit 29_182
bit 29_183
bit 29_185
bit 29_186
bit 29_187
bit 29_188
bit 29_189
bit 29_190
bit 29_191
bit 29_195
bit 29_198
bit 29_199
bit 29_201
bit 29_202
bit 29_203
bit 29_204
bit 29_205
bit 29_206
bit 29_207
bit 29_211
bit 29_214
bit 29_215
bit 29_217
bit 29_218
bit 29_219
bit 29_220
bit 29_221
bit 29_222
bit 29_223
bit 29_227
bit 29_230
bit 29_231
bit 29_233
bit 29_234
bit 29_235
bit 29_236
bit 29_237
bit 29_238
bit 29_239
bit 29_240
bit 29_241
bit 29_243
bit 29_246
bit 29_247
bit 29_249
bit 29_250
bit 29_251
bit 29_252
bit 29_253
bit 29_254
bit 29_255
bit 29_270
bit 29_271
bit 29_274
bit 29_275
bit 29_276
bit 29_277
bit 29_278
bit 29_279
bit 29_280
bit 29_281
bit 29_282
bit 29_283
bit 29_284
bit 29_285
bit 29_286
bit 29_287
bit 29_291
bit 29_294
bit 29_295
bit 29_297
bit 29_298
bit 29_299
bit 29_300
bit 29_301
bit 29_302
bit 29_303
bit 29_307
bit 29_310
bit 29_311
bit 29_313
bit 29_314
bit 29_315
bit 29_316
bit 29_317
bit 29_318
bit 29_319
bit 29_323
bit 29_326
bit 29_327
bit 29_329
bit 29_330
bit 29_331
bit 29_332
bit 29_333
bit 29_334
bit 29_335
bit 29_339
bit 29_342
bit 29_343
bit 29_345
bit 29_346
bit 29_347
bit 29_348
bit 29_349
bit 29_350
bit 29_351
bit 29_355
bit 29_358
bit 29_359
bit 29_361
bit 29_362
bit 29_363
bit 29_364
bit 29_365
bit 29_366
bit 29_367
bit 29_371
bit 29_374
bit 29_375
bit 29_377
bit 29_378
bit 29_379
bit 29_380
bit 29_381
bit 29_382
bit 29_383
bit 29_409
bit 29_412
bit 29_413
bit 29_414
bit 29_415
bit 29_425
bit 29_428
bit 29_429
bit 29_430
bit 29_431
bit 29_441
bit 29_444
bit 29_445
bit 29_446
bit 29_447
bit 29_457
bit 29_460
bit 29_461
bit 29_462
bit 29_463
bit 29_473
bit 29_476
bit 29_477
bit 29_478
bit 29_479
bit 29_489
bit 29_492
bit 29_493
bit 29_494
bit 29_495
bit 29_505
bit 29_508
bit 29_509
bit 29_510
bit 29_511
bit 29_521
bit 29_524
bit 29_525
bit 29_526
bit 29_527

0
zynq7/mask_dsp_l.origin_info.db Normal file
View File

0
zynq7/mask_dsp_r.origin_info.db Normal file
View File

0
zynq7/mask_hclk_l.origin_info.db Normal file
View File

0
zynq7/mask_hclk_r.origin_info.db Normal file
View File

120
zynq7/mask_liob33.db
View File

@ -69,6 +69,7 @@ bit 02_14
bit 02_15
bit 02_22
bit 02_23
bit 02_26
bit 02_30
bit 02_31
bit 02_42
@ -81,30 +82,27 @@ bit 02_58
bit 02_59
bit 02_62
bit 02_63
bit 02_66
bit 02_67
bit 02_69
bit 02_70
bit 02_71
bit 02_74
bit 02_75
bit 02_77
bit 02_78
bit 02_79
bit 02_86
bit 02_87
bit 02_93
bit 02_94
bit 02_95
bit 02_102
bit 02_106
bit 02_110
bit 02_111
bit 02_118
bit 02_125
bit 02_126
bit 02_127
bit 03_02
bit 03_04
bit 03_05
bit 03_06
bit 03_10
bit 03_12
@ -114,20 +112,16 @@ bit 03_21
bit 03_29
bit 03_44
bit 03_45
bit 03_52
bit 03_53
bit 03_60
bit 03_61
bit 03_62
bit 03_66
bit 03_69
bit 03_70
bit 03_74
bit 03_76
bit 03_77
bit 03_78
bit 03_93
bit 03_109
bit 03_110
bit 03_116
bit 03_125
@ -141,9 +135,9 @@ bit 04_14
bit 04_15
bit 04_19
bit 04_28
bit 04_29
bit 04_30
bit 04_44
bit 04_46
bit 04_47
bit 04_51
bit 04_55
@ -151,21 +145,22 @@ bit 04_59
bit 04_60
bit 04_61
bit 04_63
bit 04_71
bit 04_75
bit 04_76
bit 04_77
bit 04_78
bit 04_79
bit 04_83
bit 04_87
bit 04_92
bit 04_93
bit 04_94
bit 04_103
bit 04_108
bit 04_111
bit 04_115
bit 04_119
bit 04_124
bit 04_125
bit 04_127
bit 05_01
bit 05_02
@ -175,7 +170,9 @@ bit 05_10
bit 05_13
bit 05_17
bit 05_18
bit 05_26
bit 05_42
bit 05_44
bit 05_49
bit 05_50
bit 05_52
@ -183,24 +180,18 @@ bit 05_53
bit 05_54
bit 05_58
bit 05_60
bit 05_62
bit 05_65
bit 05_66
bit 05_68
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
bit 05_77
bit 05_78
bit 05_81
bit 05_82
bit 05_86
bit 05_110
bit 05_113
bit 05_114
bit 05_117
bit 05_118
bit 05_119
bit 05_126
bit 06_01
@ -219,11 +210,12 @@ bit 06_15
bit 06_17
bit 06_20
bit 06_22
bit 06_23
bit 06_27
bit 06_28
bit 06_29
bit 06_30
bit 06_31
bit 06_39
bit 06_43
bit 06_44
bit 06_45
@ -233,8 +225,9 @@ bit 06_53
bit 06_59
bit 06_60
bit 06_61
bit 06_65
bit 06_63
bit 06_66
bit 06_68
bit 06_70
bit 06_71
bit 06_74
@ -252,8 +245,8 @@ bit 06_93
bit 06_94
bit 06_95
bit 06_103
bit 06_105
bit 06_107
bit 06_108
bit 06_121
bit 06_123
bit 06_124
@ -266,7 +259,6 @@ bit 07_05
bit 07_06
bit 07_07
bit 07_08
bit 07_10
bit 07_11
bit 07_13
bit 07_14
@ -277,13 +269,12 @@ bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_27
bit 07_30
bit 07_31
bit 07_32
bit 07_36
bit 07_38
bit 07_40
bit 07_42
bit 07_43
bit 07_46
bit 07_47
@ -297,7 +288,6 @@ bit 07_59
bit 07_62
bit 07_63
bit 07_64
bit 07_66
bit 07_67
bit 07_68
bit 07_69
@ -310,6 +300,7 @@ bit 07_78
bit 07_79
bit 07_80
bit 07_83
bit 07_84
bit 07_86
bit 07_87
bit 07_88
@ -327,6 +318,7 @@ bit 07_111
bit 07_112
bit 07_115
bit 07_118
bit 07_119
bit 07_120
bit 07_126
bit 07_127
@ -352,7 +344,6 @@ bit 08_22
bit 08_23
bit 08_24
bit 08_25
bit 08_26
bit 08_27
bit 08_28
bit 08_29
@ -369,12 +360,14 @@ bit 08_43
bit 08_46
bit 08_47
bit 08_49
bit 08_53
bit 08_54
bit 08_55
bit 08_56
bit 08_57
bit 08_58
bit 08_59
bit 08_61
bit 08_62
bit 08_63
bit 08_64
@ -444,7 +437,6 @@ bit 09_16
bit 09_19
bit 09_20
bit 09_22
bit 09_23
bit 09_24
bit 09_27
bit 09_34
@ -455,7 +447,6 @@ bit 09_39
bit 09_40
bit 09_41
bit 09_47
bit 09_49
bit 09_50
bit 09_51
bit 09_52
@ -463,6 +454,7 @@ bit 09_53
bit 09_56
bit 09_57
bit 09_58
bit 09_59
bit 09_63
bit 09_64
bit 09_65
@ -474,14 +466,13 @@ bit 09_75
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
bit 09_91
bit 09_98
bit 09_99
bit 09_100
bit 09_101
bit 09_104
bit 09_106
bit 09_107
bit 09_111
@ -494,12 +485,11 @@ bit 09_122
bit 09_123
bit 09_127
bit 10_00
bit 10_01
bit 10_02
bit 10_03
bit 10_04
bit 10_05
bit 10_07
bit 10_08
bit 10_09
bit 10_10
bit 10_11
@ -510,7 +500,6 @@ bit 10_16
bit 10_17
bit 10_18
bit 10_19
bit 10_21
bit 10_23
bit 10_25
bit 10_26
@ -529,13 +518,15 @@ bit 10_46
bit 10_47
bit 10_49
bit 10_50
bit 10_51
bit 10_52
bit 10_53
bit 10_55
bit 10_56
bit 10_57
bit 10_58
bit 10_59
bit 10_60
bit 10_62
bit 10_63
bit 10_64
bit 10_65
@ -553,7 +544,6 @@ bit 10_79
bit 10_80
bit 10_81
bit 10_82
bit 10_83
bit 10_85
bit 10_87
bit 10_88
@ -571,6 +561,7 @@ bit 10_107
bit 10_110
bit 10_111
bit 10_114
bit 10_115
bit 10_117
bit 10_119
bit 10_120
@ -586,12 +577,12 @@ bit 11_07
bit 11_08
bit 11_09
bit 11_10
bit 11_11
bit 11_13
bit 11_15
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_21
bit 11_23
bit 11_24
@ -607,7 +598,6 @@ bit 11_40
bit 11_41
bit 11_42
bit 11_43
bit 11_44
bit 11_47
bit 11_49
bit 11_50
@ -620,9 +610,11 @@ bit 11_58
bit 11_59
bit 11_60
bit 11_63
bit 11_64
bit 11_65
bit 11_66
bit 11_67
bit 11_68
bit 11_69
bit 11_71
bit 11_73
@ -633,10 +625,13 @@ bit 11_79
bit 11_81
bit 11_82
bit 11_87
bit 11_89
bit 11_90
bit 11_91
bit 11_95
bit 11_97
bit 11_98
bit 11_100
bit 11_101
bit 11_103
bit 11_105
@ -650,6 +645,7 @@ bit 11_119
bit 11_121
bit 11_122
bit 11_123
bit 11_125
bit 11_127
bit 12_00
bit 12_01
@ -668,7 +664,6 @@ bit 12_16
bit 12_17
bit 12_21
bit 12_23
bit 12_24
bit 12_25
bit 12_26
bit 12_27
@ -684,10 +679,9 @@ bit 12_42
bit 12_43
bit 12_46
bit 12_47
bit 12_48
bit 12_49
bit 12_50
bit 12_51
bit 12_52
bit 12_53
bit 12_55
bit 12_57
@ -707,17 +701,16 @@ bit 12_78
bit 12_79
bit 12_81
bit 12_82
bit 12_83
bit 12_85
bit 12_87
bit 12_89
bit 12_90
bit 12_91
bit 12_93
bit 12_94
bit 12_95
bit 12_97
bit 12_98
bit 12_100
bit 12_101
bit 12_103
bit 12_105
@ -727,13 +720,12 @@ bit 12_110
bit 12_111
bit 12_113
bit 12_114
bit 12_115
bit 12_117
bit 12_119
bit 12_120
bit 12_121
bit 12_122
bit 12_123
bit 12_124
bit 12_127
bit 13_00
bit 13_01
@ -754,12 +746,12 @@ bit 13_16
bit 13_17
bit 13_18
bit 13_19
bit 13_20
bit 13_22
bit 13_23
bit 13_24
bit 13_25
bit 13_26
bit 13_28
bit 13_30
bit 13_31
bit 13_33
@ -783,12 +775,12 @@ bit 13_57
bit 13_58
bit 13_59
bit 13_60
bit 13_61
bit 13_62
bit 13_63
bit 13_64
bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
@ -810,11 +802,10 @@ bit 13_88
bit 13_89
bit 13_90
bit 13_92
bit 13_93
bit 13_94
bit 13_95
bit 13_97
bit 13_98
bit 13_100
bit 13_101
bit 13_102
bit 13_103
@ -834,6 +825,7 @@ bit 13_122
bit 13_123
bit 13_124
bit 13_125
bit 13_126
bit 13_127
bit 14_00
bit 14_01
@ -841,7 +833,6 @@ bit 14_02
bit 14_03
bit 14_04
bit 14_05
bit 14_07
bit 14_09
bit 14_10
bit 14_11
@ -855,6 +846,7 @@ bit 14_19
bit 14_20
bit 14_25
bit 14_26
bit 14_28
bit 14_29
bit 14_30
bit 14_31
@ -877,31 +869,31 @@ bit 14_76
bit 14_77
bit 14_78
bit 14_79
bit 14_80
bit 14_82
bit 14_83
bit 14_84
bit 14_87
bit 14_88
bit 14_89
bit 14_90
bit 14_93
bit 14_94
bit 14_95
bit 14_98
bit 14_100
bit 14_106
bit 14_104
bit 14_114
bit 14_116
bit 14_120
bit 14_122
bit 14_126
bit 15_00
bit 15_01
bit 15_02
bit 15_03
bit 15_04
bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_09
bit 15_10
bit 15_12
@ -934,9 +926,10 @@ bit 15_63
bit 15_64
bit 15_65
bit 15_66
bit 15_67
bit 15_68
bit 15_69
bit 15_71
bit 15_72
bit 15_73
bit 15_74
bit 15_75
@ -946,7 +939,7 @@ bit 15_78
bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_85
bit 15_87
bit 15_89
bit 15_90
@ -965,6 +958,7 @@ bit 15_113
bit 15_119
bit 15_121
bit 15_123
bit 15_125
bit 15_127
bit 16_02
bit 16_06
@ -1033,9 +1027,9 @@ bit 17_23
bit 17_24
bit 17_30
bit 17_31
bit 17_32
bit 17_35
bit 17_38
bit 17_39
bit 17_40
bit 17_42
bit 17_43
@ -1084,7 +1078,6 @@ bit 18_06
bit 18_07
bit 18_08
bit 18_14
bit 18_17
bit 18_20
bit 18_22
bit 18_23
@ -1140,7 +1133,6 @@ bit 19_01
bit 19_03
bit 19_07
bit 19_08
bit 19_09
bit 19_14
bit 19_17
bit 19_20
@ -1160,7 +1152,6 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1280,7 +1271,6 @@ bit 21_122
bit 21_126
bit 22_02
bit 22_06
bit 22_07
bit 22_09
bit 22_15
bit 22_21
@ -1288,10 +1278,8 @@ bit 22_22
bit 22_23
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1300,7 +1288,6 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1308,6 +1295,7 @@ bit 22_60
bit 22_62
bit 22_66
bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_85
@ -1342,7 +1330,6 @@ bit 23_23
bit 23_24
bit 23_30
bit 23_31
bit 23_32
bit 23_35
bit 23_38
bit 23_40
@ -1368,6 +1355,7 @@ bit 23_80
bit 23_85
bit 23_86
bit 23_87
bit 23_88
bit 23_94
bit 23_95
bit 23_96
@ -1461,7 +1449,6 @@ bit 25_00
bit 25_02
bit 25_06
bit 25_07
bit 25_08
bit 25_09
bit 25_15
bit 25_16
@ -1487,7 +1474,6 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58

120
zynq7/mask_riob33.db
View File

@ -69,6 +69,7 @@ bit 02_14
bit 02_15
bit 02_22
bit 02_23
bit 02_26
bit 02_30
bit 02_31
bit 02_42
@ -81,30 +82,27 @@ bit 02_58
bit 02_59
bit 02_62
bit 02_63
bit 02_66
bit 02_67
bit 02_69
bit 02_70
bit 02_71
bit 02_74
bit 02_75
bit 02_77
bit 02_78
bit 02_79
bit 02_86
bit 02_87
bit 02_93
bit 02_94
bit 02_95
bit 02_102
bit 02_106
bit 02_110
bit 02_111
bit 02_118
bit 02_125
bit 02_126
bit 02_127
bit 03_02
bit 03_04
bit 03_05
bit 03_06
bit 03_10
bit 03_12
@ -114,20 +112,16 @@ bit 03_21
bit 03_29
bit 03_44
bit 03_45
bit 03_52
bit 03_53
bit 03_60
bit 03_61
bit 03_62
bit 03_66
bit 03_69
bit 03_70
bit 03_74
bit 03_76
bit 03_77
bit 03_78
bit 03_93
bit 03_109
bit 03_110
bit 03_116
bit 03_125
@ -141,9 +135,9 @@ bit 04_14
bit 04_15
bit 04_19
bit 04_28
bit 04_29
bit 04_30
bit 04_44
bit 04_46
bit 04_47
bit 04_51
bit 04_55
@ -151,21 +145,22 @@ bit 04_59
bit 04_60
bit 04_61
bit 04_63
bit 04_71
bit 04_75
bit 04_76
bit 04_77
bit 04_78
bit 04_79
bit 04_83
bit 04_87
bit 04_92
bit 04_93
bit 04_94
bit 04_103
bit 04_108
bit 04_111
bit 04_115
bit 04_119
bit 04_124
bit 04_125
bit 04_127
bit 05_01
bit 05_02
@ -175,7 +170,9 @@ bit 05_10
bit 05_13
bit 05_17
bit 05_18
bit 05_26
bit 05_42
bit 05_44
bit 05_49
bit 05_50
bit 05_52
@ -183,24 +180,18 @@ bit 05_53
bit 05_54
bit 05_58
bit 05_60
bit 05_62
bit 05_65
bit 05_66
bit 05_68
bit 05_69
bit 05_70
bit 05_73
bit 05_74
bit 05_76
bit 05_77
bit 05_78
bit 05_81
bit 05_82
bit 05_86
bit 05_110
bit 05_113
bit 05_114
bit 05_117
bit 05_118
bit 05_119
bit 05_126
bit 06_01
@ -219,11 +210,12 @@ bit 06_15
bit 06_17
bit 06_20
bit 06_22
bit 06_23
bit 06_27
bit 06_28
bit 06_29
bit 06_30
bit 06_31
bit 06_39
bit 06_43
bit 06_44
bit 06_45
@ -233,8 +225,9 @@ bit 06_53
bit 06_59
bit 06_60
bit 06_61
bit 06_65
bit 06_63
bit 06_66
bit 06_68
bit 06_70
bit 06_71
bit 06_74
@ -252,8 +245,8 @@ bit 06_93
bit 06_94
bit 06_95
bit 06_103
bit 06_105
bit 06_107
bit 06_108
bit 06_121
bit 06_123
bit 06_124
@ -266,7 +259,6 @@ bit 07_05
bit 07_06
bit 07_07
bit 07_08
bit 07_10
bit 07_11
bit 07_13
bit 07_14
@ -277,13 +269,12 @@ bit 07_20
bit 07_22
bit 07_23
bit 07_24
bit 07_27
bit 07_30
bit 07_31
bit 07_32
bit 07_36
bit 07_38
bit 07_40
bit 07_42
bit 07_43
bit 07_46
bit 07_47
@ -297,7 +288,6 @@ bit 07_59
bit 07_62
bit 07_63
bit 07_64
bit 07_66
bit 07_67
bit 07_68
bit 07_69
@ -310,6 +300,7 @@ bit 07_78
bit 07_79
bit 07_80
bit 07_83
bit 07_84
bit 07_86
bit 07_87
bit 07_88
@ -327,6 +318,7 @@ bit 07_111
bit 07_112
bit 07_115
bit 07_118
bit 07_119
bit 07_120
bit 07_126
bit 07_127
@ -352,7 +344,6 @@ bit 08_22
bit 08_23
bit 08_24
bit 08_25
bit 08_26
bit 08_27
bit 08_28
bit 08_29
@ -369,12 +360,14 @@ bit 08_43
bit 08_46
bit 08_47
bit 08_49
bit 08_53
bit 08_54
bit 08_55
bit 08_56
bit 08_57
bit 08_58
bit 08_59
bit 08_61
bit 08_62
bit 08_63
bit 08_64
@ -444,7 +437,6 @@ bit 09_16
bit 09_19
bit 09_20
bit 09_22
bit 09_23
bit 09_24
bit 09_27
bit 09_34
@ -455,7 +447,6 @@ bit 09_39
bit 09_40
bit 09_41
bit 09_47
bit 09_49
bit 09_50
bit 09_51
bit 09_52
@ -463,6 +454,7 @@ bit 09_53
bit 09_56
bit 09_57
bit 09_58
bit 09_59
bit 09_63
bit 09_64
bit 09_65
@ -474,14 +466,13 @@ bit 09_75
bit 09_77
bit 09_79
bit 09_80
bit 09_82
bit 09_83
bit 09_84
bit 09_91
bit 09_98
bit 09_99
bit 09_100
bit 09_101
bit 09_104
bit 09_106
bit 09_107
bit 09_111
@ -494,12 +485,11 @@ bit 09_122
bit 09_123
bit 09_127
bit 10_00
bit 10_01
bit 10_02
bit 10_03
bit 10_04
bit 10_05
bit 10_07
bit 10_08
bit 10_09
bit 10_10
bit 10_11
@ -510,7 +500,6 @@ bit 10_16
bit 10_17
bit 10_18
bit 10_19
bit 10_21
bit 10_23
bit 10_25
bit 10_26
@ -529,13 +518,15 @@ bit 10_46
bit 10_47
bit 10_49
bit 10_50
bit 10_51
bit 10_52
bit 10_53
bit 10_55
bit 10_56
bit 10_57
bit 10_58
bit 10_59
bit 10_60
bit 10_62
bit 10_63
bit 10_64
bit 10_65
@ -553,7 +544,6 @@ bit 10_79
bit 10_80
bit 10_81
bit 10_82
bit 10_83
bit 10_85
bit 10_87
bit 10_88
@ -571,6 +561,7 @@ bit 10_107
bit 10_110
bit 10_111
bit 10_114
bit 10_115
bit 10_117
bit 10_119
bit 10_120
@ -586,12 +577,12 @@ bit 11_07
bit 11_08
bit 11_09
bit 11_10
bit 11_11
bit 11_13
bit 11_15
bit 11_17
bit 11_18
bit 11_19
bit 11_20
bit 11_21
bit 11_23
bit 11_24
@ -607,7 +598,6 @@ bit 11_40
bit 11_41
bit 11_42
bit 11_43
bit 11_44
bit 11_47
bit 11_49
bit 11_50
@ -620,9 +610,11 @@ bit 11_58
bit 11_59
bit 11_60
bit 11_63
bit 11_64
bit 11_65
bit 11_66
bit 11_67
bit 11_68
bit 11_69
bit 11_71
bit 11_73
@ -633,10 +625,13 @@ bit 11_79
bit 11_81
bit 11_82
bit 11_87
bit 11_89
bit 11_90
bit 11_91
bit 11_95
bit 11_97
bit 11_98
bit 11_100
bit 11_101
bit 11_103
bit 11_105
@ -650,6 +645,7 @@ bit 11_119
bit 11_121
bit 11_122
bit 11_123
bit 11_125
bit 11_127
bit 12_00
bit 12_01
@ -668,7 +664,6 @@ bit 12_16
bit 12_17
bit 12_21
bit 12_23
bit 12_24
bit 12_25
bit 12_26
bit 12_27
@ -684,10 +679,9 @@ bit 12_42
bit 12_43
bit 12_46
bit 12_47
bit 12_48
bit 12_49
bit 12_50
bit 12_51
bit 12_52
bit 12_53
bit 12_55
bit 12_57
@ -707,17 +701,16 @@ bit 12_78
bit 12_79
bit 12_81
bit 12_82
bit 12_83
bit 12_85
bit 12_87
bit 12_89
bit 12_90
bit 12_91
bit 12_93
bit 12_94
bit 12_95
bit 12_97
bit 12_98
bit 12_100
bit 12_101
bit 12_103
bit 12_105
@ -727,13 +720,12 @@ bit 12_110
bit 12_111
bit 12_113
bit 12_114
bit 12_115
bit 12_117
bit 12_119
bit 12_120
bit 12_121
bit 12_122
bit 12_123
bit 12_124
bit 12_127
bit 13_00
bit 13_01
@ -754,12 +746,12 @@ bit 13_16
bit 13_17
bit 13_18
bit 13_19
bit 13_20
bit 13_22
bit 13_23
bit 13_24
bit 13_25
bit 13_26
bit 13_28
bit 13_30
bit 13_31
bit 13_33
@ -783,12 +775,12 @@ bit 13_57
bit 13_58
bit 13_59
bit 13_60
bit 13_61
bit 13_62
bit 13_63
bit 13_64
bit 13_65
bit 13_66
bit 13_67
bit 13_68
bit 13_69
bit 13_70
@ -810,11 +802,10 @@ bit 13_88
bit 13_89
bit 13_90
bit 13_92
bit 13_93
bit 13_94
bit 13_95
bit 13_97
bit 13_98
bit 13_100
bit 13_101
bit 13_102
bit 13_103
@ -834,6 +825,7 @@ bit 13_122
bit 13_123
bit 13_124
bit 13_125
bit 13_126
bit 13_127
bit 14_00
bit 14_01
@ -841,7 +833,6 @@ bit 14_02
bit 14_03
bit 14_04
bit 14_05
bit 14_07
bit 14_09
bit 14_10
bit 14_11
@ -855,6 +846,7 @@ bit 14_19
bit 14_20
bit 14_25
bit 14_26
bit 14_28
bit 14_29
bit 14_30
bit 14_31
@ -877,31 +869,31 @@ bit 14_76
bit 14_77
bit 14_78
bit 14_79
bit 14_80
bit 14_82
bit 14_83
bit 14_84
bit 14_87
bit 14_88
bit 14_89
bit 14_90
bit 14_93
bit 14_94
bit 14_95
bit 14_98
bit 14_100
bit 14_106
bit 14_104
bit 14_114
bit 14_116
bit 14_120
bit 14_122
bit 14_126
bit 15_00
bit 15_01
bit 15_02
bit 15_03
bit 15_04
bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_09
bit 15_10
bit 15_12
@ -934,9 +926,10 @@ bit 15_63
bit 15_64
bit 15_65
bit 15_66
bit 15_67
bit 15_68
bit 15_69
bit 15_71
bit 15_72
bit 15_73
bit 15_74
bit 15_75
@ -946,7 +939,7 @@ bit 15_78
bit 15_79
bit 15_80
bit 15_81
bit 15_82
bit 15_85
bit 15_87
bit 15_89
bit 15_90
@ -965,6 +958,7 @@ bit 15_113
bit 15_119
bit 15_121
bit 15_123
bit 15_125
bit 15_127
bit 16_02
bit 16_06
@ -1033,9 +1027,9 @@ bit 17_23
bit 17_24
bit 17_30
bit 17_31
bit 17_32
bit 17_35
bit 17_38
bit 17_39
bit 17_40
bit 17_42
bit 17_43
@ -1084,7 +1078,6 @@ bit 18_06
bit 18_07
bit 18_08
bit 18_14
bit 18_17
bit 18_20
bit 18_22
bit 18_23
@ -1140,7 +1133,6 @@ bit 19_01
bit 19_03
bit 19_07
bit 19_08
bit 19_09
bit 19_14
bit 19_17
bit 19_20
@ -1160,7 +1152,6 @@ bit 19_46
bit 19_47
bit 19_49
bit 19_50
bit 19_54
bit 19_55
bit 19_56
bit 19_57
@ -1280,7 +1271,6 @@ bit 21_122
bit 21_126
bit 22_02
bit 22_06
bit 22_07
bit 22_09
bit 22_15
bit 22_21
@ -1288,10 +1278,8 @@ bit 22_22
bit 22_23
bit 22_30
bit 22_31
bit 22_32
bit 22_35
bit 22_38
bit 22_40
bit 22_42
bit 22_43
bit 22_44
@ -1300,7 +1288,6 @@ bit 22_47
bit 22_48
bit 22_51
bit 22_54
bit 22_55
bit 22_56
bit 22_57
bit 22_58
@ -1308,6 +1295,7 @@ bit 22_60
bit 22_62
bit 22_66
bit 22_70
bit 22_71
bit 22_73
bit 22_79
bit 22_85
@ -1342,7 +1330,6 @@ bit 23_23
bit 23_24
bit 23_30
bit 23_31
bit 23_32
bit 23_35
bit 23_38
bit 23_40
@ -1368,6 +1355,7 @@ bit 23_80
bit 23_85
bit 23_86
bit 23_87
bit 23_88
bit 23_94
bit 23_95
bit 23_96
@ -1461,7 +1449,6 @@ bit 25_00
bit 25_02
bit 25_06
bit 25_07
bit 25_08
bit 25_09
bit 25_15
bit 25_16
@ -1487,7 +1474,6 @@ bit 25_48
bit 25_51
bit 25_52
bit 25_54
bit 25_55
bit 25_56
bit 25_57
bit 25_58

0
zynq7/ppips_bram_int_interface_l.origin_info.db Normal file
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zynq7/ppips_bram_int_interface_r.origin_info.db Normal file
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zynq7/ppips_bram_l.origin_info.db Normal file
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zynq7/ppips_bram_r.origin_info.db Normal file
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zynq7/ppips_clbll_l.origin_info.db Normal file
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zynq7/ppips_clbll_r.origin_info.db Normal file
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zynq7/ppips_clblm_l.origin_info.db Normal file
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zynq7/ppips_clblm_r.origin_info.db Normal file
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zynq7/ppips_dsp_l.origin_info.db Normal file
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zynq7/ppips_dsp_r.origin_info.db Normal file
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zynq7/ppips_hclk_l.origin_info.db Normal file
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zynq7/ppips_hclk_r.origin_info.db Normal file
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0
zynq7/ppips_int_l.origin_info.db Normal file
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0
zynq7/ppips_int_r.origin_info.db Normal file
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2
zynq7/segbits_clbll_l.db
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@ -328,6 +328,7 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.NOCLKINV !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
@ -667,6 +668,7 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.NOCLKINV !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13

2
zynq7/segbits_clbll_l.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLL_L.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_L.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_L.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_L.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_L.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
@ -671,6 +672,7 @@ CLBLL_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11

2
zynq7/segbits_clbll_r.db
View File

@ -328,6 +328,7 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.NOCLKINV !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 !00_12 !30_13 !30_14
@ -667,6 +668,7 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.NOCLKINV !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13

2
zynq7/segbits_clbll_r.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLL_R.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLL_R.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLL_R.SLICEL_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLL_R.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLL_R.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12
@ -671,6 +672,7 @@ CLBLL_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLL_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLL_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLL_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLL_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11

5
zynq7/segbits_clblm_l.db
View File

@ -328,6 +328,7 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.NOCLKINV !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
@ -350,6 +351,7 @@ CLBLM_L.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_L.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
@ -436,6 +438,7 @@ CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
@ -524,6 +527,7 @@ CLBLM_L.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
@ -682,6 +686,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.NOCLKINV !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14

5
zynq7/segbits_clblm_l.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLM_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_L.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
@ -350,6 +351,7 @@ CLBLM_L.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
@ -436,6 +438,7 @@ CLBLM_L.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
@ -528,6 +531,7 @@ CLBLM_L.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
@ -686,6 +690,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_L.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_L.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_L.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_L.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12

5
zynq7/segbits_clblm_r.db
View File

@ -328,6 +328,7 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.O6 !30_53 !31_53 31_56 !31_57
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.NOCLKINV !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.CIN !01_11 31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 !01_11 !31_12 !31_13
@ -350,6 +351,7 @@ CLBLM_R.SLICEM_X0.AFFMUX.F7 30_00 30_01 !30_02 !30_03
CLBLM_R.SLICEM_X0.AFFMUX.O5 30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
@ -436,6 +438,7 @@ CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 30_24 !30_25 !30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 30_24 !30_25 !30_26 !30_27
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
@ -524,6 +527,7 @@ CLBLM_R.SLICEM_X0.CFFMUX.O5 30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 !01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
@ -682,6 +686,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.NOCLKINV !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN !00_12 30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 !00_12 !30_13 !30_14

5
zynq7/segbits_clblm_r.origin_info.db
View File

@ -332,6 +332,7 @@ CLBLM_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56
CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31
CLBLM_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32
CLBLM_R.SLICEL_X1.NOCLKINV origin:011-clb-ffconfig !00_52
CLBLM_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13
CLBLM_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11
@ -350,6 +351,7 @@ CLBLM_R.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.BDI1_BMC31 origin:019-clb-ndi1mux !00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14
@ -436,6 +438,7 @@ CLBLM_R.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.DI_CMC31 origin:019-clb-ndi1mux !00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30
@ -528,6 +531,7 @@ CLBLM_R.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.DI_DMC31 origin:019-clb-ndi1mux !01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46
@ -686,6 +690,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48
CLBLM_R.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32
CLBLM_R.SLICEM_X0.NOCLKINV origin:011-clb-ffconfig !01_51
CLBLM_R.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14
CLBLM_R.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12

928
zynq7/segbits_clk_hrow_bot_r.db
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1774
zynq7/segbits_clk_hrow_bot_r.origin_info.db
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960
zynq7/segbits_clk_hrow_top_r.db
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1774
zynq7/segbits_clk_hrow_top_r.origin_info.db
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318
zynq7/segbits_int_l.origin_info.db
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@ -6,9 +6,9 @@ INT_L.BYP_ALT0.ER1END0 origin:050-pip-seed !22_07 17_07 23_07 24_07 25_07
INT_L.BYP_ALT0.FAN_BOUNCE2 origin:050-pip-seed !22_07 21_07 23_07 24_07 25_07
INT_L.BYP_ALT0.FAN_BOUNCE7 origin:050-pip-seed !23_07 21_07 22_07 24_07 25_07
INT_L.BYP_ALT0.GFAN0 origin:054-pip-fan-alt !22_07 !23_07 !25_07 20_07 24_07
INT_L.BYP_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_L.BYP_ALT0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_L.BYP_ALT0.NE2END0 origin:050-pip-seed !22_07 !23_07 !24_07 19_06 25_07
INT_L.BYP_ALT0.NL1END0 origin:050-pip-seed !23_07 18_06 22_07 24_07 25_07
INT_L.BYP_ALT0.NN2END0 origin:050-pip-seed !22_07 !23_07 !25_07 19_06 24_07
@ -30,9 +30,9 @@ INT_L.BYP_ALT1.ER1END0 origin:050-pip-seed !22_15 16_15 23_15 24_15 25_15
INT_L.BYP_ALT1.FAN_BOUNCE5 origin:050-pip-seed !23_15 21_15 22_15 24_15 25_15
INT_L.BYP_ALT1.FAN_BOUNCE6 origin:050-pip-seed !22_15 21_15 23_15 24_15 25_15
INT_L.BYP_ALT1.GFAN0 origin:054-pip-fan-alt !22_15 !23_15 !25_15 20_15 24_15
INT_L.BYP_ALT1.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_L.BYP_ALT1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_L.BYP_ALT1.NE2END1 origin:050-pip-seed !22_15 !23_15 !24_15 16_15 25_15
INT_L.BYP_ALT1.NL1END1 origin:050-pip-seed !23_15 18_14 22_15 24_15 25_15
INT_L.BYP_ALT1.NN2END1 origin:050-pip-seed !22_15 !23_15 !25_15 16_15 24_15
@ -54,9 +54,9 @@ INT_L.BYP_ALT2.ER1END2 origin:050-pip-seed !22_39 17_39 23_39 24_39 25_39
INT_L.BYP_ALT2.FAN_BOUNCE1 origin:050-pip-seed !23_39 21_39 22_39 24_39 25_39
INT_L.BYP_ALT2.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_39 21_39 23_39 24_39 25_39
INT_L.BYP_ALT2.GFAN1 origin:054-pip-fan-alt !22_39 !23_39 !25_39 20_39 24_39
INT_L.BYP_ALT2.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_L.BYP_ALT2.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_L.BYP_ALT2.NE2END2 origin:050-pip-seed !22_39 !23_39 !24_39 19_38 25_39
INT_L.BYP_ALT2.NL1END2 origin:050-pip-seed !23_39 18_38 22_39 24_39 25_39
INT_L.BYP_ALT2.NN2END2 origin:050-pip-seed !22_39 !23_39 !25_39 19_38 24_39
@ -78,9 +78,9 @@ INT_L.BYP_ALT3.ER1END2 origin:050-pip-seed !22_47 16_47 23_47 24_47 25_47
INT_L.BYP_ALT3.FAN_BOUNCE3 origin:050-pip-seed !23_47 21_47 22_47 24_47 25_47
INT_L.BYP_ALT3.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_47 21_47 23_47 24_47 25_47
INT_L.BYP_ALT3.GFAN1 origin:054-pip-fan-alt !22_47 !23_47 !25_47 20_47 24_47
INT_L.BYP_ALT3.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_L.BYP_ALT3.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_L.BYP_ALT3.NE2END3 origin:050-pip-seed !22_47 !23_47 !24_47 16_47 25_47
INT_L.BYP_ALT3.NL1BEG_N3 origin:050-pip-seed !23_47 18_46 22_47 24_47 25_47
INT_L.BYP_ALT3.NN2END3 origin:050-pip-seed !22_47 !23_47 !25_47 16_47 24_47
@ -102,9 +102,9 @@ INT_L.BYP_ALT4.ER1END1 origin:050-pip-seed !22_23 17_23 23_23 24_23 25_23
INT_L.BYP_ALT4.FAN_BOUNCE1 origin:050-pip-seed !23_23 21_23 22_23 24_23 25_23
INT_L.BYP_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_23 21_23 23_23 24_23 25_23
INT_L.BYP_ALT4.GFAN0 origin:054-pip-fan-alt !22_23 !23_23 !25_23 20_23 24_23
INT_L.BYP_ALT4.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_L.BYP_ALT4.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_L.BYP_ALT4.NE2END1 origin:050-pip-seed !22_23 !23_23 !24_23 19_22 25_23
INT_L.BYP_ALT4.NL1END1 origin:050-pip-seed !23_23 18_22 22_23 24_23 25_23
INT_L.BYP_ALT4.NN2END1 origin:050-pip-seed !22_23 !23_23 !25_23 19_22 24_23
@ -126,9 +126,9 @@ INT_L.BYP_ALT5.ER1END1 origin:050-pip-seed !22_31 16_31 23_31 24_31 25_31
INT_L.BYP_ALT5.FAN_BOUNCE3 origin:050-pip-seed !23_31 21_31 22_31 24_31 25_31
INT_L.BYP_ALT5.FAN_BOUNCE5 origin:050-pip-seed !22_31 21_31 23_31 24_31 25_31
INT_L.BYP_ALT5.GFAN0 origin:054-pip-fan-alt !22_31 !23_31 !25_31 20_31 24_31
INT_L.BYP_ALT5.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_L.BYP_ALT5.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_L.BYP_ALT5.NE2END2 origin:050-pip-seed !22_31 !23_31 !24_31 16_31 25_31
INT_L.BYP_ALT5.NL1END2 origin:050-pip-seed !23_31 18_30 22_31 24_31 25_31
INT_L.BYP_ALT5.NN2END2 origin:050-pip-seed !22_31 !23_31 !25_31 16_31 24_31
@ -150,8 +150,8 @@ INT_L.BYP_ALT6.ER1END3 origin:050-pip-seed !22_55 17_55 23_55 24_55 25_55
INT_L.BYP_ALT6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_55 21_55 22_55 24_55 25_55
INT_L.BYP_ALT6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_55 21_55 23_55 24_55 25_55
INT_L.BYP_ALT6.GFAN1 origin:054-pip-fan-alt !22_55 !23_55 !25_55 20_55 24_55
INT_L.BYP_ALT6.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_L.BYP_ALT6.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_55 20_55 23_55 24_55 25_55
INT_L.BYP_ALT6.NE2END3 origin:050-pip-seed !22_55 !23_55 !24_55 19_54 25_55
INT_L.BYP_ALT6.NL1BEG_N3 origin:050-pip-seed !23_55 18_54 22_55 24_55 25_55
@ -174,8 +174,8 @@ INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_L.BYP_ALT7.NE2END_S3_0 origin:050-pip-seed !22_63 !23_63 !24_63 16_63 25_63
INT_L.BYP_ALT7.NL1END_S3_0 origin:050-pip-seed !23_63 18_62 22_63 24_63 25_63
@ -373,7 +373,7 @@ INT_L.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_L.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_L.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@ -584,7 +584,7 @@ INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
INT_L.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
INT_L.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
@ -806,9 +806,9 @@ INT_L.IMUX_L0.ER1END_N3_3 origin:050-pip-seed !22_01 18_00 23_01 24_01 25_01
INT_L.IMUX_L0.FAN_BOUNCE2 origin:050-pip-seed !22_01 21_01 23_01 24_01 25_01
INT_L.IMUX_L0.FAN_BOUNCE7 origin:050-pip-seed !23_01 21_01 22_01 24_01 25_01
INT_L.IMUX_L0.GFAN0 origin:049-int-imux-gfan !22_01 !23_01 !25_01 20_01 24_01
INT_L.IMUX_L0.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_L.IMUX_L0.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_L.IMUX_L0.NE2END0 origin:050-pip-seed !22_01 !23_01 !24_01 16_01 25_01
INT_L.IMUX_L0.NL1END0 origin:050-pip-seed !23_01 17_01 22_01 24_01 25_01
INT_L.IMUX_L0.NN2END0 origin:050-pip-seed !22_01 !23_01 !25_01 16_01 24_01
@ -830,9 +830,9 @@ INT_L.IMUX_L1.ER1END0 origin:050-pip-seed !22_09 19_08 23_09 24_09 25_09
INT_L.IMUX_L1.FAN_BOUNCE5 origin:050-pip-seed !23_09 21_09 22_09 24_09 25_09
INT_L.IMUX_L1.FAN_BOUNCE6 origin:050-pip-seed !22_09 21_09 23_09 24_09 25_09
INT_L.IMUX_L1.GFAN0 origin:049-int-imux-gfan !22_09 !23_09 !25_09 20_09 24_09
INT_L.IMUX_L1.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_L.IMUX_L1.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_L.IMUX_L1.NE2END0 origin:050-pip-seed !22_09 !23_09 !24_09 19_08 25_09
INT_L.IMUX_L1.NL1END1 origin:050-pip-seed !23_09 17_09 22_09 24_09 25_09
INT_L.IMUX_L1.NN2END0 origin:050-pip-seed !22_09 !23_09 !25_09 19_08 24_09
@ -854,9 +854,9 @@ INT_L.IMUX_L10.ER1END0 origin:050-pip-seed !23_18 17_18 22_18 24_18 25_18
INT_L.IMUX_L10.FAN_BOUNCE1 origin:050-pip-seed !22_18 20_18 23_18 24_18 25_18
INT_L.IMUX_L10.FAN_BOUNCE7 origin:050-pip-seed !23_18 20_18 22_18 24_18 25_18
INT_L.IMUX_L10.GFAN0 origin:049-int-imux-gfan !22_18 !23_18 !24_18 21_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_L.IMUX_L10.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_L.IMUX_L10.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_L.IMUX_L10.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_L.IMUX_L10.NE2END1 origin:050-pip-seed !22_18 !23_18 !25_18 17_18 24_18
INT_L.IMUX_L10.NL1END1 origin:050-pip-seed !22_18 16_18 23_18 24_18 25_18
INT_L.IMUX_L10.NN2END1 origin:050-pip-seed !22_18 !23_18 !24_18 17_18 25_18
@ -878,9 +878,9 @@ INT_L.IMUX_L11.ER1END1 origin:050-pip-seed !23_26 18_27 22_26 24_26 25_26
INT_L.IMUX_L11.FAN_BOUNCE3 origin:050-pip-seed !22_26 20_26 23_26 24_26 25_26
INT_L.IMUX_L11.FAN_BOUNCE5 origin:050-pip-seed !23_26 20_26 22_26 24_26 25_26
INT_L.IMUX_L11.GFAN0 origin:049-int-imux-gfan !22_26 !23_26 !24_26 21_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_L.IMUX_L11.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_L.IMUX_L11.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_L.IMUX_L11.NE2END1 origin:050-pip-seed !22_26 !23_26 !25_26 16_26 24_26
INT_L.IMUX_L11.NL1END2 origin:050-pip-seed !22_26 16_26 23_26 24_26 25_26
INT_L.IMUX_L11.NN2END1 origin:050-pip-seed !22_26 !23_26 !24_26 16_26 25_26
@ -902,9 +902,9 @@ INT_L.IMUX_L12.ER1END1 origin:050-pip-seed !23_34 17_34 22_34 24_34 25_34
INT_L.IMUX_L12.FAN_BOUNCE1 origin:050-pip-seed !22_34 20_34 23_34 24_34 25_34
INT_L.IMUX_L12.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_34 20_34 22_34 24_34 25_34
INT_L.IMUX_L12.GFAN1 origin:049-int-imux-gfan !22_34 !23_34 !24_34 21_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_L.IMUX_L12.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_L.IMUX_L12.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_L.IMUX_L12.NE2END2 origin:050-pip-seed !22_34 !23_34 !25_34 17_34 24_34
INT_L.IMUX_L12.NL1END2 origin:050-pip-seed !22_34 16_34 23_34 24_34 25_34
INT_L.IMUX_L12.NN2END2 origin:050-pip-seed !22_34 !23_34 !24_34 17_34 25_34
@ -926,9 +926,9 @@ INT_L.IMUX_L13.ER1END2 origin:050-pip-seed !23_42 18_43 22_42 24_42 25_42
INT_L.IMUX_L13.FAN_BOUNCE3 origin:050-pip-seed !22_42 20_42 23_42 24_42 25_42
INT_L.IMUX_L13.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_42 20_42 22_42 24_42 25_42
INT_L.IMUX_L13.GFAN1 origin:049-int-imux-gfan !22_42 !23_42 !24_42 21_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_L.IMUX_L13.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_L.IMUX_L13.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_L.IMUX_L13.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_L.IMUX_L13.NE2END2 origin:050-pip-seed !22_42 !23_42 !25_42 16_42 24_42
INT_L.IMUX_L13.NL1BEG_N3 origin:050-pip-seed !22_42 16_42 23_42 24_42 25_42
INT_L.IMUX_L13.NN2END2 origin:050-pip-seed !22_42 !23_42 !24_42 16_42 25_42
@ -950,9 +950,9 @@ INT_L.IMUX_L14.ER1END2 origin:050-pip-seed !23_50 17_50 22_50 24_50 25_50
INT_L.IMUX_L14.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_50 20_50 23_50 24_50 25_50
INT_L.IMUX_L14.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_50 20_50 22_50 24_50 25_50
INT_L.IMUX_L14.GFAN1 origin:049-int-imux-gfan !22_50 !23_50 !24_50 21_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_50 !23_50 !25_50 21_50 24_50
INT_L.IMUX_L14.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_L.IMUX_L14.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_L.IMUX_L14.NE2END3 origin:050-pip-seed !22_50 !23_50 !25_50 17_50 24_50
INT_L.IMUX_L14.NL1BEG_N3 origin:050-pip-seed !22_50 16_50 23_50 24_50 25_50
INT_L.IMUX_L14.NN2END3 origin:050-pip-seed !22_50 !23_50 !24_50 17_50 25_50
@ -974,9 +974,9 @@ INT_L.IMUX_L15.ER1END3 origin:050-pip-seed !23_58 18_59 22_58 24_58 25_58
INT_L.IMUX_L15.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_58 20_58 23_58 24_58 25_58
INT_L.IMUX_L15.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_58 20_58 22_58 24_58 25_58
INT_L.IMUX_L15.GFAN1 origin:049-int-imux-gfan !22_58 !23_58 !24_58 21_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_58 !23_58 !25_58 21_58 24_58
INT_L.IMUX_L15.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_L.IMUX_L15.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_L.IMUX_L15.NE2END3 origin:050-pip-seed !22_58 !23_58 !25_58 16_58 24_58
INT_L.IMUX_L15.NL1END_S3_0 origin:050-pip-seed !22_58 16_58 23_58 24_58 25_58
INT_L.IMUX_L15.NN2END3 origin:050-pip-seed !22_58 !23_58 !24_58 16_58 25_58
@ -998,9 +998,9 @@ INT_L.IMUX_L16.ER1END_N3_3 origin:050-pip-seed !22_03 19_02 23_03 24_03 25_03
INT_L.IMUX_L16.FAN_BOUNCE2 origin:050-pip-seed !22_03 21_03 23_03 24_03 25_03
INT_L.IMUX_L16.FAN_BOUNCE7 origin:050-pip-seed !23_03 21_03 22_03 24_03 25_03
INT_L.IMUX_L16.GFAN0 origin:049-int-imux-gfan !22_03 !23_03 !25_03 20_03 24_03
INT_L.IMUX_L16.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_L.IMUX_L16.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_L.IMUX_L16.NE2END0 origin:050-pip-seed !22_03 !23_03 !24_03 19_02 25_03
INT_L.IMUX_L16.NL1END0 origin:050-pip-seed !23_03 18_02 22_03 24_03 25_03
INT_L.IMUX_L16.NN2END0 origin:050-pip-seed !22_03 !23_03 !25_03 19_02 24_03
@ -1022,9 +1022,9 @@ INT_L.IMUX_L17.ER1END0 origin:050-pip-seed !22_11 16_11 23_11 24_11 25_11
INT_L.IMUX_L17.FAN_BOUNCE5 origin:050-pip-seed !23_11 21_11 22_11 24_11 25_11
INT_L.IMUX_L17.FAN_BOUNCE6 origin:050-pip-seed !22_11 21_11 23_11 24_11 25_11
INT_L.IMUX_L17.GFAN0 origin:049-int-imux-gfan !22_11 !23_11 !25_11 20_11 24_11
INT_L.IMUX_L17.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_L.IMUX_L17.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_L.IMUX_L17.NE2END0 origin:050-pip-seed !22_11 !23_11 !24_11 18_10 25_11
INT_L.IMUX_L17.NL1END1 origin:050-pip-seed !23_11 18_10 22_11 24_11 25_11
INT_L.IMUX_L17.NN2END0 origin:050-pip-seed !22_11 !23_11 !25_11 18_10 24_11
@ -1046,9 +1046,9 @@ INT_L.IMUX_L18.ER1END0 origin:050-pip-seed !22_19 19_18 23_19 24_19 25_19
INT_L.IMUX_L18.FAN_BOUNCE1 origin:050-pip-seed !23_19 21_19 22_19 24_19 25_19
INT_L.IMUX_L18.FAN_BOUNCE7 origin:050-pip-seed !22_19 21_19 23_19 24_19 25_19
INT_L.IMUX_L18.GFAN0 origin:049-int-imux-gfan !22_19 !23_19 !25_19 20_19 24_19
INT_L.IMUX_L18.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_L.IMUX_L18.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_L.IMUX_L18.NE2END1 origin:050-pip-seed !22_19 !23_19 !24_19 19_18 25_19
INT_L.IMUX_L18.NL1END1 origin:050-pip-seed !23_19 18_18 22_19 24_19 25_19
INT_L.IMUX_L18.NN2END1 origin:050-pip-seed !22_19 !23_19 !25_19 19_18 24_19
@ -1070,9 +1070,9 @@ INT_L.IMUX_L19.ER1END1 origin:050-pip-seed !22_27 16_27 23_27 24_27 25_27
INT_L.IMUX_L19.FAN_BOUNCE3 origin:050-pip-seed !23_27 21_27 22_27 24_27 25_27
INT_L.IMUX_L19.FAN_BOUNCE5 origin:050-pip-seed !22_27 21_27 23_27 24_27 25_27
INT_L.IMUX_L19.GFAN0 origin:049-int-imux-gfan !22_27 !23_27 !25_27 20_27 24_27
INT_L.IMUX_L19.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_L.IMUX_L19.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_L.IMUX_L19.NE2END1 origin:050-pip-seed !22_27 !23_27 !24_27 18_26 25_27
INT_L.IMUX_L19.NL1END2 origin:050-pip-seed !23_27 18_26 22_27 24_27 25_27
INT_L.IMUX_L19.NN2END1 origin:050-pip-seed !22_27 !23_27 !25_27 18_26 24_27
@ -1094,9 +1094,9 @@ INT_L.IMUX_L2.ER1END0 origin:050-pip-seed !22_17 18_16 23_17 24_17 25_17
INT_L.IMUX_L2.FAN_BOUNCE1 origin:050-pip-seed !23_17 21_17 22_17 24_17 25_17
INT_L.IMUX_L2.FAN_BOUNCE7 origin:050-pip-seed !22_17 21_17 23_17 24_17 25_17
INT_L.IMUX_L2.GFAN0 origin:049-int-imux-gfan !22_17 !23_17 !25_17 20_17 24_17
INT_L.IMUX_L2.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_L.IMUX_L2.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_L.IMUX_L2.NE2END1 origin:050-pip-seed !22_17 !23_17 !24_17 16_17 25_17
INT_L.IMUX_L2.NL1END1 origin:050-pip-seed !23_17 17_17 22_17 24_17 25_17
INT_L.IMUX_L2.NN2END1 origin:050-pip-seed !22_17 !23_17 !25_17 16_17 24_17
@ -1118,9 +1118,9 @@ INT_L.IMUX_L20.ER1END1 origin:050-pip-seed !22_35 19_34 23_35 24_35 25_35
INT_L.IMUX_L20.FAN_BOUNCE1 origin:050-pip-seed !23_35 21_35 22_35 24_35 25_35
INT_L.IMUX_L20.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_35 21_35 23_35 24_35 25_35
INT_L.IMUX_L20.GFAN1 origin:049-int-imux-gfan !22_35 !23_35 !25_35 20_35 24_35
INT_L.IMUX_L20.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_L.IMUX_L20.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_L.IMUX_L20.NE2END2 origin:050-pip-seed !22_35 !23_35 !24_35 19_34 25_35
INT_L.IMUX_L20.NL1END2 origin:050-pip-seed !23_35 18_34 22_35 24_35 25_35
INT_L.IMUX_L20.NN2END2 origin:050-pip-seed !22_35 !23_35 !25_35 19_34 24_35
@ -1143,8 +1143,8 @@ INT_L.IMUX_L21.FAN_BOUNCE3 origin:050-pip-seed !23_43 21_43 22_43 24_43 25_43
INT_L.IMUX_L21.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_43 21_43 23_43 24_43 25_43
INT_L.IMUX_L21.GFAN1 origin:049-int-imux-gfan !22_43 !23_43 !25_43 20_43 24_43
INT_L.IMUX_L21.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_43 20_43 22_43 24_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_L.IMUX_L21.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_L.IMUX_L21.NE2END2 origin:050-pip-seed !22_43 !23_43 !24_43 18_42 25_43
INT_L.IMUX_L21.NL1BEG_N3 origin:050-pip-seed !23_43 18_42 22_43 24_43 25_43
INT_L.IMUX_L21.NN2END2 origin:050-pip-seed !22_43 !23_43 !25_43 18_42 24_43
@ -1166,9 +1166,9 @@ INT_L.IMUX_L22.ER1END2 origin:050-pip-seed !22_51 19_50 23_51 24_51 25_51
INT_L.IMUX_L22.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_51 21_51 22_51 24_51 25_51
INT_L.IMUX_L22.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_51 21_51 23_51 24_51 25_51
INT_L.IMUX_L22.GFAN1 origin:049-int-imux-gfan !22_51 !23_51 !25_51 20_51 24_51
INT_L.IMUX_L22.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_L.IMUX_L22.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_L.IMUX_L22.NE2END3 origin:050-pip-seed !22_51 !23_51 !24_51 19_50 25_51
INT_L.IMUX_L22.NL1BEG_N3 origin:050-pip-seed !23_51 18_50 22_51 24_51 25_51
INT_L.IMUX_L22.NN2END3 origin:050-pip-seed !22_51 !23_51 !25_51 19_50 24_51
@ -1190,9 +1190,9 @@ INT_L.IMUX_L23.ER1END3 origin:050-pip-seed !22_59 16_59 23_59 24_59 25_59
INT_L.IMUX_L23.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_59 21_59 22_59 24_59 25_59
INT_L.IMUX_L23.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_59 21_59 23_59 24_59 25_59
INT_L.IMUX_L23.GFAN1 origin:049-int-imux-gfan !22_59 !23_59 !25_59 20_59 24_59
INT_L.IMUX_L23.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_L.IMUX_L23.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_L.IMUX_L23.NE2END3 origin:050-pip-seed !22_59 !23_59 !24_59 18_58 25_59
INT_L.IMUX_L23.NL1END_S3_0 origin:050-pip-seed !23_59 18_58 22_59 24_59 25_59
INT_L.IMUX_L23.NN2END3 origin:050-pip-seed !22_59 !23_59 !25_59 18_58 24_59
@ -1214,9 +1214,9 @@ INT_L.IMUX_L24.ER1END0 origin:050-pip-seed !23_04 18_05 22_04 24_04 25_04
INT_L.IMUX_L24.FAN_BOUNCE2 origin:050-pip-seed !23_04 20_04 22_04 24_04 25_04
INT_L.IMUX_L24.FAN_BOUNCE7 origin:050-pip-seed !22_04 20_04 23_04 24_04 25_04
INT_L.IMUX_L24.GFAN0 origin:049-int-imux-gfan !22_04 !23_04 !24_04 21_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_L.IMUX_L24.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_L.IMUX_L24.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_L.IMUX_L24.NE2END0 origin:050-pip-seed !22_04 !23_04 !25_04 18_05 24_04
INT_L.IMUX_L24.NL1END0 origin:050-pip-seed !22_04 19_05 23_04 24_04 25_04
INT_L.IMUX_L24.NN2END0 origin:050-pip-seed !22_04 !23_04 !24_04 18_05 25_04
@ -1238,9 +1238,9 @@ INT_L.IMUX_L25.ER1END0 origin:050-pip-seed !23_12 17_12 22_12 24_12 25_12
INT_L.IMUX_L25.FAN_BOUNCE5 origin:050-pip-seed !22_12 20_12 23_12 24_12 25_12
INT_L.IMUX_L25.FAN_BOUNCE6 origin:050-pip-seed !23_12 20_12 22_12 24_12 25_12
INT_L.IMUX_L25.GFAN0 origin:049-int-imux-gfan !22_12 !23_12 !24_12 21_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_L.IMUX_L25.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_L.IMUX_L25.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_L.IMUX_L25.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_L.IMUX_L25.NE2END1 origin:050-pip-seed !22_12 !23_12 !25_12 19_13 24_12
INT_L.IMUX_L25.NL1END1 origin:050-pip-seed !22_12 19_13 23_12 24_12 25_12
INT_L.IMUX_L25.NN2END1 origin:050-pip-seed !22_12 !23_12 !24_12 19_13 25_12
@ -1262,8 +1262,8 @@ INT_L.IMUX_L26.ER1END1 origin:050-pip-seed !23_20 18_21 22_20 24_20 25_20
INT_L.IMUX_L26.FAN_BOUNCE1 origin:050-pip-seed !22_20 20_20 23_20 24_20 25_20
INT_L.IMUX_L26.FAN_BOUNCE7 origin:050-pip-seed !23_20 20_20 22_20 24_20 25_20
INT_L.IMUX_L26.GFAN0 origin:049-int-imux-gfan !22_20 !23_20 !24_20 21_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_L.IMUX_L26.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_L.IMUX_L26.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_L.IMUX_L26.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_20 21_20 23_20 24_20 25_20
INT_L.IMUX_L26.NE2END1 origin:050-pip-seed !22_20 !23_20 !25_20 18_21 24_20
INT_L.IMUX_L26.NL1END1 origin:050-pip-seed !22_20 19_21 23_20 24_20 25_20
@ -1286,9 +1286,9 @@ INT_L.IMUX_L27.ER1END1 origin:050-pip-seed !23_28 17_28 22_28 24_28 25_28
INT_L.IMUX_L27.FAN_BOUNCE3 origin:050-pip-seed !22_28 20_28 23_28 24_28 25_28
INT_L.IMUX_L27.FAN_BOUNCE5 origin:050-pip-seed !23_28 20_28 22_28 24_28 25_28
INT_L.IMUX_L27.GFAN0 origin:049-int-imux-gfan !22_28 !23_28 !24_28 21_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_28 21_28 23_28 24_28 25_28
INT_L.IMUX_L27.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_L.IMUX_L27.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_L.IMUX_L27.NE2END2 origin:050-pip-seed !22_28 !23_28 !25_28 19_29 24_28
INT_L.IMUX_L27.NL1END2 origin:050-pip-seed !22_28 19_29 23_28 24_28 25_28
INT_L.IMUX_L27.NN2END2 origin:050-pip-seed !22_28 !23_28 !24_28 19_29 25_28
@ -1311,8 +1311,8 @@ INT_L.IMUX_L28.FAN_BOUNCE1 origin:050-pip-seed !22_36 20_36 23_36 24_36 25_36
INT_L.IMUX_L28.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_36 20_36 22_36 24_36 25_36
INT_L.IMUX_L28.GFAN1 origin:049-int-imux-gfan !22_36 !23_36 !24_36 21_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_36 21_36 23_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_L.IMUX_L28.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_L.IMUX_L28.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_L.IMUX_L28.NE2END2 origin:050-pip-seed !22_36 !23_36 !25_36 18_37 24_36
INT_L.IMUX_L28.NL1END2 origin:050-pip-seed !22_36 19_37 23_36 24_36 25_36
INT_L.IMUX_L28.NN2END2 origin:050-pip-seed !22_36 !23_36 !24_36 18_37 25_36
@ -1334,9 +1334,9 @@ INT_L.IMUX_L29.ER1END2 origin:050-pip-seed !23_44 17_44 22_44 24_44 25_44
INT_L.IMUX_L29.FAN_BOUNCE3 origin:050-pip-seed !22_44 20_44 23_44 24_44 25_44
INT_L.IMUX_L29.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_44 20_44 22_44 24_44 25_44
INT_L.IMUX_L29.GFAN1 origin:049-int-imux-gfan !22_44 !23_44 !24_44 21_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_L.IMUX_L29.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_L.IMUX_L29.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_L.IMUX_L29.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_L.IMUX_L29.NE2END3 origin:050-pip-seed !22_44 !23_44 !25_44 19_45 24_44
INT_L.IMUX_L29.NL1BEG_N3 origin:050-pip-seed !22_44 19_45 23_44 24_44 25_44
INT_L.IMUX_L29.NN2END3 origin:050-pip-seed !22_44 !23_44 !24_44 19_45 25_44
@ -1358,9 +1358,9 @@ INT_L.IMUX_L3.ER1END1 origin:050-pip-seed !22_25 19_24 23_25 24_25 25_25
INT_L.IMUX_L3.FAN_BOUNCE3 origin:050-pip-seed !23_25 21_25 22_25 24_25 25_25
INT_L.IMUX_L3.FAN_BOUNCE5 origin:050-pip-seed !22_25 21_25 23_25 24_25 25_25
INT_L.IMUX_L3.GFAN0 origin:049-int-imux-gfan !22_25 !23_25 !25_25 20_25 24_25
INT_L.IMUX_L3.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_L.IMUX_L3.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_L.IMUX_L3.NE2END1 origin:050-pip-seed !22_25 !23_25 !24_25 19_24 25_25
INT_L.IMUX_L3.NL1END2 origin:050-pip-seed !23_25 17_25 22_25 24_25 25_25
INT_L.IMUX_L3.NN2END1 origin:050-pip-seed !22_25 !23_25 !25_25 19_24 24_25
@ -1382,9 +1382,9 @@ INT_L.IMUX_L30.ER1END3 origin:050-pip-seed !23_52 18_53 22_52 24_52 25_52
INT_L.IMUX_L30.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_52 20_52 23_52 24_52 25_52
INT_L.IMUX_L30.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_52 20_52 22_52 24_52 25_52
INT_L.IMUX_L30.GFAN1 origin:049-int-imux-gfan !22_52 !23_52 !24_52 21_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_L.IMUX_L30.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_L.IMUX_L30.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_L.IMUX_L30.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_L.IMUX_L30.NE2END3 origin:050-pip-seed !22_52 !23_52 !25_52 18_53 24_52
INT_L.IMUX_L30.NL1BEG_N3 origin:050-pip-seed !22_52 19_53 23_52 24_52 25_52
INT_L.IMUX_L30.NN2END3 origin:050-pip-seed !22_52 !23_52 !24_52 18_53 25_52
@ -1406,9 +1406,9 @@ INT_L.IMUX_L31.ER1END3 origin:050-pip-seed !23_60 17_60 22_60 24_60 25_60
INT_L.IMUX_L31.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_60 20_60 23_60 24_60 25_60
INT_L.IMUX_L31.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_60 20_60 22_60 24_60 25_60
INT_L.IMUX_L31.GFAN1 origin:049-int-imux-gfan !22_60 !23_60 !24_60 21_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_L.IMUX_L31.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_L.IMUX_L31.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_L.IMUX_L31.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_L.IMUX_L31.NE2END_S3_0 origin:050-pip-seed !22_60 !23_60 !25_60 19_61 24_60
INT_L.IMUX_L31.NL1END_S3_0 origin:050-pip-seed !22_60 19_61 23_60 24_60 25_60
INT_L.IMUX_L31.NN2END_S2_0 origin:050-pip-seed !22_60 !23_60 !24_60 19_61 25_60
@ -1430,8 +1430,8 @@ INT_L.IMUX_L32.ER1END0 origin:050-pip-seed !22_05 16_05 23_05 24_05 25_05
INT_L.IMUX_L32.FAN_BOUNCE2 origin:050-pip-seed !22_05 21_05 23_05 24_05 25_05
INT_L.IMUX_L32.FAN_BOUNCE7 origin:050-pip-seed !23_05 21_05 22_05 24_05 25_05
INT_L.IMUX_L32.GFAN0 origin:049-int-imux-gfan !22_05 !23_05 !25_05 20_05 24_05
INT_L.IMUX_L32.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_L.IMUX_L32.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_05 !23_05 !24_05 20_05 25_05
INT_L.IMUX_L32.NE2END0 origin:050-pip-seed !22_05 !23_05 !24_05 16_05 25_05
INT_L.IMUX_L32.NL1END0 origin:050-pip-seed !23_05 17_05 22_05 24_05 25_05
@ -1455,8 +1455,8 @@ INT_L.IMUX_L33.FAN_BOUNCE5 origin:050-pip-seed !23_13 21_13 22_13 24_13 25_13
INT_L.IMUX_L33.FAN_BOUNCE6 origin:050-pip-seed !22_13 21_13 23_13 24_13 25_13
INT_L.IMUX_L33.GFAN0 origin:049-int-imux-gfan !22_13 !23_13 !25_13 20_13 24_13
INT_L.IMUX_L33.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_13 !23_13 !24_13 20_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_L.IMUX_L33.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_L.IMUX_L33.NE2END1 origin:050-pip-seed !22_13 !23_13 !24_13 17_13 25_13
INT_L.IMUX_L33.NL1END1 origin:050-pip-seed !23_13 17_13 22_13 24_13 25_13
INT_L.IMUX_L33.NN2END1 origin:050-pip-seed !22_13 !23_13 !25_13 17_13 24_13
@ -1478,9 +1478,9 @@ INT_L.IMUX_L34.ER1END1 origin:050-pip-seed !22_21 16_21 23_21 24_21 25_21
INT_L.IMUX_L34.FAN_BOUNCE1 origin:050-pip-seed !23_21 21_21 22_21 24_21 25_21
INT_L.IMUX_L34.FAN_BOUNCE7 origin:050-pip-seed !22_21 21_21 23_21 24_21 25_21
INT_L.IMUX_L34.GFAN0 origin:049-int-imux-gfan !22_21 !23_21 !25_21 20_21 24_21
INT_L.IMUX_L34.LOGIC_OUTS_L19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_L.IMUX_L34.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_L.IMUX_L34.NE2END1 origin:050-pip-seed !22_21 !23_21 !24_21 16_21 25_21
INT_L.IMUX_L34.NL1END1 origin:050-pip-seed !23_21 17_21 22_21 24_21 25_21
INT_L.IMUX_L34.NN2END1 origin:050-pip-seed !22_21 !23_21 !25_21 16_21 24_21
@ -1502,9 +1502,9 @@ INT_L.IMUX_L35.ER1END1 origin:050-pip-seed !22_29 19_28 23_29 24_29 25_29
INT_L.IMUX_L35.FAN_BOUNCE3 origin:050-pip-seed !23_29 21_29 22_29 24_29 25_29
INT_L.IMUX_L35.FAN_BOUNCE5 origin:050-pip-seed !22_29 21_29 23_29 24_29 25_29
INT_L.IMUX_L35.GFAN0 origin:049-int-imux-gfan !22_29 !23_29 !25_29 20_29 24_29
INT_L.IMUX_L35.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_L.IMUX_L35.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_L.IMUX_L35.NE2END2 origin:050-pip-seed !22_29 !23_29 !24_29 17_29 25_29
INT_L.IMUX_L35.NL1END2 origin:050-pip-seed !23_29 17_29 22_29 24_29 25_29
INT_L.IMUX_L35.NN2END2 origin:050-pip-seed !22_29 !23_29 !25_29 17_29 24_29
@ -1526,9 +1526,9 @@ INT_L.IMUX_L36.ER1END2 origin:050-pip-seed !22_37 16_37 23_37 24_37 25_37
INT_L.IMUX_L36.FAN_BOUNCE1 origin:050-pip-seed !23_37 21_37 22_37 24_37 25_37
INT_L.IMUX_L36.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_37 21_37 23_37 24_37 25_37
INT_L.IMUX_L36.GFAN1 origin:049-int-imux-gfan !22_37 !23_37 !25_37 20_37 24_37
INT_L.IMUX_L36.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_L.IMUX_L36.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_L.IMUX_L36.NE2END2 origin:050-pip-seed !22_37 !23_37 !24_37 16_37 25_37
INT_L.IMUX_L36.NL1END2 origin:050-pip-seed !23_37 17_37 22_37 24_37 25_37
INT_L.IMUX_L36.NN2END2 origin:050-pip-seed !22_37 !23_37 !25_37 16_37 24_37
@ -1550,9 +1550,9 @@ INT_L.IMUX_L37.ER1END2 origin:050-pip-seed !22_45 19_44 23_45 24_45 25_45
INT_L.IMUX_L37.FAN_BOUNCE3 origin:050-pip-seed !23_45 21_45 22_45 24_45 25_45
INT_L.IMUX_L37.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_45 21_45 23_45 24_45 25_45
INT_L.IMUX_L37.GFAN1 origin:049-int-imux-gfan !22_45 !23_45 !25_45 20_45 24_45
INT_L.IMUX_L37.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_L.IMUX_L37.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_L.IMUX_L37.NE2END3 origin:050-pip-seed !22_45 !23_45 !24_45 17_45 25_45
INT_L.IMUX_L37.NL1BEG_N3 origin:050-pip-seed !23_45 17_45 22_45 24_45 25_45
INT_L.IMUX_L37.NN2END3 origin:050-pip-seed !22_45 !23_45 !25_45 17_45 24_45
@ -1574,9 +1574,9 @@ INT_L.IMUX_L38.ER1END3 origin:050-pip-seed !22_53 16_53 23_53 24_53 25_53
INT_L.IMUX_L38.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_53 21_53 22_53 24_53 25_53
INT_L.IMUX_L38.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_53 21_53 23_53 24_53 25_53
INT_L.IMUX_L38.GFAN1 origin:049-int-imux-gfan !22_53 !23_53 !25_53 20_53 24_53
INT_L.IMUX_L38.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_L.IMUX_L38.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_L.IMUX_L38.NE2END3 origin:050-pip-seed !22_53 !23_53 !24_53 16_53 25_53
INT_L.IMUX_L38.NL1BEG_N3 origin:050-pip-seed !23_53 17_53 22_53 24_53 25_53
INT_L.IMUX_L38.NN2END3 origin:050-pip-seed !22_53 !23_53 !25_53 16_53 24_53
@ -1598,9 +1598,9 @@ INT_L.IMUX_L39.ER1END3 origin:050-pip-seed !22_61 19_60 23_61 24_61 25_61
INT_L.IMUX_L39.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_61 21_61 22_61 24_61 25_61
INT_L.IMUX_L39.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_61 21_61 23_61 24_61 25_61
INT_L.IMUX_L39.GFAN1 origin:049-int-imux-gfan !22_61 !23_61 !25_61 20_61 24_61
INT_L.IMUX_L39.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_L.IMUX_L39.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_L.IMUX_L39.NE2END_S3_0 origin:050-pip-seed !22_61 !23_61 !24_61 17_61 25_61
INT_L.IMUX_L39.NL1END_S3_0 origin:050-pip-seed !23_61 17_61 22_61 24_61 25_61
INT_L.IMUX_L39.NN2END_S2_0 origin:050-pip-seed !22_61 !23_61 !25_61 17_61 24_61
@ -1622,9 +1622,9 @@ INT_L.IMUX_L4.ER1END1 origin:050-pip-seed !22_33 18_32 23_33 24_33 25_33
INT_L.IMUX_L4.FAN_BOUNCE1 origin:050-pip-seed !23_33 21_33 22_33 24_33 25_33
INT_L.IMUX_L4.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_33 21_33 23_33 24_33 25_33
INT_L.IMUX_L4.GFAN1 origin:049-int-imux-gfan !22_33 !23_33 !25_33 20_33 24_33
INT_L.IMUX_L4.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_L.IMUX_L4.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_L.IMUX_L4.NE2END2 origin:050-pip-seed !22_33 !23_33 !24_33 16_33 25_33
INT_L.IMUX_L4.NL1END2 origin:050-pip-seed !23_33 17_33 22_33 24_33 25_33
INT_L.IMUX_L4.NN2END2 origin:050-pip-seed !22_33 !23_33 !25_33 16_33 24_33
@ -1646,9 +1646,9 @@ INT_L.IMUX_L40.ER1END0 origin:050-pip-seed !23_06 19_07 22_06 24_06 25_06
INT_L.IMUX_L40.FAN_BOUNCE2 origin:050-pip-seed !23_06 20_06 22_06 24_06 25_06
INT_L.IMUX_L40.FAN_BOUNCE7 origin:050-pip-seed !22_06 20_06 23_06 24_06 25_06
INT_L.IMUX_L40.GFAN0 origin:049-int-imux-gfan !22_06 !23_06 !24_06 21_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L12 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_L.IMUX_L40.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_L.IMUX_L40.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_L.IMUX_L40.NE2END0 origin:050-pip-seed !22_06 !23_06 !25_06 17_06 24_06
INT_L.IMUX_L40.NL1END0 origin:050-pip-seed !22_06 16_06 23_06 24_06 25_06
INT_L.IMUX_L40.NN2END0 origin:050-pip-seed !22_06 !23_06 !24_06 17_06 25_06
@ -1670,9 +1670,9 @@ INT_L.IMUX_L41.ER1END0 origin:050-pip-seed !23_14 18_15 22_14 24_14 25_14
INT_L.IMUX_L41.FAN_BOUNCE5 origin:050-pip-seed !22_14 20_14 23_14 24_14 25_14
INT_L.IMUX_L41.FAN_BOUNCE6 origin:050-pip-seed !23_14 20_14 22_14 24_14 25_14
INT_L.IMUX_L41.GFAN0 origin:049-int-imux-gfan !22_14 !23_14 !24_14 21_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_L.IMUX_L41.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L8 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_L.IMUX_L41.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_L.IMUX_L41.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_L.IMUX_L41.NE2END1 origin:050-pip-seed !22_14 !23_14 !25_14 18_15 24_14
INT_L.IMUX_L41.NL1END1 origin:050-pip-seed !22_14 16_14 23_14 24_14 25_14
INT_L.IMUX_L41.NN2END1 origin:050-pip-seed !22_14 !23_14 !24_14 18_15 25_14
@ -1695,8 +1695,8 @@ INT_L.IMUX_L42.FAN_BOUNCE1 origin:050-pip-seed !22_22 20_22 23_22 24_22 25_22
INT_L.IMUX_L42.FAN_BOUNCE7 origin:050-pip-seed !23_22 20_22 22_22 24_22 25_22
INT_L.IMUX_L42.GFAN0 origin:049-int-imux-gfan !22_22 !23_22 !24_22 21_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 21_22 24_22
INT_L.IMUX_L42.LOGIC_OUTS_L5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L9 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L5 origin:051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_L.IMUX_L42.LOGIC_OUTS_L9 origin:051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_L.IMUX_L42.NE2END1 origin:050-pip-seed !22_22 !23_22 !25_22 17_22 24_22
INT_L.IMUX_L42.NL1END1 origin:050-pip-seed !22_22 16_22 23_22 24_22 25_22
INT_L.IMUX_L42.NN2END1 origin:050-pip-seed !22_22 !23_22 !24_22 17_22 25_22
@ -1718,8 +1718,8 @@ INT_L.IMUX_L43.ER1END1 origin:050-pip-seed !23_30 18_31 22_30 24_30 25_30
INT_L.IMUX_L43.FAN_BOUNCE3 origin:050-pip-seed !22_30 20_30 23_30 24_30 25_30
INT_L.IMUX_L43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
INT_L.IMUX_L43.GFAN0 origin:049-int-imux-gfan !22_30 !23_30 !24_30 21_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L13 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_L.IMUX_L43.LOGIC_OUTS_L23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
INT_L.IMUX_L43.NE2END2 origin:050-pip-seed !22_30 !23_30 !25_30 18_31 24_30
INT_L.IMUX_L43.NL1END2 origin:050-pip-seed !22_30 16_30 23_30 24_30 25_30
@ -1742,9 +1742,9 @@ INT_L.IMUX_L44.ER1END2 origin:050-pip-seed !23_38 19_39 22_38 24_38 25_38
INT_L.IMUX_L44.FAN_BOUNCE1 origin:050-pip-seed !22_38 20_38 23_38 24_38 25_38
INT_L.IMUX_L44.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_38 20_38 22_38 24_38 25_38
INT_L.IMUX_L44.GFAN1 origin:049-int-imux-gfan !22_38 !23_38 !24_38 21_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L14 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_L.IMUX_L44.LOGIC_OUTS_L14 origin:051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L2 origin:051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_L.IMUX_L44.LOGIC_OUTS_L20 origin:051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_L.IMUX_L44.NE2END2 origin:050-pip-seed !22_38 !23_38 !25_38 17_38 24_38
INT_L.IMUX_L44.NL1END2 origin:050-pip-seed !22_38 16_38 23_38 24_38 25_38
INT_L.IMUX_L44.NN2END2 origin:050-pip-seed !22_38 !23_38 !24_38 17_38 25_38
@ -1766,9 +1766,9 @@ INT_L.IMUX_L45.ER1END2 origin:050-pip-seed !23_46 18_47 22_46 24_46 25_46
INT_L.IMUX_L45.FAN_BOUNCE3 origin:050-pip-seed !22_46 20_46 23_46 24_46 25_46
INT_L.IMUX_L45.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_46 20_46 22_46 24_46 25_46
INT_L.IMUX_L45.GFAN1 origin:049-int-imux-gfan !22_46 !23_46 !24_46 21_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_L.IMUX_L45.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_L.IMUX_L45.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_L.IMUX_L45.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_L.IMUX_L45.NE2END3 origin:050-pip-seed !22_46 !23_46 !25_46 18_47 24_46
INT_L.IMUX_L45.NL1BEG_N3 origin:050-pip-seed !22_46 16_46 23_46 24_46 25_46
INT_L.IMUX_L45.NN2END3 origin:050-pip-seed !22_46 !23_46 !24_46 18_47 25_46
@ -1791,8 +1791,8 @@ INT_L.IMUX_L46.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_54 20_54 23_54 24_54 25_5
INT_L.IMUX_L46.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_54 20_54 22_54 24_54 25_54
INT_L.IMUX_L46.GFAN1 origin:049-int-imux-gfan !22_54 !23_54 !24_54 21_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !22_54 21_54 23_54 24_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_L.IMUX_L46.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_L.IMUX_L46.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_L.IMUX_L46.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_L.IMUX_L46.NE2END3 origin:050-pip-seed !22_54 !23_54 !25_54 17_54 24_54
INT_L.IMUX_L46.NL1BEG_N3 origin:050-pip-seed !22_54 16_54 23_54 24_54 25_54
INT_L.IMUX_L46.NN2END3 origin:050-pip-seed !22_54 !23_54 !24_54 17_54 25_54
@ -1815,8 +1815,8 @@ INT_L.IMUX_L47.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_62 20_62 23_62 24_62 25_6
INT_L.IMUX_L47.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_62 20_62 22_62 24_62 25_62
INT_L.IMUX_L47.GFAN1 origin:049-int-imux-gfan !22_62 !23_62 !24_62 21_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !22_62 21_62 23_62 24_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_L.IMUX_L47.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_L.IMUX_L47.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_L.IMUX_L47.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_L.IMUX_L47.NE2END_S3_0 origin:050-pip-seed !22_62 !23_62 !25_62 18_63 24_62
INT_L.IMUX_L47.NL1END_S3_0 origin:050-pip-seed !22_62 16_62 23_62 24_62 25_62
INT_L.IMUX_L47.NN2END_S2_0 origin:050-pip-seed !22_62 !23_62 !24_62 18_63 25_62
@ -1838,9 +1838,9 @@ INT_L.IMUX_L5.ER1END2 origin:050-pip-seed !22_41 19_40 23_41 24_41 25_41
INT_L.IMUX_L5.FAN_BOUNCE3 origin:050-pip-seed !23_41 21_41 22_41 24_41 25_41
INT_L.IMUX_L5.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_41 21_41 23_41 24_41 25_41
INT_L.IMUX_L5.GFAN1 origin:049-int-imux-gfan !22_41 !23_41 !25_41 20_41 24_41
INT_L.IMUX_L5.LOGIC_OUTS_L10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L10 origin:051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L16 origin:051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_L.IMUX_L5.LOGIC_OUTS_L6 origin:051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_L.IMUX_L5.NE2END2 origin:050-pip-seed !22_41 !23_41 !24_41 19_40 25_41
INT_L.IMUX_L5.NL1BEG_N3 origin:050-pip-seed !23_41 17_41 22_41 24_41 25_41
INT_L.IMUX_L5.NN2END2 origin:050-pip-seed !22_41 !23_41 !25_41 19_40 24_41
@ -1862,9 +1862,9 @@ INT_L.IMUX_L6.ER1END2 origin:050-pip-seed !22_49 18_48 23_49 24_49 25_49
INT_L.IMUX_L6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_49 21_49 22_49 24_49 25_49
INT_L.IMUX_L6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_49 21_49 23_49 24_49 25_49
INT_L.IMUX_L6.GFAN1 origin:049-int-imux-gfan !22_49 !23_49 !25_49 20_49 24_49
INT_L.IMUX_L6.LOGIC_OUTS_L11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L11 origin:051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L17 origin:051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_L.IMUX_L6.LOGIC_OUTS_L7 origin:051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_L.IMUX_L6.NE2END3 origin:050-pip-seed !22_49 !23_49 !24_49 16_49 25_49
INT_L.IMUX_L6.NL1BEG_N3 origin:050-pip-seed !23_49 17_49 22_49 24_49 25_49
INT_L.IMUX_L6.NN2END3 origin:050-pip-seed !22_49 !23_49 !25_49 16_49 24_49
@ -1886,9 +1886,9 @@ INT_L.IMUX_L7.ER1END3 origin:050-pip-seed !22_57 19_56 23_57 24_57 25_57
INT_L.IMUX_L7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_57 21_57 22_57 24_57 25_57
INT_L.IMUX_L7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_57 21_57 23_57 24_57 25_57
INT_L.IMUX_L7.GFAN1 origin:049-int-imux-gfan !22_57 !23_57 !25_57 20_57 24_57
INT_L.IMUX_L7.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_L.IMUX_L7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_L.IMUX_L7.NE2END3 origin:050-pip-seed !22_57 !23_57 !24_57 19_56 25_57
INT_L.IMUX_L7.NL1END_S3_0 origin:050-pip-seed !23_57 17_57 22_57 24_57 25_57
INT_L.IMUX_L7.NN2END3 origin:050-pip-seed !22_57 !23_57 !25_57 19_56 24_57
@ -1910,9 +1910,9 @@ INT_L.IMUX_L8.ER1END_N3_3 origin:050-pip-seed !23_02 17_02 22_02 24_02 25_02
INT_L.IMUX_L8.FAN_BOUNCE2 origin:050-pip-seed !23_02 20_02 22_02 24_02 25_02
INT_L.IMUX_L8.FAN_BOUNCE7 origin:050-pip-seed !22_02 20_02 23_02 24_02 25_02
INT_L.IMUX_L8.GFAN0 origin:049-int-imux-gfan !22_02 !23_02 !24_02 21_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L0 origin:051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L12 origin:051-pip-imuxlout-bypalts !22_02 21_02 23_02 24_02 25_02
INT_L.IMUX_L8.LOGIC_OUTS_L22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_L.IMUX_L8.LOGIC_OUTS_L22 origin:051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_L.IMUX_L8.NE2END0 origin:050-pip-seed !22_02 !23_02 !25_02 17_02 24_02
INT_L.IMUX_L8.NL1END0 origin:050-pip-seed !22_02 16_02 23_02 24_02 25_02
INT_L.IMUX_L8.NN2END0 origin:050-pip-seed !22_02 !23_02 !24_02 17_02 25_02
@ -1934,8 +1934,8 @@ INT_L.IMUX_L9.ER1END0 origin:050-pip-seed !23_10 18_11 22_10 24_10 25_10
INT_L.IMUX_L9.FAN_BOUNCE5 origin:050-pip-seed !22_10 20_10 23_10 24_10 25_10
INT_L.IMUX_L9.FAN_BOUNCE6 origin:050-pip-seed !23_10 20_10 22_10 24_10 25_10
INT_L.IMUX_L9.GFAN0 origin:049-int-imux-gfan !22_10 !23_10 !24_10 21_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_L.IMUX_L9.LOGIC_OUTS_L4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L18 origin:051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_L.IMUX_L9.LOGIC_OUTS_L4 origin:051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_L.IMUX_L9.LOGIC_OUTS_L8 origin:051-pip-imuxlout-bypalts !22_10 21_10 23_10 24_10 25_10
INT_L.IMUX_L9.NE2END0 origin:050-pip-seed !22_10 !23_10 !25_10 16_10 24_10
INT_L.IMUX_L9.NL1END1 origin:050-pip-seed !22_10 16_10 23_10 24_10 25_10
@ -2391,7 +2391,7 @@ INT_L.NN6BEG1.NN6END1 origin:050-pip-seed 02_22 07_23
INT_L.NN6BEG1.NW2END1 origin:050-pip-seed 03_22 04_20
INT_L.NN6BEG1.NW6END1 origin:050-pip-seed 04_20 07_23
INT_L.NN6BEG1.SE2END1 origin:050-pip-seed 03_22 05_22
INT_L.NN6BEG1.SE6END1 origin:056-pip-rem 05_22 07_23
INT_L.NN6BEG1.SE6END1 origin:050-pip-seed 05_22 07_23
INT_L.NN6BEG1.WW2END0 origin:050-pip-seed 02_23 04_20
INT_L.NN6BEG1.WW4END1 origin:050-pip-seed 04_20 04_23
INT_L.NN6BEG2.EE2END2 origin:050-pip-seed 02_39 05_38
@ -2827,7 +2827,7 @@ INT_L.SE6BEG3.LV_L18 origin:056-pip-rem 04_59 05_57
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@ -3255,7 +3255,7 @@ INT_L.SW6BEG0.SW6END0 origin:050-pip-seed 03_13 05_12
INT_L.SW6BEG0.WW2END0 origin:050-pip-seed 03_12 05_15
INT_L.SW6BEG0.WW4END1 origin:050-pip-seed 05_12 05_15
INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L1 origin:050-pip-seed 02_29 04_30
INT_L.SW6BEG1.LOGIC_OUTS_L13 origin:050-pip-seed 03_28 04_30
@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46
INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_33 07_33
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

324
zynq7/segbits_int_r.origin_info.db
View File

@ -6,9 +6,9 @@ INT_R.BYP_ALT0.ER1END0 origin:050-pip-seed !22_07 17_07 23_07 24_07 25_07
INT_R.BYP_ALT0.FAN_BOUNCE2 origin:050-pip-seed !22_07 21_07 23_07 24_07 25_07
INT_R.BYP_ALT0.FAN_BOUNCE7 origin:050-pip-seed !23_07 21_07 22_07 24_07 25_07
INT_R.BYP_ALT0.GFAN0 origin:054-pip-fan-alt !22_07 !23_07 !25_07 20_07 24_07
INT_R.BYP_ALT0.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_07 20_07 23_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_07 20_07 22_07 24_07 25_07
INT_R.BYP_ALT0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_07 !23_07 !24_07 20_07 25_07
INT_R.BYP_ALT0.NE2END0 origin:050-pip-seed !22_07 !23_07 !24_07 19_06 25_07
INT_R.BYP_ALT0.NL1END0 origin:050-pip-seed !23_07 18_06 22_07 24_07 25_07
INT_R.BYP_ALT0.NN2END0 origin:050-pip-seed !22_07 !23_07 !25_07 19_06 24_07
@ -30,9 +30,9 @@ INT_R.BYP_ALT1.ER1END0 origin:050-pip-seed !22_15 16_15 23_15 24_15 25_15
INT_R.BYP_ALT1.FAN_BOUNCE5 origin:050-pip-seed !23_15 21_15 22_15 24_15 25_15
INT_R.BYP_ALT1.FAN_BOUNCE6 origin:050-pip-seed !22_15 21_15 23_15 24_15 25_15
INT_R.BYP_ALT1.GFAN0 origin:054-pip-fan-alt !22_15 !23_15 !25_15 20_15 24_15
INT_R.BYP_ALT1.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_15 !23_15 !24_15 20_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_15 20_15 23_15 24_15 25_15
INT_R.BYP_ALT1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_15 20_15 22_15 24_15 25_15
INT_R.BYP_ALT1.NE2END1 origin:050-pip-seed !22_15 !23_15 !24_15 16_15 25_15
INT_R.BYP_ALT1.NL1END1 origin:050-pip-seed !23_15 18_14 22_15 24_15 25_15
INT_R.BYP_ALT1.NN2END1 origin:050-pip-seed !22_15 !23_15 !25_15 16_15 24_15
@ -54,9 +54,9 @@ INT_R.BYP_ALT2.ER1END2 origin:050-pip-seed !22_39 17_39 23_39 24_39 25_39
INT_R.BYP_ALT2.FAN_BOUNCE1 origin:050-pip-seed !23_39 21_39 22_39 24_39 25_39
INT_R.BYP_ALT2.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_39 21_39 23_39 24_39 25_39
INT_R.BYP_ALT2.GFAN1 origin:054-pip-fan-alt !22_39 !23_39 !25_39 20_39 24_39
INT_R.BYP_ALT2.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_39 20_39 22_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_39 20_39 23_39 24_39 25_39
INT_R.BYP_ALT2.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_39 !23_39 !24_39 20_39 25_39
INT_R.BYP_ALT2.NE2END2 origin:050-pip-seed !22_39 !23_39 !24_39 19_38 25_39
INT_R.BYP_ALT2.NL1END2 origin:050-pip-seed !23_39 18_38 22_39 24_39 25_39
INT_R.BYP_ALT2.NN2END2 origin:050-pip-seed !22_39 !23_39 !25_39 19_38 24_39
@ -78,9 +78,9 @@ INT_R.BYP_ALT3.ER1END2 origin:050-pip-seed !22_47 16_47 23_47 24_47 25_47
INT_R.BYP_ALT3.FAN_BOUNCE3 origin:050-pip-seed !23_47 21_47 22_47 24_47 25_47
INT_R.BYP_ALT3.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_47 21_47 23_47 24_47 25_47
INT_R.BYP_ALT3.GFAN1 origin:054-pip-fan-alt !22_47 !23_47 !25_47 20_47 24_47
INT_R.BYP_ALT3.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_47 20_47 22_47 24_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_47 !23_47 !24_47 20_47 25_47
INT_R.BYP_ALT3.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_47 20_47 23_47 24_47 25_47
INT_R.BYP_ALT3.NE2END3 origin:050-pip-seed !22_47 !23_47 !24_47 16_47 25_47
INT_R.BYP_ALT3.NL1BEG_N3 origin:050-pip-seed !23_47 18_46 22_47 24_47 25_47
INT_R.BYP_ALT3.NN2END3 origin:050-pip-seed !22_47 !23_47 !25_47 16_47 24_47
@ -102,9 +102,9 @@ INT_R.BYP_ALT4.ER1END1 origin:050-pip-seed !22_23 17_23 23_23 24_23 25_23
INT_R.BYP_ALT4.FAN_BOUNCE1 origin:050-pip-seed !23_23 21_23 22_23 24_23 25_23
INT_R.BYP_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_23 21_23 23_23 24_23 25_23
INT_R.BYP_ALT4.GFAN0 origin:054-pip-fan-alt !22_23 !23_23 !25_23 20_23 24_23
INT_R.BYP_ALT4.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_23 !23_23 !24_23 20_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_23 20_23 23_23 24_23 25_23
INT_R.BYP_ALT4.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_23 20_23 22_23 24_23 25_23
INT_R.BYP_ALT4.NE2END1 origin:050-pip-seed !22_23 !23_23 !24_23 19_22 25_23
INT_R.BYP_ALT4.NL1END1 origin:050-pip-seed !23_23 18_22 22_23 24_23 25_23
INT_R.BYP_ALT4.NN2END1 origin:050-pip-seed !22_23 !23_23 !25_23 19_22 24_23
@ -126,9 +126,9 @@ INT_R.BYP_ALT5.ER1END1 origin:050-pip-seed !22_31 16_31 23_31 24_31 25_31
INT_R.BYP_ALT5.FAN_BOUNCE3 origin:050-pip-seed !23_31 21_31 22_31 24_31 25_31
INT_R.BYP_ALT5.FAN_BOUNCE5 origin:050-pip-seed !22_31 21_31 23_31 24_31 25_31
INT_R.BYP_ALT5.GFAN0 origin:054-pip-fan-alt !22_31 !23_31 !25_31 20_31 24_31
INT_R.BYP_ALT5.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_31 20_31 23_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_31 20_31 22_31 24_31 25_31
INT_R.BYP_ALT5.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_31 !23_31 !24_31 20_31 25_31
INT_R.BYP_ALT5.NE2END2 origin:050-pip-seed !22_31 !23_31 !24_31 16_31 25_31
INT_R.BYP_ALT5.NL1END2 origin:050-pip-seed !23_31 18_30 22_31 24_31 25_31
INT_R.BYP_ALT5.NN2END2 origin:050-pip-seed !22_31 !23_31 !25_31 16_31 24_31
@ -150,8 +150,8 @@ INT_R.BYP_ALT6.ER1END3 origin:050-pip-seed !22_55 17_55 23_55 24_55 25_55
INT_R.BYP_ALT6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_55 21_55 22_55 24_55 25_55
INT_R.BYP_ALT6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_55 21_55 23_55 24_55 25_55
INT_R.BYP_ALT6.GFAN1 origin:054-pip-fan-alt !22_55 !23_55 !25_55 20_55 24_55
INT_R.BYP_ALT6.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_55 20_55 22_55 24_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_55 !23_55 !24_55 20_55 25_55
INT_R.BYP_ALT6.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_55 20_55 23_55 24_55 25_55
INT_R.BYP_ALT6.NE2END3 origin:050-pip-seed !22_55 !23_55 !24_55 19_54 25_55
INT_R.BYP_ALT6.NL1BEG_N3 origin:050-pip-seed !23_55 18_54 22_55 24_55 25_55
@ -174,8 +174,8 @@ INT_R.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
INT_R.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_R.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
INT_R.BYP_ALT7.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
INT_R.BYP_ALT7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_R.BYP_ALT7.NE2END_S3_0 origin:050-pip-seed !22_63 !23_63 !24_63 16_63 25_63
INT_R.BYP_ALT7.NL1END_S3_0 origin:050-pip-seed !23_63 18_62 22_63 24_63 25_63
@ -353,7 +353,7 @@ INT_R.EE4BEG0.SE6END0 origin:050-pip-seed 03_09 06_08
INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
INT_R.EE4BEG1.EE2END1 origin:050-pip-seed 03_24 03_25
INT_R.EE4BEG1.EE4END1 origin:050-pip-seed 03_25 05_24
INT_R.EE4BEG1.LH6 origin:056-pip-rem 05_24 07_25
@ -373,7 +373,7 @@ INT_R.EE4BEG1.SE6END1 origin:050-pip-seed 03_25 06_24
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
INT_R.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@ -393,7 +393,7 @@ INT_R.EE4BEG2.SE6END2 origin:050-pip-seed 03_41 06_40
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
@ -413,7 +413,7 @@ INT_R.EE4BEG3.SE6END3 origin:050-pip-seed 03_57 06_56
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@ -806,9 +806,9 @@ INT_R.IMUX0.ER1END_N3_3 origin:050-pip-seed !22_01 18_00 23_01 24_01 25_01
INT_R.IMUX0.FAN_BOUNCE2 origin:050-pip-seed !22_01 21_01 23_01 24_01 25_01
INT_R.IMUX0.FAN_BOUNCE7 origin:050-pip-seed !23_01 21_01 22_01 24_01 25_01
INT_R.IMUX0.GFAN0 origin:049-int-imux-gfan !22_01 !23_01 !25_01 20_01 24_01
INT_R.IMUX0.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_R.IMUX0.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_01 20_01 23_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_01 20_01 22_01 24_01 25_01
INT_R.IMUX0.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_01 !23_01 !24_01 20_01 25_01
INT_R.IMUX0.NE2END0 origin:050-pip-seed !22_01 !23_01 !24_01 16_01 25_01
INT_R.IMUX0.NL1END0 origin:050-pip-seed !23_01 17_01 22_01 24_01 25_01
INT_R.IMUX0.NN2END0 origin:050-pip-seed !22_01 !23_01 !25_01 16_01 24_01
@ -830,9 +830,9 @@ INT_R.IMUX1.ER1END0 origin:050-pip-seed !22_09 19_08 23_09 24_09 25_09
INT_R.IMUX1.FAN_BOUNCE5 origin:050-pip-seed !23_09 21_09 22_09 24_09 25_09
INT_R.IMUX1.FAN_BOUNCE6 origin:050-pip-seed !22_09 21_09 23_09 24_09 25_09
INT_R.IMUX1.GFAN0 origin:049-int-imux-gfan !22_09 !23_09 !25_09 20_09 24_09
INT_R.IMUX1.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_R.IMUX1.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_09 !23_09 !24_09 20_09 25_09
INT_R.IMUX1.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_09 20_09 23_09 24_09 25_09
INT_R.IMUX1.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_09 20_09 22_09 24_09 25_09
INT_R.IMUX1.NE2END0 origin:050-pip-seed !22_09 !23_09 !24_09 19_08 25_09
INT_R.IMUX1.NL1END1 origin:050-pip-seed !23_09 17_09 22_09 24_09 25_09
INT_R.IMUX1.NN2END0 origin:050-pip-seed !22_09 !23_09 !25_09 19_08 24_09
@ -854,9 +854,9 @@ INT_R.IMUX10.ER1END0 origin:050-pip-seed !23_18 17_18 22_18 24_18 25_18
INT_R.IMUX10.FAN_BOUNCE1 origin:050-pip-seed !22_18 20_18 23_18 24_18 25_18
INT_R.IMUX10.FAN_BOUNCE7 origin:050-pip-seed !23_18 20_18 22_18 24_18 25_18
INT_R.IMUX10.GFAN0 origin:049-int-imux-gfan !22_18 !23_18 !24_18 21_18 25_18
INT_R.IMUX10.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_R.IMUX10.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_18 !23_18 !25_18 21_18 24_18
INT_R.IMUX10.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_18 21_18 22_18 24_18 25_18
INT_R.IMUX10.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_18 21_18 23_18 24_18 25_18
INT_R.IMUX10.NE2END1 origin:050-pip-seed !22_18 !23_18 !25_18 17_18 24_18
INT_R.IMUX10.NL1END1 origin:050-pip-seed !22_18 16_18 23_18 24_18 25_18
INT_R.IMUX10.NN2END1 origin:050-pip-seed !22_18 !23_18 !24_18 17_18 25_18
@ -878,9 +878,9 @@ INT_R.IMUX11.ER1END1 origin:050-pip-seed !23_26 18_27 22_26 24_26 25_26
INT_R.IMUX11.FAN_BOUNCE3 origin:050-pip-seed !22_26 20_26 23_26 24_26 25_26
INT_R.IMUX11.FAN_BOUNCE5 origin:050-pip-seed !23_26 20_26 22_26 24_26 25_26
INT_R.IMUX11.GFAN0 origin:049-int-imux-gfan !22_26 !23_26 !24_26 21_26 25_26
INT_R.IMUX11.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_R.IMUX11.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_26 21_26 22_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_26 21_26 23_26 24_26 25_26
INT_R.IMUX11.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_26 !23_26 !25_26 21_26 24_26
INT_R.IMUX11.NE2END1 origin:050-pip-seed !22_26 !23_26 !25_26 16_26 24_26
INT_R.IMUX11.NL1END2 origin:050-pip-seed !22_26 16_26 23_26 24_26 25_26
INT_R.IMUX11.NN2END1 origin:050-pip-seed !22_26 !23_26 !24_26 16_26 25_26
@ -902,9 +902,9 @@ INT_R.IMUX12.ER1END1 origin:050-pip-seed !23_34 17_34 22_34 24_34 25_34
INT_R.IMUX12.FAN_BOUNCE1 origin:050-pip-seed !22_34 20_34 23_34 24_34 25_34
INT_R.IMUX12.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_34 20_34 22_34 24_34 25_34
INT_R.IMUX12.GFAN1 origin:049-int-imux-gfan !22_34 !23_34 !24_34 21_34 25_34
INT_R.IMUX12.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_R.IMUX12.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_34 21_34 23_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_34 21_34 22_34 24_34 25_34
INT_R.IMUX12.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_34 !23_34 !25_34 21_34 24_34
INT_R.IMUX12.NE2END2 origin:050-pip-seed !22_34 !23_34 !25_34 17_34 24_34
INT_R.IMUX12.NL1END2 origin:050-pip-seed !22_34 16_34 23_34 24_34 25_34
INT_R.IMUX12.NN2END2 origin:050-pip-seed !22_34 !23_34 !24_34 17_34 25_34
@ -926,9 +926,9 @@ INT_R.IMUX13.ER1END2 origin:050-pip-seed !23_42 18_43 22_42 24_42 25_42
INT_R.IMUX13.FAN_BOUNCE3 origin:050-pip-seed !22_42 20_42 23_42 24_42 25_42
INT_R.IMUX13.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_42 20_42 22_42 24_42 25_42
INT_R.IMUX13.GFAN1 origin:049-int-imux-gfan !22_42 !23_42 !24_42 21_42 25_42
INT_R.IMUX13.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_R.IMUX13.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_42 21_42 23_42 24_42 25_42
INT_R.IMUX13.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_42 !23_42 !25_42 21_42 24_42
INT_R.IMUX13.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_42 21_42 22_42 24_42 25_42
INT_R.IMUX13.NE2END2 origin:050-pip-seed !22_42 !23_42 !25_42 16_42 24_42
INT_R.IMUX13.NL1BEG_N3 origin:050-pip-seed !22_42 16_42 23_42 24_42 25_42
INT_R.IMUX13.NN2END2 origin:050-pip-seed !22_42 !23_42 !24_42 16_42 25_42
@ -950,9 +950,9 @@ INT_R.IMUX14.ER1END2 origin:050-pip-seed !23_50 17_50 22_50 24_50 25_50
INT_R.IMUX14.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_50 20_50 23_50 24_50 25_50
INT_R.IMUX14.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_50 20_50 22_50 24_50 25_50
INT_R.IMUX14.GFAN1 origin:049-int-imux-gfan !22_50 !23_50 !24_50 21_50 25_50
INT_R.IMUX14.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_50 21_50 23_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_50 !23_50 !25_50 21_50 24_50
INT_R.IMUX14.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_R.IMUX14.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_50 21_50 22_50 24_50 25_50
INT_R.IMUX14.NE2END3 origin:050-pip-seed !22_50 !23_50 !25_50 17_50 24_50
INT_R.IMUX14.NL1BEG_N3 origin:050-pip-seed !22_50 16_50 23_50 24_50 25_50
INT_R.IMUX14.NN2END3 origin:050-pip-seed !22_50 !23_50 !24_50 17_50 25_50
@ -974,9 +974,9 @@ INT_R.IMUX15.ER1END3 origin:050-pip-seed !23_58 18_59 22_58 24_58 25_58
INT_R.IMUX15.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_58 20_58 23_58 24_58 25_58
INT_R.IMUX15.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_58 20_58 22_58 24_58 25_58
INT_R.IMUX15.GFAN1 origin:049-int-imux-gfan !22_58 !23_58 !24_58 21_58 25_58
INT_R.IMUX15.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_58 21_58 23_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_58 !23_58 !25_58 21_58 24_58
INT_R.IMUX15.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_R.IMUX15.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_58 21_58 22_58 24_58 25_58
INT_R.IMUX15.NE2END3 origin:050-pip-seed !22_58 !23_58 !25_58 16_58 24_58
INT_R.IMUX15.NL1END_S3_0 origin:050-pip-seed !22_58 16_58 23_58 24_58 25_58
INT_R.IMUX15.NN2END3 origin:050-pip-seed !22_58 !23_58 !24_58 16_58 25_58
@ -998,9 +998,9 @@ INT_R.IMUX16.ER1END_N3_3 origin:050-pip-seed !22_03 19_02 23_03 24_03 25_03
INT_R.IMUX16.FAN_BOUNCE2 origin:050-pip-seed !22_03 21_03 23_03 24_03 25_03
INT_R.IMUX16.FAN_BOUNCE7 origin:050-pip-seed !23_03 21_03 22_03 24_03 25_03
INT_R.IMUX16.GFAN0 origin:049-int-imux-gfan !22_03 !23_03 !25_03 20_03 24_03
INT_R.IMUX16.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_R.IMUX16.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_03 20_03 23_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_03 20_03 22_03 24_03 25_03
INT_R.IMUX16.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_03 !23_03 !24_03 20_03 25_03
INT_R.IMUX16.NE2END0 origin:050-pip-seed !22_03 !23_03 !24_03 19_02 25_03
INT_R.IMUX16.NL1END0 origin:050-pip-seed !23_03 18_02 22_03 24_03 25_03
INT_R.IMUX16.NN2END0 origin:050-pip-seed !22_03 !23_03 !25_03 19_02 24_03
@ -1022,9 +1022,9 @@ INT_R.IMUX17.ER1END0 origin:050-pip-seed !22_11 16_11 23_11 24_11 25_11
INT_R.IMUX17.FAN_BOUNCE5 origin:050-pip-seed !23_11 21_11 22_11 24_11 25_11
INT_R.IMUX17.FAN_BOUNCE6 origin:050-pip-seed !22_11 21_11 23_11 24_11 25_11
INT_R.IMUX17.GFAN0 origin:049-int-imux-gfan !22_11 !23_11 !25_11 20_11 24_11
INT_R.IMUX17.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_R.IMUX17.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_11 !23_11 !24_11 20_11 25_11
INT_R.IMUX17.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_11 20_11 23_11 24_11 25_11
INT_R.IMUX17.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_11 20_11 22_11 24_11 25_11
INT_R.IMUX17.NE2END0 origin:050-pip-seed !22_11 !23_11 !24_11 18_10 25_11
INT_R.IMUX17.NL1END1 origin:050-pip-seed !23_11 18_10 22_11 24_11 25_11
INT_R.IMUX17.NN2END0 origin:050-pip-seed !22_11 !23_11 !25_11 18_10 24_11
@ -1046,9 +1046,9 @@ INT_R.IMUX18.ER1END0 origin:050-pip-seed !22_19 19_18 23_19 24_19 25_19
INT_R.IMUX18.FAN_BOUNCE1 origin:050-pip-seed !23_19 21_19 22_19 24_19 25_19
INT_R.IMUX18.FAN_BOUNCE7 origin:050-pip-seed !22_19 21_19 23_19 24_19 25_19
INT_R.IMUX18.GFAN0 origin:049-int-imux-gfan !22_19 !23_19 !25_19 20_19 24_19
INT_R.IMUX18.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_R.IMUX18.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_19 !23_19 !24_19 20_19 25_19
INT_R.IMUX18.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_19 20_19 23_19 24_19 25_19
INT_R.IMUX18.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_19 20_19 22_19 24_19 25_19
INT_R.IMUX18.NE2END1 origin:050-pip-seed !22_19 !23_19 !24_19 19_18 25_19
INT_R.IMUX18.NL1END1 origin:050-pip-seed !23_19 18_18 22_19 24_19 25_19
INT_R.IMUX18.NN2END1 origin:050-pip-seed !22_19 !23_19 !25_19 19_18 24_19
@ -1070,9 +1070,9 @@ INT_R.IMUX19.ER1END1 origin:050-pip-seed !22_27 16_27 23_27 24_27 25_27
INT_R.IMUX19.FAN_BOUNCE3 origin:050-pip-seed !23_27 21_27 22_27 24_27 25_27
INT_R.IMUX19.FAN_BOUNCE5 origin:050-pip-seed !22_27 21_27 23_27 24_27 25_27
INT_R.IMUX19.GFAN0 origin:049-int-imux-gfan !22_27 !23_27 !25_27 20_27 24_27
INT_R.IMUX19.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_R.IMUX19.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_27 20_27 23_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_27 20_27 22_27 24_27 25_27
INT_R.IMUX19.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_27 !23_27 !24_27 20_27 25_27
INT_R.IMUX19.NE2END1 origin:050-pip-seed !22_27 !23_27 !24_27 18_26 25_27
INT_R.IMUX19.NL1END2 origin:050-pip-seed !23_27 18_26 22_27 24_27 25_27
INT_R.IMUX19.NN2END1 origin:050-pip-seed !22_27 !23_27 !25_27 18_26 24_27
@ -1094,9 +1094,9 @@ INT_R.IMUX2.ER1END0 origin:050-pip-seed !22_17 18_16 23_17 24_17 25_17
INT_R.IMUX2.FAN_BOUNCE1 origin:050-pip-seed !23_17 21_17 22_17 24_17 25_17
INT_R.IMUX2.FAN_BOUNCE7 origin:050-pip-seed !22_17 21_17 23_17 24_17 25_17
INT_R.IMUX2.GFAN0 origin:049-int-imux-gfan !22_17 !23_17 !25_17 20_17 24_17
INT_R.IMUX2.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_R.IMUX2.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_17 !23_17 !24_17 20_17 25_17
INT_R.IMUX2.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_17 20_17 23_17 24_17 25_17
INT_R.IMUX2.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_17 20_17 22_17 24_17 25_17
INT_R.IMUX2.NE2END1 origin:050-pip-seed !22_17 !23_17 !24_17 16_17 25_17
INT_R.IMUX2.NL1END1 origin:050-pip-seed !23_17 17_17 22_17 24_17 25_17
INT_R.IMUX2.NN2END1 origin:050-pip-seed !22_17 !23_17 !25_17 16_17 24_17
@ -1118,9 +1118,9 @@ INT_R.IMUX20.ER1END1 origin:050-pip-seed !22_35 19_34 23_35 24_35 25_35
INT_R.IMUX20.FAN_BOUNCE1 origin:050-pip-seed !23_35 21_35 22_35 24_35 25_35
INT_R.IMUX20.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_35 21_35 23_35 24_35 25_35
INT_R.IMUX20.GFAN1 origin:049-int-imux-gfan !22_35 !23_35 !25_35 20_35 24_35
INT_R.IMUX20.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_R.IMUX20.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_35 20_35 22_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_35 20_35 23_35 24_35 25_35
INT_R.IMUX20.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_35 !23_35 !24_35 20_35 25_35
INT_R.IMUX20.NE2END2 origin:050-pip-seed !22_35 !23_35 !24_35 19_34 25_35
INT_R.IMUX20.NL1END2 origin:050-pip-seed !23_35 18_34 22_35 24_35 25_35
INT_R.IMUX20.NN2END2 origin:050-pip-seed !22_35 !23_35 !25_35 19_34 24_35
@ -1143,8 +1143,8 @@ INT_R.IMUX21.FAN_BOUNCE3 origin:050-pip-seed !23_43 21_43 22_43 24_43 25_43
INT_R.IMUX21.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_43 21_43 23_43 24_43 25_43
INT_R.IMUX21.GFAN1 origin:049-int-imux-gfan !22_43 !23_43 !25_43 20_43 24_43
INT_R.IMUX21.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_43 20_43 22_43 24_43 25_43
INT_R.IMUX21.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_R.IMUX21.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_R.IMUX21.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_43 !23_43 !24_43 20_43 25_43
INT_R.IMUX21.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_43 20_43 23_43 24_43 25_43
INT_R.IMUX21.NE2END2 origin:050-pip-seed !22_43 !23_43 !24_43 18_42 25_43
INT_R.IMUX21.NL1BEG_N3 origin:050-pip-seed !23_43 18_42 22_43 24_43 25_43
INT_R.IMUX21.NN2END2 origin:050-pip-seed !22_43 !23_43 !25_43 18_42 24_43
@ -1166,9 +1166,9 @@ INT_R.IMUX22.ER1END2 origin:050-pip-seed !22_51 19_50 23_51 24_51 25_51
INT_R.IMUX22.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_51 21_51 22_51 24_51 25_51
INT_R.IMUX22.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_51 21_51 23_51 24_51 25_51
INT_R.IMUX22.GFAN1 origin:049-int-imux-gfan !22_51 !23_51 !25_51 20_51 24_51
INT_R.IMUX22.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_R.IMUX22.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_51 20_51 22_51 24_51 25_51
INT_R.IMUX22.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_51 !23_51 !24_51 20_51 25_51
INT_R.IMUX22.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_51 20_51 23_51 24_51 25_51
INT_R.IMUX22.NE2END3 origin:050-pip-seed !22_51 !23_51 !24_51 19_50 25_51
INT_R.IMUX22.NL1BEG_N3 origin:050-pip-seed !23_51 18_50 22_51 24_51 25_51
INT_R.IMUX22.NN2END3 origin:050-pip-seed !22_51 !23_51 !25_51 19_50 24_51
@ -1190,9 +1190,9 @@ INT_R.IMUX23.ER1END3 origin:050-pip-seed !22_59 16_59 23_59 24_59 25_59
INT_R.IMUX23.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_59 21_59 22_59 24_59 25_59
INT_R.IMUX23.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_59 21_59 23_59 24_59 25_59
INT_R.IMUX23.GFAN1 origin:049-int-imux-gfan !22_59 !23_59 !25_59 20_59 24_59
INT_R.IMUX23.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_R.IMUX23.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_59 20_59 22_59 24_59 25_59
INT_R.IMUX23.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_59 !23_59 !24_59 20_59 25_59
INT_R.IMUX23.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_59 20_59 23_59 24_59 25_59
INT_R.IMUX23.NE2END3 origin:050-pip-seed !22_59 !23_59 !24_59 18_58 25_59
INT_R.IMUX23.NL1END_S3_0 origin:050-pip-seed !23_59 18_58 22_59 24_59 25_59
INT_R.IMUX23.NN2END3 origin:050-pip-seed !22_59 !23_59 !25_59 18_58 24_59
@ -1214,9 +1214,9 @@ INT_R.IMUX24.ER1END0 origin:050-pip-seed !23_04 18_05 22_04 24_04 25_04
INT_R.IMUX24.FAN_BOUNCE2 origin:050-pip-seed !23_04 20_04 22_04 24_04 25_04
INT_R.IMUX24.FAN_BOUNCE7 origin:050-pip-seed !22_04 20_04 23_04 24_04 25_04
INT_R.IMUX24.GFAN0 origin:049-int-imux-gfan !22_04 !23_04 !24_04 21_04 25_04
INT_R.IMUX24.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_R.IMUX24.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_04 21_04 22_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_04 21_04 23_04 24_04 25_04
INT_R.IMUX24.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_04 !23_04 !25_04 21_04 24_04
INT_R.IMUX24.NE2END0 origin:050-pip-seed !22_04 !23_04 !25_04 18_05 24_04
INT_R.IMUX24.NL1END0 origin:050-pip-seed !22_04 19_05 23_04 24_04 25_04
INT_R.IMUX24.NN2END0 origin:050-pip-seed !22_04 !23_04 !24_04 18_05 25_04
@ -1238,9 +1238,9 @@ INT_R.IMUX25.ER1END0 origin:050-pip-seed !23_12 17_12 22_12 24_12 25_12
INT_R.IMUX25.FAN_BOUNCE5 origin:050-pip-seed !22_12 20_12 23_12 24_12 25_12
INT_R.IMUX25.FAN_BOUNCE6 origin:050-pip-seed !23_12 20_12 22_12 24_12 25_12
INT_R.IMUX25.GFAN0 origin:049-int-imux-gfan !22_12 !23_12 !24_12 21_12 25_12
INT_R.IMUX25.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_R.IMUX25.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_12 !23_12 !25_12 21_12 24_12
INT_R.IMUX25.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_12 21_12 22_12 24_12 25_12
INT_R.IMUX25.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_12 21_12 23_12 24_12 25_12
INT_R.IMUX25.NE2END1 origin:050-pip-seed !22_12 !23_12 !25_12 19_13 24_12
INT_R.IMUX25.NL1END1 origin:050-pip-seed !22_12 19_13 23_12 24_12 25_12
INT_R.IMUX25.NN2END1 origin:050-pip-seed !22_12 !23_12 !24_12 19_13 25_12
@ -1262,8 +1262,8 @@ INT_R.IMUX26.ER1END1 origin:050-pip-seed !23_20 18_21 22_20 24_20 25_20
INT_R.IMUX26.FAN_BOUNCE1 origin:050-pip-seed !22_20 20_20 23_20 24_20 25_20
INT_R.IMUX26.FAN_BOUNCE7 origin:050-pip-seed !23_20 20_20 22_20 24_20 25_20
INT_R.IMUX26.GFAN0 origin:049-int-imux-gfan !22_20 !23_20 !24_20 21_20 25_20
INT_R.IMUX26.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_R.IMUX26.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_R.IMUX26.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_20 !23_20 !25_20 21_20 24_20
INT_R.IMUX26.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_20 21_20 22_20 24_20 25_20
INT_R.IMUX26.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_20 21_20 23_20 24_20 25_20
INT_R.IMUX26.NE2END1 origin:050-pip-seed !22_20 !23_20 !25_20 18_21 24_20
INT_R.IMUX26.NL1END1 origin:050-pip-seed !22_20 19_21 23_20 24_20 25_20
@ -1286,9 +1286,9 @@ INT_R.IMUX27.ER1END1 origin:050-pip-seed !23_28 17_28 22_28 24_28 25_28
INT_R.IMUX27.FAN_BOUNCE3 origin:050-pip-seed !22_28 20_28 23_28 24_28 25_28
INT_R.IMUX27.FAN_BOUNCE5 origin:050-pip-seed !23_28 20_28 22_28 24_28 25_28
INT_R.IMUX27.GFAN0 origin:049-int-imux-gfan !22_28 !23_28 !24_28 21_28 25_28
INT_R.IMUX27.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_28 21_28 22_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_28 21_28 23_28 24_28 25_28
INT_R.IMUX27.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_R.IMUX27.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_28 !23_28 !25_28 21_28 24_28
INT_R.IMUX27.NE2END2 origin:050-pip-seed !22_28 !23_28 !25_28 19_29 24_28
INT_R.IMUX27.NL1END2 origin:050-pip-seed !22_28 19_29 23_28 24_28 25_28
INT_R.IMUX27.NN2END2 origin:050-pip-seed !22_28 !23_28 !24_28 19_29 25_28
@ -1311,8 +1311,8 @@ INT_R.IMUX28.FAN_BOUNCE1 origin:050-pip-seed !22_36 20_36 23_36 24_36 25_36
INT_R.IMUX28.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_36 20_36 22_36 24_36 25_36
INT_R.IMUX28.GFAN1 origin:049-int-imux-gfan !22_36 !23_36 !24_36 21_36 25_36
INT_R.IMUX28.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_36 21_36 23_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_R.IMUX28.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_36 21_36 22_36 24_36 25_36
INT_R.IMUX28.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_36 !23_36 !25_36 21_36 24_36
INT_R.IMUX28.NE2END2 origin:050-pip-seed !22_36 !23_36 !25_36 18_37 24_36
INT_R.IMUX28.NL1END2 origin:050-pip-seed !22_36 19_37 23_36 24_36 25_36
INT_R.IMUX28.NN2END2 origin:050-pip-seed !22_36 !23_36 !24_36 18_37 25_36
@ -1334,9 +1334,9 @@ INT_R.IMUX29.ER1END2 origin:050-pip-seed !23_44 17_44 22_44 24_44 25_44
INT_R.IMUX29.FAN_BOUNCE3 origin:050-pip-seed !22_44 20_44 23_44 24_44 25_44
INT_R.IMUX29.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_44 20_44 22_44 24_44 25_44
INT_R.IMUX29.GFAN1 origin:049-int-imux-gfan !22_44 !23_44 !24_44 21_44 25_44
INT_R.IMUX29.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_R.IMUX29.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_44 21_44 23_44 24_44 25_44
INT_R.IMUX29.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_44 !23_44 !25_44 21_44 24_44
INT_R.IMUX29.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_44 21_44 22_44 24_44 25_44
INT_R.IMUX29.NE2END3 origin:050-pip-seed !22_44 !23_44 !25_44 19_45 24_44
INT_R.IMUX29.NL1BEG_N3 origin:050-pip-seed !22_44 19_45 23_44 24_44 25_44
INT_R.IMUX29.NN2END3 origin:050-pip-seed !22_44 !23_44 !24_44 19_45 25_44
@ -1358,9 +1358,9 @@ INT_R.IMUX3.ER1END1 origin:050-pip-seed !22_25 19_24 23_25 24_25 25_25
INT_R.IMUX3.FAN_BOUNCE3 origin:050-pip-seed !23_25 21_25 22_25 24_25 25_25
INT_R.IMUX3.FAN_BOUNCE5 origin:050-pip-seed !22_25 21_25 23_25 24_25 25_25
INT_R.IMUX3.GFAN0 origin:049-int-imux-gfan !22_25 !23_25 !25_25 20_25 24_25
INT_R.IMUX3.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_R.IMUX3.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_25 20_25 23_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_25 20_25 22_25 24_25 25_25
INT_R.IMUX3.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_25 !23_25 !24_25 20_25 25_25
INT_R.IMUX3.NE2END1 origin:050-pip-seed !22_25 !23_25 !24_25 19_24 25_25
INT_R.IMUX3.NL1END2 origin:050-pip-seed !23_25 17_25 22_25 24_25 25_25
INT_R.IMUX3.NN2END1 origin:050-pip-seed !22_25 !23_25 !25_25 19_24 24_25
@ -1382,9 +1382,9 @@ INT_R.IMUX30.ER1END3 origin:050-pip-seed !23_52 18_53 22_52 24_52 25_52
INT_R.IMUX30.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_52 20_52 23_52 24_52 25_52
INT_R.IMUX30.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_52 20_52 22_52 24_52 25_52
INT_R.IMUX30.GFAN1 origin:049-int-imux-gfan !22_52 !23_52 !24_52 21_52 25_52
INT_R.IMUX30.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_R.IMUX30.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_52 21_52 23_52 24_52 25_52
INT_R.IMUX30.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_52 !23_52 !25_52 21_52 24_52
INT_R.IMUX30.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_52 21_52 22_52 24_52 25_52
INT_R.IMUX30.NE2END3 origin:050-pip-seed !22_52 !23_52 !25_52 18_53 24_52
INT_R.IMUX30.NL1BEG_N3 origin:050-pip-seed !22_52 19_53 23_52 24_52 25_52
INT_R.IMUX30.NN2END3 origin:050-pip-seed !22_52 !23_52 !24_52 18_53 25_52
@ -1406,9 +1406,9 @@ INT_R.IMUX31.ER1END3 origin:050-pip-seed !23_60 17_60 22_60 24_60 25_60
INT_R.IMUX31.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_60 20_60 23_60 24_60 25_60
INT_R.IMUX31.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_60 20_60 22_60 24_60 25_60
INT_R.IMUX31.GFAN1 origin:049-int-imux-gfan !22_60 !23_60 !24_60 21_60 25_60
INT_R.IMUX31.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_R.IMUX31.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_60 21_60 23_60 24_60 25_60
INT_R.IMUX31.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_60 !23_60 !25_60 21_60 24_60
INT_R.IMUX31.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_60 21_60 22_60 24_60 25_60
INT_R.IMUX31.NE2END_S3_0 origin:050-pip-seed !22_60 !23_60 !25_60 19_61 24_60
INT_R.IMUX31.NL1END_S3_0 origin:050-pip-seed !22_60 19_61 23_60 24_60 25_60
INT_R.IMUX31.NN2END_S2_0 origin:050-pip-seed !22_60 !23_60 !24_60 19_61 25_60
@ -1430,8 +1430,8 @@ INT_R.IMUX32.ER1END0 origin:050-pip-seed !22_05 16_05 23_05 24_05 25_05
INT_R.IMUX32.FAN_BOUNCE2 origin:050-pip-seed !22_05 21_05 23_05 24_05 25_05
INT_R.IMUX32.FAN_BOUNCE7 origin:050-pip-seed !23_05 21_05 22_05 24_05 25_05
INT_R.IMUX32.GFAN0 origin:049-int-imux-gfan !22_05 !23_05 !25_05 20_05 24_05
INT_R.IMUX32.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !22_05 20_05 23_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !23_05 20_05 22_05 24_05 25_05
INT_R.IMUX32.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_05 !23_05 !24_05 20_05 25_05
INT_R.IMUX32.NE2END0 origin:050-pip-seed !22_05 !23_05 !24_05 16_05 25_05
INT_R.IMUX32.NL1END0 origin:050-pip-seed !23_05 17_05 22_05 24_05 25_05
@ -1455,8 +1455,8 @@ INT_R.IMUX33.FAN_BOUNCE5 origin:050-pip-seed !23_13 21_13 22_13 24_13 25_13
INT_R.IMUX33.FAN_BOUNCE6 origin:050-pip-seed !22_13 21_13 23_13 24_13 25_13
INT_R.IMUX33.GFAN0 origin:049-int-imux-gfan !22_13 !23_13 !25_13 20_13 24_13
INT_R.IMUX33.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_13 !23_13 !24_13 20_13 25_13
INT_R.IMUX33.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !22_13 20_13 23_13 24_13 25_13
INT_R.IMUX33.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !23_13 20_13 22_13 24_13 25_13
INT_R.IMUX33.NE2END1 origin:050-pip-seed !22_13 !23_13 !24_13 17_13 25_13
INT_R.IMUX33.NL1END1 origin:050-pip-seed !23_13 17_13 22_13 24_13 25_13
INT_R.IMUX33.NN2END1 origin:050-pip-seed !22_13 !23_13 !25_13 17_13 24_13
@ -1478,9 +1478,9 @@ INT_R.IMUX34.ER1END1 origin:050-pip-seed !22_21 16_21 23_21 24_21 25_21
INT_R.IMUX34.FAN_BOUNCE1 origin:050-pip-seed !23_21 21_21 22_21 24_21 25_21
INT_R.IMUX34.FAN_BOUNCE7 origin:050-pip-seed !22_21 21_21 23_21 24_21 25_21
INT_R.IMUX34.GFAN0 origin:049-int-imux-gfan !22_21 !23_21 !25_21 20_21 24_21
INT_R.IMUX34.LOGIC_OUTS19 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_R.IMUX34.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_21 !23_21 !24_21 20_21 25_21
INT_R.IMUX34.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !22_21 20_21 23_21 24_21 25_21
INT_R.IMUX34.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !23_21 20_21 22_21 24_21 25_21
INT_R.IMUX34.NE2END1 origin:050-pip-seed !22_21 !23_21 !24_21 16_21 25_21
INT_R.IMUX34.NL1END1 origin:050-pip-seed !23_21 17_21 22_21 24_21 25_21
INT_R.IMUX34.NN2END1 origin:050-pip-seed !22_21 !23_21 !25_21 16_21 24_21
@ -1502,9 +1502,9 @@ INT_R.IMUX35.ER1END1 origin:050-pip-seed !22_29 19_28 23_29 24_29 25_29
INT_R.IMUX35.FAN_BOUNCE3 origin:050-pip-seed !23_29 21_29 22_29 24_29 25_29
INT_R.IMUX35.FAN_BOUNCE5 origin:050-pip-seed !22_29 21_29 23_29 24_29 25_29
INT_R.IMUX35.GFAN0 origin:049-int-imux-gfan !22_29 !23_29 !25_29 20_29 24_29
INT_R.IMUX35.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS23 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_R.IMUX35.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !22_29 20_29 23_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !23_29 20_29 22_29 24_29 25_29
INT_R.IMUX35.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_29 !23_29 !24_29 20_29 25_29
INT_R.IMUX35.NE2END2 origin:050-pip-seed !22_29 !23_29 !24_29 17_29 25_29
INT_R.IMUX35.NL1END2 origin:050-pip-seed !23_29 17_29 22_29 24_29 25_29
INT_R.IMUX35.NN2END2 origin:050-pip-seed !22_29 !23_29 !25_29 17_29 24_29
@ -1526,9 +1526,9 @@ INT_R.IMUX36.ER1END2 origin:050-pip-seed !22_37 16_37 23_37 24_37 25_37
INT_R.IMUX36.FAN_BOUNCE1 origin:050-pip-seed !23_37 21_37 22_37 24_37 25_37
INT_R.IMUX36.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_37 21_37 23_37 24_37 25_37
INT_R.IMUX36.GFAN1 origin:049-int-imux-gfan !22_37 !23_37 !25_37 20_37 24_37
INT_R.IMUX36.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_R.IMUX36.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_37 20_37 22_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_37 20_37 23_37 24_37 25_37
INT_R.IMUX36.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_37 !23_37 !24_37 20_37 25_37
INT_R.IMUX36.NE2END2 origin:050-pip-seed !22_37 !23_37 !24_37 16_37 25_37
INT_R.IMUX36.NL1END2 origin:050-pip-seed !23_37 17_37 22_37 24_37 25_37
INT_R.IMUX36.NN2END2 origin:050-pip-seed !22_37 !23_37 !25_37 16_37 24_37
@ -1550,9 +1550,9 @@ INT_R.IMUX37.ER1END2 origin:050-pip-seed !22_45 19_44 23_45 24_45 25_45
INT_R.IMUX37.FAN_BOUNCE3 origin:050-pip-seed !23_45 21_45 22_45 24_45 25_45
INT_R.IMUX37.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_45 21_45 23_45 24_45 25_45
INT_R.IMUX37.GFAN1 origin:049-int-imux-gfan !22_45 !23_45 !25_45 20_45 24_45
INT_R.IMUX37.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_R.IMUX37.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_45 20_45 22_45 24_45 25_45
INT_R.IMUX37.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_45 !23_45 !24_45 20_45 25_45
INT_R.IMUX37.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_45 20_45 23_45 24_45 25_45
INT_R.IMUX37.NE2END3 origin:050-pip-seed !22_45 !23_45 !24_45 17_45 25_45
INT_R.IMUX37.NL1BEG_N3 origin:050-pip-seed !23_45 17_45 22_45 24_45 25_45
INT_R.IMUX37.NN2END3 origin:050-pip-seed !22_45 !23_45 !25_45 17_45 24_45
@ -1574,9 +1574,9 @@ INT_R.IMUX38.ER1END3 origin:050-pip-seed !22_53 16_53 23_53 24_53 25_53
INT_R.IMUX38.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_53 21_53 22_53 24_53 25_53
INT_R.IMUX38.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_53 21_53 23_53 24_53 25_53
INT_R.IMUX38.GFAN1 origin:049-int-imux-gfan !22_53 !23_53 !25_53 20_53 24_53
INT_R.IMUX38.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_R.IMUX38.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_53 20_53 22_53 24_53 25_53
INT_R.IMUX38.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_53 !23_53 !24_53 20_53 25_53
INT_R.IMUX38.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_53 20_53 23_53 24_53 25_53
INT_R.IMUX38.NE2END3 origin:050-pip-seed !22_53 !23_53 !24_53 16_53 25_53
INT_R.IMUX38.NL1BEG_N3 origin:050-pip-seed !23_53 17_53 22_53 24_53 25_53
INT_R.IMUX38.NN2END3 origin:050-pip-seed !22_53 !23_53 !25_53 16_53 24_53
@ -1598,9 +1598,9 @@ INT_R.IMUX39.ER1END3 origin:050-pip-seed !22_61 19_60 23_61 24_61 25_61
INT_R.IMUX39.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_61 21_61 22_61 24_61 25_61
INT_R.IMUX39.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_61 21_61 23_61 24_61 25_61
INT_R.IMUX39.GFAN1 origin:049-int-imux-gfan !22_61 !23_61 !25_61 20_61 24_61
INT_R.IMUX39.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_R.IMUX39.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_61 20_61 22_61 24_61 25_61
INT_R.IMUX39.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_61 !23_61 !24_61 20_61 25_61
INT_R.IMUX39.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_61 20_61 23_61 24_61 25_61
INT_R.IMUX39.NE2END_S3_0 origin:050-pip-seed !22_61 !23_61 !24_61 17_61 25_61
INT_R.IMUX39.NL1END_S3_0 origin:050-pip-seed !23_61 17_61 22_61 24_61 25_61
INT_R.IMUX39.NN2END_S2_0 origin:050-pip-seed !22_61 !23_61 !25_61 17_61 24_61
@ -1622,9 +1622,9 @@ INT_R.IMUX4.ER1END1 origin:050-pip-seed !22_33 18_32 23_33 24_33 25_33
INT_R.IMUX4.FAN_BOUNCE1 origin:050-pip-seed !23_33 21_33 22_33 24_33 25_33
INT_R.IMUX4.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_33 21_33 23_33 24_33 25_33
INT_R.IMUX4.GFAN1 origin:049-int-imux-gfan !22_33 !23_33 !25_33 20_33 24_33
INT_R.IMUX4.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_R.IMUX4.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !23_33 20_33 22_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !22_33 20_33 23_33 24_33 25_33
INT_R.IMUX4.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_33 !23_33 !24_33 20_33 25_33
INT_R.IMUX4.NE2END2 origin:050-pip-seed !22_33 !23_33 !24_33 16_33 25_33
INT_R.IMUX4.NL1END2 origin:050-pip-seed !23_33 17_33 22_33 24_33 25_33
INT_R.IMUX4.NN2END2 origin:050-pip-seed !22_33 !23_33 !25_33 16_33 24_33
@ -1646,9 +1646,9 @@ INT_R.IMUX40.ER1END0 origin:050-pip-seed !23_06 19_07 22_06 24_06 25_06
INT_R.IMUX40.FAN_BOUNCE2 origin:050-pip-seed !23_06 20_06 22_06 24_06 25_06
INT_R.IMUX40.FAN_BOUNCE7 origin:050-pip-seed !22_06 20_06 23_06 24_06 25_06
INT_R.IMUX40.GFAN0 origin:049-int-imux-gfan !22_06 !23_06 !24_06 21_06 25_06
INT_R.IMUX40.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS12 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_R.IMUX40.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_06 21_06 22_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_06 21_06 23_06 24_06 25_06
INT_R.IMUX40.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_06 !23_06 !25_06 21_06 24_06
INT_R.IMUX40.NE2END0 origin:050-pip-seed !22_06 !23_06 !25_06 17_06 24_06
INT_R.IMUX40.NL1END0 origin:050-pip-seed !22_06 16_06 23_06 24_06 25_06
INT_R.IMUX40.NN2END0 origin:050-pip-seed !22_06 !23_06 !24_06 17_06 25_06
@ -1670,9 +1670,9 @@ INT_R.IMUX41.ER1END0 origin:050-pip-seed !23_14 18_15 22_14 24_14 25_14
INT_R.IMUX41.FAN_BOUNCE5 origin:050-pip-seed !22_14 20_14 23_14 24_14 25_14
INT_R.IMUX41.FAN_BOUNCE6 origin:050-pip-seed !23_14 20_14 22_14 24_14 25_14
INT_R.IMUX41.GFAN0 origin:049-int-imux-gfan !22_14 !23_14 !24_14 21_14 25_14
INT_R.IMUX41.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_R.IMUX41.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS8 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_14 !23_14 !25_14 21_14 24_14
INT_R.IMUX41.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_14 21_14 22_14 24_14 25_14
INT_R.IMUX41.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_14 21_14 23_14 24_14 25_14
INT_R.IMUX41.NE2END1 origin:050-pip-seed !22_14 !23_14 !25_14 18_15 24_14
INT_R.IMUX41.NL1END1 origin:050-pip-seed !22_14 16_14 23_14 24_14 25_14
INT_R.IMUX41.NN2END1 origin:050-pip-seed !22_14 !23_14 !24_14 18_15 25_14
@ -1695,8 +1695,8 @@ INT_R.IMUX42.FAN_BOUNCE1 origin:050-pip-seed !22_22 20_22 23_22 24_22 25_22
INT_R.IMUX42.FAN_BOUNCE7 origin:050-pip-seed !23_22 20_22 22_22 24_22 25_22
INT_R.IMUX42.GFAN0 origin:049-int-imux-gfan !22_22 !23_22 !24_22 21_22 25_22
INT_R.IMUX42.LOGIC_OUTS19 origin:051-pip-imuxlout-bypalts !22_22 !23_22 !25_22 21_22 24_22
INT_R.IMUX42.LOGIC_OUTS5 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS9 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS5 origin:051-pip-imuxlout-bypalts !23_22 21_22 22_22 24_22 25_22
INT_R.IMUX42.LOGIC_OUTS9 origin:051-pip-imuxlout-bypalts !22_22 21_22 23_22 24_22 25_22
INT_R.IMUX42.NE2END1 origin:050-pip-seed !22_22 !23_22 !25_22 17_22 24_22
INT_R.IMUX42.NL1END1 origin:050-pip-seed !22_22 16_22 23_22 24_22 25_22
INT_R.IMUX42.NN2END1 origin:050-pip-seed !22_22 !23_22 !24_22 17_22 25_22
@ -1718,8 +1718,8 @@ INT_R.IMUX43.ER1END1 origin:050-pip-seed !23_30 18_31 22_30 24_30 25_30
INT_R.IMUX43.FAN_BOUNCE3 origin:050-pip-seed !22_30 20_30 23_30 24_30 25_30
INT_R.IMUX43.FAN_BOUNCE5 origin:050-pip-seed !23_30 20_30 22_30 24_30 25_30
INT_R.IMUX43.GFAN0 origin:049-int-imux-gfan !22_30 !23_30 !24_30 21_30 25_30
INT_R.IMUX43.LOGIC_OUTS1 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS13 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS1 origin:051-pip-imuxlout-bypalts !23_30 21_30 22_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS13 origin:051-pip-imuxlout-bypalts !22_30 21_30 23_30 24_30 25_30
INT_R.IMUX43.LOGIC_OUTS23 origin:051-pip-imuxlout-bypalts !22_30 !23_30 !25_30 21_30 24_30
INT_R.IMUX43.NE2END2 origin:050-pip-seed !22_30 !23_30 !25_30 18_31 24_30
INT_R.IMUX43.NL1END2 origin:050-pip-seed !22_30 16_30 23_30 24_30 25_30
@ -1742,9 +1742,9 @@ INT_R.IMUX44.ER1END2 origin:050-pip-seed !23_38 19_39 22_38 24_38 25_38
INT_R.IMUX44.FAN_BOUNCE1 origin:050-pip-seed !22_38 20_38 23_38 24_38 25_38
INT_R.IMUX44.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_38 20_38 22_38 24_38 25_38
INT_R.IMUX44.GFAN1 origin:049-int-imux-gfan !22_38 !23_38 !24_38 21_38 25_38
INT_R.IMUX44.LOGIC_OUTS14 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS2 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS20 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_R.IMUX44.LOGIC_OUTS14 origin:051-pip-imuxlout-bypalts !22_38 21_38 23_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS2 origin:051-pip-imuxlout-bypalts !23_38 21_38 22_38 24_38 25_38
INT_R.IMUX44.LOGIC_OUTS20 origin:051-pip-imuxlout-bypalts !22_38 !23_38 !25_38 21_38 24_38
INT_R.IMUX44.NE2END2 origin:050-pip-seed !22_38 !23_38 !25_38 17_38 24_38
INT_R.IMUX44.NL1END2 origin:050-pip-seed !22_38 16_38 23_38 24_38 25_38
INT_R.IMUX44.NN2END2 origin:050-pip-seed !22_38 !23_38 !24_38 17_38 25_38
@ -1766,9 +1766,9 @@ INT_R.IMUX45.ER1END2 origin:050-pip-seed !23_46 18_47 22_46 24_46 25_46
INT_R.IMUX45.FAN_BOUNCE3 origin:050-pip-seed !22_46 20_46 23_46 24_46 25_46
INT_R.IMUX45.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_46 20_46 22_46 24_46 25_46
INT_R.IMUX45.GFAN1 origin:049-int-imux-gfan !22_46 !23_46 !24_46 21_46 25_46
INT_R.IMUX45.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_R.IMUX45.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !22_46 21_46 23_46 24_46 25_46
INT_R.IMUX45.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_46 !23_46 !25_46 21_46 24_46
INT_R.IMUX45.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !23_46 21_46 22_46 24_46 25_46
INT_R.IMUX45.NE2END3 origin:050-pip-seed !22_46 !23_46 !25_46 18_47 24_46
INT_R.IMUX45.NL1BEG_N3 origin:050-pip-seed !22_46 16_46 23_46 24_46 25_46
INT_R.IMUX45.NN2END3 origin:050-pip-seed !22_46 !23_46 !24_46 18_47 25_46
@ -1791,8 +1791,8 @@ INT_R.IMUX46.FAN_BOUNCE_S3_0 origin:050-pip-seed !22_54 20_54 23_54 24_54 25_54
INT_R.IMUX46.FAN_BOUNCE_S3_2 origin:050-pip-seed !23_54 20_54 22_54 24_54 25_54
INT_R.IMUX46.GFAN1 origin:049-int-imux-gfan !22_54 !23_54 !24_54 21_54 25_54
INT_R.IMUX46.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !22_54 21_54 23_54 24_54 25_54
INT_R.IMUX46.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_R.IMUX46.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_R.IMUX46.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_54 !23_54 !25_54 21_54 24_54
INT_R.IMUX46.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !23_54 21_54 22_54 24_54 25_54
INT_R.IMUX46.NE2END3 origin:050-pip-seed !22_54 !23_54 !25_54 17_54 24_54
INT_R.IMUX46.NL1BEG_N3 origin:050-pip-seed !22_54 16_54 23_54 24_54 25_54
INT_R.IMUX46.NN2END3 origin:050-pip-seed !22_54 !23_54 !24_54 17_54 25_54
@ -1815,8 +1815,8 @@ INT_R.IMUX47.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_62 20_62 23_62 24_62 25_62
INT_R.IMUX47.FAN_BOUNCE_S3_6 origin:050-pip-seed !23_62 20_62 22_62 24_62 25_62
INT_R.IMUX47.GFAN1 origin:049-int-imux-gfan !22_62 !23_62 !24_62 21_62 25_62
INT_R.IMUX47.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !22_62 21_62 23_62 24_62 25_62
INT_R.IMUX47.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_R.IMUX47.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_R.IMUX47.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_62 !23_62 !25_62 21_62 24_62
INT_R.IMUX47.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !23_62 21_62 22_62 24_62 25_62
INT_R.IMUX47.NE2END_S3_0 origin:050-pip-seed !22_62 !23_62 !25_62 18_63 24_62
INT_R.IMUX47.NL1END_S3_0 origin:050-pip-seed !22_62 16_62 23_62 24_62 25_62
INT_R.IMUX47.NN2END_S2_0 origin:050-pip-seed !22_62 !23_62 !24_62 18_63 25_62
@ -1838,9 +1838,9 @@ INT_R.IMUX5.ER1END2 origin:050-pip-seed !22_41 19_40 23_41 24_41 25_41
INT_R.IMUX5.FAN_BOUNCE3 origin:050-pip-seed !23_41 21_41 22_41 24_41 25_41
INT_R.IMUX5.FAN_BOUNCE_S3_4 origin:050-pip-seed !22_41 21_41 23_41 24_41 25_41
INT_R.IMUX5.GFAN1 origin:049-int-imux-gfan !22_41 !23_41 !25_41 20_41 24_41
INT_R.IMUX5.LOGIC_OUTS10 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS16 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_R.IMUX5.LOGIC_OUTS6 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS10 origin:051-pip-imuxlout-bypalts !23_41 20_41 22_41 24_41 25_41
INT_R.IMUX5.LOGIC_OUTS16 origin:051-pip-imuxlout-bypalts !22_41 !23_41 !24_41 20_41 25_41
INT_R.IMUX5.LOGIC_OUTS6 origin:051-pip-imuxlout-bypalts !22_41 20_41 23_41 24_41 25_41
INT_R.IMUX5.NE2END2 origin:050-pip-seed !22_41 !23_41 !24_41 19_40 25_41
INT_R.IMUX5.NL1BEG_N3 origin:050-pip-seed !23_41 17_41 22_41 24_41 25_41
INT_R.IMUX5.NN2END2 origin:050-pip-seed !22_41 !23_41 !25_41 19_40 24_41
@ -1862,9 +1862,9 @@ INT_R.IMUX6.ER1END2 origin:050-pip-seed !22_49 18_48 23_49 24_49 25_49
INT_R.IMUX6.FAN_BOUNCE_S3_0 origin:050-pip-seed !23_49 21_49 22_49 24_49 25_49
INT_R.IMUX6.FAN_BOUNCE_S3_2 origin:050-pip-seed !22_49 21_49 23_49 24_49 25_49
INT_R.IMUX6.GFAN1 origin:049-int-imux-gfan !22_49 !23_49 !25_49 20_49 24_49
INT_R.IMUX6.LOGIC_OUTS11 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS17 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_R.IMUX6.LOGIC_OUTS7 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS11 origin:051-pip-imuxlout-bypalts !23_49 20_49 22_49 24_49 25_49
INT_R.IMUX6.LOGIC_OUTS17 origin:051-pip-imuxlout-bypalts !22_49 !23_49 !24_49 20_49 25_49
INT_R.IMUX6.LOGIC_OUTS7 origin:051-pip-imuxlout-bypalts !22_49 20_49 23_49 24_49 25_49
INT_R.IMUX6.NE2END3 origin:050-pip-seed !22_49 !23_49 !24_49 16_49 25_49
INT_R.IMUX6.NL1BEG_N3 origin:050-pip-seed !23_49 17_49 22_49 24_49 25_49
INT_R.IMUX6.NN2END3 origin:050-pip-seed !22_49 !23_49 !25_49 16_49 24_49
@ -1886,9 +1886,9 @@ INT_R.IMUX7.ER1END3 origin:050-pip-seed !22_57 19_56 23_57 24_57 25_57
INT_R.IMUX7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_57 21_57 22_57 24_57 25_57
INT_R.IMUX7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_57 21_57 23_57 24_57 25_57
INT_R.IMUX7.GFAN1 origin:049-int-imux-gfan !22_57 !23_57 !25_57 20_57 24_57
INT_R.IMUX7.LOGIC_OUTS15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_R.IMUX7.LOGIC_OUTS3 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_57 20_57 22_57 24_57 25_57
INT_R.IMUX7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_57 !23_57 !24_57 20_57 25_57
INT_R.IMUX7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_57 20_57 23_57 24_57 25_57
INT_R.IMUX7.NE2END3 origin:050-pip-seed !22_57 !23_57 !24_57 19_56 25_57
INT_R.IMUX7.NL1END_S3_0 origin:050-pip-seed !23_57 17_57 22_57 24_57 25_57
INT_R.IMUX7.NN2END3 origin:050-pip-seed !22_57 !23_57 !25_57 19_56 24_57
@ -1910,9 +1910,9 @@ INT_R.IMUX8.ER1END_N3_3 origin:050-pip-seed !23_02 17_02 22_02 24_02 25_02
INT_R.IMUX8.FAN_BOUNCE2 origin:050-pip-seed !23_02 20_02 22_02 24_02 25_02
INT_R.IMUX8.FAN_BOUNCE7 origin:050-pip-seed !22_02 20_02 23_02 24_02 25_02
INT_R.IMUX8.GFAN0 origin:049-int-imux-gfan !22_02 !23_02 !24_02 21_02 25_02
INT_R.IMUX8.LOGIC_OUTS0 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS0 origin:051-pip-imuxlout-bypalts !23_02 21_02 22_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS12 origin:051-pip-imuxlout-bypalts !22_02 21_02 23_02 24_02 25_02
INT_R.IMUX8.LOGIC_OUTS22 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_R.IMUX8.LOGIC_OUTS22 origin:051-pip-imuxlout-bypalts !22_02 !23_02 !25_02 21_02 24_02
INT_R.IMUX8.NE2END0 origin:050-pip-seed !22_02 !23_02 !25_02 17_02 24_02
INT_R.IMUX8.NL1END0 origin:050-pip-seed !22_02 16_02 23_02 24_02 25_02
INT_R.IMUX8.NN2END0 origin:050-pip-seed !22_02 !23_02 !24_02 17_02 25_02
@ -1934,8 +1934,8 @@ INT_R.IMUX9.ER1END0 origin:050-pip-seed !23_10 18_11 22_10 24_10 25_10
INT_R.IMUX9.FAN_BOUNCE5 origin:050-pip-seed !22_10 20_10 23_10 24_10 25_10
INT_R.IMUX9.FAN_BOUNCE6 origin:050-pip-seed !23_10 20_10 22_10 24_10 25_10
INT_R.IMUX9.GFAN0 origin:049-int-imux-gfan !22_10 !23_10 !24_10 21_10 25_10
INT_R.IMUX9.LOGIC_OUTS18 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_R.IMUX9.LOGIC_OUTS4 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_R.IMUX9.LOGIC_OUTS18 origin:051-pip-imuxlout-bypalts !22_10 !23_10 !25_10 21_10 24_10
INT_R.IMUX9.LOGIC_OUTS4 origin:051-pip-imuxlout-bypalts !23_10 21_10 22_10 24_10 25_10
INT_R.IMUX9.LOGIC_OUTS8 origin:051-pip-imuxlout-bypalts !22_10 21_10 23_10 24_10 25_10
INT_R.IMUX9.NE2END0 origin:050-pip-seed !22_10 !23_10 !25_10 16_10 24_10
INT_R.IMUX9.NL1END1 origin:050-pip-seed !22_10 16_10 23_10 24_10 25_10
@ -2173,7 +2173,7 @@ INT_R.NE6BEG2.NW6END2 origin:050-pip-seed 04_37 06_36
INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
INT_R.NE6BEG3.EE2END3 origin:050-pip-seed 03_52 05_55
INT_R.NE6BEG3.EE4END3 origin:050-pip-seed 05_52 05_55
INT_R.NE6BEG3.LH0 origin:056-pip-rem 04_54 05_52
@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17
@ -3125,7 +3125,7 @@ INT_R.SS6BEG2.LOGIC_OUTS6 origin:050-pip-seed 03_46 06_46
INT_R.SS6BEG2.LVB0 origin:056-pip-rem 04_47 06_46
INT_R.SS6BEG2.LVB12 origin:056-pip-rem 04_47 05_45
INT_R.SS6BEG2.NW2END3 origin:050-pip-seed 03_46 05_46
INT_R.SS6BEG2.NW6END3 origin:056-pip-rem 05_46 07_47
INT_R.SS6BEG2.NW6END3 origin:050-pip-seed 05_46 07_47
INT_R.SS6BEG2.SE2END2 origin:050-pip-seed 03_46 04_44
INT_R.SS6BEG2.SE6END2 origin:050-pip-seed 04_44 07_47
INT_R.SS6BEG2.SS2END2 origin:050-pip-seed 02_46 02_47
@ -3255,7 +3255,7 @@ INT_R.SW6BEG0.SW6END0 origin:050-pip-seed 03_13 05_12
INT_R.SW6BEG0.WW2END0 origin:050-pip-seed 03_12 05_15
INT_R.SW6BEG0.WW4END1 origin:050-pip-seed 05_12 05_15
INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_29 04_30
INT_R.SW6BEG1.LOGIC_OUTS13 origin:050-pip-seed 03_28 04_30
@ -3275,7 +3275,7 @@ INT_R.SW6BEG1.SW6END1 origin:050-pip-seed 03_29 05_28
INT_R.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
INT_R.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_44 04_46
INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
@ -3623,7 +3623,7 @@ INT_R.WW4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_49 07_49
INT_R.WW4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_49 04_50
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49

40
zynq7/segbits_riob33.db
View File

@ -76,13 +76,13 @@ RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56
RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52
RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42
RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 38_14 38_40 38_42 39_09 39_41
RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09
RIOB33.IOB_Y1.INOUT 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I 38_38
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
@ -106,23 +106,23 @@ RIOB33.IOB_Y1.TFF.ZINIT_Q 31_52
RIOB33.IOB_Y1.ZINV_D 28_18
RIOB33.IOB_Y1.IDELMUXE3.0 28_26
RIOB33.IOB_Y1.IFFDELMUXE3.0 29_11
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63

40
zynq7/segbits_riob33.origin_info.db
View File

@ -80,31 +80,31 @@ RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 28_34
RIOB33.IOB_Y1.IFFDELMUXE3.0 origin:035-iob-ilogic 29_11
RIOB33.IOB_Y1.INOUT origin:030-iob 31_60
RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 38_14 38_40 38_42 39_09 39_41
RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09
RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10
RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_14 38_42 39_41
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 origin:030-iob !38_02 !38_08 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_00 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 origin:030-iob !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_40 !38_42 !39_01 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 origin:030-iob !38_08 !38_10 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 origin:030-iob !38_00 !38_02 !38_40 !38_42 !39_09 !39_41 30_41 32_16 33_61 38_08 38_10 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 origin:030-iob !38_00 !38_02 !38_08 !38_10 !38_32 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 origin:030-iob !38_00 !38_02 !38_08 !38_32 !38_40 !38_42 !39_41 30_41 32_16 33_61 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_32 !38_40 !38_42 !39_01 !39_41 30_41 32_16 33_61 38_00 38_02 38_14 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !38_32 !38_40 !38_42 !39_01 !39_09 !39_41 30_41 32_16 33_61 38_08 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 origin:030-iob !38_02 !38_08 30_41 32_16 33_61 38_00 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 origin:030-iob !38_10 !39_09 30_41 32_16 33_61 38_00 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 origin:030-iob !38_08 !38_10 !39_01 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !39_09 30_41 32_16 33_61 38_02 38_08 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 origin:030-iob !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_02 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 30_41 32_16 33_61 38_08 38_10 38_14 38_32 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 origin:030-iob !38_00 !38_02 !38_08 !38_10 !38_32 !39_01 !39_09 30_41 32_16 33_61 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 origin:030-iob !38_00 !38_02 !38_08 !38_32 30_41 32_16 33_61 38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_32 !39_01 30_41 32_16 33_61 38_00 38_02 38_14 38_62 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !38_32 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_14 38_40 38_42 39_41
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 origin:030-iob !38_02 !38_08 !38_14 !38_32 !38_40 !38_42 !39_01 !39_15 !39_41 30_41 32_16 33_61 38_00 38_10 38_62 39_09 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_00 38_02 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_02 38_08 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 !39_01 !39_15 !39_41 30_41 32_16 33_61 38_00 38_02 38_62 39_09 39_63
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !38_14 !38_32 !38_40 !38_42 !39_09 !39_15 !39_41 30_41 32_16 33_61 38_08 38_10 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 origin:030-iob !38_02 !38_08 !38_14 !38_32 !39_01 !39_15 30_41 32_16 33_61 38_00 38_10 38_62 39_09 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_08 !38_10 !38_14 !38_32 !39_09 !39_15 30_41 32_16 33_61 38_00 38_02 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_00 !38_10 !38_14 !38_32 !39_09 !39_15 30_41 32_16 33_61 38_02 38_08 38_62 39_01 39_63
RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_08 !38_10 !38_14 !38_32 !39_01 !39_15 30_41 32_16 33_61 38_00 38_02 38_62 39_09 39_63
RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !38_14 !38_32 !39_09 !39_15 30_41 32_16 33_61 38_08 38_10 38_62 39_01 39_63
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !30_35
RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
RIOB33.IOB_Y1.OFF.ZINIT_Q origin:036-iob-ologic 32_30

468
zynq7/tilegrid.json
View File

@ -139433,7 +139433,14 @@
"type": "RIOB33"
},
"RIOI3_SING_X31Y0": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 126,
"grid_y": 103,
"sites": {
@ -139444,7 +139451,14 @@
"type": "RIOI3_SING"
},
"RIOI3_SING_X31Y49": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 126,
"grid_y": 53,
"sites": {
@ -139455,7 +139469,14 @@
"type": "RIOI3_SING"
},
"RIOI3_SING_X31Y50": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 0,
"words": 2
}
},
"grid_x": 126,
"grid_y": 51,
"sites": {
@ -139466,7 +139487,14 @@
"type": "RIOI3_SING"
},
"RIOI3_SING_X31Y99": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 99,
"words": 2
}
},
"grid_x": 126,
"grid_y": 1,
"sites": {
@ -139477,7 +139505,14 @@
"type": "RIOI3_SING"
},
"RIOI3_TBYTESRC_X31Y19": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 38,
"words": 4
}
},
"grid_x": 126,
"grid_y": 84,
"sites": {
@ -139491,7 +139526,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y31": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 63,
"words": 4
}
},
"grid_x": 126,
"grid_y": 71,
"sites": {
@ -139505,7 +139547,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y43": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 87,
"words": 4
}
},
"grid_x": 126,
"grid_y": 59,
"sites": {
@ -139519,7 +139568,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y57": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 14,
"words": 4
}
},
"grid_x": 126,
"grid_y": 44,
"sites": {
@ -139533,7 +139589,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y69": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 38,
"words": 4
}
},
"grid_x": 126,
"grid_y": 32,
"sites": {
@ -139547,7 +139610,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y7": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 14,
"words": 4
}
},
"grid_x": 126,
"grid_y": 96,
"sites": {
@ -139561,7 +139631,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y81": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 63,
"words": 4
}
},
"grid_x": 126,
"grid_y": 19,
"sites": {
@ -139575,7 +139652,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTESRC_X31Y93": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 87,
"words": 4
}
},
"grid_x": 126,
"grid_y": 7,
"sites": {
@ -139589,7 +139673,14 @@
"type": "RIOI3_TBYTESRC"
},
"RIOI3_TBYTETERM_X31Y13": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 26,
"words": 4
}
},
"grid_x": 126,
"grid_y": 90,
"sites": {
@ -139603,7 +139694,14 @@
"type": "RIOI3_TBYTETERM"
},
"RIOI3_TBYTETERM_X31Y37": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 75,
"words": 4
}
},
"grid_x": 126,
"grid_y": 65,
"sites": {
@ -139617,7 +139715,14 @@
"type": "RIOI3_TBYTETERM"
},
"RIOI3_TBYTETERM_X31Y63": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 26,
"words": 4
}
},
"grid_x": 126,
"grid_y": 38,
"sites": {
@ -139631,7 +139736,14 @@
"type": "RIOI3_TBYTETERM"
},
"RIOI3_TBYTETERM_X31Y87": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 75,
"words": 4
}
},
"grid_x": 126,
"grid_y": 13,
"sites": {
@ -139645,7 +139757,14 @@
"type": "RIOI3_TBYTETERM"
},
"RIOI3_X31Y1": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 2,
"words": 4
}
},
"grid_x": 126,
"grid_y": 102,
"sites": {
@ -139659,7 +139778,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y11": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 22,
"words": 4
}
},
"grid_x": 126,
"grid_y": 92,
"sites": {
@ -139673,7 +139799,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y15": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 30,
"words": 4
}
},
"grid_x": 126,
"grid_y": 88,
"sites": {
@ -139687,7 +139820,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y17": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 34,
"words": 4
}
},
"grid_x": 126,
"grid_y": 86,
"sites": {
@ -139701,7 +139841,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y21": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 42,
"words": 4
}
},
"grid_x": 126,
"grid_y": 82,
"sites": {
@ -139715,7 +139862,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y23": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 46,
"words": 4
}
},
"grid_x": 126,
"grid_y": 80,
"sites": {
@ -139729,7 +139883,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y25": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 51,
"words": 4
}
},
"grid_x": 126,
"grid_y": 77,
"sites": {
@ -139743,7 +139904,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y27": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 55,
"words": 4
}
},
"grid_x": 126,
"grid_y": 75,
"sites": {
@ -139757,7 +139925,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y29": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 59,
"words": 4
}
},
"grid_x": 126,
"grid_y": 73,
"sites": {
@ -139771,7 +139946,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y3": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 6,
"words": 4
}
},
"grid_x": 126,
"grid_y": 100,
"sites": {
@ -139785,7 +139967,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y33": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 67,
"words": 4
}
},
"grid_x": 126,
"grid_y": 69,
"sites": {
@ -139799,7 +139988,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y35": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 71,
"words": 4
}
},
"grid_x": 126,
"grid_y": 67,
"sites": {
@ -139813,7 +140009,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y39": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 79,
"words": 4
}
},
"grid_x": 126,
"grid_y": 63,
"sites": {
@ -139827,7 +140030,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y41": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 83,
"words": 4
}
},
"grid_x": 126,
"grid_y": 61,
"sites": {
@ -139841,7 +140051,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y45": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 91,
"words": 4
}
},
"grid_x": 126,
"grid_y": 57,
"sites": {
@ -139855,7 +140072,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y47": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 95,
"words": 4
}
},
"grid_x": 126,
"grid_y": 55,
"sites": {
@ -139869,7 +140093,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y5": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 10,
"words": 4
}
},
"grid_x": 126,
"grid_y": 98,
"sites": {
@ -139883,7 +140114,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y51": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 2,
"words": 4
}
},
"grid_x": 126,
"grid_y": 50,
"sites": {
@ -139897,7 +140135,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y53": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 6,
"words": 4
}
},
"grid_x": 126,
"grid_y": 48,
"sites": {
@ -139911,7 +140156,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y55": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 10,
"words": 4
}
},
"grid_x": 126,
"grid_y": 46,
"sites": {
@ -139925,7 +140177,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y59": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 18,
"words": 4
}
},
"grid_x": 126,
"grid_y": 42,
"sites": {
@ -139939,7 +140198,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y61": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 22,
"words": 4
}
},
"grid_x": 126,
"grid_y": 40,
"sites": {
@ -139953,7 +140219,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y65": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 30,
"words": 4
}
},
"grid_x": 126,
"grid_y": 36,
"sites": {
@ -139967,7 +140240,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y67": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 34,
"words": 4
}
},
"grid_x": 126,
"grid_y": 34,
"sites": {
@ -139981,7 +140261,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y71": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 42,
"words": 4
}
},
"grid_x": 126,
"grid_y": 30,
"sites": {
@ -139995,7 +140282,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y73": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 46,
"words": 4
}
},
"grid_x": 126,
"grid_y": 28,
"sites": {
@ -140009,7 +140303,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y75": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 51,
"words": 4
}
},
"grid_x": 126,
"grid_y": 25,
"sites": {
@ -140023,7 +140324,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y77": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 55,
"words": 4
}
},
"grid_x": 126,
"grid_y": 23,
"sites": {
@ -140037,7 +140345,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y79": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 59,
"words": 4
}
},
"grid_x": 126,
"grid_y": 21,
"sites": {
@ -140051,7 +140366,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y83": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 67,
"words": 4
}
},
"grid_x": 126,
"grid_y": 17,
"sites": {
@ -140065,7 +140387,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y85": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 71,
"words": 4
}
},
"grid_x": 126,
"grid_y": 15,
"sites": {
@ -140079,7 +140408,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y89": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 79,
"words": 4
}
},
"grid_x": 126,
"grid_y": 11,
"sites": {
@ -140093,7 +140429,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y9": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00401B80",
"frames": 42,
"offset": 18,
"words": 4
}
},
"grid_x": 126,
"grid_y": 94,
"sites": {
@ -140107,7 +140450,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y91": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 83,
"words": 4
}
},
"grid_x": 126,
"grid_y": 9,
"sites": {
@ -140121,7 +140471,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y95": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 91,
"words": 4
}
},
"grid_x": 126,
"grid_y": 5,
"sites": {
@ -140135,7 +140492,14 @@
"type": "RIOI3"
},
"RIOI3_X31Y97": {
"bits": {},
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00001B80",
"frames": 42,
"offset": 95,
"words": 4
}
},
"grid_x": 126,
"grid_y": 3,
"sites": {

6
zynq7/timings/BRAM_INT_INTERFACE_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRAM_INT_INTERFACE_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

336
zynq7/timings/BRAM_L.sdf
View File

@ -3,4 +3,340 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "RAMBFIFO36E1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ADDRA15L (posedge CLKARDCLKU) (-0.515::0.357))
(SETUP ADDRA15L (posedge CLKARDCLKU) (-0.357::0.515))
(HOLD ADDRAU (posedge CLKARDCLKU) (-0.566::0.360))
(SETUP ADDRAU (posedge CLKARDCLKU) (-0.360::0.566))
(HOLD ADDRB15L (posedge CLKBWRCLKU) (-0.515::0.357))
(SETUP ADDRB15L (posedge CLKBWRCLKU) (-0.357::0.515))
(HOLD ADDRBU (posedge CLKBWRCLKU) (-0.566::0.360))
(SETUP ADDRBU (posedge CLKBWRCLKU) (-0.360::0.566))
(HOLD WEAU (posedge CLKARDCLKU) (-0.532::0.197))
(SETUP WEAU (posedge CLKARDCLKU) (-0.197::0.532))
(HOLD WEBU (posedge CLKBWRCLKU) (-0.532::0.197))
(SETUP WEBU (posedge CLKBWRCLKU) (-0.197::0.532))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_L_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAL (posedge CLKARDCLKL) (-0.342::0.067))
(SETUP RSTREGAL (posedge CLKARDCLKL) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAU (posedge CLKARDCLKU) (-0.342::0.067))
(SETUP RSTREGAU (posedge CLKARDCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_L_1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge REGCLKBU) (-0.360::0.155))
(SETUP REGCEBU (posedge REGCLKBU) (-0.155::0.360))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge CLKBWRCLKU) (-0.360::0.155))
(SETUP REGCEBU (posedge CLKBWRCLKU) (-0.155::0.360))
(HOLD RSTREGBU (posedge CLKBWRCLKU) (-0.342::0.067))
(SETUP RSTREGBU (posedge CLKBWRCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1_IS18K_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH REGCLKBU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH REGCLKBU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ENARDENU (posedge CLKARDCLKU) (-0.443::0.227))
(SETUP ENARDENU (posedge CLKARDCLKU) (-0.227::0.443))
(HOLD ENBWRENU (posedge CLKBWRCLKU) (-0.443::0.227))
(SETUP ENBWRENU (posedge CLKBWRCLKU) (-0.227::0.443))
(HOLD RSTRAMAU (posedge CLKARDCLKU) (-0.359::0.453))
(SETUP RSTRAMAU (posedge CLKARDCLKU) (-0.453::0.359))
(HOLD RSTRAMBU (posedge CLKBWRCLKU) (-0.359::0.453))
(SETUP RSTRAMBU (posedge CLKBWRCLKU) (-0.453::0.359))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL ALMOSTEMPTY (0.256::0.290)(0.530::0.864))
(IOPATH CLKARDCLKL EMPTY (0.251::0.295)(0.521::0.875))
(IOPATH CLKARDCLKL RDCOUNT (0.318::0.407)(0.660::1.147))
(IOPATH CLKARDCLKL RDERR (0.269::0.313)(0.562::0.981))
(IOPATH CLKBWRCLKL ALMOSTFULL (0.268::0.313)(0.558::0.919))
(IOPATH CLKBWRCLKL FULL (0.266::0.313)(0.555::1.041))
(IOPATH CLKBWRCLKL WRCOUNT (0.340::0.395)(0.701::1.106))
(IOPATH CLKBWRCLKL WRERR (0.265::0.313)(0.549::0.914))
(IOPATH RSTRAMARSTL ALMOSTEMPTY (0.271::0.324)(0.552::0.963))
(IOPATH RSTRAMARSTL ALMOSTFULL (0.284::0.333)(0.585::0.990))
(IOPATH RSTRAMARSTL EMPTY (0.279::0.321)(0.575::0.960))
(IOPATH RSTRAMARSTL FULL (0.283::0.329)(0.586::0.983))
(IOPATH RSTRAMARSTL RDCOUNT (0.315::0.378)(0.637::1.093))
(IOPATH RSTRAMARSTL RDERR (0.292::0.338)(0.594::1.005))
(IOPATH RSTRAMARSTL WRCOUNT (0.322::0.378)(0.660::1.097))
(IOPATH RSTRAMARSTL WRERR (0.287::0.331)(0.587::0.982))
)
)
(TIMINGCHECK
(HOLD ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(SETUP ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(HOLD ENBWRENL (posedge CLKBWRCLKL) (-0.466::0.426))
(SETUP ENBWRENL (posedge CLKBWRCLKL) (-0.426::0.466))
(RECOVERY RSTRAMARSTL (posedge CLKARDCLKL) (0.957::2.368))
(REMOVAL RSTRAMARSTL (posedge CLKARDCLKL) (-2.368::-0.957))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_36_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIADIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPADIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPADIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIBDIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIBDIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPBDIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPBDIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPADOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPADOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPBDOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPBDOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKBWRCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKBWRCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
)

336
zynq7/timings/BRAM_R.sdf
View File

@ -3,4 +3,340 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "RAMBFIFO36E1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ADDRA15L (posedge CLKARDCLKU) (-0.515::0.357))
(SETUP ADDRA15L (posedge CLKARDCLKU) (-0.357::0.515))
(HOLD ADDRAU (posedge CLKARDCLKU) (-0.566::0.360))
(SETUP ADDRAU (posedge CLKARDCLKU) (-0.360::0.566))
(HOLD ADDRB15L (posedge CLKBWRCLKU) (-0.515::0.357))
(SETUP ADDRB15L (posedge CLKBWRCLKU) (-0.357::0.515))
(HOLD ADDRBU (posedge CLKBWRCLKU) (-0.566::0.360))
(SETUP ADDRBU (posedge CLKBWRCLKU) (-0.360::0.566))
(HOLD WEAU (posedge CLKARDCLKU) (-0.532::0.197))
(SETUP WEAU (posedge CLKARDCLKU) (-0.197::0.532))
(HOLD WEBU (posedge CLKBWRCLKU) (-0.532::0.197))
(SETUP WEBU (posedge CLKBWRCLKU) (-0.197::0.532))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_L_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAL (posedge CLKARDCLKL) (-0.342::0.067))
(SETUP RSTREGAL (posedge CLKARDCLKL) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOA_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEAL (posedge CLKARDCLKL) (-0.360::0.155))
(SETUP REGCEAL (posedge CLKARDCLKL) (-0.155::0.360))
(HOLD RSTREGAU (posedge CLKARDCLKU) (-0.342::0.067))
(SETUP RSTREGAU (posedge CLKARDCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_L_1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge REGCLKBU) (-0.360::0.155))
(SETUP REGCEBU (posedge REGCLKBU) (-0.155::0.360))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD REGCEBU (posedge CLKBWRCLKU) (-0.360::0.155))
(SETUP REGCEBU (posedge CLKBWRCLKU) (-0.155::0.360))
(HOLD RSTREGBU (posedge CLKBWRCLKU) (-0.342::0.067))
(SETUP RSTREGBU (posedge CLKBWRCLKU) (-0.067::0.342))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_DOB_REG_U_1_IS18K_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH REGCLKBU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH REGCLKBU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD ENARDENU (posedge CLKARDCLKU) (-0.443::0.227))
(SETUP ENARDENU (posedge CLKARDCLKU) (-0.227::0.443))
(HOLD ENBWRENU (posedge CLKBWRCLKU) (-0.443::0.227))
(SETUP ENBWRENU (posedge CLKBWRCLKU) (-0.227::0.443))
(HOLD RSTRAMAU (posedge CLKARDCLKU) (-0.359::0.453))
(SETUP RSTRAMAU (posedge CLKARDCLKU) (-0.453::0.359))
(HOLD RSTRAMBU (posedge CLKBWRCLKU) (-0.359::0.453))
(SETUP RSTRAMBU (posedge CLKBWRCLKU) (-0.453::0.359))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1_ISFIFO_TRUE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL ALMOSTEMPTY (0.256::0.290)(0.530::0.864))
(IOPATH CLKARDCLKL EMPTY (0.251::0.295)(0.521::0.875))
(IOPATH CLKARDCLKL RDCOUNT (0.318::0.407)(0.660::1.147))
(IOPATH CLKARDCLKL RDERR (0.269::0.313)(0.562::0.981))
(IOPATH CLKBWRCLKL ALMOSTFULL (0.268::0.313)(0.558::0.919))
(IOPATH CLKBWRCLKL FULL (0.266::0.313)(0.555::1.041))
(IOPATH CLKBWRCLKL WRCOUNT (0.340::0.395)(0.701::1.106))
(IOPATH CLKBWRCLKL WRERR (0.265::0.313)(0.549::0.914))
(IOPATH RSTRAMARSTL ALMOSTEMPTY (0.271::0.324)(0.552::0.963))
(IOPATH RSTRAMARSTL ALMOSTFULL (0.284::0.333)(0.585::0.990))
(IOPATH RSTRAMARSTL EMPTY (0.279::0.321)(0.575::0.960))
(IOPATH RSTRAMARSTL FULL (0.283::0.329)(0.586::0.983))
(IOPATH RSTRAMARSTL RDCOUNT (0.315::0.378)(0.637::1.093))
(IOPATH RSTRAMARSTL RDERR (0.292::0.338)(0.594::1.005))
(IOPATH RSTRAMARSTL WRCOUNT (0.322::0.378)(0.660::1.097))
(IOPATH RSTRAMARSTL WRERR (0.287::0.331)(0.587::0.982))
)
)
(TIMINGCHECK
(HOLD ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(SETUP ENARDENL (posedge CLKARDCLKL) (-0.427::0.427))
(HOLD ENBWRENL (posedge CLKBWRCLKL) (-0.466::0.426))
(SETUP ENBWRENL (posedge CLKBWRCLKL) (-0.426::0.466))
(RECOVERY RSTRAMARSTL (posedge CLKARDCLKL) (0.957::2.368))
(REMOVAL RSTRAMARSTL (posedge CLKARDCLKL) (-2.368::-0.957))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_36_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIADIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPADIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPADIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_FIFO18_WRITE_MODE_L_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIBDIL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIBDIL (posedge CLKBWRCLKL) (-0.667::0.737))
(HOLD DIPBDIPL (posedge CLKBWRCLKL) (-0.737::0.667))
(SETUP DIPBDIPL (posedge CLKBWRCLKL) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPADOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOA_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOADOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPADOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKL DOPBDOPL (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_L_FIFO18_DOB_REG_L_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKL DOBDOL (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKL DOPBDOPL (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18SDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_NC_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_RF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.405::0.241))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.241::0.405))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.405::0.241))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.241::0.405))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.405::0.241))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_RAMB18TDP_U_WRITE_MODE_U_WF_EN_ECC_READ_FALSE_EN_ECC_WRITE_FALSE")
(INSTANCE RAMBFIFO36E1)
(TIMINGCHECK
(HOLD DIADIU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIADIU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIBDIU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIBDIU (posedge CLKBWRCLKU) (-0.667::0.737))
(HOLD DIPADIPU (posedge CLKARDCLKU) (-0.737::0.667))
(SETUP DIPADIPU (posedge CLKARDCLKU) (-0.667::0.737))
(HOLD DIPBDIPU (posedge CLKBWRCLKU) (-0.737::0.667))
(SETUP DIPBDIPU (posedge CLKBWRCLKU) (-0.667::0.737))
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18SDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKARDCLKU DOPADOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOA_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKARDCLKU DOADOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKARDCLKU DOPADOPU (0.204::0.327)(0.468::0.882))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_0_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.585::1.098)(1.353::2.454))
(IOPATH CLKBWRCLKU DOPBDOPU (0.585::1.098)(1.353::2.454))
)
)
)
(CELL
(CELLTYPE "RAMBFIFO36E1RAM_MODE_U_RAMB18TDP_U_DOB_REG_U_1_EN_ECC_READ_FALSE")
(INSTANCE RAMBFIFO36E1)
(DELAY
(ABSOLUTE
(IOPATH CLKBWRCLKU DOBDOU (0.204::0.327)(0.468::0.882))
(IOPATH CLKBWRCLKU DOPBDOPU (0.204::0.327)(0.468::0.882))
)
)
)
)

6
zynq7/timings/BRKH_BRAM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_CLB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_CLK.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_CMT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_DSP_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_DSP_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/BRKH_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/B_TERM_INT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/B_TERM_INT_PSS.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/B_TERM_VBRK.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CFG_CENTER_BOT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

15
zynq7/timings/CFG_CENTER_MID.sdf
View File

@ -14,19 +14,18 @@
(CELL
(CELLTYPE "ICAP")
(INSTANCE ICAP)
(DELAY
(ABSOLUTE
(IOPATH CLK O (3.616::4.160)(4.520::5.200))
)
)
(TIMINGCHECK
(HOLD CSIB (posedge CLK) (0.000::0.000))
(SETUP CSIB (posedge CLK) (3.390::3.900))
(HOLD I (posedge CLK) (0.000::0.000))
(SETUP I (posedge CLK) (2.237::2.574))
(HOLD RDWRB (posedge CLK) (0.000::0.000))
(SETUP RDWRB (posedge CLK) (5.587::6.427))
)
)
(CELL
(CELLTYPE "ICAP_I")
(INSTANCE ICAP)
(TIMINGCHECK
(HOLD CLK (posedge CLK) (0.000::0.000))
(SETUP CLK (posedge CLK) (2.237::2.574))
)
)
)

6
zynq7/timings/CFG_SECURITY_BOT_PELE1.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CFG_SECURITY_MID_PELE1.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CFG_SECURITY_TOP_PELE1.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

42
zynq7/timings/CLBLL_L.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)

42
zynq7/timings/CLBLL_R.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)

84
zynq7/timings/CLBLM_L.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)
@ -720,15 +754,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.184::0.229)(0.455::0.565))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -737,6 +774,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.648::0.804))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -811,15 +853,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.211::0.262))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.197::0.245)(0.489::0.606))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -828,6 +873,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.247::0.308)(0.689::0.855))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -868,6 +918,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.161::0.201)(0.493::0.611))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.645::0.800))
)
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5LRAM")
(INSTANCE SLICEM/A5LUT)

84
zynq7/timings/CLBLM_R.sdf
View File

@ -246,15 +246,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.181::0.225))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.057::-0.046))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.182::0.227)(0.445::0.552))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -263,6 +266,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.616::0.764))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -279,15 +287,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.011::-0.009))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.074::-0.060))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.055::-0.045))
(SETUP INIT (posedge CLK) (0.345::0.428))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.195::0.243)(0.476::0.591))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.288::0.358))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -296,6 +307,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.246::0.306)(0.662::0.821))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.326::0.404))
(REMOVAL SR (posedge CLK) (-0.305::-0.248))
@ -336,6 +352,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.164::0.204)(0.487::0.604))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEL)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.638::0.791))
)
)
)
(CELL
(CELLTYPE "LUT5")
(INSTANCE SLICEL/A5LUT)
@ -720,15 +754,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.194::0.241))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "FF_INIT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.184::0.229)(0.455::0.565))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -737,6 +774,11 @@
(CELL
(CELLTYPE "FF_INIT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.233::0.290)(0.648::0.804))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -811,15 +853,18 @@
(TIMINGCHECK
(HOLD CE (posedge CLK) (-0.007::-0.005))
(HOLD DIN (posedge CLK) (0.211::0.262))
(HOLD INIT (posedge CLK) (-0.050::-0.041))
(SETUP CE (posedge CLK) (0.088::0.109))
(SETUP DIN (posedge CLK) (-0.074::-0.060))
(SETUP INIT (posedge CLK) (0.445::0.552))
)
)
(CELL
(CELLTYPE "REG_INIT_FF_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.197::0.245)(0.489::0.606))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.314::0.389))
(REMOVAL SR (posedge CLK) (-0.292::-0.238))
@ -828,6 +873,11 @@
(CELL
(CELLTYPE "REG_INIT_FF_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.247::0.308)(0.689::0.855))
)
)
(TIMINGCHECK
(RECOVERY SR (posedge CLK) (0.279::0.347))
(REMOVAL SR (posedge CLK) (-0.285::-0.232))
@ -868,6 +918,24 @@
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QH")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.161::0.201)(0.493::0.611))
)
)
)
(CELL
(CELLTYPE "REG_INIT_LAT_QL")
(INSTANCE SLICEM)
(DELAY
(ABSOLUTE
(IOPATH SR Q (0.198::0.246)(0.645::0.800))
)
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5LRAM")
(INSTANCE SLICEM/A5LUT)

6
zynq7/timings/CLK_BUFG_REBUF.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_FEED.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

9
zynq7/timings/CLK_HROW_BOT_R.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFHCE")
(INSTANCE BUFHCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.020::0.043)(0.081::0.132))
)
)
)
(CELL
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
(INSTANCE BUFHCE)

9
zynq7/timings/CLK_HROW_TOP_R.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFHCE")
(INSTANCE BUFHCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.020::0.043)(0.081::0.132))
)
)
)
(CELL
(CELLTYPE "BUFHCE_CE_TYPE_ASYNC")
(INSTANCE BUFHCE)

6
zynq7/timings/CLK_MTBF2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_PMV.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_PMV2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_PMV2_SVT.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_PMVIOB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/CLK_TERM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

36
zynq7/timings/CMT_FIFO_L.sdf
View File

@ -6,6 +6,24 @@
(CELL
(CELLTYPE "IN_FIFO_IN_FIFOIN_FIFO")
(INSTANCE IN_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.196::0.226)(0.462::0.531))
(IOPATH RDCLK EMPTY (0.193::0.222)(0.536::0.617))
(IOPATH RDCLK Q0 (0.142::0.163)(0.517::0.595))
(IOPATH RDCLK Q1 (0.142::0.163)(0.556::0.640))
(IOPATH RDCLK Q2 (0.150::0.173)(0.548::0.630))
(IOPATH RDCLK Q3 (0.154::0.177)(0.583::0.671))
(IOPATH RDCLK Q4 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q5 (0.142::0.163)(0.527::0.606))
(IOPATH RDCLK Q6 (0.142::0.163)(0.492::0.566))
(IOPATH RDCLK Q7 (0.151::0.174)(0.550::0.632))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH WRCLK ALMOSTFULL (0.153::0.176)(0.462::0.531))
(IOPATH WRCLK FULL (0.152::0.175)(0.665::0.765))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.080::-0.070))
(SETUP D0 (posedge WRCLK) (0.473::0.544))
@ -32,6 +50,24 @@
(CELL
(CELLTYPE "OUT_FIFO_OUT_FIFOOUT_FIFO")
(INSTANCE OUT_FIFO)
(DELAY
(ABSOLUTE
(IOPATH RDCLK ALMOSTEMPTY (0.131::0.151)(0.282::0.324))
(IOPATH RDCLK EMPTY (0.137::0.157)(0.414::0.476))
(IOPATH RDCLK Q0 (0.145::0.166)(0.586::0.674))
(IOPATH RDCLK Q1 (0.141::0.162)(0.586::0.674))
(IOPATH RDCLK Q2 (0.138::0.159)(0.586::0.674))
(IOPATH RDCLK Q3 (0.143::0.164)(0.586::0.674))
(IOPATH RDCLK SCANOUT (1.663::1.914)(1.953::2.246))
(IOPATH RDEN Q0 (0.040::0.046)(0.161::0.185))
(IOPATH RDEN Q1 (0.042::0.049)(0.168::0.193))
(IOPATH RDEN Q2 (0.032::0.036)(0.143::0.164))
(IOPATH RDEN Q3 (0.033::0.038)(0.149::0.172))
(IOPATH WRCLK ALMOSTFULL (0.138::0.159)(0.300::0.345))
(IOPATH WRCLK FULL (0.137::0.157)(0.296::0.340))
(IOPATH WRCLK SCANOUT (1.663::1.914)(1.953::2.246))
)
)
(TIMINGCHECK
(HOLD D0 (posedge WRCLK) (-0.022::-0.019))
(SETUP D0 (posedge WRCLK) (0.381::0.438))

6
zynq7/timings/CMT_PMV_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

261
zynq7/timings/CMT_TOP_L_LOWER_B.sdf
View File

@ -8,6 +8,9 @@
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH PSCLK PSDONE (0.318::0.338)(0.758::0.805))
(IOPATH RST CLKFBSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST CLKINSTOPPED (0.348::0.370)(0.549::0.583))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
@ -29,229 +32,229 @@
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_00")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_01")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT4 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN2 CLKOUT4 (0.263::0.279)(0.492::0.522))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_BUF_IN")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_BUF_IN")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN1 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUT (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKFBOUTB (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT0B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT1B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT2B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT3B (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT5 (0.255::-0.260)(0.433::-0.240))
(IOPATH CLKIN2 CLKOUT6 (0.255::-0.260)(0.433::-0.240))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_INTERNAL")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT6 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_COMPENSATION_ZHOLD")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT6 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_00")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUTB (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3B (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT6 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD")
(CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TMUX_MUX_SEL_01")
(INSTANCE MMCME2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUTB (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3B (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT6 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

36
zynq7/timings/CMT_TOP_L_LOWER_T.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))

53
zynq7/timings/CMT_TOP_L_UPPER_B.sdf
View File

@ -65,6 +65,11 @@
(IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402))
(IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198))
(IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198))
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271))
(IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708))
(IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458))
(IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487))
)
)
(TIMINGCHECK
@ -184,17 +189,6 @@
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_ADV")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH CTSBUS OCLK (0.351::0.373)(0.529::0.562))
(IOPATH DQSBUS OCLK (0.346::0.367)(0.518::0.550))
(IOPATH DTSBUS OCLK (0.137::0.145)(0.254::0.270))
)
)
)
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF")
(INSTANCE PHASER_OUT_PHY)
@ -324,6 +318,14 @@
(CELL
(CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY")
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198))
(IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291))
(IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267))
(IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358))
)
)
(TIMINGCHECK
(HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000))
(SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134))
@ -394,6 +396,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -406,6 +411,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -454,6 +462,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -466,6 +477,9 @@
(INSTANCE PHASER_OUT_PHY)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000))
(IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000))
@ -496,6 +510,23 @@
(CELL
(CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL")
(INSTANCE PHY_CONTROL)
(DELAY
(ABSOLUTE
(IOPATH MEMREFCLK AUXOUTPUT (0.265::0.305)(0.542::0.624))
(IOPATH MEMREFCLK INBURSTPENDING (0.316::0.363)(0.689::0.792))
(IOPATH MEMREFCLK INRANKA (0.306::0.353)(0.660::0.759))
(IOPATH MEMREFCLK INRANKB (0.316::0.363)(0.688::0.791))
(IOPATH MEMREFCLK INRANKC (0.319::0.367)(0.697::0.802))
(IOPATH MEMREFCLK INRANKD (0.310::0.357)(0.667::0.768))
(IOPATH MEMREFCLK OUTBURSTPENDING (0.311::0.358)(0.676::0.778))
(IOPATH MEMREFCLK PCENABLECALIB (0.265::0.305)(0.590::0.679))
(IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622))
(IOPATH MEMREFCLK TESTOUTPUT (0.504::0.579)(1.131::1.301))
(IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389))
(IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369))
(IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423))
)
)
(TIMINGCHECK
(HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233))
(SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011))

132
zynq7/timings/CMT_TOP_L_UPPER_T.sdf
View File

@ -8,6 +8,8 @@
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH DCLK DO (0.286::0.304)(0.691::0.734))
(IOPATH DCLK DRDY (0.286::0.304)(0.927::0.984))
(IOPATH RST LOCKED (3.000::3.000)(3.000::3.000))
)
)
@ -23,109 +25,109 @@
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_00")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_BUF_IN")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN2 CLKOUT5 (0.144::-0.210)(0.360::-0.140))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_01")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_EXTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH TMUX_MUX_SEL TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_BUF_IN")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_INTERNAL")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKFBOUT (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT0 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT1 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT2 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT3 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT4 (0.144::-0.210)(0.360::-0.140))
(IOPATH COMPENSATION CLKOUT5 (0.144::-0.210)(0.360::-0.140))
(IOPATH CLKIN1 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN2 CLKOUT5 (0.050::0.053)(0.083::0.088))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_EXTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_COMPENSATION_ZHOLD")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN1 CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH CLKIN2 CLKOUT5 (0.000::0.000)(0.000::0.000))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_INTERNAL")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_00")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKFBOUT (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT0 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT1 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT2 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT3 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088))
(IOPATH COMPENSATION CLKOUT5 (0.050::0.053)(0.083::0.088))
(IOPATH CLKIN1 TMUXOUT (0.527::0.560)(0.979::1.040))
(IOPATH CLKIN2 TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)
(CELL
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_ZHOLD")
(CELLTYPE "PLLE2_ADV_PLLE2_ADVPLLE2_ADV_TMUX_MUX_SEL_01")
(INSTANCE PLLE2_ADV)
(DELAY
(ABSOLUTE
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKFBOUT (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT0 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT1 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT2 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT3 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000))
(IOPATH COMPENSATION CLKOUT5 (0.000::0.000)(0.000::0.000))
(IOPATH CLKFBIN TMUXOUT (0.527::0.560)(0.979::1.040))
)
)
)

6
zynq7/timings/HCLK_BRAM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_CLB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

9
zynq7/timings/HCLK_CMT_L.sdf
View File

@ -3,6 +3,15 @@
(SDFVERSION "3.0")
(TIMESCALE 1ns)
(CELL
(CELLTYPE "BUFMRCE")
(INSTANCE BUFMRCE)
(DELAY
(ABSOLUTE
(IOPATH I O (0.033::0.035)(0.097::0.103))
)
)
)
(CELL
(CELLTYPE "BUFMRCE_CE_TYPE_SYNC_INIT_OUT_0")
(INSTANCE BUFMRCE)

6
zynq7/timings/HCLK_DSP_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_DSP_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_FEEDTHRU_1.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_FEEDTHRU_1_PELE.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_FEEDTHRU_2.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_FIFO_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_INT_INTERFACE.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_IOB.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_L.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_R.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_TERM.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

6
zynq7/timings/HCLK_VBRK.sdf
View File

@ -1,6 +0,0 @@
(DELAYFILE
(SDFVERSION "3.0")
(TIMESCALE 1ns)
)

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