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Updating DB based on "Move rempips experiment to fuzzers/056-rempips, Update database" 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2017-11-20 05:16:09 +00:00
parent a751c39fca
commit 04b399c2d1
2 changed files with 10 additions and 0 deletions
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7
artix7/segbits_int_l.db
View File

@ -1941,6 +1941,8 @@ INT_L.IMUX_L9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10
INT_L.IMUX_L9.WL1END0 !22_10 18_11 23_10 24_10 25_10
INT_L.IMUX_L9.WR1END0 !23_10 17_10 22_10 24_10 25_10
INT_L.IMUX_L9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10
INT_L.LVB_L0.SE2END3 00_51 01_42
INT_L.LV_L18.WR1END0 00_01 01_01
INT_L.NE2BEG0.EE2END0 09_04 14_04
INT_L.NE2BEG0.EE4END0 09_04 13_04
INT_L.NE2BEG0.EL1END0 09_05 12_04
@ -2029,6 +2031,7 @@ INT_L.NE6BEG0.LOGIC_OUTS_L18 04_06 06_04
INT_L.NE6BEG0.LOGIC_OUTS_L22 06_04 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L4 02_05 04_06
INT_L.NE6BEG0.LOGIC_OUTS_L8 03_04 04_06
INT_L.NE6BEG0.LV_L0 04_06 05_04
INT_L.NE6BEG0.NE2END0 02_05 03_05
INT_L.NE6BEG0.NE6END0 03_05 05_04
INT_L.NE6BEG0.NN2END0 03_04 03_05
@ -2545,6 +2548,7 @@ INT_L.NW6BEG3.LOGIC_OUTS_L17 06_50 07_51
INT_L.NW6BEG3.LOGIC_OUTS_L21 05_49 07_51
INT_L.NW6BEG3.LOGIC_OUTS_L3 03_50 05_49
INT_L.NW6BEG3.LOGIC_OUTS_L7 03_50 06_50
INT_L.NW6BEG3.LV_L18 04_51 05_49
INT_L.NW6BEG3.NE2END3 03_50 05_50
INT_L.NW6BEG3.NE6END3 04_51 05_50
INT_L.NW6BEG3.NN2END3 02_51 05_50
@ -2993,6 +2997,7 @@ INT_L.SS6BEG2.LOGIC_OUTS_L16 06_46 07_47
INT_L.SS6BEG2.LOGIC_OUTS_L2 03_46 05_45
INT_L.SS6BEG2.LOGIC_OUTS_L20 05_45 07_47
INT_L.SS6BEG2.LOGIC_OUTS_L6 03_46 06_46
INT_L.SS6BEG2.LVB_L0 04_47 06_46
INT_L.SS6BEG2.NW2END3 03_46 05_46
INT_L.SS6BEG2.NW6END3 05_46 07_47
INT_L.SS6BEG2.SE2END2 03_46 04_44
@ -3127,6 +3132,7 @@ INT_L.SW6BEG1.LOGIC_OUTS_L19 06_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L23 04_30 06_28
INT_L.SW6BEG1.LOGIC_OUTS_L5 02_29 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L9 03_28 07_29
INT_L.SW6BEG1.LV_L9 04_30 05_28
INT_L.SW6BEG1.NW2END2 02_29 05_31
INT_L.SW6BEG1.NW6END2 05_31 06_28
INT_L.SW6BEG1.SE2END1 02_29 04_29
@ -3413,6 +3419,7 @@ INT_L.WW2BEG3.WL1END3 09_63 12_62
INT_L.WW2BEG3.WR1END_S1_0 09_62 12_62
INT_L.WW2BEG3.WW2END3 11_62 14_62
INT_L.WW2BEG3.WW4END_S0_0 11_62 13_62
INT_L.WW4BEG0.LH12 05_00 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L0 02_01 04_02
INT_L.WW4BEG0.LOGIC_OUTS_L12 03_00 04_02
INT_L.WW4BEG0.LOGIC_OUTS_L18 06_00 07_01

3
artix7/segbits_int_r.db
View File

@ -1941,6 +1941,7 @@ INT_R.IMUX9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10
INT_R.IMUX9.WL1END0 !22_10 18_11 23_10 24_10 25_10
INT_R.IMUX9.WR1END0 !23_10 17_10 22_10 24_10 25_10
INT_R.IMUX9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10
INT_R.LV18.LH6 00_06 01_02
INT_R.NE2BEG0.EE2END0 09_04 14_04
INT_R.NE2BEG0.EE4END0 09_04 13_04
INT_R.NE2BEG0.EL1END0 09_05 12_04
@ -2261,6 +2262,7 @@ INT_R.NN6BEG0.LOGIC_OUTS18 06_06 07_07
INT_R.NN6BEG0.LOGIC_OUTS22 05_05 07_07
INT_R.NN6BEG0.LOGIC_OUTS4 03_06 06_06
INT_R.NN6BEG0.LOGIC_OUTS8 02_07 06_06
INT_R.NN6BEG0.LV0 04_07 06_06
INT_R.NN6BEG0.NE2END0 02_06 03_06
INT_R.NN6BEG0.NE6END0 02_06 04_07
INT_R.NN6BEG0.NN2END0 02_06 02_07
@ -3145,6 +3147,7 @@ INT_R.SW6BEG2.LOGIC_OUTS16 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS2 02_45 07_45
INT_R.SW6BEG2.LOGIC_OUTS20 06_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS6 02_45 04_46
INT_R.SW6BEG2.LVB12 05_44 07_45
INT_R.SW6BEG2.NW2END3 02_45 05_47
INT_R.SW6BEG2.NW6END3 05_47 06_44
INT_R.SW6BEG2.SE2END2 02_45 04_45