936 lines
40 KiB
Python
936 lines
40 KiB
Python
#
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# prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools
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#
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# Copyright (C) 2024 The Project Peppercorn Authors.
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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from enum import Enum
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from dataclasses import dataclass
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PLL_X_POS = 33
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PLL_Y_POS = 131
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SERDES_X_POS = 1
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SERDES_Y_POS = 131
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def max_row():
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return 131
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def max_col():
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return 163
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def num_rows():
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return max_row() + 3
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def num_cols():
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return max_col() + 3
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def is_sb(x,y):
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if (x>=-1 and x<=162 and y>=-1 and y<=130):
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return (x+1) % 2 == (y+1) % 2
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return False
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def is_sb_big(x,y):
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if (x>=-1 and x<=162 and y>=-1 and y<=130):
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if (x+1) % 2 == 1 and (y+1) % 2 == 1:
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return False if (x+1) % 4 == (y+1) % 4 else True
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if (x+1) % 2 == 0 and (y+1) % 2 == 0:
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return False if (x+1) % 4 != (y+1) % 4 else True
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return False
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def is_sb_sml(x,y):
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if (x>=-1 and x<=162 and y>=-1 and y<=130):
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if (x+1) % 2 == 1 and (y+1) % 2 == 1:
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return True if (x+1) % 4 == (y+1) % 4 else False
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if (x+1) % 2 == 0 and (y+1) % 2 == 0:
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return True if (x+1) % 4 != (y+1) % 4 else False
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return False
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def get_sb_type(x,y):
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return "SB_BIG" if is_sb_big(x,y) else "SB_SML"
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def is_cpe(x,y):
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return x>=1 and x<=160 and y>=1 and y<=128
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def is_outmux(x,y):
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return is_cpe(x,y) and (x+1) % 2 == (y+1) % 2
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def is_edge_left(x,y):
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return x==-2 and y>=1 and y<=128
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def is_edge_right(x,y):
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return x==max_col() and y>=1 and y<=128
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def is_edge_bottom(x,y):
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return y==-2 and x>=1 and x<=160
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def is_edge_top(x,y):
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return y==max_row() and x>=28 and x<=160
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def is_edge_io(x,y):
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if (y==-2 and x>=5 and x<=40): # IO Bank S3/WA
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return True
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if (y==-2 and x>=57 and x<=92): # IO Bank S1/WB
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return True
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if (y==-2 and x>=101 and x<=136): # IO Bank S2/WC
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return True
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if (x==-2 and y>=25 and y<=60): # IO Bank W1/SA
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return True
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if (x==-2 and y>=69 and y<=104): # IO Bank W2/SB
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return True
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if (x==max_col() and y>=25 and y<=60): # IO Bank E1/NA
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return True
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if (x==max_col() and y>=69 and y<=104): # IO Bank E2/NB
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return True
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if (y==max_row() and x>=57 and x<=92): # IO Bank N1/EA
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return True
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if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB
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return True
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@dataclass
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class IOName:
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bank : str
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port : str
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num : int
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def get_io_name(x,y):
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if (y==-2 and x>=5 and x<=40): # IO Bank S3/WA
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x-=5
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return IOName("S3", "A" if x % 4==0 else "B", x//4)
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if (y==-2 and x>=57 and x<=92): # IO Bank S1/WB
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x-=57
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return IOName("S1", "A" if x % 4==0 else "B", x//4)
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if (y==-2 and x>=101 and x<=136): # IO Bank S2/WC
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x-=101
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return IOName("S2", "A" if x % 4==0 else "B", x//4)
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if (x==-2 and y>=25 and y<=60): # IO Bank W1/SA
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y-=25
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return IOName("W1", "A" if y % 4==0 else "B", y//4)
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if (x==-2 and y>=69 and y<=104): # IO Bank W2/SB
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y-=69
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return IOName("W2", "A" if y % 4==0 else "B", y//4)
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if (x==max_col() and y>=25 and y<=60): # IO Bank E1/NA
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y-=25
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return IOName("E1", "A" if y % 4==0 else "B", y//4)
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if (x==max_col() and y>=69 and y<=104): # IO Bank E2/NB
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y-=69
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return IOName("E2", "A" if y % 4==0 else "B", y//4)
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if (y==max_row() and x>=57 and x<=92): # IO Bank N1/EA
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x-=57
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return IOName("N1", "A" if x % 4==0 else "B", x//4)
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if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB
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x-=101
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return IOName("N2", "A" if x % 4==0 else "B", x//4)
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def is_gpio(x,y):
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if is_edge_io(x,y):
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if (y==-2 or y==max_row()):
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return x % 2==1
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if (x==-2 or x==max_col()):
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return y % 2==1
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return False
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def is_pll(x,y):
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return x==PLL_X_POS and y==PLL_Y_POS
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def is_serdes(x,y):
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return x==SERDES_X_POS and y==SERDES_Y_POS
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def base_loc(x,y):
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return (((x-1) & ~1) + 1, ((y-1) & ~1) + 1)
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class PinType(Enum):
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INPUT = 0
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OUTPUT = 1
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INOUT = 2
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@dataclass
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class Primitive:
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name : str
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type : str
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z : int
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@dataclass
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class Pin:
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name : str
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dir : PinType
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wire_type : str
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@dataclass
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class Group:
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name : str
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type : str
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@dataclass
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class Endpoint:
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name : str
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type : str
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@dataclass
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class MUX:
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src : str
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dst : str
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name : str
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bits : int
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value : int
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invert: bool
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visible: bool
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@dataclass
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class Location:
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x : int
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y : int
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@dataclass
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class Connection:
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x : int
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y : int
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name : str
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PRIMITIVES_PINS = {
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"CPE": [
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Pin("RAM_I1" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("RAM_I2" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN5" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN6" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN7" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("IN8" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE_B"),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE_B"),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE_B"),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE_B"),
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Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("RAM_O1" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("RAM_O2" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE_B"),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE_T"),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE_T"),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE_T"),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE_T"),
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],
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"GPIO" : [
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Pin("IN1" , PinType.OUTPUT,"GPIO_WIRE"),
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Pin("IN2" , PinType.OUTPUT,"GPIO_WIRE"),
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Pin("OUT1" , PinType.INPUT, "GPIO_WIRE"),
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Pin("OUT2" , PinType.INPUT, "GPIO_WIRE"),
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Pin("OUT3" , PinType.INPUT, "GPIO_WIRE"),
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Pin("OUT4" , PinType.INPUT, "GPIO_WIRE"),
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Pin("DDR" , PinType.INPUT, "GPIO_WIRE"),
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Pin("RESET" , PinType.INPUT, "GPIO_WIRE"),
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Pin("CLOCK1", PinType.INPUT, "GPIO_WIRE"),
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Pin("CLOCK2", PinType.INPUT, "GPIO_WIRE"),
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Pin("CLOCK3", PinType.INPUT, "GPIO_WIRE"),
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Pin("CLOCK4", PinType.INPUT, "GPIO_WIRE"),
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Pin("DI" , PinType.INPUT, "GPIO_WIRE"),
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Pin("DO" , PinType.OUTPUT,"GPIO_WIRE"),
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Pin("OE" , PinType.OUTPUT,"GPIO_WIRE"),
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],
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"BUFG" : [
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Pin("I" , PinType.INPUT, "BUFG_WIRE"),
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Pin("O" , PinType.OUTPUT,"BUFG_WIRE"),
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],
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"PLL" : [
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Pin("CLK_REF", PinType.INPUT, "PLL_WIRE"),
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Pin("USR_CLK_REF", PinType.INPUT, "PLL_WIRE"),
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Pin("USR_SEL_A_B", PinType.INPUT, "PLL_WIRE"),
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Pin("CLK_FEEDBACK", PinType.INPUT, "PLL_WIRE"),
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Pin("USR_LOCKED_STDY_RST", PinType.INPUT, "PLL_WIRE"),
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Pin("CLK0", PinType.OUTPUT,"PLL_WIRE"),
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Pin("CLK90", PinType.OUTPUT,"PLL_WIRE"),
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Pin("CLK180", PinType.OUTPUT,"PLL_WIRE"),
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Pin("CLK270", PinType.OUTPUT,"PLL_WIRE"),
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Pin("CLK_REF_OUT", PinType.OUTPUT,"PLL_WIRE"),
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Pin("USR_PLL_LOCKED_STDY", PinType.OUTPUT,"PLL_WIRE"),
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Pin("USR_PLL_LOCKED", PinType.OUTPUT,"PLL_WIRE"),
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],
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}
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def get_groups_for_type(type):
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groups = []
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def create_group(name, type):
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groups.append(Group(name,type))
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if "CPE" in type:
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# CPE
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for p in range(1,13):
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create_group(f"IM_P{p:02d}", "IM")
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if "OM" in type and p>=9:
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create_group(f"OM_P{p:02d}", "OM")
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if "SB_BIG" in type:
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# SB_BIG
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for p in range(1,13):
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create_group(f"SB_BIG_P{p:02d}", "SB_BIG")
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if "SB_SML" in type:
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# SB_SML
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for p in range(1,13):
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create_group(f"SB_SML_P{p:02d}", "SB_SML")
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#if "GPIO" in type:
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# # GPIO
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if "IOES" in type:
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# IOES
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create_group("IOES", "IOES")
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if "LES" in type:
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# LES
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create_group("LES", "LES")
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if "RES" in type:
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# RES
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create_group("RES", "RES")
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if "TES" in type:
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# TES
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create_group("TES", "TES")
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if "BES" in type:
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# BES
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create_group("BES", "BES")
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return groups
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def get_primitives_for_type(type):
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primitives = []
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if "CPE" in type:
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primitives.append(Primitive("CPE","CPE",0))
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if "GPIO" in type:
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primitives.append(Primitive("GPIO","GPIO",0))
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if "PLL" in type:
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primitives.append(Primitive("BUFG0","BUFG",0))
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primitives.append(Primitive("BUFG1","BUFG",1))
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primitives.append(Primitive("BUFG2","BUFG",2))
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primitives.append(Primitive("BUFG3","BUFG",3))
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primitives.append(Primitive("PLL0","PLL",4))
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primitives.append(Primitive("PLL1","PLL",5))
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primitives.append(Primitive("PLL2","PLL",6))
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primitives.append(Primitive("PLL3","PLL",7))
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return primitives
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def get_primitive_pins(bel):
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return PRIMITIVES_PINS[bel]
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def get_endpoints_for_type(type):
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wires = []
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def create_wire(name, type):
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wires.append(Endpoint(name,type))
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for prim in get_primitives_for_type(type):
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for pin in get_primitive_pins(prim.type):
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create_wire(f"{prim.name}.{pin.name}", type=f"{pin.wire_type}")
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if "CPE" in type:
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for p in range(1,13):
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plane = f"{p:02d}"
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for i in range(8):
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create_wire(f"IM.P{plane}.D{i}", type="IM_WIRE")
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create_wire(f"IM.P{plane}.Y", type="IM_WIRE")
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if "OM" in type and p>=9:
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for i in range(4):
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create_wire(f"OM.P{plane}.D{i}", type="OM_WIRE")
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create_wire(f"OM.P{plane}.Y", type="OM_WIRE")
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if "SB_BIG" in type:
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for p in range(1,13):
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plane = f"{p:02d}"
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create_wire(f"SB_BIG.P{plane}.D0", type="SB_BIG_WIRE")
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for i in range(1,5):
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create_wire(f"SB_BIG.P{plane}.D2_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.D3_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.D4_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.D5_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.D6_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.D7_{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.Y{i}", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.YDIAG", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.X34", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.X14", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.X12", type="SB_BIG_WIRE")
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create_wire(f"SB_BIG.P{plane}.X23", type="SB_BIG_WIRE")
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for i in range(1,5):
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create_wire(f"SB_DRIVE.P{plane}.D{i}.IN", type="SB_DRIVE_WIRE")
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create_wire(f"SB_DRIVE.P{plane}.D{i}.OUT", type="SB_DRIVE_WIRE")
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if "SB_SML" in type:
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for p in range(1,13):
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plane = f"{p:02d}"
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create_wire(f"SB_SML.P{plane}.D0", type="SB_SML_WIRE")
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for i in range(1,5):
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create_wire(f"SB_SML.P{plane}.D2_{i}", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.D3_{i}", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.Y{i}", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.Y{i}_int", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.YDIAG", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.YDIAG_int", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X34", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X14", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X12", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X23", type="SB_SML_WIRE")
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if "IOES" in type:
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create_wire("IOES.IO_IN1", type="IOES_WIRE")
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create_wire("IOES.IO_IN2", type="IOES_WIRE")
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for p in range(1,13):
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plane = f"{p:02d}"
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create_wire(f"IOES.SB_IN_{plane}", type="IOES_WIRE")
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create_wire(f"IOES.ALTIN_{plane}", type="IOES_WIRE")
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if "LES" in type:
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for p in range(1,9):
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create_wire(f"LES.SB_Y3.P{p}", type="LES_WIRE")
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create_wire(f"LES.MDIE1.P{p}", type="LES_WIRE")
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for i in range(4):
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create_wire(f"LES.CLOCK{i}", type="LES_WIRE")
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create_wire("LES.CPE_CINX", type="LES_WIRE")
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create_wire("LES.CPE_PINX", type="LES_WIRE")
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if "BES" in type:
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for p in range(1,9):
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create_wire(f"BES.SB_Y4.P{p}", type="BES_WIRE")
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create_wire(f"BES.MDIE2.P{p}", type="BES_WIRE")
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for i in range(4):
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create_wire(f"BES.CLOCK{i}", type="BES_WIRE")
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create_wire("BES.P_CINY1", type="BES_WIRE")
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create_wire("BES.P_PINY1", type="BES_WIRE")
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create_wire("BES.P_CINY2", type="BES_WIRE")
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create_wire("BES.P_PINY2", type="BES_WIRE")
|
|
create_wire("BES.CPE_CINY1", type="BES_WIRE")
|
|
create_wire("BES.CPE_PINY1", type="BES_WIRE")
|
|
create_wire("BES.CPE_CINY2", type="BES_WIRE")
|
|
create_wire("BES.CPE_PINY2", type="BES_WIRE")
|
|
|
|
if "RES" in type:
|
|
create_wire("RES.CPE_RAM_O1", type="RES_WIRE")
|
|
create_wire("RES.CPE_RAM_O2", type="RES_WIRE")
|
|
create_wire("RES.CPE_COUTX", type="RES_WIRE")
|
|
create_wire("RES.CPE_POUTX", type="RES_WIRE")
|
|
for p in range(1,9):
|
|
create_wire(f"RES.SB_Y1.P{p}", type="RES_WIRE")
|
|
create_wire(f"RES.MDIE1.P{p}", type="RES_WIRE")
|
|
for i in range(4):
|
|
create_wire(f"RES.CLOCK{i}", type="RES_WIRE")
|
|
|
|
if "TES" in type:
|
|
create_wire("TES.CPE_RAM_O1", type="TES_WIRE")
|
|
create_wire("TES.CPE_RAM_O2", type="TES_WIRE")
|
|
create_wire("TES.CPE_COUTY1", type="TES_WIRE")
|
|
create_wire("TES.CPE_POUTY1", type="TES_WIRE")
|
|
create_wire("TES.CPE_COUTY2", type="TES_WIRE")
|
|
create_wire("TES.CPE_POUTY2", type="TES_WIRE")
|
|
for p in range(1,9):
|
|
create_wire(f"TES.SB_Y2.P{p}", type="TES_WIRE")
|
|
create_wire(f"TES.MDIE2.P{p}", type="TES_WIRE")
|
|
for i in range(4):
|
|
create_wire(f"TES.CLOCK{i}", type="TES_WIRE")
|
|
|
|
if "PLL" in type:
|
|
# CLKIN
|
|
create_wire("CLKIN.CLK0", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK1", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK2", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK3", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.SER_CLK", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK_REF_INT0", type="CLKIN_INT_WIRE") # internal
|
|
create_wire("CLKIN.CLK_REF_INT1", type="CLKIN_INT_WIRE") # internal
|
|
create_wire("CLKIN.CLK_REF_INT2", type="CLKIN_INT_WIRE") # internal
|
|
create_wire("CLKIN.CLK_REF_INT3", type="CLKIN_INT_WIRE") # internal
|
|
create_wire("CLKIN.CLK_REF_0", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK_REF_1", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK_REF_2", type="CLKIN_WIRE")
|
|
create_wire("CLKIN.CLK_REF_3", type="CLKIN_WIRE")
|
|
# GLBOUT
|
|
create_wire("GLBOUT.CLK0_0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK90_0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK180_0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK270_0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK_INT_0", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_SEL_INT_0", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_REF_OUT0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.USR_GLB0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.GLB0", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK0_1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK90_1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK180_1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK270_1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK_INT_1", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_SEL_INT_1", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_REF_OUT1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.USR_GLB1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.GLB1", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK0_2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK90_2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK180_2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK270_2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK_INT_2", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_SEL_INT_2", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_REF_OUT2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.USR_GLB2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.GLB2", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK0_3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK90_3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK180_3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK270_3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.CLK_INT_3", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_SEL_INT_3", type="GLBOUT_INT_WIRE")
|
|
create_wire("GLBOUT.CLK_REF_OUT3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.USR_GLB3", type="GLBOUT_WIRE")
|
|
create_wire("GLBOUT.GLB3", type="GLBOUT_WIRE")
|
|
|
|
return wires
|
|
|
|
def get_mux_connections_for_type(type):
|
|
muxes = []
|
|
def create_mux(src, dst, bits, value, invert, name = None, visible = True):
|
|
name = dst if name is None else name
|
|
muxes.append(MUX(src, dst, name, bits, value, invert, visible))
|
|
|
|
if "CPE" in type:
|
|
# CPE
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
for i in range(8):
|
|
create_mux(f"IM.P{plane}.D{i}", f"IM.P{plane}.Y", 3, i, True, f"IM.P{plane}")
|
|
if "OM" in type and p>=9:
|
|
for i in range(4):
|
|
create_mux(f"OM.P{plane}.D{i}", f"OM.P{plane}.Y", 2, i, True, f"OM.P{plane}")
|
|
|
|
if "SB_BIG" in type:
|
|
# SB_BIG
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
# Per Y output mux
|
|
for i in range(1,5):
|
|
create_mux(f"SB_BIG.P{plane}.D0", f"SB_BIG.P{plane}.Y{i}", 3, 0, True)
|
|
create_mux(f"SB_BIG.P{plane}.YDIAG", f"SB_BIG.P{plane}.Y{i}", 3, 1, True)
|
|
create_mux(f"SB_BIG.P{plane}.D2_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 2, True)
|
|
create_mux(f"SB_BIG.P{plane}.D3_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 3, True)
|
|
create_mux(f"SB_BIG.P{plane}.D4_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 4, True)
|
|
create_mux(f"SB_BIG.P{plane}.D5_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 5, True)
|
|
create_mux(f"SB_BIG.P{plane}.D6_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 6, True)
|
|
create_mux(f"SB_BIG.P{plane}.D7_{i}", f"SB_BIG.P{plane}.Y{i}", 3, 7, True)
|
|
|
|
# YDIAG output mux
|
|
create_mux(f"SB_BIG.P{plane}.Y1", f"SB_BIG.P{plane}.YDIAG", 3, 0, True)
|
|
create_mux(f"SB_BIG.P{plane}.Y2", f"SB_BIG.P{plane}.YDIAG", 3, 1, True)
|
|
create_mux(f"SB_BIG.P{plane}.Y3", f"SB_BIG.P{plane}.YDIAG", 3, 2, True)
|
|
create_mux(f"SB_BIG.P{plane}.Y4", f"SB_BIG.P{plane}.YDIAG", 3, 3, True)
|
|
create_mux(f"SB_BIG.P{plane}.X34", f"SB_BIG.P{plane}.YDIAG", 3, 4, True)
|
|
create_mux(f"SB_BIG.P{plane}.X14", f"SB_BIG.P{plane}.YDIAG", 3, 5, True)
|
|
create_mux(f"SB_BIG.P{plane}.X12", f"SB_BIG.P{plane}.YDIAG", 3, 6, True)
|
|
create_mux(f"SB_BIG.P{plane}.X23", f"SB_BIG.P{plane}.YDIAG", 3, 7, True)
|
|
|
|
for i in range(1,5):
|
|
create_mux(f"SB_DRIVE.P{plane}.D{i}.IN", f"SB_DRIVE.P{plane}.D{i}.OUT", 1, 1, False, f"SB_DRIVE.P{plane}.D{i}")
|
|
|
|
if "SB_SML" in type:
|
|
# SB_SML
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
# Per Y output mux
|
|
for i in range(1,5):
|
|
create_mux(f"SB_SML.P{plane}.D0", f"SB_SML.P{plane}.Y{i}_int", 2, 0, False, f"SB_SML.P{plane}.Y{i}")
|
|
create_mux(f"SB_SML.P{plane}.YDIAG_int",f"SB_SML.P{plane}.Y{i}_int", 2, 1, False, f"SB_SML.P{plane}.Y{i}")
|
|
create_mux(f"SB_SML.P{plane}.D2_{i}", f"SB_SML.P{plane}.Y{i}_int", 2, 2, False, f"SB_SML.P{plane}.Y{i}")
|
|
create_mux(f"SB_SML.P{plane}.D3_{i}", f"SB_SML.P{plane}.Y{i}_int", 2, 3, False, f"SB_SML.P{plane}.Y{i}")
|
|
|
|
# YDIAG output mux
|
|
create_mux(f"SB_SML.P{plane}.Y1_int", f"SB_SML.P{plane}.YDIAG_int", 3, 0, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.Y2_int", f"SB_SML.P{plane}.YDIAG_int", 3, 1, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.Y3_int", f"SB_SML.P{plane}.YDIAG_int", 3, 2, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.YDIAG_int", 3, 3, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.X34", f"SB_SML.P{plane}.YDIAG_int", 3, 4, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.X14", f"SB_SML.P{plane}.YDIAG_int", 3, 5, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.X12", f"SB_SML.P{plane}.YDIAG_int", 3, 6, False, f"SB_SML.P{plane}.YDIAG")
|
|
create_mux(f"SB_SML.P{plane}.X23", f"SB_SML.P{plane}.YDIAG_int", 3, 7, False, f"SB_SML.P{plane}.YDIAG")
|
|
|
|
create_mux(f"SB_SML.P{plane}.Y1_int", f"SB_SML.P{plane}.Y1", 1, 1, True, f"SB_SML.P{plane}.Y1_INT", False)
|
|
create_mux(f"SB_SML.P{plane}.Y2_int", f"SB_SML.P{plane}.Y2", 1, 1, True, f"SB_SML.P{plane}.Y2_INT", False)
|
|
create_mux(f"SB_SML.P{plane}.Y3_int", f"SB_SML.P{plane}.Y3", 1, 1, True, f"SB_SML.P{plane}.Y3_INT", False)
|
|
create_mux(f"SB_SML.P{plane}.Y4_int", f"SB_SML.P{plane}.Y4", 1, 1, True, f"SB_SML.P{plane}.Y4_INT", False)
|
|
create_mux(f"SB_SML.P{plane}.YDIAG_int", f"SB_SML.P{plane}.YDIAG", 1, 1, True, f"SB_SML.P{plane}.YDIAG_INT", False)
|
|
|
|
#if "GPIO" in type:
|
|
# # GPIO
|
|
if "IOES" in type:
|
|
# IOES
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
io_in = 1 if p % 2 else 2
|
|
create_mux(f"IOES.IO_IN{io_in}", f"IOES.SB_IN_{plane}", 1, 0, False)
|
|
create_mux(f"IOES.ALTIN_{plane}", f"IOES.SB_IN_{plane}", 1, 1, False)
|
|
|
|
if "PLL" in type:
|
|
create_mux("CLKIN.CLK0", "CLKIN.CLK_REF_INT0", 3, 0, False, "CLKIN.REF0")
|
|
create_mux("CLKIN.CLK1", "CLKIN.CLK_REF_INT0", 3, 1, False, "CLKIN.REF0")
|
|
create_mux("CLKIN.CLK2", "CLKIN.CLK_REF_INT0", 3, 2, False, "CLKIN.REF0")
|
|
create_mux("CLKIN.CLK3", "CLKIN.CLK_REF_INT0", 3, 3, False, "CLKIN.REF0")
|
|
create_mux("CLKIN.SER_CLK", "CLKIN.CLK_REF_INT0", 3, 4, False, "CLKIN.REF0")
|
|
create_mux("CLKIN.CLK_REF_INT0", "CLKIN.CLK_REF_0", 1, 0, False, "CLKIN.REF0_INV")
|
|
|
|
create_mux("CLKIN.CLK0", "CLKIN.CLK_REF_INT1", 3, 0, False, "CLKIN.REF1")
|
|
create_mux("CLKIN.CLK1", "CLKIN.CLK_REF_INT1", 3, 1, False, "CLKIN.REF1")
|
|
create_mux("CLKIN.CLK2", "CLKIN.CLK_REF_INT1", 3, 2, False, "CLKIN.REF1")
|
|
create_mux("CLKIN.CLK3", "CLKIN.CLK_REF_INT1", 3, 3, False, "CLKIN.REF1")
|
|
create_mux("CLKIN.SER_CLK", "CLKIN.CLK_REF_INT1", 3, 4, False, "CLKIN.REF1")
|
|
create_mux("CLKIN.CLK_REF_INT1", "CLKIN.CLK_REF_1", 1, 0, False, "CLKIN.REF1_INV")
|
|
|
|
create_mux("CLKIN.CLK0", "CLKIN.CLK_REF_INT2", 3, 0, False, "CLKIN.REF2")
|
|
create_mux("CLKIN.CLK1", "CLKIN.CLK_REF_INT2", 3, 1, False, "CLKIN.REF2")
|
|
create_mux("CLKIN.CLK2", "CLKIN.CLK_REF_INT2", 3, 2, False, "CLKIN.REF2")
|
|
create_mux("CLKIN.CLK3", "CLKIN.CLK_REF_INT2", 3, 3, False, "CLKIN.REF2")
|
|
create_mux("CLKIN.SER_CLK", "CLKIN.CLK_REF_INT2", 3, 4, False, "CLKIN.REF2")
|
|
create_mux("CLKIN.CLK_REF_INT2", "CLKIN.CLK_REF_2", 1, 0, False, "CLKIN.REF2_INV")
|
|
|
|
create_mux("CLKIN.CLK0", "CLKIN.CLK_REF_INT3", 3, 0, False, "CLKIN.REF3")
|
|
create_mux("CLKIN.CLK1", "CLKIN.CLK_REF_INT3", 3, 1, False, "CLKIN.REF3")
|
|
create_mux("CLKIN.CLK2", "CLKIN.CLK_REF_INT3", 3, 2, False, "CLKIN.REF3")
|
|
create_mux("CLKIN.CLK3", "CLKIN.CLK_REF_INT3", 3, 3, False, "CLKIN.REF3")
|
|
create_mux("CLKIN.SER_CLK", "CLKIN.CLK_REF_INT3", 3, 4, False, "CLKIN.REF3")
|
|
create_mux("CLKIN.CLK_REF_INT3", "CLKIN.CLK_REF_3", 1, 0, False, "CLKIN.REF3_INV")
|
|
|
|
# GLBOUT
|
|
|
|
create_mux("GLBOUT.CLK_REF_OUT0", "GLBOUT.CLK_INT_0", 3, 0, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK0_1", "GLBOUT.CLK_INT_0", 3, 1, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK0_2", "GLBOUT.CLK_INT_0", 3, 2, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK0_3", "GLBOUT.CLK_INT_0", 3, 3, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK0_0", "GLBOUT.CLK_INT_0", 3, 4, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK90_0", "GLBOUT.CLK_INT_0", 3, 5, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK180_0", "GLBOUT.CLK_INT_0", 3, 6, False, "GLBOUT.GLB0")
|
|
create_mux("GLBOUT.CLK270_0", "GLBOUT.CLK_INT_0", 3, 7, False, "GLBOUT.GLB0")
|
|
|
|
create_mux("GLBOUT.CLK_INT_0", "GLBOUT.CLK_SEL_INT_0", 1, 0, False, "GLBOUT.USR_GLB0")
|
|
create_mux("GLBOUT.USR_GLB0", "GLBOUT.CLK_SEL_INT_0", 1, 1, False, "GLBOUT.USR_GLB0")
|
|
|
|
create_mux("GLBOUT.CLK_SEL_INT_0", "GLBOUT.GLB0", 1, 1, False, "GLBOUT.USR_GLB0_EN")
|
|
|
|
|
|
create_mux("GLBOUT.CLK_REF_OUT1", "GLBOUT.CLK_INT_1", 3, 0, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK90_0", "GLBOUT.CLK_INT_1", 3, 1, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK90_2", "GLBOUT.CLK_INT_1", 3, 2, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK90_3", "GLBOUT.CLK_INT_1", 3, 3, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK0_1", "GLBOUT.CLK_INT_1", 3, 4, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK90_1", "GLBOUT.CLK_INT_1", 3, 5, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK180_1", "GLBOUT.CLK_INT_1", 3, 6, False, "GLBOUT.GLB1")
|
|
create_mux("GLBOUT.CLK270_1", "GLBOUT.CLK_INT_1", 3, 7, False, "GLBOUT.GLB1")
|
|
|
|
create_mux("GLBOUT.CLK_INT_1", "GLBOUT.CLK_SEL_INT_1", 1, 0, False, "GLBOUT.USR_GLB1")
|
|
create_mux("GLBOUT.USR_GLB1", "GLBOUT.CLK_SEL_INT_1", 1, 1, False, "GLBOUT.USR_GLB1")
|
|
|
|
create_mux("GLBOUT.CLK_SEL_INT_1", "GLBOUT.GLB1", 1, 1, False, "GLBOUT.USR_GLB1_EN")
|
|
|
|
create_mux("GLBOUT.CLK_REF_OUT2", "GLBOUT.CLK_INT_2", 3, 0, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK180_0", "GLBOUT.CLK_INT_2", 3, 1, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK180_1", "GLBOUT.CLK_INT_2", 3, 2, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK180_3", "GLBOUT.CLK_INT_2", 3, 3, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK0_2", "GLBOUT.CLK_INT_2", 3, 4, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK90_2", "GLBOUT.CLK_INT_2", 3, 5, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK180_2", "GLBOUT.CLK_INT_2", 3, 6, False, "GLBOUT.GLB2")
|
|
create_mux("GLBOUT.CLK270_2", "GLBOUT.CLK_INT_2", 3, 7, False, "GLBOUT.GLB2")
|
|
|
|
create_mux("GLBOUT.CLK_INT_2", "GLBOUT.CLK_SEL_INT_2", 1, 0, False, "GLBOUT.USR_GLB2")
|
|
create_mux("GLBOUT.USR_GLB2", "GLBOUT.CLK_SEL_INT_2", 1, 1, False, "GLBOUT.USR_GLB2")
|
|
|
|
create_mux("GLBOUT.CLK_SEL_INT_2", "GLBOUT.GLB2", 1, 1, False, "GLBOUT.USR_GLB2_EN")
|
|
|
|
create_mux("GLBOUT.CLK_REF_OUT3", "GLBOUT.CLK_INT_3", 3, 0, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK270_1", "GLBOUT.CLK_INT_3", 3, 1, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK270_2", "GLBOUT.CLK_INT_3", 3, 2, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK270_3", "GLBOUT.CLK_INT_3", 3, 3, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK0_3", "GLBOUT.CLK_INT_3", 3, 4, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK90_3", "GLBOUT.CLK_INT_3", 3, 5, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK180_3", "GLBOUT.CLK_INT_3", 3, 6, False, "GLBOUT.GLB3")
|
|
create_mux("GLBOUT.CLK270_3", "GLBOUT.CLK_INT_3", 3, 7, False, "GLBOUT.GLB3")
|
|
|
|
create_mux("GLBOUT.CLK_INT_3", "GLBOUT.CLK_SEL_INT_3", 1, 0, False, "GLBOUT.USR_GLB3")
|
|
create_mux("GLBOUT.USR_GLB3", "GLBOUT.CLK_SEL_INT_3", 1, 1, False, "GLBOUT.USR_GLB3")
|
|
|
|
create_mux("GLBOUT.CLK_SEL_INT_3", "GLBOUT.GLB3", 1, 1, False, "GLBOUT.USR_GLB3_EN")
|
|
|
|
return muxes
|
|
|
|
def get_tile_types(x,y):
|
|
val = list()
|
|
if is_cpe(x,y):
|
|
val.append("CPE")
|
|
val.append("IM")
|
|
if is_outmux(x,y):
|
|
val.append("OM")
|
|
|
|
if is_sb_big(x,y):
|
|
val.append("SB_BIG")
|
|
if is_sb_sml(x,y):
|
|
val.append("SB_SML")
|
|
if is_gpio(x,y):
|
|
val.append("GPIO")
|
|
if is_edge_io(x,y):
|
|
val.append("IOES")
|
|
if is_edge_top(x,y):
|
|
val.append("TES")
|
|
if is_edge_bottom(x,y):
|
|
val.append("BES")
|
|
if is_edge_left(x,y):
|
|
val.append("LES")
|
|
if is_edge_right(x,y):
|
|
val.append("RES")
|
|
if is_pll(x,y):
|
|
val.append("PLL")
|
|
if is_serdes(x,y):
|
|
val.append("SERDES")
|
|
return val
|
|
|
|
def get_tile_type(x,y):
|
|
val = get_tile_types(x,y)
|
|
if not val:
|
|
val.append("NONE")
|
|
return "_".join(val)
|
|
|
|
def get_tile_type_list():
|
|
tt = set()
|
|
for y in range(-2, max_row()+1):
|
|
for x in range(-2, max_col()+1):
|
|
tt.add(get_tile_type(x,y))
|
|
|
|
return tt
|
|
|
|
def alt_plane(dir,plane):
|
|
alt = [[5, 6, 7, 8, 1, 2, 3, 4,11,12, 9,10],
|
|
[9,10,11,12, 9,10,11,12,12,11,10, 9]]
|
|
return alt[dir][plane-1]
|
|
|
|
def prev_plane(p):
|
|
return (p-2) % 12 + 1
|
|
|
|
def next_plane(p):
|
|
return p % 12 + 1
|
|
|
|
class Die:
|
|
def __init__(self, name : str, die_x : int, die_y : int):
|
|
self.name = name
|
|
self.die_x = die_x
|
|
self.die_y = die_y
|
|
self.debug_conn = False
|
|
self.offset_x = die_x * num_cols()
|
|
self.offset_y = die_y * num_rows()
|
|
self.io_pad_names = dict()
|
|
for y in range(-2, max_row()+1):
|
|
for x in range(-2, max_col()+1):
|
|
if is_gpio(x,y):
|
|
io = get_io_name(x,y)
|
|
if io.bank not in self.io_pad_names:
|
|
self.io_pad_names[io.bank] = dict()
|
|
if io.port not in self.io_pad_names[io.bank]:
|
|
self.io_pad_names[io.bank][io.port] = dict()
|
|
if io.num not in self.io_pad_names[io.bank][io.port]:
|
|
self.io_pad_names[io.bank][io.port][io.num] = dict()
|
|
self.io_pad_names[io.bank][io.port][io.num] = Location(x + self.offset_x, y + self.offset_y)
|
|
|
|
def create_conn(self, src_x,src_y, src, dst_x, dst_y, dst):
|
|
key_val = f"{src_x + self.offset_x}/{src_y + self.offset_y}/{src}"
|
|
key = Connection(src_x + self.offset_x, src_y +self. offset_y, src)
|
|
item = Connection(dst_x + self.offset_x, dst_y + self.offset_y, dst)
|
|
if key_val not in self.conn:
|
|
self.conn[key_val] = list()
|
|
self.conn[key_val].append(key)
|
|
self.conn[key_val].append(item)
|
|
if self.debug_conn:
|
|
print(f"({src_x + self.offset_x},{src_y}) {src} => ({dst_x + self.offset_x},{dst_y + self.offset_y}) {dst}")
|
|
|
|
def create_cpe(self, x,y):
|
|
self.create_conn(x,y,"IM.P01.Y", x,y,"CPE.IN1")
|
|
self.create_conn(x,y,"IM.P02.Y", x,y,"CPE.IN2")
|
|
self.create_conn(x,y,"IM.P03.Y", x,y,"CPE.IN3")
|
|
self.create_conn(x,y,"IM.P04.Y", x,y,"CPE.IN4")
|
|
self.create_conn(x,y,"IM.P05.Y", x,y,"CPE.IN5")
|
|
self.create_conn(x,y,"IM.P06.Y", x,y,"CPE.IN6")
|
|
self.create_conn(x,y,"IM.P07.Y", x,y,"CPE.IN7")
|
|
self.create_conn(x,y,"IM.P08.Y", x,y,"CPE.IN8")
|
|
self.create_conn(x,y,"IM.P09.Y", x,y,"CPE.CLK")
|
|
self.create_conn(x,y,"IM.P10.Y", x,y,"CPE.EN")
|
|
self.create_conn(x,y,"IM.P11.Y", x,y,"CPE.SR")
|
|
if is_cpe(x,y-1):
|
|
self.create_conn(x,y-1,"CPE.COUTY1", x,y,"CPE.CINY1")
|
|
self.create_conn(x,y-1,"CPE.COUTY2", x,y,"CPE.CINY2")
|
|
self.create_conn(x,y-1,"CPE.POUTY1", x,y,"CPE.PINY1")
|
|
self.create_conn(x,y-1,"CPE.POUTY2", x,y,"CPE.PINY2")
|
|
if is_cpe(x-1,y):
|
|
self.create_conn(x-1,y,"CPE.COUTX", x,y,"CPE.CINX")
|
|
self.create_conn(x-1,y,"CPE.POUTX", x,y,"CPE.PINX")
|
|
|
|
def create_inmux(self, x,y):
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
|
|
# D0 - D3 are from nearby SBs
|
|
offset = 2 if is_sb(x,y) else 1
|
|
self.create_conn(x-offset,y,f"{get_sb_type(x-offset,y)}.P{plane}.Y1", x,y,f"IM.P{plane}.D0")
|
|
self.create_conn(x,y-offset,f"{get_sb_type(x,y-offset)}.P{plane}.Y2", x,y,f"IM.P{plane}.D1")
|
|
self.create_conn(x+offset,y,f"{get_sb_type(x+offset,y)}.P{plane}.Y3", x,y,f"IM.P{plane}.D2")
|
|
self.create_conn(x,y+offset,f"{get_sb_type(x,y+offset)}.P{plane}.Y4", x,y,f"IM.P{plane}.D3")
|
|
|
|
# D4 and D5 are from diagonal INMUX
|
|
if is_cpe(x-1,y-1):
|
|
self.create_conn(x-1,y-1,f"IM.P{plane}.Y", x,y,f"IM.P{plane}.D4")
|
|
if is_cpe(x+1,y+1):
|
|
self.create_conn(x+1,y+1,f"IM.P{plane}.Y", x,y,f"IM.P{plane}.D5")
|
|
|
|
# D6 and D7 are from alternate planes
|
|
alt = f"{alt_plane(0,p):02d}"
|
|
self.create_conn(x,y,f"IM.P{alt}.Y", x,y,f"IM.P{plane}.D6")
|
|
alt = f"{alt_plane(1,p):02d}"
|
|
self.create_conn(x,y,f"IM.P{alt}.Y", x,y,f"IM.P{plane}.D7")
|
|
|
|
def create_sb(self, x,y):
|
|
x_0,y_0 = base_loc(x,y)
|
|
sb_type = get_sb_type(x,y)
|
|
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
# Handling input D0
|
|
if is_cpe(x,y):
|
|
# Core section SBs are connected to CPE
|
|
if p < 9:
|
|
# planes 1..8
|
|
x_cpe = x_0 + (1 if (p-1) & 2 else 0)
|
|
y_cpe = y_0 + (1 if (p-1) & 1 else 0)
|
|
# alternate patterns for lower-left SB(1,1) and upper-right SB(2,2)
|
|
out = [ 2, 1, 2, 1, 1, 2, 1, 2] if x & 1 else [ 1, 2, 1, 2, 2, 1, 2, 1]
|
|
self.create_conn(x_cpe,y_cpe,f"CPE.OUT{out[p-1]}", x,y,f"{sb_type}.P{plane}.D0")
|
|
else:
|
|
# planes 9..12
|
|
self.create_conn(x,y,f"OM.P{plane}.Y", x,y,f"{sb_type}.P{plane}.D0")
|
|
# Handling GPIO connections is done in create_io
|
|
# Handling inputs D2_* till D7_*
|
|
distances = [2, 4, 8, 12, 16, 20] if is_sb_big(x,y) else [2, 4]
|
|
for i,distance in enumerate(distances):
|
|
for direction in range(4):
|
|
sb_x, sb_y = x, y
|
|
match direction:
|
|
case 0 :
|
|
sb_x -= distance
|
|
case 1 :
|
|
sb_y -= distance
|
|
case 2 :
|
|
sb_x += distance
|
|
case 3 :
|
|
sb_y += distance
|
|
if is_sb(sb_x,sb_y):
|
|
src = f"{get_sb_type(sb_x,sb_y)}.P{plane}.Y{direction+1}"
|
|
# Long distance signals are coming from SB_DRIVE
|
|
if (distance>4):
|
|
src = f"SB_DRIVE.P{plane}.D{direction+1}.OUT"
|
|
self.create_conn(sb_x,sb_y, src, x,y,f"{get_sb_type(x,y)}.P{plane}.D{i+2}_{direction+1}")
|
|
|
|
# Diagonal inputs
|
|
# X12 and X34 on edges are unconnected
|
|
if is_sb(x-1,y-1):
|
|
self.create_conn(x-1,y-1,f"{get_sb_type(x-1,y-1)}.P{plane}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X12")
|
|
if is_sb(x+1,y+1):
|
|
self.create_conn(x+1,y+1,f"{get_sb_type(x+1,y+1)}.P{plane}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X34")
|
|
self.create_conn(x,y,f"{get_sb_type(x,y)}.P{prev_plane(p):02d}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X14")
|
|
self.create_conn(x,y,f"{get_sb_type(x,y)}.P{next_plane(p):02d}.YDIAG", x,y,f"{get_sb_type(x,y)}.P{plane}.X23")
|
|
|
|
def create_outmux(self, x,y):
|
|
x_0,y_0 = base_loc(x,y)
|
|
for p in range(9,13):
|
|
plane = f"{p:02d}"
|
|
# alternating patters depending of plane and outmux position
|
|
outputs = [2, 2, 1, 1] if p % 2 == x & 1 else [1, 1, 2, 2]
|
|
self.create_conn(x_0, y_0, f"CPE.OUT{outputs[0]}", x,y, f"OM.P{plane}.D0")
|
|
self.create_conn(x_0, y_0+1, f"CPE.OUT{outputs[1]}", x,y, f"OM.P{plane}.D1")
|
|
self.create_conn(x_0+1, y_0, f"CPE.OUT{outputs[2]}", x,y, f"OM.P{plane}.D2")
|
|
self.create_conn(x_0+1, y_0+1, f"CPE.OUT{outputs[3]}", x,y, f"OM.P{plane}.D3")
|
|
|
|
def create_io(self, x,y):
|
|
cpe_x, cpe_y = gpio_x, gpio_y = sb_x, sb_y = x, y
|
|
alt = False
|
|
if is_edge_left(sb_x,sb_y):
|
|
output = "Y3"
|
|
cpe_x += 3
|
|
if is_sb(sb_x+1,sb_y):
|
|
sb_x += 1
|
|
else:
|
|
sb_x += 2
|
|
gpio_y -= 1
|
|
alt = True
|
|
elif is_edge_right(sb_x,sb_y):
|
|
output = "Y1"
|
|
cpe_x -= 3
|
|
if is_sb(sb_x-1,sb_y):
|
|
sb_x -= 1
|
|
gpio_y -= 1
|
|
alt = True
|
|
else:
|
|
sb_x -= 2
|
|
elif is_edge_bottom(sb_x,sb_y):
|
|
output = "Y4"
|
|
cpe_y += 3
|
|
if is_sb(sb_x,sb_y+1):
|
|
sb_y += 1
|
|
else:
|
|
sb_y += 2
|
|
gpio_x -= 1
|
|
alt = True
|
|
else:
|
|
output = "Y2"
|
|
cpe_y -= 3
|
|
if is_sb(sb_x,sb_y-1):
|
|
sb_y -= 1
|
|
gpio_x -= 1
|
|
alt = True
|
|
else:
|
|
sb_y -= 2
|
|
|
|
for p in range(1,13):
|
|
plane = f"{p:02d}"
|
|
self.create_conn(sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.{output}", x,y, f"IOES.ALTIN_{plane}")
|
|
self.create_conn(x,y, f"IOES.SB_IN_{plane}", sb_x,sb_y,f"{get_sb_type(sb_x,sb_y)}.P{plane}.D0")
|
|
self.create_conn(gpio_x,gpio_y,"GPIO.IN1", x,y, "IOES.IO_IN1")
|
|
self.create_conn(gpio_x,gpio_y,"GPIO.IN2", x,y, "IOES.IO_IN2")
|
|
|
|
if alt:
|
|
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O1", gpio_x,gpio_y,"GPIO.OUT3")
|
|
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O2", gpio_x,gpio_y,"GPIO.OUT4")
|
|
else:
|
|
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O1", gpio_x,gpio_y,"GPIO.OUT1")
|
|
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O2", gpio_x,gpio_y,"GPIO.OUT2")
|
|
|
|
def create_pll(self):
|
|
self.create_conn(-2, 101, "GPIO.IN1", PLL_X_POS, PLL_Y_POS, "CLKIN.CLK0")
|
|
|
|
def create_in_die_connections(self, conn):
|
|
self.conn = conn
|
|
for y in range(-2, max_row()+1):
|
|
for x in range(-2, max_col()+1):
|
|
if is_cpe(x,y):
|
|
self.create_cpe(x,y)
|
|
self.create_inmux(x,y)
|
|
if is_outmux(x,y):
|
|
self.create_outmux(x,y)
|
|
if is_sb(x,y):
|
|
self.create_sb(x,y)
|
|
if is_edge_io(x,y):
|
|
self.create_io(x,y)
|
|
self.create_pll()
|
|
|
|
|