Miodrag Milanovic d814a80c66 Fixed PLL wires		2025-03-10 09:49:28 +01:00
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__init__.py	Start modeling chip die	2024-12-09 10:57:04 +01:00
chip.py	Add DDR connections	2025-02-06 08:56:32 +01:00
die.py	Fixed PLL wires	2025-03-10 09:49:28 +01:00