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prjpeppercorn
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prjpeppercorn/gatemate
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Miodrag Milanovic cd9c9b3e3b Added serdes and use real ram port names 2025-03-04 13:10:40 +01:00
..
__init__.py Start modeling chip die 2024-12-09 10:57:04 +01:00
chip.py Add DDR connections 2025-02-06 08:56:32 +01:00
die.py Added serdes and use real ram port names 2025-03-04 13:10:40 +01:00