Miodrag Milanovic
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e7ca710859
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small change in model
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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d68f6fb08b
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Add CPE_COMP and CPE_CPLINES
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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6e63a05636
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Resolve name conflicts
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2983a7f4ff
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Bump database version
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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78ac740eee
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Cleanup
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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aff4544421
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Cleanups
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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c27ceac7a0
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Added CPOUT and MUXOUT
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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4ba2a563a1
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Update primitives z locations
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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497e5cc2a1
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C_2D_IN flag
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2bdf4065c0
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Add comb to seq connection
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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1a1a3488f7
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Improved model of CPE
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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ff2445f353
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Add D2D support
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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08b35c4538
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Add DDR pin information
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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2aa7ef65ba
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Add in tile position
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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a0afc3aea3
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Fixed wrong bank mapping
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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04a2dc2dc3
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Support reading multi die bitstreams
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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84c5734c9c
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clangformat
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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aacc795393
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Write proper multi die bitstream
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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58a098407b
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Bump version to 1.2
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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b5dda7196f
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Add PAD connections so we do not loose that info
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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dfc6458d5a
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Use _ as separator for PLL CFGs
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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83785af4ea
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GLBOUT and PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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f4ab570a39
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PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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bce9877556
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Create CLKIN and GLBOUT as primitives
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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8e3c659210
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Download only with delay files
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2025-06-05 07:00:12 +02:00 |
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Miodrag Milanovic
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5b9b1d013e
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Add timing modification delays
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2025-06-02 11:18:16 +02:00 |
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Miodrag Milanovic
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7800a49b4d
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Export database version
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2025-05-27 15:23:16 +02:00 |
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Miodrag Milanovic
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91eca20d10
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Add timing information from dly files
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2025-05-27 15:21:14 +02:00 |
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Miodrag Milanovic
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eb77def664
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Removed pins that can not be addressed
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2025-05-15 10:28:21 +02:00 |
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Miodrag Milanovic
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415de01bbe
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Extract SERDES config
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2025-04-30 09:57:28 +02:00 |
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Miodrag Milanovic
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69ed9f73ab
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Switch to standard type
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2025-04-28 17:38:40 +02:00 |
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Miodrag Milanovic
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adc3f7b133
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Support SERDES in bitstream
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2025-04-04 10:53:12 +02:00 |
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Miodrag Milanovic
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d79df6a1e0
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Fix due to documentation error
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2025-04-03 09:46:27 +02:00 |
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Miodrag Milanovic
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599b7a8c9c
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Store relative constraints in chipdb
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2025-04-02 13:53:34 +02:00 |
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Miodrag Milanovic
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7288755e01
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Fix direction
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2025-03-22 14:12:09 +01:00 |
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Miodrag Milanovic
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9ccc8588c0
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RAM configuration bits
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2025-03-21 10:01:41 +01:00 |
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Miodrag Milanovic
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dd3591cfa9
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Group RAM data 40 bytes per row
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2025-03-20 12:50:18 +01:00 |
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Miodrag Milanovic
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2645240bf9
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Add flags for clock source
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2025-03-18 09:20:12 +01:00 |
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Miodrag Milanovic
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74197786e5
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Export pad bank information
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2025-03-13 12:12:40 +01:00 |
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Miodrag Milanovic
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d9313105b4
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Remove some virtual pins
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2025-03-11 15:52:39 +01:00 |
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Miodrag Milanovic
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6bcef60680
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Remove GPIO reset signal
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2025-03-10 11:16:15 +01:00 |
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Miodrag Milanovic
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d814a80c66
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Fixed PLL wires
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2025-03-10 09:49:28 +01:00 |
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Miodrag Milanovic
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8e0cb69fd7
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Off by one PLL config creating error
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2025-03-07 09:57:56 +01:00 |
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Miodrag Milanovic
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f7491ee70d
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Update SERDES pin names
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2025-03-07 09:17:15 +01:00 |
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Miodrag Milanovic
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b8d2d4a45a
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Update DDR_I for S1-3
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2025-03-07 09:05:48 +01:00 |
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Miodrag Milanovic
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405cda1585
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Added CFG_CTRL
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2025-03-04 14:58:54 +01:00 |
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Miodrag Milanovic
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cd9c9b3e3b
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Added serdes and use real ram port names
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2025-03-04 13:10:40 +01:00 |
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Miodrag Milanovic
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4a2de30408
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Add missing GPIO clock signals
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2025-03-04 11:31:40 +01:00 |
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Miodrag Milanovic
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e0dc4ed695
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Added RAM block connections
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2025-03-04 10:53:08 +01:00 |
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Miodrag Milanovic
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7bb1399132
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add alternate CPE inputs
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2025-02-24 08:18:58 +01:00 |