Miodrag Milanovic
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f081ba87cb
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Bump version to 1.9
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2025-10-17 11:56:29 +02:00 |
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Miodrag Milanovic
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867835f7bb
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Better naming for D2D and pass trough TES as on hardware
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2025-10-07 13:11:27 +02:00 |
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Miodrag Milanovic
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781780f017
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Fix TES and RES
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2025-10-07 12:24:43 +02:00 |
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Miodrag Milanovic
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36f6b5eec4
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Bump version to 1.8
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2025-09-23 08:08:07 +02:00 |
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Miodrag Milanovic
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dda08d7bcd
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Use proper timing info
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2025-09-12 10:02:38 +02:00 |
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Miodrag Milanovic
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8dfe05b5c5
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put back old delay values
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2025-09-11 16:45:42 +02:00 |
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Miodrag Milanovic
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5bae9cae91
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del_dummy is default delay
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2025-09-11 15:21:09 +02:00 |
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Miodrag Milanovic
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5a03c49c49
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sortout multidie connections
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2025-09-11 15:07:57 +02:00 |
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Miodrag Milanovic
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81bb1c5cb8
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additional wires for IO and CLK for SB_BIG/SML
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2025-09-11 14:58:21 +02:00 |
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Miodrag Milanovic
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3aec20a773
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use sam delay
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2025-09-11 14:11:47 +02:00 |
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Miodrag Milanovic
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eae068fa3e
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fix
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2025-09-11 11:49:06 +02:00 |
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Miodrag Milanovic
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d4f1bea09d
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convert some connections to pips
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2025-09-11 10:34:34 +02:00 |
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Miodrag Milanovic
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56c2bed294
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Cleanup BRAM
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2025-09-04 15:57:16 +02:00 |
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Miodrag Milanovic
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f6654f83a7
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bump chipdb
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2025-09-02 14:04:37 +02:00 |
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Miodrag Milanovic
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0747679717
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Add bridge
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2025-09-02 08:07:43 +02:00 |
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Miodrag Milanovic
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d04286b39a
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bump database version
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2025-08-29 14:57:41 +02:00 |
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Miodrag Milanovic
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b8c59f9f80
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Cleanup
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2025-08-29 14:47:59 +02:00 |
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Miodrag Milanovic
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74265fd1b8
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Split BRAMs into halfs
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2025-08-28 15:09:49 +02:00 |
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Miodrag Milanovic
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6ad315609d
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Bump database version
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2025-08-14 11:53:29 +02:00 |
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Miodrag Milanovic
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10b52f37f1
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Added IOSEL
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2025-08-13 15:49:44 +02:00 |
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Miodrag Milanovic
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0fb182de18
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rename to match port names
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2025-08-13 12:52:04 +02:00 |
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Miodrag Milanovic
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7d94d89855
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Fix direction
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2025-08-13 12:51:33 +02:00 |
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Miodrag Milanovic
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c89ea91209
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Preps for MX8 support
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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a08f3ddba4
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Added few more connections
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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37e6d93a30
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Connect upper and lower L2T4
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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e7ca710859
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small change in model
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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d68f6fb08b
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Add CPE_COMP and CPE_CPLINES
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2983a7f4ff
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Bump database version
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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78ac740eee
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Cleanup
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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aff4544421
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Cleanups
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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c27ceac7a0
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Added CPOUT and MUXOUT
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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4ba2a563a1
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Update primitives z locations
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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497e5cc2a1
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C_2D_IN flag
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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2bdf4065c0
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Add comb to seq connection
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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1a1a3488f7
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Improved model of CPE
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2025-07-07 10:12:59 +02:00 |
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Miodrag Milanovic
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ff2445f353
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Add D2D support
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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08b35c4538
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Add DDR pin information
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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2aa7ef65ba
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Add in tile position
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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a0afc3aea3
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Fixed wrong bank mapping
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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58a098407b
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Bump version to 1.2
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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b5dda7196f
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Add PAD connections so we do not loose that info
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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83785af4ea
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GLBOUT and PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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f4ab570a39
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PLL fixes
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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bce9877556
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Create CLKIN and GLBOUT as primitives
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2025-06-18 08:31:49 +02:00 |
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Miodrag Milanovic
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5b9b1d013e
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Add timing modification delays
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2025-06-02 11:18:16 +02:00 |
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Miodrag Milanovic
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7800a49b4d
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Export database version
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2025-05-27 15:23:16 +02:00 |
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Miodrag Milanovic
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91eca20d10
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Add timing information from dly files
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2025-05-27 15:21:14 +02:00 |
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Miodrag Milanovic
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eb77def664
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Removed pins that can not be addressed
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2025-05-15 10:28:21 +02:00 |
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Miodrag Milanovic
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599b7a8c9c
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Store relative constraints in chipdb
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2025-04-02 13:53:34 +02:00 |
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Miodrag Milanovic
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7288755e01
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Fix direction
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2025-03-22 14:12:09 +01:00 |