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prjpeppercorn
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Removed pins that can not be addressed

This commit is contained in:
Miodrag Milanovic 2025-05-15 10:28:21 +02:00
parent 415de01bbe
commit eb77def664
1 changed files with 0 additions and 291 deletions
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291
gatemate/die.py
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@ -906,198 +906,6 @@ PRIMITIVES_PINS = {
Pin("FRD_ADDRX[14]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FRD_ADDR[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FRD_ADDRX[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_WRAO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_WRAI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_CAS_WRBO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_WRBI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_CAS_BMAO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_BMAI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_CAS_BMBO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_BMBI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_CAS_RDAO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_RDAI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_CAS_RDBO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_CAS_RDBI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[0]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[1]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[2]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[3]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[4]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[5]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[6]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[7]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[8]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[9]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[10]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[11]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[12]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[13]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[14]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAO[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[0]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[1]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[2]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[3]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[4]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[5]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[6]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[7]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[8]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[9]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[10]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[11]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[12]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[13]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[14]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAI[15]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[0]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[1]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[2]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[3]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[4]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[5]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[6]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[7]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[8]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[9]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[10]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[11]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[12]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[13]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[14]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRAO[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[0]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[1]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[2]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[3]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[4]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[5]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[6]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[7]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[8]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[9]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[10]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[11]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[12]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[13]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[14]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRAI[15]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[0]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[1]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[2]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[3]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[4]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[5]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[6]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[7]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[8]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[9]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[10]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[11]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[12]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[13]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[14]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBO[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[0]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[1]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[2]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[3]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[4]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[5]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[6]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[7]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[8]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[9]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[10]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[11]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[12]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[13]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[14]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBI[15]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[0]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[1]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[2]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[3]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[4]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[5]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[6]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[7]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[8]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[9]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[10]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[11]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[12]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[13]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[14]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LADDRBO[15]", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[0]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[1]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[2]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[3]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[4]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[5]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[6]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[7]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[8]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[9]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[10]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[11]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[12]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[13]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[14]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UADDRBI[15]", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA0CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA0CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA0ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA0ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA0WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA0WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA0CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA0CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA0ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA0ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA0WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA0WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA1CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA1CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA1ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA1ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UA1WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LA1WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA1CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA1CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA1ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA1ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LA1WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UA1WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB0CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB0CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB0ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB0ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB0WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB0WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB0CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB0CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB0ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB0ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB0WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB0WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB1CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB1CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB1ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB1ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_UB1WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_LB1WEI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB1CLKO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB1CLKI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB1ENO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB1ENI", PinType.INPUT,"RAM_WIRE"),
Pin("FORW_LB1WEO", PinType.OUTPUT,"RAM_WIRE"),
Pin("FORW_UB1WEI", PinType.INPUT,"RAM_WIRE"),
Pin("CLOCK1", PinType.INPUT,"RAM_WIRE"),
Pin("CLOCK2", PinType.INPUT,"RAM_WIRE"),
Pin("CLOCK3", PinType.INPUT,"RAM_WIRE"),
Pin("CLOCK4", PinType.INPUT,"RAM_WIRE"),
],
"SERDES" : [
Pin("TX_DETECT_RX_I", PinType.INPUT,"SERDES_WIRE"),
@ -3581,105 +3389,6 @@ class Die:
def create_ram(self, x, y):
self.create_ram_io_conn("RAM", "RAM", x, y)
if is_ram(x,y-16):
self.create_conn(x,y,"RAM.FORW_CAS_WRAO", x,y-16,"RAM.FORW_CAS_WRAI")
self.create_conn(x,y,"RAM.FORW_CAS_WRBO", x,y-16,"RAM.FORW_CAS_WRBI")
self.create_conn(x,y,"RAM.FORW_CAS_BMAO", x,y-16,"RAM.FORW_CAS_BMAI")
self.create_conn(x,y,"RAM.FORW_CAS_BMBO", x,y-16,"RAM.FORW_CAS_BMBI")
self.create_conn(x,y,"RAM.FORW_CAS_RDAO", x,y-16,"RAM.FORW_CAS_RDAI")
self.create_conn(x,y,"RAM.FORW_CAS_RDBO", x,y-16,"RAM.FORW_CAS_RDBI")
self.create_conn(x,y,"RAM.FORW_UADDRAO[0]", x,y-16,"RAM.FORW_UADDRAI[0]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[1]", x,y-16,"RAM.FORW_UADDRAI[1]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[2]", x,y-16,"RAM.FORW_UADDRAI[2]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[3]", x,y-16,"RAM.FORW_UADDRAI[3]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[4]", x,y-16,"RAM.FORW_UADDRAI[4]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[5]", x,y-16,"RAM.FORW_UADDRAI[5]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[6]", x,y-16,"RAM.FORW_UADDRAI[6]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[7]", x,y-16,"RAM.FORW_UADDRAI[7]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[8]", x,y-16,"RAM.FORW_UADDRAI[8]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[9]", x,y-16,"RAM.FORW_UADDRAI[9]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[10]", x,y-16,"RAM.FORW_UADDRAI[10]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[11]", x,y-16,"RAM.FORW_UADDRAI[11]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[12]", x,y-16,"RAM.FORW_UADDRAI[12]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[13]", x,y-16,"RAM.FORW_UADDRAI[13]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[14]", x,y-16,"RAM.FORW_UADDRAI[14]")
self.create_conn(x,y,"RAM.FORW_UADDRAO[15]", x,y-16,"RAM.FORW_UADDRAI[15]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[0]", x,y-16,"RAM.FORW_LADDRAI[0]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[1]", x,y-16,"RAM.FORW_LADDRAI[1]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[2]", x,y-16,"RAM.FORW_LADDRAI[2]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[3]", x,y-16,"RAM.FORW_LADDRAI[3]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[4]", x,y-16,"RAM.FORW_LADDRAI[4]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[5]", x,y-16,"RAM.FORW_LADDRAI[5]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[6]", x,y-16,"RAM.FORW_LADDRAI[6]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[7]", x,y-16,"RAM.FORW_LADDRAI[7]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[8]", x,y-16,"RAM.FORW_LADDRAI[8]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[9]", x,y-16,"RAM.FORW_LADDRAI[9]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[10]", x,y-16,"RAM.FORW_LADDRAI[10]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[11]", x,y-16,"RAM.FORW_LADDRAI[11]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[12]", x,y-16,"RAM.FORW_LADDRAI[12]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[13]", x,y-16,"RAM.FORW_LADDRAI[13]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[14]", x,y-16,"RAM.FORW_LADDRAI[14]")
self.create_conn(x,y,"RAM.FORW_LADDRAO[15]", x,y-16,"RAM.FORW_LADDRAI[15]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[0]", x,y-16,"RAM.FORW_UADDRBI[0]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[1]", x,y-16,"RAM.FORW_UADDRBI[1]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[2]", x,y-16,"RAM.FORW_UADDRBI[2]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[3]", x,y-16,"RAM.FORW_UADDRBI[3]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[4]", x,y-16,"RAM.FORW_UADDRBI[4]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[5]", x,y-16,"RAM.FORW_UADDRBI[5]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[6]", x,y-16,"RAM.FORW_UADDRBI[6]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[7]", x,y-16,"RAM.FORW_UADDRBI[7]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[8]", x,y-16,"RAM.FORW_UADDRBI[8]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[9]", x,y-16,"RAM.FORW_UADDRBI[9]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[10]", x,y-16,"RAM.FORW_UADDRBI[10]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[11]", x,y-16,"RAM.FORW_UADDRBI[11]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[12]", x,y-16,"RAM.FORW_UADDRBI[12]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[13]", x,y-16,"RAM.FORW_UADDRBI[13]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[14]", x,y-16,"RAM.FORW_UADDRBI[14]")
self.create_conn(x,y,"RAM.FORW_UADDRBO[15]", x,y-16,"RAM.FORW_UADDRBI[15]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[0]", x,y-16,"RAM.FORW_LADDRBI[0]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[1]", x,y-16,"RAM.FORW_LADDRBI[1]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[2]", x,y-16,"RAM.FORW_LADDRBI[2]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[3]", x,y-16,"RAM.FORW_LADDRBI[3]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[4]", x,y-16,"RAM.FORW_LADDRBI[4]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[5]", x,y-16,"RAM.FORW_LADDRBI[5]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[6]", x,y-16,"RAM.FORW_LADDRBI[6]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[7]", x,y-16,"RAM.FORW_LADDRBI[7]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[8]", x,y-16,"RAM.FORW_LADDRBI[8]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[9]", x,y-16,"RAM.FORW_LADDRBI[9]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[10]", x,y-16,"RAM.FORW_LADDRBI[10]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[11]", x,y-16,"RAM.FORW_LADDRBI[11]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[12]", x,y-16,"RAM.FORW_LADDRBI[12]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[13]", x,y-16,"RAM.FORW_LADDRBI[13]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[14]", x,y-16,"RAM.FORW_LADDRBI[14]")
self.create_conn(x,y,"RAM.FORW_LADDRBO[15]", x,y-16,"RAM.FORW_LADDRBI[15]")
self.create_conn(x,y,"RAM.FORW_UA0CLKO", x,y-16,"RAM.FORW_UA0CLKI")
self.create_conn(x,y,"RAM.FORW_UA0ENO", x,y-16,"RAM.FORW_UA0ENI")
self.create_conn(x,y,"RAM.FORW_UA0WEO", x,y-16,"RAM.FORW_UA0WEI")
self.create_conn(x,y,"RAM.FORW_LA0CLKO", x,y-16,"RAM.FORW_LA0CLKI")
self.create_conn(x,y,"RAM.FORW_LA0ENO", x,y-16,"RAM.FORW_LA0ENI")
self.create_conn(x,y,"RAM.FORW_LA0WEO", x,y-16,"RAM.FORW_LA0WEI")
self.create_conn(x,y,"RAM.FORW_UA1CLKO", x,y-16,"RAM.FORW_UA1CLKI")
self.create_conn(x,y,"RAM.FORW_UA1ENO", x,y-16,"RAM.FORW_UA1ENI")
self.create_conn(x,y,"RAM.FORW_UA1WEO", x,y-16,"RAM.FORW_UA1WEI")
self.create_conn(x,y,"RAM.FORW_LA1CLKO", x,y-16,"RAM.FORW_LA1CLKI")
self.create_conn(x,y,"RAM.FORW_LA1ENO", x,y-16,"RAM.FORW_LA1ENI")
self.create_conn(x,y,"RAM.FORW_LA1WEO", x,y-16,"RAM.FORW_LA1WEI")
self.create_conn(x,y,"RAM.FORW_UB0CLKO", x,y-16,"RAM.FORW_UB0CLKI")
self.create_conn(x,y,"RAM.FORW_UB0ENO", x,y-16,"RAM.FORW_UB0ENI")
self.create_conn(x,y,"RAM.FORW_UB0WEO", x,y-16,"RAM.FORW_UB0WEI")
self.create_conn(x,y,"RAM.FORW_LB0CLKO", x,y-16,"RAM.FORW_LB0CLKI")
self.create_conn(x,y,"RAM.FORW_LB0ENO", x,y-16,"RAM.FORW_LB0ENI")
self.create_conn(x,y,"RAM.FORW_LB0WEO", x,y-16,"RAM.FORW_LB0WEI")
self.create_conn(x,y,"RAM.FORW_UB1CLKO", x,y-16,"RAM.FORW_UB1CLKI")
self.create_conn(x,y,"RAM.FORW_UB1ENO", x,y-16,"RAM.FORW_UB1ENI")
self.create_conn(x,y,"RAM.FORW_UB1WEO", x,y-16,"RAM.FORW_UB1WEI")
self.create_conn(x,y,"RAM.FORW_LB1CLKO", x,y-16,"RAM.FORW_LB1CLKI")
self.create_conn(x,y,"RAM.FORW_LB1ENO", x,y-16,"RAM.FORW_LB1ENI")
self.create_conn(x,y,"RAM.FORW_LB1WEO", x,y-16,"RAM.FORW_LB1WEI")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, y, "RAM.CLOCK1")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, y, "RAM.CLOCK2")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, y, "RAM.CLOCK3")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, y, "RAM.CLOCK4")
def create_in_die_connections(self, conn):
self.conn = conn