add GPIO
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parent
f4d2de3359
commit
c5e7893710
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@ -115,6 +115,21 @@ CPE_PINS = {
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"POUTY2" : PinType.OUTPUT
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"POUTY2" : PinType.OUTPUT
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}
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}
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GPIO_PINS = {
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"IN1" : PinType.OUTPUT,
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"IN2" : PinType.OUTPUT,
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"OUT1" : PinType.INPUT,
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"OUT2" : PinType.INPUT,
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"OUT3" : PinType.INPUT,
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"OUT4" : PinType.INPUT,
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"DDR" : PinType.INPUT,
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"RESET" : PinType.INPUT,
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"CLOCK1" : PinType.INPUT,
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"CLOCK2" : PinType.INPUT,
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"CLOCK3" : PinType.INPUT,
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"CLOCK4" : PinType.INPUT,
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}
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def get_groups_for_type(type):
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def get_groups_for_type(type):
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groups = []
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groups = []
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def create_group(name, type):
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def create_group(name, type):
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@ -142,11 +157,15 @@ def get_groups_for_type(type):
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def get_bels_for_type(type):
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def get_bels_for_type(type):
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if type.startswith("CPE"):
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if type.startswith("CPE"):
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return [{"name":"CPE", "type":"CPE", "z":0}]
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return [{"name":"CPE", "type":"CPE", "z":0}]
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if "GPIO" in type:
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return [{"name":"GPIO", "type":"GPIO", "z":0}]
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return []
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return []
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def get_bel_pins(bel):
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def get_bel_pins(bel):
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if bel == "CPE":
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if bel == "CPE":
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return CPE_PINS.items()
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return CPE_PINS.items()
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elif bel == "GPIO":
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return GPIO_PINS.items()
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return []
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return []
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@ -236,8 +255,21 @@ def get_endpoints_for_type(type):
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create_wire(f"SB_SML.P{plane}.X14", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X14", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X12", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X12", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X23", type="SB_SML_WIRE")
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create_wire(f"SB_SML.P{plane}.X23", type="SB_SML_WIRE")
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#if "GPIO" in type:
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if "GPIO" in type:
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# # GPIO
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# GPIO
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create_wire("GPIO.IN1", type="GPIO_WIRE")
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create_wire("GPIO.IN2", type="GPIO_WIRE")
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create_wire("GPIO.OUT1", type="GPIO_WIRE")
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create_wire("GPIO.OUT2", type="GPIO_WIRE")
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create_wire("GPIO.OUT3", type="GPIO_WIRE")
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create_wire("GPIO.OUT4", type="GPIO_WIRE")
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create_wire("GPIO.DDR", type="GPIO_WIRE")
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create_wire("GPIO.RESET", type="GPIO_WIRE")
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create_wire("GPIO.CLOCK1", type="GPIO_WIRE")
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create_wire("GPIO.CLOCK2", type="GPIO_WIRE")
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create_wire("GPIO.CLOCK3", type="GPIO_WIRE")
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create_wire("GPIO.CLOCK4", type="GPIO_WIRE")
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#if "EDGE_IO" in type:
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#if "EDGE_IO" in type:
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# # EDGE_IO
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# # EDGE_IO
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return wires
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return wires
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