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prjpeppercorn
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Add missing GPIO clock signals

This commit is contained in:
Miodrag Milanovic 2025-03-04 11:31:40 +01:00
parent e0dc4ed695
commit 4a2de30408
1 changed files with 4 additions and 0 deletions
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4
gatemate/die.py
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@ -2076,6 +2076,10 @@ class Die:
else:
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O1", gpio_x,gpio_y,"GPIO.OUT1")
self.create_conn(cpe_x, cpe_y, "CPE.RAM_O2", gpio_x,gpio_y,"GPIO.OUT2")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", gpio_x, gpio_y, "GPIO.CLOCK1")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", gpio_x, gpio_y, "GPIO.CLOCK2")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", gpio_x, gpio_y, "GPIO.CLOCK3")
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", gpio_x, gpio_y, "GPIO.CLOCK4")
def create_pll(self):
# GPIO_W2_A[8] CLK0