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Connect upper and lower L2T4

This commit is contained in:
Miodrag Milanovic 2025-07-03 14:07:19 +02:00 committed by Miodrag Milanović
parent e7ca710859
commit 37e6d93a30
1 changed files with 7 additions and 0 deletions
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7
gatemate/die.py
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@ -272,6 +272,7 @@ PRIMITIVES_PINS = {
Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True), Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
Pin("COMBIN" ,PinType.INPUT, "CPE_WIRE", True),
Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("CPOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
Pin("MUXOUT" ,PinType.OUTPUT, "CPE_WIRE", True), Pin("MUXOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
@ -2454,6 +2455,8 @@ def get_pin_connection_name(prim, pin):
return "CPE.IN7_int" return "CPE.IN7_int"
case "IN4": case "IN4":
return "CPE.IN8_int" return "CPE.IN8_int"
case "COMBIN":
return "CPE.COMBIN_int"
case _: case _:
return f"CPE.{pin.name}" return f"CPE.{pin.name}"
elif prim.type == "CPE_LT_FULL": elif prim.type == "CPE_LT_FULL":
@ -2570,6 +2573,7 @@ def get_endpoints_for_type(type):
create_wire("CPE.COMPOUT_IN_int", type="CPE_WIRE_INT") create_wire("CPE.COMPOUT_IN_int", type="CPE_WIRE_INT")
create_wire("CPE.CPOUT1_int", type="CPE_WIRE_INT") create_wire("CPE.CPOUT1_int", type="CPE_WIRE_INT")
create_wire("CPE.CPOUT2_int", type="CPE_WIRE_INT") create_wire("CPE.CPOUT2_int", type="CPE_WIRE_INT")
create_wire("CPE.COMBIN_int", type="CPE_WIRE_INT")
create_wire("CPE.DIN1_int", type="CPE_WIRE_INT") create_wire("CPE.DIN1_int", type="CPE_WIRE_INT")
create_wire("CPE.DIN2_int", type="CPE_WIRE_INT") create_wire("CPE.DIN2_int", type="CPE_WIRE_INT")
create_wire("CPE.DOUT1_int", type="CPE_WIRE_INT") create_wire("CPE.DOUT1_int", type="CPE_WIRE_INT")
@ -2776,6 +2780,9 @@ def get_mux_connections_for_type(type):
create_mux("CPE.OUT1_int", "CPE.OUT1", 1, 0, False, visible=False, delay="del_dummy") create_mux("CPE.OUT1_int", "CPE.OUT1", 1, 0, False, visible=False, delay="del_dummy")
create_mux("CPE.OUT2_int", "CPE.OUT2", 1, 0, False, visible=False, delay="del_dummy") create_mux("CPE.OUT2_int", "CPE.OUT2", 1, 0, False, visible=False, delay="del_dummy")
# Connecting upper and lower L2T4
create_mux("CPE.COMBOUT2_int", "CPE.COMBIN_int", 1, 0, False, visible=False, delay="del_dummy")
if "SB_BIG" in type: if "SB_BIG" in type:
# SB_BIG # SB_BIG
for p in range(1,13): for p in range(1,13):