Add package pads
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@ -87,6 +87,35 @@ def is_edge_io(x,y):
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if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB
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if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB
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return True
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return True
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def get_io_name(x,y):
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if (y==-2 and x>=5 and x<=40): # IO Bank S3/WA
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x-=5
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return f"IO_WA_{("A" if x % 4==0 else "B")}{x//4}"
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if (y==-2 and x>=57 and x<=92): # IO Bank S1/WB
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x-=57
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return f"IO_WB_{("A" if x % 4==0 else "B")}{x//4}"
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if (y==-2 and x>=101 and x<=136): # IO Bank S2/WC
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x-=101
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return f"IO_WC_{("A" if x % 4==0 else "B")}{x//4}"
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if (x==-2 and y>=25 and y<=60): # IO Bank W1/SA
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y-=25
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return f"IO_SA_{("A" if y % 4==0 else "B")}{y//4}"
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if (x==-2 and y>=69 and y<=104): # IO Bank W2/SB
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y-=69
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return f"IO_SB_{("A" if y % 4==0 else "B")}{y//4}"
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if (x==max_col() and y>=25 and y<=60): # IO Bank E1/NA
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y-=25
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return f"IO_NA_{("A" if y % 4==0 else "B")}{y//4}"
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if (x==max_col() and y>=69 and y<=104): # IO Bank E2/NB
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y-=69
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return f"IO_NB_{("A" if y % 4==0 else "B")}{y//4}"
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if (y==max_row() and x>=57 and x<=92): # IO Bank N1/EA
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x-=57
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return f"IO_EA_{("A" if x % 4==0 else "B")}{x//4}"
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if (y==max_row() and x>=101 and x<=136): # IO Bank N2/EB
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x-=101
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return f"IO_EB_{("A" if x % 4==0 else "B")}{x//4}"
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def is_gpio(x,y):
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def is_gpio(x,y):
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if is_edge_io(x,y):
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if is_edge_io(x,y):
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if (y==-2 or y==max_row()):
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if (y==-2 or y==max_row()):
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@ -140,6 +169,15 @@ class Connection:
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y : int
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y : int
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name : str
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name : str
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@dataclass
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class Pad:
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x : int
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y : int
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name : str
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bel : str
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function : str
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bank : int
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PRIMITIVES_PINS = {
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PRIMITIVES_PINS = {
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"CPE": [
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"CPE": [
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Pin("RAM_I1" ,PinType.INPUT, "CPE_WIRE_L"),
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Pin("RAM_I1" ,PinType.INPUT, "CPE_WIRE_L"),
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@ -657,3 +695,11 @@ def get_connections():
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if is_edge_io(x,y):
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if is_edge_io(x,y):
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create_io(x,y)
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create_io(x,y)
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return conn.items()
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return conn.items()
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def get_package_pads():
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pads = []
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for y in range(-2, max_row()+1):
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for x in range(-2, max_col()+1):
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if is_gpio(x,y):
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pads.append(Pad(x,y,get_io_name(x,y),"GPIO","",0))
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return pads
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