565 lines
20 KiB
Python
565 lines
20 KiB
Python
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#
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# prjpeppercorn -- GateMate FPGAs Bitstream Documentation and Tools
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#
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# Copyright (C) 2024 The Project Peppercorn Authors.
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import zlib
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import struct
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from dataclasses import dataclass
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from typing import List
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@dataclass
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class T_delay_tri:
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min: int
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typ: int
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max: int
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@staticmethod
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def from_bytes(data: bytes) -> 'T_delay_tri':
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min_val, typ_val, max_val = struct.unpack('<3i', data)
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return T_delay_tri(min_val, typ_val, max_val)
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@dataclass
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class T_delay:
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rise: T_delay_tri
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fall: T_delay_tri
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@staticmethod
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def from_bytes(data: bytes) -> 'T_delay':
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rise = T_delay_tri.from_bytes(data[:12])
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fall = T_delay_tri.from_bytes(data[12:24])
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return T_delay(rise, fall)
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@dataclass
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class Tpin_pair:
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i: int
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o_or_clk: int # Represents either 'o' or 'clk' depending on the boolean case
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@dataclass
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class Tentry_rec:
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pins: Tpin_pair
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entry_no: int
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@dataclass
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class Tdel_entry:
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key: int
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edge1: int
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edge2: int
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time1: T_delay_tri
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time2: T_delay_tri
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@dataclass
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class TRAM_del_rec:
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iopath: List[Tentry_rec]
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setuphold: List[Tentry_rec]
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width: List[Tentry_rec]
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del_entry: List[Tdel_entry]
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@dataclass
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class Tdel_rec:
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val: T_delay
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conf_mux: int
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name: str
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x: int
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y: int
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plane: int
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dir: int
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inv: int
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cnt: int
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con_type: int
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@staticmethod
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def from_bytes(data: memoryview, offset: int) -> ('Tdel_rec', int):
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val = T_delay.from_bytes(data[offset:offset + 24])
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offset += 24
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conf_mux = struct.unpack_from('<i', data, offset)[0]
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offset += 4
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strlen = data[offset]
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offset += 1
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name = data[offset:offset + strlen].decode('ascii')
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offset += 23 # alignment added as well
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x, y, plane, dir, inv, cnt = struct.unpack_from('<6i', data, offset)
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offset += 24
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con_type_val = data[offset]
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offset += 4
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return Tdel_rec(val, conf_mux, name, x, y, plane, dir, inv, cnt, con_type_val), offset
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@dataclass
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class Tdel_rec_tri:
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val: T_delay_tri
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conf_mux: int
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name: str
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x: int
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y: int
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@staticmethod
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def from_bytes(mv: memoryview, offset: int) -> ('Tdel_rec_tri', int):
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val = T_delay_tri.from_bytes(mv[offset:offset+12])
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offset += 12
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conf_mux = struct.unpack_from('<i', mv, offset)[0]
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offset += 4
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strlen = mv[offset]
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offset += 1
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name = mv[offset:offset + strlen].decode('ascii')
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offset += 23
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x, y = struct.unpack_from('<2i', mv, offset)
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offset += 8
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return Tdel_rec_tri(val, conf_mux, name, x, y), offset
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def read_SB_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
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SB_del_tile_arr = []
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for i1 in range(4): # [1..4]
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level1 = []
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for i2 in range(8): # [1..8]
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level2 = []
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for i3 in range(4): # [1..4]
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level3 = []
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for i4 in range(12): # [1..12]
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level4 = []
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for i5 in range(5): # [0..4]
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level5 = []
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for i6 in range(8): # [0..7]
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chunk = mv[offset:offset + 24]
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if len(chunk) < 24:
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raise EOFError("Unexpected end of data")
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delay = T_delay.from_bytes(chunk)
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offset += 24
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level5.append(delay)
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level4.append(level5)
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level3.append(level4)
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level2.append(level3)
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level1.append(level2)
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SB_del_tile_arr.append(level1)
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return SB_del_tile_arr, offset
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@dataclass
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class ExtraTimingDelays:
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skew_report_del: int
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fix_skew_del: int
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del_rec_0: Tdel_rec
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del_min_route_SB: Tdel_rec
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del_violation_common: Tdel_rec_tri
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del_dummy: Tdel_rec
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del_Hold_D_L: Tdel_rec_tri
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del_Hold_RAM: Tdel_rec_tri
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del_Setup_D_L: Tdel_rec_tri
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del_Setup_RAM: Tdel_rec_tri
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del_Hold_SN_RN: Tdel_rec_tri
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del_Setup_SN_RN: Tdel_rec_tri
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del_Hold_RN_SN: Tdel_rec_tri
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del_Setup_RN_SN: Tdel_rec_tri
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del_bot_couty2: Tdel_rec
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del_bot_glb_couty2: Tdel_rec
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del_bot_SB_couty2: Tdel_rec
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del_bot_pouty2: Tdel_rec
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del_bot_glb_pouty2: Tdel_rec
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del_bot_SB_pouty2: Tdel_rec
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del_left_couty2: Tdel_rec
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del_left_glb_couty2: Tdel_rec
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del_left_SB_couty2: Tdel_rec
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del_left_pouty2: Tdel_rec
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del_left_glb_pouty2: Tdel_rec
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del_left_SB_pouty2: Tdel_rec
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del_inp: List[Tdel_rec]
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del_CPE_out_mux: List[Tdel_rec]
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del_CPE_CP_Q: Tdel_rec
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del_CPE_S_Q: Tdel_rec
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del_CPE_R_Q: Tdel_rec
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del_CPE_D_Q: Tdel_rec
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del_RAM_CLK_DO: Tdel_rec
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del_GLBOUT_sb_big: Tdel_rec
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del_sb_drv: Tdel_rec
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del_CP_carry_path: Tdel_rec
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del_CP_prop_path: Tdel_rec
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del_special_RAM_I: Tdel_rec
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del_RAMO_xOBF: Tdel_rec
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del_GLBOUT_IO_SEL: Tdel_rec
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del_IO_SEL_Q_out: Tdel_rec
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del_IO_SEL_Q_in: Tdel_rec
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in_delayline_per_stage: Tdel_rec
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out_delayline_per_stage: Tdel_rec
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del_IBF: Tdel_rec
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del_OBF: Tdel_rec
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del_r_OBF: Tdel_rec
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del_TOBF_ctrl: Tdel_rec
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del_LVDS_IBF: Tdel_rec
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del_LVDS_OBF: Tdel_rec
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del_LVDS_r_OBF: Tdel_rec
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del_LVDS_TOBF_ctrl: Tdel_rec
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del_CP_clkin: Tdel_rec
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del_CP_enin: Tdel_rec
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del_preplace: Tdel_rec
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del_CPE_timing_mod: List[Tdel_rec]
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@staticmethod
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def from_bytes(mv: memoryview, offset: int) -> ('ExtraTimingDelays', int):
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skew_report_del, fix_skew_del = struct.unpack_from('<2i', mv, offset)
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offset += 8
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del_rec_0, offset = Tdel_rec.from_bytes(mv, offset)
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del_min_route_SB, offset = Tdel_rec.from_bytes(mv, offset)
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del_violation_common, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_dummy, offset = Tdel_rec.from_bytes(mv, offset)
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del_Hold_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Hold_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Setup_D_L, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Setup_RAM, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Hold_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Setup_SN_RN, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Hold_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_Setup_RN_SN, offset = Tdel_rec_tri.from_bytes(mv, offset)
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del_bot_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_bot_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_bot_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_bot_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_bot_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_bot_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_glb_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_SB_couty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_glb_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_left_SB_pouty2, offset = Tdel_rec.from_bytes(mv, offset)
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del_inp = []
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for _ in range(8):
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rec, offset = Tdel_rec.from_bytes(mv, offset)
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del_inp.append(rec)
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del_CPE_out_mux = []
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for _ in range(4):
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rec, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_out_mux.append(rec)
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del_CPE_CP_Q, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_S_Q, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_R_Q, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_D_Q, offset = Tdel_rec.from_bytes(mv, offset)
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del_RAM_CLK_DO, offset = Tdel_rec.from_bytes(mv, offset)
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del_GLBOUT_sb_big, offset = Tdel_rec.from_bytes(mv, offset)
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del_sb_drv, offset = Tdel_rec.from_bytes(mv, offset)
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del_CP_carry_path, offset = Tdel_rec.from_bytes(mv, offset)
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del_CP_prop_path, offset = Tdel_rec.from_bytes(mv, offset)
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del_special_RAM_I, offset = Tdel_rec.from_bytes(mv, offset)
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del_RAMO_xOBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_GLBOUT_IO_SEL, offset = Tdel_rec.from_bytes(mv, offset)
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del_IO_SEL_Q_out, offset = Tdel_rec.from_bytes(mv, offset)
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del_IO_SEL_Q_in, offset = Tdel_rec.from_bytes(mv, offset)
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in_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset)
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out_delayline_per_stage, offset = Tdel_rec.from_bytes(mv, offset)
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del_IBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_OBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_r_OBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset)
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del_LVDS_IBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_LVDS_OBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_LVDS_r_OBF, offset = Tdel_rec.from_bytes(mv, offset)
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del_LVDS_TOBF_ctrl, offset = Tdel_rec.from_bytes(mv, offset)
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del_CP_clkin, offset = Tdel_rec.from_bytes(mv, offset)
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del_CP_enin, offset = Tdel_rec.from_bytes(mv, offset)
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del_preplace, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_timing_mod = []
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for _ in range(42):
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rec, offset = Tdel_rec.from_bytes(mv, offset)
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del_CPE_timing_mod.append(rec)
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return ExtraTimingDelays(
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skew_report_del, fix_skew_del,
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del_rec_0, del_min_route_SB,
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del_violation_common, del_dummy,
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del_Hold_D_L, del_Hold_RAM, del_Setup_D_L, del_Setup_RAM,
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del_Hold_SN_RN, del_Setup_SN_RN, del_Hold_RN_SN, del_Setup_RN_SN,
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del_bot_couty2, del_bot_glb_couty2, del_bot_SB_couty2,
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del_bot_pouty2, del_bot_glb_pouty2, del_bot_SB_pouty2,
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del_left_couty2, del_left_glb_couty2, del_left_SB_couty2,
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del_left_pouty2, del_left_glb_pouty2, del_left_SB_pouty2,
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del_inp, del_CPE_out_mux,
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del_CPE_CP_Q, del_CPE_S_Q, del_CPE_R_Q, del_CPE_D_Q,
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del_RAM_CLK_DO, del_GLBOUT_sb_big, del_sb_drv,
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del_CP_carry_path, del_CP_prop_path,
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del_special_RAM_I, del_RAMO_xOBF,
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del_GLBOUT_IO_SEL, del_IO_SEL_Q_out, del_IO_SEL_Q_in,
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in_delayline_per_stage, out_delayline_per_stage,
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del_IBF, del_OBF, del_r_OBF, del_TOBF_ctrl,
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del_LVDS_IBF, del_LVDS_OBF, del_LVDS_r_OBF, del_LVDS_TOBF_ctrl,
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del_CP_clkin, del_CP_enin, del_preplace,
|
||
|
|
del_CPE_timing_mod
|
||
|
|
), offset
|
||
|
|
|
||
|
|
def read_IM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(2): # [1..2]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(8): # [1..8]
|
||
|
|
level2 = []
|
||
|
|
for i3 in range(8): # [1..8]
|
||
|
|
level3 = []
|
||
|
|
for i4 in range(12): # [1..12]
|
||
|
|
level4 = []
|
||
|
|
for i5 in range(8): # [0..7]
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset+24])
|
||
|
|
offset += 24
|
||
|
|
level4.append(delay)
|
||
|
|
level3.append(level4)
|
||
|
|
level2.append(level3)
|
||
|
|
level1.append(level2)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_OM_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(8): # [1..8]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(8): # [1..8]
|
||
|
|
level2 = []
|
||
|
|
for i3 in range(4): # [9..12]
|
||
|
|
level3 = []
|
||
|
|
for i4 in range(4): # [0..3]
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset+24])
|
||
|
|
offset += 24
|
||
|
|
level3.append(delay)
|
||
|
|
level2.append(level3)
|
||
|
|
level1.append(level2)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_CPE_del_tile_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(10): # [0..9]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(19): # [1..19]
|
||
|
|
level2 = []
|
||
|
|
for i3 in range(10): # [1..10]
|
||
|
|
rec, offset = Tdel_rec.from_bytes(mv, offset)
|
||
|
|
level2.append(rec)
|
||
|
|
level1.append(level2)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_SB_del_rim_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(165): # [-2..162]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(4): # [1..4]
|
||
|
|
level2 = []
|
||
|
|
for i3 in range(12): # [1..12]
|
||
|
|
level3 = []
|
||
|
|
for i4 in range(5): # [0..4]
|
||
|
|
level4 = []
|
||
|
|
for i5 in range(8): # [0..7]
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset+24])
|
||
|
|
offset += 24
|
||
|
|
level4.append(delay)
|
||
|
|
level3.append(level4)
|
||
|
|
level2.append(level3)
|
||
|
|
level1.append(level2)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_Edge_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(165): # [-2..162]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(4): # [1..4]
|
||
|
|
level2 = []
|
||
|
|
for i3 in range(24): # [1..24]
|
||
|
|
level3 = []
|
||
|
|
for i4 in range(8): # [1..8]
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset+24])
|
||
|
|
offset += 24
|
||
|
|
level3.append(delay)
|
||
|
|
level2.append(level3)
|
||
|
|
level1.append(level2)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_IO_SEL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(11): # [1..11]
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(4): # [1..4]
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset+24])
|
||
|
|
offset += 24
|
||
|
|
level1.append(delay)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_CLKIN_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(7):
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(4):
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset + 24])
|
||
|
|
offset += 24
|
||
|
|
level1.append(delay)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_GLBOUT_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(28):
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(8):
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset + 24])
|
||
|
|
offset += 24
|
||
|
|
level1.append(delay)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_PLL_del_arr_from_bytes(mv: memoryview, offset: int) -> (List, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(7):
|
||
|
|
level1 = []
|
||
|
|
for i2 in range(6):
|
||
|
|
delay = T_delay.from_bytes(mv[offset:offset + 24])
|
||
|
|
offset += 24
|
||
|
|
level1.append(delay)
|
||
|
|
result.append(level1)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
def read_Tentry_rec_from_bytes(data: memoryview, offset: int) -> ('Tentry_rec', int):
|
||
|
|
pins_i, pins_val, entry_no = struct.unpack_from('<3h', data, offset)
|
||
|
|
return Tentry_rec(Tpin_pair(pins_i, pins_val), entry_no), offset + 6
|
||
|
|
|
||
|
|
def read_Tdel_entry_from_bytes(data: memoryview, offset: int) -> ('Tdel_entry', int):
|
||
|
|
key, edge1, edge2 = struct.unpack_from('<3i', data, offset)
|
||
|
|
time1 = T_delay_tri.from_bytes(data[offset + 12:offset + 24])
|
||
|
|
time2 = T_delay_tri.from_bytes(data[offset + 24:offset + 36])
|
||
|
|
return Tdel_entry(key, edge1, edge2, time1, time2), offset + 36
|
||
|
|
|
||
|
|
def read_TRAM_del_rec_from_bytes(mv: memoryview, offset: int) -> (TRAM_del_rec, int):
|
||
|
|
iopath = []
|
||
|
|
for _ in range(3001):
|
||
|
|
entry, offset = read_Tentry_rec_from_bytes(mv, offset)
|
||
|
|
iopath.append(entry)
|
||
|
|
|
||
|
|
setuphold = []
|
||
|
|
for _ in range(8001):
|
||
|
|
entry, offset = read_Tentry_rec_from_bytes(mv, offset)
|
||
|
|
setuphold.append(entry)
|
||
|
|
|
||
|
|
width = []
|
||
|
|
for _ in range(51):
|
||
|
|
entry, offset = read_Tentry_rec_from_bytes(mv, offset)
|
||
|
|
width.append(entry)
|
||
|
|
|
||
|
|
del_entry = []
|
||
|
|
offset += 2 # alignment added
|
||
|
|
for _ in range(101):
|
||
|
|
entry, offset = read_Tdel_entry_from_bytes(mv, offset)
|
||
|
|
del_entry.append(entry)
|
||
|
|
|
||
|
|
return TRAM_del_rec(iopath, setuphold, width, del_entry), offset
|
||
|
|
|
||
|
|
def read_IO_SEL_io_coef_from_bytes(mv: memoryview, offset: int) -> (list, int):
|
||
|
|
result = []
|
||
|
|
for i1 in range(4): # [1..4]
|
||
|
|
row = []
|
||
|
|
for i2 in range(27): # [1..27]
|
||
|
|
value = struct.unpack_from('<d', mv, offset)[0] # '<d' = little-endian double
|
||
|
|
offset += 8
|
||
|
|
row.append(value)
|
||
|
|
result.append(row)
|
||
|
|
return result, offset
|
||
|
|
|
||
|
|
@dataclass
|
||
|
|
class Tdel_all_rec:
|
||
|
|
SB_del_tile_arr: List[List[List[List[List[List[T_delay]]]]]]
|
||
|
|
IM_del_tile_arr: List[List[List[List[List[T_delay]]]]]
|
||
|
|
OM_del_tile_arr: List[List[List[List[T_delay]]]]
|
||
|
|
CPE_del_tile_arr: List[List[List[Tdel_rec]]]
|
||
|
|
SB_del_rim_arr: List[List[List[List[List[T_delay]]]]]
|
||
|
|
Edge_del_arr: List[List[List[List[T_delay]]]]
|
||
|
|
IO_SEL_del_arr: List[List[T_delay]]
|
||
|
|
CLKIN_del_arr: List[List[T_delay]]
|
||
|
|
GLBOUT_del_arr: List[List[T_delay]]
|
||
|
|
PLL_del_arr: List[List[T_delay]]
|
||
|
|
FPGA_ram_del_1: TRAM_del_rec
|
||
|
|
FPGA_ram_del_2: TRAM_del_rec
|
||
|
|
FPGA_ram_del_3: TRAM_del_rec
|
||
|
|
IO_SEL_io_coef: list[list[float]]
|
||
|
|
timing_delays: ExtraTimingDelays
|
||
|
|
|
||
|
|
@staticmethod
|
||
|
|
def from_bytes(data: bytes) -> 'Tdel_all_rec':
|
||
|
|
offset = 0
|
||
|
|
sb_del_tile_arr, offset = read_SB_del_tile_arr_from_bytes(data, offset)
|
||
|
|
im, offset = read_IM_del_tile_arr_from_bytes(data, offset)
|
||
|
|
om, offset = read_OM_del_tile_arr_from_bytes(data, offset)
|
||
|
|
cpe, offset = read_CPE_del_tile_arr_from_bytes(data, offset)
|
||
|
|
sb_del_rim, offset = read_SB_del_rim_arr_from_bytes(data, offset)
|
||
|
|
edge, offset = read_Edge_del_arr_from_bytes(data, offset)
|
||
|
|
io_sel, offset = read_IO_SEL_del_arr_from_bytes(data, offset)
|
||
|
|
clkin, offset = read_CLKIN_del_arr_from_bytes(data, offset)
|
||
|
|
glbout, offset = read_GLBOUT_del_arr_from_bytes(data, offset)
|
||
|
|
pll_del, offset = read_PLL_del_arr_from_bytes(data, offset)
|
||
|
|
fpga_ram_del_1, offset = read_TRAM_del_rec_from_bytes(data, offset)
|
||
|
|
fpga_ram_del_2, offset = read_TRAM_del_rec_from_bytes(data, offset)
|
||
|
|
fpga_ram_del_3, offset = read_TRAM_del_rec_from_bytes(data, offset)
|
||
|
|
io_sel_coef, offset = read_IO_SEL_io_coef_from_bytes(data, offset)
|
||
|
|
timing_delays, offset = ExtraTimingDelays.from_bytes(data, offset)
|
||
|
|
return Tdel_all_rec(sb_del_tile_arr, im, om, cpe, sb_del_rim, edge, io_sel, clkin, glbout, pll_del, fpga_ram_del_1, fpga_ram_del_2, fpga_ram_del_3,io_sel_coef, timing_delays)
|
||
|
|
|
||
|
|
|
||
|
|
def decompress_timing(input_path) -> 'Tdel_all_rec':
|
||
|
|
with open(input_path, 'rb') as f_in:
|
||
|
|
compressed_data = f_in.read()
|
||
|
|
try:
|
||
|
|
decompressed_data = zlib.decompress(compressed_data)
|
||
|
|
except zlib.error as e:
|
||
|
|
print(f"Decompression failed: {e}")
|
||
|
|
return
|
||
|
|
|
||
|
|
return Tdel_all_rec.from_bytes(decompressed_data)
|
||
|
|
|
||
|
|
# Example usage
|
||
|
|
#decompress_timing("cc_best_eco_dly.dly")
|
||
|
|
#decompress_timing("cc_best_lpr_dly.dly")
|
||
|
|
#decompress_timing("cc_best_spd_dly.dly")
|
||
|
|
#
|
||
|
|
#decompress_timing("cc_typ_eco_dly.dly")
|
||
|
|
#decompress_timing("cc_typ_lpr_dly.dly")
|
||
|
|
#decompress_timing("cc_typ_spd_dly.dly")
|
||
|
|
#
|
||
|
|
#decompress_timing("cc_worst_eco_dly.dly")
|
||
|
|
#decompress_timing("cc_worst_lpr_dly.dly")
|
||
|
|
#decompress_timing("cc_worst_spd_dly.dly")
|