99 lines
3.1 KiB
ReStructuredText
99 lines
3.1 KiB
ReStructuredText
.. _xilinx:
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Xilinx notes
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############
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To simplify further explanations, we consider the project is generated in the current directory.
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.. NOTE::
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1. Spartan Edge Accelerator Board has only pinheader, so the cable must be provided
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2. A *JTAG* <-> *SPI* bridge (used to write bitstream in FLASH) is available for some device, see
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:ghsrc:`spiOverJtag <spiOverJtag>` to check if your model is supported.
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3. Board provides the device/package model, but if the targeted board is not officially supported but the FPGA yes,
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you can use ``--fpga-part`` to provide the model.
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4. With spartan3, the flash is an independent JTAG device.
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User has to use ``--index-chain`` to access FPGA (RAM only) or flash (write/read only).
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.. WARNING::
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``*.bin`` may be loaded in memory or in flash, but this extension is a classic extension for CPU firmware and, by
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default, *openFPGALoader* loads file in memory.
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Double check ``-m`` / ``-f`` when you want to use a firmware for a softcore (or anything, other than a bitstream) to
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write somewhere in the FLASH device).
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``.bit`` file is the default format generated by *vivado*, so nothing special task must be done to generate this
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bitstream.
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``.bin`` is not, by default, produced.
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To have access to this file you need to configure the tool:
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- GUI: *Tools* -> *Settings* -> *Bitstreams* -> check ``-bin_file``.
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- TCL: append your *TCL* file with ``set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]``.
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.. WARNING::
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For alchitry board the bitstream must be configured with a buswidth of 1 or 2.
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Quad mode can't be used with alchitry's FLASH.
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Loading a bitstream
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===================
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``.bit`` and ``.bin`` are allowed to be loaded in memory.
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File load:
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.. code-block:: bash
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openFPGALoader [-m] -b arty *.runs/impl_1/*.bit (or *.bin)
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or
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.. code-block:: bash
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openFPGALoader [-m] -b spartanEdgeAccelBoard -c digilent_hs2 *.runs/impl_1/*.bit (or *.bin)
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SPI flash
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---------
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.. NOTE::
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``.bit``, ``.bin``, and ``.mcs`` are supported for FLASH.
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``.mcs`` must be generated through vivado with a tcl script like:
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.. code-block:: tcl
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set project [lindex $argv 0]
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set bitfile "${project}.runs/impl_1/${project}.bit"
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set mcsfile "${project}.runs/impl_1/${project}.mcs"
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write_cfgmem -format mcs -interface spix4 -size 16 \
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-loadbit "up 0x0 $bitfile" -loaddata "" \
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-file $mcsfile -force
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.. NOTE::
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``-interface spix4`` and ``-size 16`` depends on SPI flash capability and size.
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The tcl script is used with:
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.. code-block:: bash
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vivado -nolog -nojournal -mode batch -source script.tcl -tclargs myproject
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File load:
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.. code-block:: bash
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openFPGALoader [--fpga-part xxxx] -f -b arty *.runs/impl_1/*.mcs (or .bit / .bin)
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.. NOTE::
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``-f`` is required to write bitstream (without them ``.bit`` and ``.bin`` are loaded in memory).
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.. NOTE::
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``--fpga-part`` is only required if this information is not provided at ``board.hpp`` level or if the board is not
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officially supported.
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device/packagee format is something like xc7a35tcsg324 (arty model).
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See :ghsrc:`src/board.hpp <src/board.hpp>`, or :ghsrc:`spiOverJtag <spiOverJtag>` directory for examples.
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