69 lines
1.6 KiB
Tcl
69 lines
1.6 KiB
Tcl
set parts [lindex $argv 0]
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set project_name "spiOverJtag"
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set build_path tmp_${parts}
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file delete -force $build_path
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# Project creation
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set grade [dict create \
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xc7a35tcpg236 -1 \
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xc7a35tcsg324 -1 \
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xc7a35tftg256 -1 \
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xc7a50tcpg236 -2 \
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xc7a75tfgg484 -2 \
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xc7a100tfgg484 -2 \
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xc7a200tsbg484 -1 \
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xc7k325tffg676 -1 \
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xc7k325tffg900 -2 \
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xc7s50csga324 -1 \
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]
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set pkg_name [dict create \
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xc7a35tcpg236 xc7a_cpg236 \
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xc7a35tcsg324 xc7a_csg324 \
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xc7a35tftg256 xc7a_ftg256 \
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xc7a50tcpg236 xc7a_cpg236 \
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xc7a75tfgg484 xc7a_fgg484 \
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xc7a100tfgg484 xc7a_fgg484 \
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xc7a200tsbg484 xc7a_sbg484 \
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xc7a200tfbg484 xc7a_fbg484 \
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xc7k325tffg676 xc7k_ffg676 \
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xc7k325tffg900 xc7k_ffg900 \
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xc7s50csga324 xc7s_csga324 \
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]
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set curr_grade [dict get $grade $parts]
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set curr_pins [dict get $pkg_name $parts]
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create_project $project_name $build_path -part ${parts}${curr_grade}
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add_files -norecurse xilinx_spiOverJtag.vhd
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add_files -norecurse -fileset constrs_1 constr_${curr_pins}.xdc
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set_property VERILOG_DEFINE {TOOL_VIVADO} [current_fileset]
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# set the current synth run
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current_run -synthesis [get_runs synth_1]
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reset_run synth_1
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set obj [get_runs impl_1]
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set_property AUTO_INCREMENTAL_CHECKPOINT 1 [get_runs impl_1]
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set_property "needs_refresh" "1" $obj
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# set the current impl run
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current_run -implementation [get_runs impl_1]
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puts "INFO: Project created: $project_name"
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launch_runs synth_1 -jobs 4
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wait_on_run synth_1
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## do implementation
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launch_runs impl_1 -jobs 4
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wait_on_run impl_1
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## make bit file
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launch_runs impl_1 -jobs 4 -to_step write_bitstream
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wait_on_run impl_1
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exit
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