85 lines
1.9 KiB
Verilog
85 lines
1.9 KiB
Verilog
`default_nettype none
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/*
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* BPI Flash over JTAG for Xilinx 7-series FPGAs
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* Uses BSCANE2 primitive to access USER1 JTAG register
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*/
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module bpiOverJtag (
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/* BPI Flash interface */
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output wire [25:1] bpi_addr,
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inout wire [15:0] bpi_dq,
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output wire bpi_ce_n,
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output wire bpi_oe_n,
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output wire bpi_we_n,
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output wire bpi_adv_n
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);
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wire capture, drck, sel, update, shift;
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wire tdi, tdo;
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/* Version Interface */
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wire ver_sel, ver_cap, ver_shift, ver_drck, ver_tdi, ver_tdo;
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bpiOverJtag_core bpiOverJtag_core_inst (
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/* JTAG state/controls */
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.sel(sel),
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.capture(capture),
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.update(update),
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.shift(shift),
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.drck(drck),
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.tdi(tdi),
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.tdo(tdo),
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/* Version endpoint */
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.ver_sel(ver_sel),
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.ver_cap(ver_cap),
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.ver_shift(ver_shift),
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.ver_drck(ver_drck),
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.ver_tdi(ver_tdi),
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.ver_tdo(ver_tdo),
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/* BPI Flash physical interface */
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.bpi_addr(bpi_addr),
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.bpi_dq(bpi_dq),
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.bpi_ce_n(bpi_ce_n),
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.bpi_oe_n(bpi_oe_n),
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.bpi_we_n(bpi_we_n),
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.bpi_adv_n(bpi_adv_n)
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);
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/* BSCANE2 for main data interface (USER1) */
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BSCANE2 #(
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.JTAG_CHAIN(1)
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) bscane2_inst (
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.CAPTURE(capture),
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.DRCK(drck),
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.RESET(),
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.RUNTEST(),
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.SEL(sel),
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.SHIFT(shift),
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.TCK(),
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.TDI(tdi),
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.TMS(),
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.UPDATE(update),
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.TDO(tdo)
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);
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/* BSCANE2 for version interface (USER4) */
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BSCANE2 #(
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.JTAG_CHAIN(4)
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) bscane2_version (
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.CAPTURE(ver_cap),
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.DRCK(ver_drck),
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.RESET(),
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.RUNTEST(),
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.SEL(ver_sel),
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.SHIFT(ver_shift),
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.TCK(),
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.TDI(ver_tdi),
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.TMS(),
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.UPDATE(),
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.TDO(ver_tdo)
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);
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endmodule
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