220 lines
8.2 KiB
Verilog
220 lines
8.2 KiB
Verilog
module spiOverJtag
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(
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`ifndef virtexultrascale
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output csn,
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`ifdef spartan6
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output sck,
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`endif
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`ifdef spartan3e
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output sck,
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`endif
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output sdi_dq0,
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input sdo_dq1,
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output wpn_dq2,
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output hldn_dq3
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`endif // virtexultrascale
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`ifdef secondaryflash
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output sdi_sec_dq0,
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input sdo_sec_dq1,
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output wpn_sec_dq2,
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output hldn_sec_dq3,
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output csn_sec
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`endif // secondaryflash
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);
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wire capture, drck, sel, update;
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wire runtest;
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wire tdi;
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reg fsm_csn;
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assign wpn_dq2 = 1'b1;
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assign hldn_dq3 = 1'b1;
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// jtag -> spi flash
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assign sdi_dq0 = tdi;
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wire tdo = (sel) ? sdo_dq1 : tdi;
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assign csn = fsm_csn;
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wire tmp_cap_s = capture && sel;
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wire tmp_up_s = update && sel;
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always @(posedge drck, posedge runtest) begin
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if (runtest) begin
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fsm_csn <= 1'b1;
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end else begin
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if (tmp_cap_s) begin
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fsm_csn <= 1'b0;
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end else if (tmp_up_s) begin
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fsm_csn <= 1'b1;
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end else begin
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fsm_csn <= fsm_csn;
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end
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end
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end
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`ifdef spartan6
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assign sck = drck;
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`else // !spartan6
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`ifdef spartan3e
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assign sck = drck;
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assign runtest = tmp_up_s;
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`else // !spartan6 && !spartan3e
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`ifdef virtexultrascale
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wire [3:0] di;
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assign sdo_dq1 = di[1];
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wire [3:0] do = {hldn_dq3, wpn_dq2, 1'b0, sdi_dq0};
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wire [3:0] dts = 4'b0010;
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// secondary BSCANE3 signals
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wire sel_sec, drck_sec;
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wire sck = (sel_sec) ? drck_sec : drck;
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STARTUPE3 #(
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.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
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.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency (ns) for simulation.
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) startupe3_inst (
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.CFGCLK (), // 1-bit output: Configuration main clock output.
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.CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output.
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.DI (di), // 4-bit output: Allow receiving on the D input pin.
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.EOS (), // 1-bit output: Active-High output signal indicating the End Of Startup.
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.PREQ (), // 1-bit output: PROGRAM request to fabric output.
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.DO (do), // 4-bit input: Allows control of the D pin output.
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.DTS (dts), // 4-bit input: Allows tristate of the D pin.
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.FCSBO (csn), // 1-bit input: Controls the FCS_B pin for flash access.
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.FCSBTS (1'b0), // 1-bit input: Tristate the FCS_B pin.
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.GSR (1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port).
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.GTS (1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name).
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.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM).
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.PACK (1'b0), // 1-bit input: PROGRAM acknowledge input.
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.USRCCLKO (sck), // 1-bit input: User CCLK input.
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.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input.
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.USRDONEO (1'b1), // 1-bit input: User DONE pin output control.
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.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output.
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);
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`else // !spartan6 && !spartan3e && !virtexultrascale
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STARTUPE2 #(
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.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
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.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
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) startupe2_inst (
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.CFGCLK (), // 1-bit output: Configuration main clock output
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.CFGMCLK (), // 1-bit output: Configuration internal oscillator clock output
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.EOS (), // 1-bit output: Active high output signal indicating the End Of Startup.
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.PREQ (), // 1-bit output: PROGRAM request to fabric output
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.CLK (1'b0), // 1-bit input: User start-up clock input
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.GSR (1'b0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
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.GTS (1'b0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
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.KEYCLEARB(1'b0), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
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.PACK (1'b1), // 1-bit input: PROGRAM acknowledge input
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.USRCCLKO (drck), // 1-bit input: User CCLK input
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.USRCCLKTS(1'b0), // 1-bit input: User CCLK 3-state enable input
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.USRDONEO (1'b1), // 1-bit input: User DONE pin output control
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.USRDONETS(1'b1) // 1-bit input: User DONE 3-state enable output
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);
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`endif
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`endif
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`endif
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`ifdef spartan3e
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BSCAN_SPARTAN3 bscane2_inst (
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.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
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.DRCK1 (drck), // 1-bit output: Gated TCK output. When SEL
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// is asserted, DRCK toggles when
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// CAPTURE or SHIFT are asserted.
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.DRCK2 (), // 1-bit output: USER2 function
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.RESET (), // 1-bit output: Reset output for TAP controller.
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.SEL1 (sel), // 1-bit output: USER1 instruction active output.
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.SEL2 (), // 1-bit output: USER2 instruction active output.
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.SHIFT (), // 1-bit output: SHIFT output from TAP controller.
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.TDI (tdi), // 1-bit output: Test Data Input (TDI) output
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// from TAP controller.
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.UPDATE (update), // 1-bit output: UPDATE output from TAP controller
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.TDO1 (tdo), // 1-bit input: Test Data Output (TDO) input
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// for USER1 function.
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.TDO2 () // 1-bit input: USER2 function
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);
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`else
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`ifdef spartan6
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BSCAN_SPARTAN6 #(
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`else
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BSCANE2 #(
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`endif
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.JTAG_CHAIN(1) // Value for USER command.
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) bscane2_inst (
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.CAPTURE(capture), // 1-bit output: CAPTURE output from TAP controller.
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.DRCK (drck), // 1-bit output: Gated TCK output. When SEL
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// is asserted, DRCK toggles when
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// CAPTURE or SHIFT are asserted.
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.RESET (), // 1-bit output: Reset output for TAP controller.
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.RUNTEST(runtest), // 1-bit output: Output asserted when TAP
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// controller is in Run Test/Idle state.
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.SEL (sel), // 1-bit output: USER instruction active output.
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.SHIFT (), // 1-bit output: SHIFT output from TAP controller.
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.TCK (), // 1-bit output: Test Clock output.
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// Fabric connection to TAP Clock pin.
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.TDI (tdi), // 1-bit output: Test Data Input (TDI) output
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// from TAP controller.
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.TMS (), // 1-bit output: Test Mode Select output.
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// Fabric connection to TAP.
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.UPDATE (update), // 1-bit output: UPDATE output from TAP controller
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.TDO (tdo) // 1-bit input: Test Data Output (TDO) input
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// for USER function.
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);
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`endif
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`ifdef secondaryflash
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reg fsm_csn_sec;
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wire tdo_sec;
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assign wpn_sec_dq2 = 1'b1;
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assign hldn_sec_dq3 = 1'b1;
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assign sdi_sec_dq0 = tdi;
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assign tdo_sec = (sel_sec) ? sdo_sec_dq1 : tdi;
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assign csn_sec = fsm_csn_sec;
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wire tmp_cap_sec_s = capture && sel_sec;
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wire tmp_up_sec_s = update && sel_sec;
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always @(posedge drck_sec, posedge runtest) begin
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if (runtest) begin
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fsm_csn_sec <= 1'b1;
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end else begin
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if (tmp_cap_sec_s) begin
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fsm_csn_sec <= 1'b0;
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end else if (tmp_up_sec_s) begin
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fsm_csn_sec <= 1'b1;
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end else begin
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fsm_csn_sec <= fsm_csn_sec;
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end
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end
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end
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BSCANE2 #(
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.JTAG_CHAIN(2) // Value for USER command.
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) bscane2_sec_inst (
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.CAPTURE(), // 1-bit output: CAPTURE output from TAP controller.
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.DRCK (drck_sec), // 1-bit output: Gated TCK output. When SEL
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// is asserted, DRCK toggles when
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// CAPTURE or SHIFT are asserted.
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.RESET (), // 1-bit output: Reset output for TAP controller.
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.RUNTEST(), // 1-bit output: Output asserted when TAP
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// controller is in Run Test/Idle state.
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.SEL (sel_sec), // 1-bit output: USER instruction active output.
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.SHIFT (), // 1-bit output: SHIFT output from TAP controller.
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.TCK (), // 1-bit output: Test Clock output.
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// Fabric connection to TAP Clock pin.
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.TDI (), // 1-bit output: Test Data Input (TDI) output
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// from TAP controller.
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.TMS (), // 1-bit output: Test Mode Select output.
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// Fabric connection to TAP.
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.UPDATE (), // 1-bit output: UPDATE output from TAP controller
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.TDO (tdo_sec) // 1-bit input: Test Data Output (TDO) input
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// for USER function.
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);
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`else // secondaryflash
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assign sel_sec = 1'b0;
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assign drck_sec = 1'b0;
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`endif // secondaryflash
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endmodule
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