60 lines
1.2 KiB
Verilog
60 lines
1.2 KiB
Verilog
module spiOverJtag (
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input jtag_1_CAPTURE,
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input jtag_1_DRCK,
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input jtag_1_RESET,
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input jtag_1_RUNTEST,
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input jtag_1_SEL,
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input jtag_1_SHIFT,
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input jtag_1_TCK,
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input jtag_1_TDI,
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input jtag_1_TMS,
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input jtag_1_UPDATE,
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output jtag_1_TDO,
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output csn,
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output sck,
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output sdi_dq0,
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input sdo_dq1,
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output wpn_dq2,
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output hldn_dq3
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);
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wire capture, drck, sel, update;
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wire runtest;
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wire tdi;
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reg fsm_csn;
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assign wpn_dq2 = 1'b1;
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assign hldn_dq3 = 1'b1;
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// jtag -> spi flash
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assign sdi_dq0 = tdi;
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wire tdo = (sel) ? sdo_dq1 : tdi;
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assign csn = fsm_csn;
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wire tmp_cap_s = capture && sel;
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wire tmp_up_s = update && sel;
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always @(posedge drck, posedge runtest) begin
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if (runtest) begin
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fsm_csn <= 1'b1;
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end else begin
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if (tmp_cap_s) begin
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fsm_csn <= 1'b0;
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end else if (tmp_up_s) begin
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fsm_csn <= 1'b1;
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end else begin
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fsm_csn <= fsm_csn;
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end
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end
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end
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assign sck = drck;
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assign capture = jtag_1_CAPTURE;
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assign drck = jtag_1_DRCK;
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assign runtest = jtag_1_RUNTEST;
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assign sel = jtag_1_SEL;
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assign tdi = jtag_1_TDI;
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assign update = jtag_1_UPDATE;
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assign jtag_1_TDO = tdo;
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endmodule
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